1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2015-2018 Etnaviv Project
4 */
5
6 #include <linux/clk.h>
7 #include <linux/component.h>
8 #include <linux/delay.h>
9 #include <linux/dma-fence.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/thermal.h>
17
18 #include "etnaviv_cmdbuf.h"
19 #include "etnaviv_dump.h"
20 #include "etnaviv_gpu.h"
21 #include "etnaviv_gem.h"
22 #include "etnaviv_mmu.h"
23 #include "etnaviv_perfmon.h"
24 #include "etnaviv_sched.h"
25 #include "common.xml.h"
26 #include "state.xml.h"
27 #include "state_hi.xml.h"
28 #include "cmdstream.xml.h"
29
30 static const struct platform_device_id gpu_ids[] = {
31 { .name = "etnaviv-gpu,2d" },
32 { },
33 };
34
35 /*
36 * Driver functions:
37 */
38
etnaviv_gpu_get_param(struct etnaviv_gpu * gpu,u32 param,u64 * value)39 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
40 {
41 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
42
43 switch (param) {
44 case ETNAVIV_PARAM_GPU_MODEL:
45 *value = gpu->identity.model;
46 break;
47
48 case ETNAVIV_PARAM_GPU_REVISION:
49 *value = gpu->identity.revision;
50 break;
51
52 case ETNAVIV_PARAM_GPU_FEATURES_0:
53 *value = gpu->identity.features;
54 break;
55
56 case ETNAVIV_PARAM_GPU_FEATURES_1:
57 *value = gpu->identity.minor_features0;
58 break;
59
60 case ETNAVIV_PARAM_GPU_FEATURES_2:
61 *value = gpu->identity.minor_features1;
62 break;
63
64 case ETNAVIV_PARAM_GPU_FEATURES_3:
65 *value = gpu->identity.minor_features2;
66 break;
67
68 case ETNAVIV_PARAM_GPU_FEATURES_4:
69 *value = gpu->identity.minor_features3;
70 break;
71
72 case ETNAVIV_PARAM_GPU_FEATURES_5:
73 *value = gpu->identity.minor_features4;
74 break;
75
76 case ETNAVIV_PARAM_GPU_FEATURES_6:
77 *value = gpu->identity.minor_features5;
78 break;
79
80 case ETNAVIV_PARAM_GPU_FEATURES_7:
81 *value = gpu->identity.minor_features6;
82 break;
83
84 case ETNAVIV_PARAM_GPU_FEATURES_8:
85 *value = gpu->identity.minor_features7;
86 break;
87
88 case ETNAVIV_PARAM_GPU_FEATURES_9:
89 *value = gpu->identity.minor_features8;
90 break;
91
92 case ETNAVIV_PARAM_GPU_FEATURES_10:
93 *value = gpu->identity.minor_features9;
94 break;
95
96 case ETNAVIV_PARAM_GPU_FEATURES_11:
97 *value = gpu->identity.minor_features10;
98 break;
99
100 case ETNAVIV_PARAM_GPU_FEATURES_12:
101 *value = gpu->identity.minor_features11;
102 break;
103
104 case ETNAVIV_PARAM_GPU_STREAM_COUNT:
105 *value = gpu->identity.stream_count;
106 break;
107
108 case ETNAVIV_PARAM_GPU_REGISTER_MAX:
109 *value = gpu->identity.register_max;
110 break;
111
112 case ETNAVIV_PARAM_GPU_THREAD_COUNT:
113 *value = gpu->identity.thread_count;
114 break;
115
116 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
117 *value = gpu->identity.vertex_cache_size;
118 break;
119
120 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
121 *value = gpu->identity.shader_core_count;
122 break;
123
124 case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
125 *value = gpu->identity.pixel_pipes;
126 break;
127
128 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
129 *value = gpu->identity.vertex_output_buffer_size;
130 break;
131
132 case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
133 *value = gpu->identity.buffer_size;
134 break;
135
136 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
137 *value = gpu->identity.instruction_count;
138 break;
139
140 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
141 *value = gpu->identity.num_constants;
142 break;
143
144 case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
145 *value = gpu->identity.varyings_count;
146 break;
147
148 case ETNAVIV_PARAM_SOFTPIN_START_ADDR:
149 if (priv->mmu_global->version == ETNAVIV_IOMMU_V2)
150 *value = ETNAVIV_SOFTPIN_START_ADDRESS;
151 else
152 *value = ~0ULL;
153 break;
154
155 case ETNAVIV_PARAM_GPU_PRODUCT_ID:
156 *value = gpu->identity.product_id;
157 break;
158
159 case ETNAVIV_PARAM_GPU_CUSTOMER_ID:
160 *value = gpu->identity.customer_id;
161 break;
162
163 case ETNAVIV_PARAM_GPU_ECO_ID:
164 *value = gpu->identity.eco_id;
165 break;
166
167 default:
168 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
169 return -EINVAL;
170 }
171
172 return 0;
173 }
174
175
176 #define etnaviv_is_model_rev(gpu, mod, rev) \
177 ((gpu)->identity.model == chipModel_##mod && \
178 (gpu)->identity.revision == rev)
179 #define etnaviv_field(val, field) \
180 (((val) & field##__MASK) >> field##__SHIFT)
181
etnaviv_hw_specs(struct etnaviv_gpu * gpu)182 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
183 {
184 if (gpu->identity.minor_features0 &
185 chipMinorFeatures0_MORE_MINOR_FEATURES) {
186 u32 specs[4];
187 unsigned int streams;
188
189 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
190 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
191 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
192 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
193
194 gpu->identity.stream_count = etnaviv_field(specs[0],
195 VIVS_HI_CHIP_SPECS_STREAM_COUNT);
196 gpu->identity.register_max = etnaviv_field(specs[0],
197 VIVS_HI_CHIP_SPECS_REGISTER_MAX);
198 gpu->identity.thread_count = etnaviv_field(specs[0],
199 VIVS_HI_CHIP_SPECS_THREAD_COUNT);
200 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
201 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
202 gpu->identity.shader_core_count = etnaviv_field(specs[0],
203 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
204 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
205 VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
206 gpu->identity.vertex_output_buffer_size =
207 etnaviv_field(specs[0],
208 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
209
210 gpu->identity.buffer_size = etnaviv_field(specs[1],
211 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
212 gpu->identity.instruction_count = etnaviv_field(specs[1],
213 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
214 gpu->identity.num_constants = etnaviv_field(specs[1],
215 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
216
217 gpu->identity.varyings_count = etnaviv_field(specs[2],
218 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
219
220 /* This overrides the value from older register if non-zero */
221 streams = etnaviv_field(specs[3],
222 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
223 if (streams)
224 gpu->identity.stream_count = streams;
225 }
226
227 /* Fill in the stream count if not specified */
228 if (gpu->identity.stream_count == 0) {
229 if (gpu->identity.model >= 0x1000)
230 gpu->identity.stream_count = 4;
231 else
232 gpu->identity.stream_count = 1;
233 }
234
235 /* Convert the register max value */
236 if (gpu->identity.register_max)
237 gpu->identity.register_max = 1 << gpu->identity.register_max;
238 else if (gpu->identity.model == chipModel_GC400)
239 gpu->identity.register_max = 32;
240 else
241 gpu->identity.register_max = 64;
242
243 /* Convert thread count */
244 if (gpu->identity.thread_count)
245 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
246 else if (gpu->identity.model == chipModel_GC400)
247 gpu->identity.thread_count = 64;
248 else if (gpu->identity.model == chipModel_GC500 ||
249 gpu->identity.model == chipModel_GC530)
250 gpu->identity.thread_count = 128;
251 else
252 gpu->identity.thread_count = 256;
253
254 if (gpu->identity.vertex_cache_size == 0)
255 gpu->identity.vertex_cache_size = 8;
256
257 if (gpu->identity.shader_core_count == 0) {
258 if (gpu->identity.model >= 0x1000)
259 gpu->identity.shader_core_count = 2;
260 else
261 gpu->identity.shader_core_count = 1;
262 }
263
264 if (gpu->identity.pixel_pipes == 0)
265 gpu->identity.pixel_pipes = 1;
266
267 /* Convert virtex buffer size */
268 if (gpu->identity.vertex_output_buffer_size) {
269 gpu->identity.vertex_output_buffer_size =
270 1 << gpu->identity.vertex_output_buffer_size;
271 } else if (gpu->identity.model == chipModel_GC400) {
272 if (gpu->identity.revision < 0x4000)
273 gpu->identity.vertex_output_buffer_size = 512;
274 else if (gpu->identity.revision < 0x4200)
275 gpu->identity.vertex_output_buffer_size = 256;
276 else
277 gpu->identity.vertex_output_buffer_size = 128;
278 } else {
279 gpu->identity.vertex_output_buffer_size = 512;
280 }
281
282 switch (gpu->identity.instruction_count) {
283 case 0:
284 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
285 gpu->identity.model == chipModel_GC880)
286 gpu->identity.instruction_count = 512;
287 else
288 gpu->identity.instruction_count = 256;
289 break;
290
291 case 1:
292 gpu->identity.instruction_count = 1024;
293 break;
294
295 case 2:
296 gpu->identity.instruction_count = 2048;
297 break;
298
299 default:
300 gpu->identity.instruction_count = 256;
301 break;
302 }
303
304 if (gpu->identity.num_constants == 0)
305 gpu->identity.num_constants = 168;
306
307 if (gpu->identity.varyings_count == 0) {
308 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
309 gpu->identity.varyings_count = 12;
310 else
311 gpu->identity.varyings_count = 8;
312 }
313
314 /*
315 * For some cores, two varyings are consumed for position, so the
316 * maximum varying count needs to be reduced by one.
317 */
318 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
319 etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
320 etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
321 etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
322 etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
323 etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
324 etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
325 etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
326 etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
327 etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
328 etnaviv_is_model_rev(gpu, GC880, 0x5106))
329 gpu->identity.varyings_count -= 1;
330 }
331
etnaviv_hw_identify(struct etnaviv_gpu * gpu)332 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
333 {
334 u32 chipIdentity;
335
336 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
337
338 /* Special case for older graphic cores. */
339 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
340 gpu->identity.model = chipModel_GC500;
341 gpu->identity.revision = etnaviv_field(chipIdentity,
342 VIVS_HI_CHIP_IDENTITY_REVISION);
343 } else {
344 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
345
346 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
347 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
348 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);
349
350 /*
351 * Reading these two registers on GC600 rev 0x19 result in a
352 * unhandled fault: external abort on non-linefetch
353 */
354 if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) {
355 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
356 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
357 }
358
359 /*
360 * !!!! HACK ALERT !!!!
361 * Because people change device IDs without letting software
362 * know about it - here is the hack to make it all look the
363 * same. Only for GC400 family.
364 */
365 if ((gpu->identity.model & 0xff00) == 0x0400 &&
366 gpu->identity.model != chipModel_GC420) {
367 gpu->identity.model = gpu->identity.model & 0x0400;
368 }
369
370 /* Another special case */
371 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
372 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
373
374 if (chipDate == 0x20080814 && chipTime == 0x12051100) {
375 /*
376 * This IP has an ECO; put the correct
377 * revision in it.
378 */
379 gpu->identity.revision = 0x1051;
380 }
381 }
382
383 /*
384 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
385 * reality it's just a re-branded GC3000. We can identify this
386 * core by the upper half of the revision register being all 1.
387 * Fix model/rev here, so all other places can refer to this
388 * core by its real identity.
389 */
390 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
391 gpu->identity.model = chipModel_GC3000;
392 gpu->identity.revision &= 0xffff;
393 }
394
395 if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617))
396 gpu->identity.eco_id = 1;
397
398 if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511))
399 gpu->identity.eco_id = 1;
400 }
401
402 dev_info(gpu->dev, "model: GC%x, revision: %x\n",
403 gpu->identity.model, gpu->identity.revision);
404
405 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
406 /*
407 * If there is a match in the HWDB, we aren't interested in the
408 * remaining register values, as they might be wrong.
409 */
410 if (etnaviv_fill_identity_from_hwdb(gpu))
411 return;
412
413 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
414
415 /* Disable fast clear on GC700. */
416 if (gpu->identity.model == chipModel_GC700)
417 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
418
419 /* These models/revisions don't have the 2D pipe bit */
420 if ((gpu->identity.model == chipModel_GC500 &&
421 gpu->identity.revision <= 2) ||
422 gpu->identity.model == chipModel_GC300)
423 gpu->identity.features |= chipFeatures_PIPE_2D;
424
425 if ((gpu->identity.model == chipModel_GC500 &&
426 gpu->identity.revision < 2) ||
427 (gpu->identity.model == chipModel_GC300 &&
428 gpu->identity.revision < 0x2000)) {
429
430 /*
431 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
432 * registers.
433 */
434 gpu->identity.minor_features0 = 0;
435 gpu->identity.minor_features1 = 0;
436 gpu->identity.minor_features2 = 0;
437 gpu->identity.minor_features3 = 0;
438 gpu->identity.minor_features4 = 0;
439 gpu->identity.minor_features5 = 0;
440 } else
441 gpu->identity.minor_features0 =
442 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
443
444 if (gpu->identity.minor_features0 &
445 chipMinorFeatures0_MORE_MINOR_FEATURES) {
446 gpu->identity.minor_features1 =
447 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
448 gpu->identity.minor_features2 =
449 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
450 gpu->identity.minor_features3 =
451 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
452 gpu->identity.minor_features4 =
453 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
454 gpu->identity.minor_features5 =
455 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
456 }
457
458 /* GC600/300 idle register reports zero bits where modules aren't present */
459 if (gpu->identity.model == chipModel_GC600 ||
460 gpu->identity.model == chipModel_GC300)
461 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
462 VIVS_HI_IDLE_STATE_RA |
463 VIVS_HI_IDLE_STATE_SE |
464 VIVS_HI_IDLE_STATE_PA |
465 VIVS_HI_IDLE_STATE_SH |
466 VIVS_HI_IDLE_STATE_PE |
467 VIVS_HI_IDLE_STATE_DE |
468 VIVS_HI_IDLE_STATE_FE;
469
470 etnaviv_hw_specs(gpu);
471 }
472
etnaviv_gpu_load_clock(struct etnaviv_gpu * gpu,u32 clock)473 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
474 {
475 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
476 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
477 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
478 }
479
etnaviv_gpu_update_clock(struct etnaviv_gpu * gpu)480 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
481 {
482 if (gpu->identity.minor_features2 &
483 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
484 clk_set_rate(gpu->clk_core,
485 gpu->base_rate_core >> gpu->freq_scale);
486 clk_set_rate(gpu->clk_shader,
487 gpu->base_rate_shader >> gpu->freq_scale);
488 } else {
489 unsigned int fscale = 1 << (6 - gpu->freq_scale);
490 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
491
492 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
493 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
494 etnaviv_gpu_load_clock(gpu, clock);
495 }
496
497 /*
498 * Choose number of wait cycles to target a ~30us (1/32768) max latency
499 * until new work is picked up by the FE when it polls in the idle loop.
500 * If the GPU base frequency is unknown use 200 wait cycles.
501 */
502 gpu->fe_waitcycles = clamp(gpu->base_rate_core >> (15 - gpu->freq_scale),
503 200UL, 0xffffUL);
504 }
505
etnaviv_hw_reset(struct etnaviv_gpu * gpu)506 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
507 {
508 u32 control, idle;
509 unsigned long timeout;
510 bool failed = true;
511
512 /* We hope that the GPU resets in under one second */
513 timeout = jiffies + msecs_to_jiffies(1000);
514
515 while (time_is_after_jiffies(timeout)) {
516 /* enable clock */
517 unsigned int fscale = 1 << (6 - gpu->freq_scale);
518 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
519 etnaviv_gpu_load_clock(gpu, control);
520
521 /* isolate the GPU. */
522 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
523 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
524
525 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
526 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
527 VIVS_MMUv2_AHB_CONTROL_RESET);
528 } else {
529 /* set soft reset. */
530 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
531 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
532 }
533
534 /* wait for reset. */
535 usleep_range(10, 20);
536
537 /* reset soft reset bit. */
538 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
539 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
540
541 /* reset GPU isolation. */
542 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
543 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
544
545 /* read idle register. */
546 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
547
548 /* try resetting again if FE is not idle */
549 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
550 dev_dbg(gpu->dev, "FE is not idle\n");
551 continue;
552 }
553
554 /* read reset register. */
555 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
556
557 /* is the GPU idle? */
558 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
559 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
560 dev_dbg(gpu->dev, "GPU is not idle\n");
561 continue;
562 }
563
564 /* disable debug registers, as they are not normally needed */
565 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
566 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
567
568 failed = false;
569 break;
570 }
571
572 if (failed) {
573 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
574 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
575
576 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
577 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
578 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
579 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
580
581 return -EBUSY;
582 }
583
584 /* We rely on the GPU running, so program the clock */
585 etnaviv_gpu_update_clock(gpu);
586
587 gpu->state = ETNA_GPU_STATE_RESET;
588 gpu->exec_state = -1;
589 if (gpu->mmu_context)
590 etnaviv_iommu_context_put(gpu->mmu_context);
591 gpu->mmu_context = NULL;
592
593 return 0;
594 }
595
etnaviv_gpu_enable_mlcg(struct etnaviv_gpu * gpu)596 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
597 {
598 u32 pmc, ppc;
599
600 /* enable clock gating */
601 ppc = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
602 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
603
604 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
605 if (gpu->identity.revision == 0x4301 ||
606 gpu->identity.revision == 0x4302)
607 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
608
609 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, ppc);
610
611 pmc = gpu_read_power(gpu, VIVS_PM_MODULE_CONTROLS);
612
613 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
614 if (gpu->identity.model >= chipModel_GC400 &&
615 gpu->identity.model != chipModel_GC420 &&
616 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
617 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
618
619 /*
620 * Disable PE clock gating on revs < 5.0.0.0 when HZ is
621 * present without a bug fix.
622 */
623 if (gpu->identity.revision < 0x5000 &&
624 gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
625 !(gpu->identity.minor_features1 &
626 chipMinorFeatures1_DISABLE_PE_GATING))
627 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
628
629 if (gpu->identity.revision < 0x5422)
630 pmc |= BIT(15); /* Unknown bit */
631
632 /* Disable TX clock gating on affected core revisions. */
633 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
634 etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
635 etnaviv_is_model_rev(gpu, GC7000, 0x6202) ||
636 etnaviv_is_model_rev(gpu, GC7000, 0x6203))
637 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
638
639 /* Disable SE and RA clock gating on affected core revisions. */
640 if (etnaviv_is_model_rev(gpu, GC7000, 0x6202))
641 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
642 VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;
643
644 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
645 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
646
647 gpu_write_power(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
648 }
649
etnaviv_gpu_start_fe(struct etnaviv_gpu * gpu,u32 address,u16 prefetch)650 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
651 {
652 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
653 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
654 VIVS_FE_COMMAND_CONTROL_ENABLE |
655 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
656
657 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
658 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
659 VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
660 VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
661 }
662 }
663
etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu * gpu,struct etnaviv_iommu_context * context)664 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu,
665 struct etnaviv_iommu_context *context)
666 {
667 u16 prefetch;
668 u32 address;
669
670 WARN_ON(gpu->state != ETNA_GPU_STATE_INITIALIZED);
671
672 /* setup the MMU */
673 etnaviv_iommu_restore(gpu, context);
674
675 /* Start command processor */
676 prefetch = etnaviv_buffer_init(gpu);
677 address = etnaviv_cmdbuf_get_va(&gpu->buffer,
678 &gpu->mmu_context->cmdbuf_mapping);
679
680 etnaviv_gpu_start_fe(gpu, address, prefetch);
681
682 gpu->state = ETNA_GPU_STATE_RUNNING;
683 }
684
etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu * gpu)685 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
686 {
687 /*
688 * Base value for VIVS_PM_PULSE_EATER register on models where it
689 * cannot be read, extracted from vivante kernel driver.
690 */
691 u32 pulse_eater = 0x01590880;
692
693 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
694 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
695 pulse_eater |= BIT(23);
696
697 }
698
699 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
700 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
701 pulse_eater &= ~BIT(16);
702 pulse_eater |= BIT(17);
703 }
704
705 if ((gpu->identity.revision > 0x5420) &&
706 (gpu->identity.features & chipFeatures_PIPE_3D))
707 {
708 /* Performance fix: disable internal DFS */
709 pulse_eater = gpu_read_power(gpu, VIVS_PM_PULSE_EATER);
710 pulse_eater |= BIT(18);
711 }
712
713 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
714 }
715
etnaviv_gpu_hw_init(struct etnaviv_gpu * gpu)716 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
717 {
718 WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED ||
719 gpu->state == ETNA_GPU_STATE_RESET));
720
721 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
722 etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
723 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
724 u32 mc_memory_debug;
725
726 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
727
728 if (gpu->identity.revision == 0x5007)
729 mc_memory_debug |= 0x0c;
730 else
731 mc_memory_debug |= 0x08;
732
733 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
734 }
735
736 /* enable module-level clock gating */
737 etnaviv_gpu_enable_mlcg(gpu);
738
739 /*
740 * Update GPU AXI cache atttribute to "cacheable, no allocate".
741 * This is necessary to prevent the iMX6 SoC locking up.
742 */
743 gpu_write(gpu, VIVS_HI_AXI_CONFIG,
744 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
745 VIVS_HI_AXI_CONFIG_ARCACHE(2));
746
747 /* GC2000 rev 5108 needs a special bus config */
748 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
749 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
750 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
751 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
752 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
753 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
754 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
755 }
756
757 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
758 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
759 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
760 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
761 }
762
763 /* setup the pulse eater */
764 etnaviv_gpu_setup_pulse_eater(gpu);
765
766 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
767
768 gpu->state = ETNA_GPU_STATE_INITIALIZED;
769 }
770
etnaviv_gpu_init(struct etnaviv_gpu * gpu)771 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
772 {
773 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
774 dma_addr_t cmdbuf_paddr;
775 int ret, i;
776
777 ret = pm_runtime_get_sync(gpu->dev);
778 if (ret < 0) {
779 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
780 goto pm_put;
781 }
782
783 etnaviv_hw_identify(gpu);
784
785 if (gpu->identity.model == 0) {
786 dev_err(gpu->dev, "Unknown GPU model\n");
787 ret = -ENXIO;
788 goto fail;
789 }
790
791 if (gpu->identity.nn_core_count > 0)
792 dev_warn(gpu->dev, "etnaviv has been instantiated on a NPU, "
793 "for which the UAPI is still experimental\n");
794
795 /* Exclude VG cores with FE2.0 */
796 if (gpu->identity.features & chipFeatures_PIPE_VG &&
797 gpu->identity.features & chipFeatures_FE20) {
798 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
799 ret = -ENXIO;
800 goto fail;
801 }
802
803 /*
804 * On cores with security features supported, we claim control over the
805 * security states.
806 */
807 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
808 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
809 gpu->sec_mode = ETNA_SEC_KERNEL;
810
811 gpu->state = ETNA_GPU_STATE_IDENTIFIED;
812
813 ret = etnaviv_hw_reset(gpu);
814 if (ret) {
815 dev_err(gpu->dev, "GPU reset failed\n");
816 goto fail;
817 }
818
819 ret = etnaviv_iommu_global_init(gpu);
820 if (ret)
821 goto fail;
822
823 /*
824 * If the GPU is part of a system with DMA addressing limitations,
825 * request pages for our SHM backend buffers from the DMA32 zone to
826 * hopefully avoid performance killing SWIOTLB bounce buffering.
827 */
828 if (dma_addressing_limited(gpu->dev))
829 priv->shm_gfp_mask |= GFP_DMA32;
830
831 /* Create buffer: */
832 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer,
833 PAGE_SIZE);
834 if (ret) {
835 dev_err(gpu->dev, "could not create command buffer\n");
836 goto fail;
837 }
838
839 /*
840 * Set the GPU linear window to cover the cmdbuf region, as the GPU
841 * won't be able to start execution otherwise. The alignment to 128M is
842 * chosen arbitrarily but helps in debugging, as the MMU offset
843 * calculations are much more straight forward this way.
844 *
845 * On MC1.0 cores the linear window offset is ignored by the TS engine,
846 * leading to inconsistent memory views. Avoid using the offset on those
847 * cores if possible, otherwise disable the TS feature.
848 */
849 cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M);
850
851 if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
852 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
853 if (cmdbuf_paddr >= SZ_2G)
854 priv->mmu_global->memory_base = SZ_2G;
855 else
856 priv->mmu_global->memory_base = cmdbuf_paddr;
857 } else if (cmdbuf_paddr + SZ_128M >= SZ_2G) {
858 dev_info(gpu->dev,
859 "Need to move linear window on MC1.0, disabling TS\n");
860 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
861 priv->mmu_global->memory_base = SZ_2G;
862 }
863
864 /* Setup event management */
865 spin_lock_init(&gpu->event_spinlock);
866 init_completion(&gpu->event_free);
867 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
868 for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
869 complete(&gpu->event_free);
870
871 /* Now program the hardware */
872 mutex_lock(&gpu->lock);
873 etnaviv_gpu_hw_init(gpu);
874 mutex_unlock(&gpu->lock);
875
876 pm_runtime_mark_last_busy(gpu->dev);
877 pm_runtime_put_autosuspend(gpu->dev);
878
879 return 0;
880
881 fail:
882 pm_runtime_mark_last_busy(gpu->dev);
883 pm_put:
884 pm_runtime_put_autosuspend(gpu->dev);
885
886 return ret;
887 }
888
889 #ifdef CONFIG_DEBUG_FS
890 struct dma_debug {
891 u32 address[2];
892 u32 state[2];
893 };
894
verify_dma(struct etnaviv_gpu * gpu,struct dma_debug * debug)895 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
896 {
897 u32 i;
898
899 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
900 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
901
902 for (i = 0; i < 500; i++) {
903 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
904 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
905
906 if (debug->address[0] != debug->address[1])
907 break;
908
909 if (debug->state[0] != debug->state[1])
910 break;
911 }
912 }
913
etnaviv_gpu_debugfs(struct etnaviv_gpu * gpu,struct seq_file * m)914 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
915 {
916 struct dma_debug debug;
917 u32 dma_lo, dma_hi, axi, idle;
918 int ret;
919
920 seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
921
922 ret = pm_runtime_get_sync(gpu->dev);
923 if (ret < 0)
924 goto pm_put;
925
926 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
927 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
928 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
929 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
930
931 verify_dma(gpu, &debug);
932
933 seq_puts(m, "\tidentity\n");
934 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model);
935 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision);
936 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id);
937 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id);
938 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id);
939
940 seq_puts(m, "\tfeatures\n");
941 seq_printf(m, "\t major_features: 0x%08x\n",
942 gpu->identity.features);
943 seq_printf(m, "\t minor_features0: 0x%08x\n",
944 gpu->identity.minor_features0);
945 seq_printf(m, "\t minor_features1: 0x%08x\n",
946 gpu->identity.minor_features1);
947 seq_printf(m, "\t minor_features2: 0x%08x\n",
948 gpu->identity.minor_features2);
949 seq_printf(m, "\t minor_features3: 0x%08x\n",
950 gpu->identity.minor_features3);
951 seq_printf(m, "\t minor_features4: 0x%08x\n",
952 gpu->identity.minor_features4);
953 seq_printf(m, "\t minor_features5: 0x%08x\n",
954 gpu->identity.minor_features5);
955 seq_printf(m, "\t minor_features6: 0x%08x\n",
956 gpu->identity.minor_features6);
957 seq_printf(m, "\t minor_features7: 0x%08x\n",
958 gpu->identity.minor_features7);
959 seq_printf(m, "\t minor_features8: 0x%08x\n",
960 gpu->identity.minor_features8);
961 seq_printf(m, "\t minor_features9: 0x%08x\n",
962 gpu->identity.minor_features9);
963 seq_printf(m, "\t minor_features10: 0x%08x\n",
964 gpu->identity.minor_features10);
965 seq_printf(m, "\t minor_features11: 0x%08x\n",
966 gpu->identity.minor_features11);
967
968 seq_puts(m, "\tspecs\n");
969 seq_printf(m, "\t stream_count: %d\n",
970 gpu->identity.stream_count);
971 seq_printf(m, "\t register_max: %d\n",
972 gpu->identity.register_max);
973 seq_printf(m, "\t thread_count: %d\n",
974 gpu->identity.thread_count);
975 seq_printf(m, "\t vertex_cache_size: %d\n",
976 gpu->identity.vertex_cache_size);
977 seq_printf(m, "\t shader_core_count: %d\n",
978 gpu->identity.shader_core_count);
979 seq_printf(m, "\t nn_core_count: %d\n",
980 gpu->identity.nn_core_count);
981 seq_printf(m, "\t pixel_pipes: %d\n",
982 gpu->identity.pixel_pipes);
983 seq_printf(m, "\t vertex_output_buffer_size: %d\n",
984 gpu->identity.vertex_output_buffer_size);
985 seq_printf(m, "\t buffer_size: %d\n",
986 gpu->identity.buffer_size);
987 seq_printf(m, "\t instruction_count: %d\n",
988 gpu->identity.instruction_count);
989 seq_printf(m, "\t num_constants: %d\n",
990 gpu->identity.num_constants);
991 seq_printf(m, "\t varyings_count: %d\n",
992 gpu->identity.varyings_count);
993
994 seq_printf(m, "\taxi: 0x%08x\n", axi);
995 seq_printf(m, "\tidle: 0x%08x\n", idle);
996 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
997 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
998 seq_puts(m, "\t FE is not idle\n");
999 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
1000 seq_puts(m, "\t DE is not idle\n");
1001 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
1002 seq_puts(m, "\t PE is not idle\n");
1003 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
1004 seq_puts(m, "\t SH is not idle\n");
1005 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
1006 seq_puts(m, "\t PA is not idle\n");
1007 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
1008 seq_puts(m, "\t SE is not idle\n");
1009 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
1010 seq_puts(m, "\t RA is not idle\n");
1011 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
1012 seq_puts(m, "\t TX is not idle\n");
1013 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
1014 seq_puts(m, "\t VG is not idle\n");
1015 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
1016 seq_puts(m, "\t IM is not idle\n");
1017 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
1018 seq_puts(m, "\t FP is not idle\n");
1019 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
1020 seq_puts(m, "\t TS is not idle\n");
1021 if ((idle & VIVS_HI_IDLE_STATE_BL) == 0)
1022 seq_puts(m, "\t BL is not idle\n");
1023 if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0)
1024 seq_puts(m, "\t ASYNCFE is not idle\n");
1025 if ((idle & VIVS_HI_IDLE_STATE_MC) == 0)
1026 seq_puts(m, "\t MC is not idle\n");
1027 if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0)
1028 seq_puts(m, "\t PPA is not idle\n");
1029 if ((idle & VIVS_HI_IDLE_STATE_WD) == 0)
1030 seq_puts(m, "\t WD is not idle\n");
1031 if ((idle & VIVS_HI_IDLE_STATE_NN) == 0)
1032 seq_puts(m, "\t NN is not idle\n");
1033 if ((idle & VIVS_HI_IDLE_STATE_TP) == 0)
1034 seq_puts(m, "\t TP is not idle\n");
1035 if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
1036 seq_puts(m, "\t AXI low power mode\n");
1037
1038 if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
1039 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
1040 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
1041 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
1042
1043 seq_puts(m, "\tMC\n");
1044 seq_printf(m, "\t read0: 0x%08x\n", read0);
1045 seq_printf(m, "\t read1: 0x%08x\n", read1);
1046 seq_printf(m, "\t write: 0x%08x\n", write);
1047 }
1048
1049 seq_puts(m, "\tDMA ");
1050
1051 if (debug.address[0] == debug.address[1] &&
1052 debug.state[0] == debug.state[1]) {
1053 seq_puts(m, "seems to be stuck\n");
1054 } else if (debug.address[0] == debug.address[1]) {
1055 seq_puts(m, "address is constant\n");
1056 } else {
1057 seq_puts(m, "is running\n");
1058 }
1059
1060 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
1061 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
1062 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
1063 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
1064 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
1065 dma_lo, dma_hi);
1066
1067 ret = 0;
1068
1069 pm_runtime_mark_last_busy(gpu->dev);
1070 pm_put:
1071 pm_runtime_put_autosuspend(gpu->dev);
1072
1073 return ret;
1074 }
1075 #endif
1076
1077 /* fence object management */
1078 struct etnaviv_fence {
1079 struct etnaviv_gpu *gpu;
1080 struct dma_fence base;
1081 };
1082
to_etnaviv_fence(struct dma_fence * fence)1083 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1084 {
1085 return container_of(fence, struct etnaviv_fence, base);
1086 }
1087
etnaviv_fence_get_driver_name(struct dma_fence * fence)1088 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1089 {
1090 return "etnaviv";
1091 }
1092
etnaviv_fence_get_timeline_name(struct dma_fence * fence)1093 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1094 {
1095 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1096
1097 return dev_name(f->gpu->dev);
1098 }
1099
etnaviv_fence_signaled(struct dma_fence * fence)1100 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1101 {
1102 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1103
1104 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
1105 }
1106
etnaviv_fence_release(struct dma_fence * fence)1107 static void etnaviv_fence_release(struct dma_fence *fence)
1108 {
1109 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1110
1111 kfree_rcu(f, base.rcu);
1112 }
1113
1114 static const struct dma_fence_ops etnaviv_fence_ops = {
1115 .get_driver_name = etnaviv_fence_get_driver_name,
1116 .get_timeline_name = etnaviv_fence_get_timeline_name,
1117 .signaled = etnaviv_fence_signaled,
1118 .release = etnaviv_fence_release,
1119 };
1120
etnaviv_gpu_fence_alloc(struct etnaviv_gpu * gpu)1121 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1122 {
1123 struct etnaviv_fence *f;
1124
1125 /*
1126 * GPU lock must already be held, otherwise fence completion order might
1127 * not match the seqno order assigned here.
1128 */
1129 lockdep_assert_held(&gpu->lock);
1130
1131 f = kzalloc(sizeof(*f), GFP_KERNEL);
1132 if (!f)
1133 return NULL;
1134
1135 f->gpu = gpu;
1136
1137 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1138 gpu->fence_context, ++gpu->next_fence);
1139
1140 return &f->base;
1141 }
1142
1143 /* returns true if fence a comes after fence b */
fence_after(u32 a,u32 b)1144 static inline bool fence_after(u32 a, u32 b)
1145 {
1146 return (s32)(a - b) > 0;
1147 }
1148
1149 /*
1150 * event management:
1151 */
1152
event_alloc(struct etnaviv_gpu * gpu,unsigned nr_events,unsigned int * events)1153 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1154 unsigned int *events)
1155 {
1156 unsigned long timeout = msecs_to_jiffies(10 * 10000);
1157 unsigned i, acquired = 0, rpm_count = 0;
1158 int ret;
1159
1160 for (i = 0; i < nr_events; i++) {
1161 unsigned long remaining;
1162
1163 remaining = wait_for_completion_timeout(&gpu->event_free, timeout);
1164
1165 if (!remaining) {
1166 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1167 ret = -EBUSY;
1168 goto out;
1169 }
1170
1171 acquired++;
1172 timeout = remaining;
1173 }
1174
1175 spin_lock(&gpu->event_spinlock);
1176
1177 for (i = 0; i < nr_events; i++) {
1178 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1179
1180 events[i] = event;
1181 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1182 set_bit(event, gpu->event_bitmap);
1183 }
1184
1185 spin_unlock(&gpu->event_spinlock);
1186
1187 for (i = 0; i < nr_events; i++) {
1188 ret = pm_runtime_resume_and_get(gpu->dev);
1189 if (ret)
1190 goto out_rpm;
1191 rpm_count++;
1192 }
1193
1194 return 0;
1195
1196 out_rpm:
1197 for (i = 0; i < rpm_count; i++)
1198 pm_runtime_put_autosuspend(gpu->dev);
1199 out:
1200 for (i = 0; i < acquired; i++)
1201 complete(&gpu->event_free);
1202
1203 return ret;
1204 }
1205
event_free(struct etnaviv_gpu * gpu,unsigned int event)1206 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1207 {
1208 if (!test_bit(event, gpu->event_bitmap)) {
1209 dev_warn(gpu->dev, "event %u is already marked as free",
1210 event);
1211 } else {
1212 clear_bit(event, gpu->event_bitmap);
1213 complete(&gpu->event_free);
1214 }
1215
1216 pm_runtime_put_autosuspend(gpu->dev);
1217 }
1218
1219 /*
1220 * Cmdstream submission/retirement:
1221 */
etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu * gpu,u32 id,struct drm_etnaviv_timespec * timeout)1222 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1223 u32 id, struct drm_etnaviv_timespec *timeout)
1224 {
1225 struct dma_fence *fence;
1226 int ret;
1227
1228 /*
1229 * Look up the fence and take a reference. We might still find a fence
1230 * whose refcount has already dropped to zero. dma_fence_get_rcu
1231 * pretends we didn't find a fence in that case.
1232 */
1233 rcu_read_lock();
1234 fence = xa_load(&gpu->user_fences, id);
1235 if (fence)
1236 fence = dma_fence_get_rcu(fence);
1237 rcu_read_unlock();
1238
1239 if (!fence)
1240 return 0;
1241
1242 if (!timeout) {
1243 /* No timeout was requested: just test for completion */
1244 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1245 } else {
1246 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1247
1248 ret = dma_fence_wait_timeout(fence, true, remaining);
1249 if (ret == 0)
1250 ret = -ETIMEDOUT;
1251 else if (ret != -ERESTARTSYS)
1252 ret = 0;
1253
1254 }
1255
1256 dma_fence_put(fence);
1257 return ret;
1258 }
1259
1260 /*
1261 * Wait for an object to become inactive. This, on it's own, is not race
1262 * free: the object is moved by the scheduler off the active list, and
1263 * then the iova is put. Moreover, the object could be re-submitted just
1264 * after we notice that it's become inactive.
1265 *
1266 * Although the retirement happens under the gpu lock, we don't want to hold
1267 * that lock in this function while waiting.
1268 */
etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu * gpu,struct etnaviv_gem_object * etnaviv_obj,struct drm_etnaviv_timespec * timeout)1269 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1270 struct etnaviv_gem_object *etnaviv_obj,
1271 struct drm_etnaviv_timespec *timeout)
1272 {
1273 unsigned long remaining;
1274 long ret;
1275
1276 if (!timeout)
1277 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1278
1279 remaining = etnaviv_timeout_to_jiffies(timeout);
1280
1281 ret = wait_event_interruptible_timeout(gpu->fence_event,
1282 !is_active(etnaviv_obj),
1283 remaining);
1284 if (ret > 0)
1285 return 0;
1286 else if (ret == -ERESTARTSYS)
1287 return -ERESTARTSYS;
1288 else
1289 return -ETIMEDOUT;
1290 }
1291
sync_point_perfmon_sample(struct etnaviv_gpu * gpu,struct etnaviv_event * event,unsigned int flags)1292 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1293 struct etnaviv_event *event, unsigned int flags)
1294 {
1295 const struct etnaviv_gem_submit *submit = event->submit;
1296 unsigned int i;
1297
1298 for (i = 0; i < submit->nr_pmrs; i++) {
1299 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1300
1301 if (pmr->flags == flags)
1302 etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1303 }
1304 }
1305
sync_point_perfmon_sample_pre(struct etnaviv_gpu * gpu,struct etnaviv_event * event)1306 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1307 struct etnaviv_event *event)
1308 {
1309 u32 val;
1310
1311 /* disable clock gating */
1312 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
1313 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1314 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
1315
1316 /* enable debug register */
1317 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1318 val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1319 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1320
1321 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1322 }
1323
sync_point_perfmon_sample_post(struct etnaviv_gpu * gpu,struct etnaviv_event * event)1324 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1325 struct etnaviv_event *event)
1326 {
1327 const struct etnaviv_gem_submit *submit = event->submit;
1328 unsigned int i;
1329 u32 val;
1330
1331 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1332
1333 for (i = 0; i < submit->nr_pmrs; i++) {
1334 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1335
1336 *pmr->bo_vma = pmr->sequence;
1337 }
1338
1339 /* disable debug register */
1340 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1341 val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1342 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1343
1344 /* enable clock gating */
1345 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
1346 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1347 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
1348 }
1349
1350
1351 /* add bo's to gpu's ring, and kick gpu: */
etnaviv_gpu_submit(struct etnaviv_gem_submit * submit)1352 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1353 {
1354 struct etnaviv_gpu *gpu = submit->gpu;
1355 struct dma_fence *gpu_fence;
1356 unsigned int i, nr_events = 1, event[3];
1357 int ret;
1358
1359 /*
1360 * if there are performance monitor requests we need to have
1361 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1362 * requests.
1363 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1364 * and update the sequence number for userspace.
1365 */
1366 if (submit->nr_pmrs)
1367 nr_events = 3;
1368
1369 ret = event_alloc(gpu, nr_events, event);
1370 if (ret) {
1371 DRM_ERROR("no free events\n");
1372 pm_runtime_put_noidle(gpu->dev);
1373 return NULL;
1374 }
1375
1376 mutex_lock(&gpu->lock);
1377
1378 gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1379 if (!gpu_fence) {
1380 for (i = 0; i < nr_events; i++)
1381 event_free(gpu, event[i]);
1382
1383 goto out_unlock;
1384 }
1385
1386 if (gpu->state == ETNA_GPU_STATE_INITIALIZED)
1387 etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context);
1388
1389 if (submit->prev_mmu_context)
1390 etnaviv_iommu_context_put(submit->prev_mmu_context);
1391 submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context);
1392
1393 if (submit->nr_pmrs) {
1394 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1395 kref_get(&submit->refcount);
1396 gpu->event[event[1]].submit = submit;
1397 etnaviv_sync_point_queue(gpu, event[1]);
1398 }
1399
1400 gpu->event[event[0]].fence = gpu_fence;
1401 submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1402 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context,
1403 event[0], &submit->cmdbuf);
1404
1405 if (submit->nr_pmrs) {
1406 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1407 kref_get(&submit->refcount);
1408 gpu->event[event[2]].submit = submit;
1409 etnaviv_sync_point_queue(gpu, event[2]);
1410 }
1411
1412 out_unlock:
1413 mutex_unlock(&gpu->lock);
1414
1415 return gpu_fence;
1416 }
1417
sync_point_worker(struct work_struct * work)1418 static void sync_point_worker(struct work_struct *work)
1419 {
1420 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1421 sync_point_work);
1422 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1423 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1424
1425 event->sync_point(gpu, event);
1426 etnaviv_submit_put(event->submit);
1427 event_free(gpu, gpu->sync_point_event);
1428
1429 /* restart FE last to avoid GPU and IRQ racing against this worker */
1430 etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1431 }
1432
etnaviv_gpu_recover_hang(struct etnaviv_gem_submit * submit)1433 void etnaviv_gpu_recover_hang(struct etnaviv_gem_submit *submit)
1434 {
1435 struct etnaviv_gpu *gpu = submit->gpu;
1436 char *comm = NULL, *cmd = NULL;
1437 struct task_struct *task;
1438 unsigned int i;
1439
1440 dev_err(gpu->dev, "recover hung GPU!\n");
1441
1442 task = get_pid_task(submit->pid, PIDTYPE_PID);
1443 if (task) {
1444 comm = kstrdup(task->comm, GFP_KERNEL);
1445 cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
1446 put_task_struct(task);
1447 }
1448
1449 if (comm && cmd)
1450 dev_err(gpu->dev, "offending task: %s (%s)\n", comm, cmd);
1451
1452 kfree(cmd);
1453 kfree(comm);
1454
1455 if (pm_runtime_get_sync(gpu->dev) < 0)
1456 goto pm_put;
1457
1458 mutex_lock(&gpu->lock);
1459
1460 etnaviv_hw_reset(gpu);
1461
1462 /* complete all events, the GPU won't do it after the reset */
1463 spin_lock(&gpu->event_spinlock);
1464 for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS)
1465 event_free(gpu, i);
1466 spin_unlock(&gpu->event_spinlock);
1467
1468 etnaviv_gpu_hw_init(gpu);
1469
1470 mutex_unlock(&gpu->lock);
1471 pm_runtime_mark_last_busy(gpu->dev);
1472 pm_put:
1473 pm_runtime_put_autosuspend(gpu->dev);
1474 }
1475
dump_mmu_fault(struct etnaviv_gpu * gpu)1476 static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1477 {
1478 static const char *fault_reasons[] = {
1479 "slave not present",
1480 "page not present",
1481 "write violation",
1482 "out of bounds",
1483 "read security violation",
1484 "write security violation",
1485 };
1486
1487 u32 status_reg, status;
1488 int i;
1489
1490 if (gpu->sec_mode == ETNA_SEC_NONE)
1491 status_reg = VIVS_MMUv2_STATUS;
1492 else
1493 status_reg = VIVS_MMUv2_SEC_STATUS;
1494
1495 status = gpu_read(gpu, status_reg);
1496 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1497
1498 for (i = 0; i < 4; i++) {
1499 const char *reason = "unknown";
1500 u32 address_reg;
1501 u32 mmu_status;
1502
1503 mmu_status = (status >> (i * 4)) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK;
1504 if (!mmu_status)
1505 continue;
1506
1507 if ((mmu_status - 1) < ARRAY_SIZE(fault_reasons))
1508 reason = fault_reasons[mmu_status - 1];
1509
1510 if (gpu->sec_mode == ETNA_SEC_NONE)
1511 address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1512 else
1513 address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1514
1515 dev_err_ratelimited(gpu->dev,
1516 "MMU %d fault (%s) addr 0x%08x\n",
1517 i, reason, gpu_read(gpu, address_reg));
1518 }
1519 }
1520
irq_handler(int irq,void * data)1521 static irqreturn_t irq_handler(int irq, void *data)
1522 {
1523 struct etnaviv_gpu *gpu = data;
1524 irqreturn_t ret = IRQ_NONE;
1525
1526 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1527
1528 if (intr != 0) {
1529 int event;
1530
1531 pm_runtime_mark_last_busy(gpu->dev);
1532
1533 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1534
1535 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1536 dev_err(gpu->dev, "AXI bus error\n");
1537 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1538 }
1539
1540 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1541 dump_mmu_fault(gpu);
1542 gpu->state = ETNA_GPU_STATE_FAULT;
1543 drm_sched_fault(&gpu->sched);
1544 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1545 }
1546
1547 while ((event = ffs(intr)) != 0) {
1548 struct dma_fence *fence;
1549
1550 event -= 1;
1551
1552 intr &= ~(1 << event);
1553
1554 dev_dbg(gpu->dev, "event %u\n", event);
1555
1556 if (gpu->event[event].sync_point) {
1557 gpu->sync_point_event = event;
1558 queue_work(gpu->wq, &gpu->sync_point_work);
1559 }
1560
1561 fence = gpu->event[event].fence;
1562 if (!fence)
1563 continue;
1564
1565 gpu->event[event].fence = NULL;
1566
1567 /*
1568 * Events can be processed out of order. Eg,
1569 * - allocate and queue event 0
1570 * - allocate event 1
1571 * - event 0 completes, we process it
1572 * - allocate and queue event 0
1573 * - event 1 and event 0 complete
1574 * we can end up processing event 0 first, then 1.
1575 */
1576 if (fence_after(fence->seqno, gpu->completed_fence))
1577 gpu->completed_fence = fence->seqno;
1578 dma_fence_signal(fence);
1579
1580 event_free(gpu, event);
1581 }
1582
1583 ret = IRQ_HANDLED;
1584 }
1585
1586 return ret;
1587 }
1588
etnaviv_gpu_clk_enable(struct etnaviv_gpu * gpu)1589 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1590 {
1591 int ret;
1592
1593 ret = clk_prepare_enable(gpu->clk_reg);
1594 if (ret)
1595 return ret;
1596
1597 ret = clk_prepare_enable(gpu->clk_bus);
1598 if (ret)
1599 goto disable_clk_reg;
1600
1601 ret = clk_prepare_enable(gpu->clk_core);
1602 if (ret)
1603 goto disable_clk_bus;
1604
1605 ret = clk_prepare_enable(gpu->clk_shader);
1606 if (ret)
1607 goto disable_clk_core;
1608
1609 return 0;
1610
1611 disable_clk_core:
1612 clk_disable_unprepare(gpu->clk_core);
1613 disable_clk_bus:
1614 clk_disable_unprepare(gpu->clk_bus);
1615 disable_clk_reg:
1616 clk_disable_unprepare(gpu->clk_reg);
1617
1618 return ret;
1619 }
1620
etnaviv_gpu_clk_disable(struct etnaviv_gpu * gpu)1621 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1622 {
1623 clk_disable_unprepare(gpu->clk_shader);
1624 clk_disable_unprepare(gpu->clk_core);
1625 clk_disable_unprepare(gpu->clk_bus);
1626 clk_disable_unprepare(gpu->clk_reg);
1627
1628 return 0;
1629 }
1630
etnaviv_gpu_wait_idle(struct etnaviv_gpu * gpu,unsigned int timeout_ms)1631 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1632 {
1633 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1634
1635 do {
1636 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1637
1638 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1639 return 0;
1640
1641 if (time_is_before_jiffies(timeout)) {
1642 dev_warn(gpu->dev,
1643 "timed out waiting for idle: idle=0x%x\n",
1644 idle);
1645 return -ETIMEDOUT;
1646 }
1647
1648 udelay(5);
1649 } while (1);
1650 }
1651
etnaviv_gpu_hw_suspend(struct etnaviv_gpu * gpu)1652 static void etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1653 {
1654 if (gpu->state == ETNA_GPU_STATE_RUNNING) {
1655 /* Replace the last WAIT with END */
1656 mutex_lock(&gpu->lock);
1657 etnaviv_buffer_end(gpu);
1658 mutex_unlock(&gpu->lock);
1659
1660 /*
1661 * We know that only the FE is busy here, this should
1662 * happen quickly (as the WAIT is only 200 cycles). If
1663 * we fail, just warn and continue.
1664 */
1665 etnaviv_gpu_wait_idle(gpu, 100);
1666
1667 gpu->state = ETNA_GPU_STATE_INITIALIZED;
1668 }
1669
1670 gpu->exec_state = -1;
1671 }
1672
etnaviv_gpu_hw_resume(struct etnaviv_gpu * gpu)1673 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1674 {
1675 int ret;
1676
1677 ret = mutex_lock_killable(&gpu->lock);
1678 if (ret)
1679 return ret;
1680
1681 etnaviv_gpu_update_clock(gpu);
1682 etnaviv_gpu_hw_init(gpu);
1683
1684 mutex_unlock(&gpu->lock);
1685
1686 return 0;
1687 }
1688
1689 static int
etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device * cdev,unsigned long * state)1690 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1691 unsigned long *state)
1692 {
1693 *state = 6;
1694
1695 return 0;
1696 }
1697
1698 static int
etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device * cdev,unsigned long * state)1699 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1700 unsigned long *state)
1701 {
1702 struct etnaviv_gpu *gpu = cdev->devdata;
1703
1704 *state = gpu->freq_scale;
1705
1706 return 0;
1707 }
1708
1709 static int
etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device * cdev,unsigned long state)1710 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1711 unsigned long state)
1712 {
1713 struct etnaviv_gpu *gpu = cdev->devdata;
1714
1715 mutex_lock(&gpu->lock);
1716 gpu->freq_scale = state;
1717 if (!pm_runtime_suspended(gpu->dev))
1718 etnaviv_gpu_update_clock(gpu);
1719 mutex_unlock(&gpu->lock);
1720
1721 return 0;
1722 }
1723
1724 static const struct thermal_cooling_device_ops cooling_ops = {
1725 .get_max_state = etnaviv_gpu_cooling_get_max_state,
1726 .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1727 .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1728 };
1729
etnaviv_gpu_bind(struct device * dev,struct device * master,void * data)1730 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1731 void *data)
1732 {
1733 struct drm_device *drm = data;
1734 struct etnaviv_drm_private *priv = drm->dev_private;
1735 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1736 int ret;
1737
1738 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1739 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1740 (char *)dev_name(dev), gpu, &cooling_ops);
1741 if (IS_ERR(gpu->cooling))
1742 return PTR_ERR(gpu->cooling);
1743 }
1744
1745 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1746 if (!gpu->wq) {
1747 ret = -ENOMEM;
1748 goto out_thermal;
1749 }
1750
1751 ret = etnaviv_sched_init(gpu);
1752 if (ret)
1753 goto out_workqueue;
1754
1755 if (!IS_ENABLED(CONFIG_PM)) {
1756 ret = etnaviv_gpu_clk_enable(gpu);
1757 if (ret < 0)
1758 goto out_sched;
1759 }
1760
1761 gpu->drm = drm;
1762 gpu->fence_context = dma_fence_context_alloc(1);
1763 xa_init_flags(&gpu->user_fences, XA_FLAGS_ALLOC);
1764 spin_lock_init(&gpu->fence_spinlock);
1765
1766 INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1767 init_waitqueue_head(&gpu->fence_event);
1768
1769 priv->gpu[priv->num_gpus++] = gpu;
1770
1771 return 0;
1772
1773 out_sched:
1774 etnaviv_sched_fini(gpu);
1775
1776 out_workqueue:
1777 destroy_workqueue(gpu->wq);
1778
1779 out_thermal:
1780 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1781 thermal_cooling_device_unregister(gpu->cooling);
1782
1783 return ret;
1784 }
1785
etnaviv_gpu_unbind(struct device * dev,struct device * master,void * data)1786 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1787 void *data)
1788 {
1789 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1790
1791 DBG("%s", dev_name(gpu->dev));
1792
1793 destroy_workqueue(gpu->wq);
1794
1795 etnaviv_sched_fini(gpu);
1796
1797 if (IS_ENABLED(CONFIG_PM)) {
1798 pm_runtime_get_sync(gpu->dev);
1799 pm_runtime_put_sync_suspend(gpu->dev);
1800 } else {
1801 etnaviv_gpu_hw_suspend(gpu);
1802 etnaviv_gpu_clk_disable(gpu);
1803 }
1804
1805 if (gpu->mmu_context)
1806 etnaviv_iommu_context_put(gpu->mmu_context);
1807
1808 etnaviv_cmdbuf_free(&gpu->buffer);
1809 etnaviv_iommu_global_fini(gpu);
1810
1811 gpu->drm = NULL;
1812 xa_destroy(&gpu->user_fences);
1813
1814 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1815 thermal_cooling_device_unregister(gpu->cooling);
1816 gpu->cooling = NULL;
1817 }
1818
1819 static const struct component_ops gpu_ops = {
1820 .bind = etnaviv_gpu_bind,
1821 .unbind = etnaviv_gpu_unbind,
1822 };
1823
1824 static const struct of_device_id etnaviv_gpu_match[] = {
1825 {
1826 .compatible = "vivante,gc"
1827 },
1828 { /* sentinel */ }
1829 };
1830 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1831
etnaviv_gpu_platform_probe(struct platform_device * pdev)1832 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1833 {
1834 struct device *dev = &pdev->dev;
1835 struct etnaviv_gpu *gpu;
1836 int err;
1837
1838 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1839 if (!gpu)
1840 return -ENOMEM;
1841
1842 gpu->dev = &pdev->dev;
1843 mutex_init(&gpu->lock);
1844 mutex_init(&gpu->sched_lock);
1845
1846 /* Map registers: */
1847 gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
1848 if (IS_ERR(gpu->mmio))
1849 return PTR_ERR(gpu->mmio);
1850
1851 /* Get Interrupt: */
1852 gpu->irq = platform_get_irq(pdev, 0);
1853 if (gpu->irq < 0)
1854 return gpu->irq;
1855
1856 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1857 dev_name(gpu->dev), gpu);
1858 if (err) {
1859 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1860 return err;
1861 }
1862
1863 /* Get Clocks: */
1864 gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg");
1865 DBG("clk_reg: %p", gpu->clk_reg);
1866 if (IS_ERR(gpu->clk_reg))
1867 return PTR_ERR(gpu->clk_reg);
1868
1869 gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus");
1870 DBG("clk_bus: %p", gpu->clk_bus);
1871 if (IS_ERR(gpu->clk_bus))
1872 return PTR_ERR(gpu->clk_bus);
1873
1874 gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1875 DBG("clk_core: %p", gpu->clk_core);
1876 if (IS_ERR(gpu->clk_core))
1877 return PTR_ERR(gpu->clk_core);
1878 gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1879
1880 gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader");
1881 DBG("clk_shader: %p", gpu->clk_shader);
1882 if (IS_ERR(gpu->clk_shader))
1883 return PTR_ERR(gpu->clk_shader);
1884 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1885
1886 /* TODO: figure out max mapped size */
1887 dev_set_drvdata(dev, gpu);
1888
1889 /*
1890 * We treat the device as initially suspended. The runtime PM
1891 * autosuspend delay is rather arbitary: no measurements have
1892 * yet been performed to determine an appropriate value.
1893 */
1894 pm_runtime_use_autosuspend(gpu->dev);
1895 pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1896 pm_runtime_enable(gpu->dev);
1897
1898 err = component_add(&pdev->dev, &gpu_ops);
1899 if (err < 0) {
1900 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1901 return err;
1902 }
1903
1904 return 0;
1905 }
1906
etnaviv_gpu_platform_remove(struct platform_device * pdev)1907 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1908 {
1909 component_del(&pdev->dev, &gpu_ops);
1910 pm_runtime_disable(&pdev->dev);
1911 return 0;
1912 }
1913
etnaviv_gpu_rpm_suspend(struct device * dev)1914 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1915 {
1916 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1917 u32 idle, mask;
1918
1919 /* If there are any jobs in the HW queue, we're not idle */
1920 if (atomic_read(&gpu->sched.hw_rq_count))
1921 return -EBUSY;
1922
1923 /* Check whether the hardware (except FE and MC) is idle */
1924 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE |
1925 VIVS_HI_IDLE_STATE_MC);
1926 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1927 if (idle != mask) {
1928 dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n",
1929 idle);
1930 return -EBUSY;
1931 }
1932
1933 etnaviv_gpu_hw_suspend(gpu);
1934
1935 gpu->state = ETNA_GPU_STATE_IDENTIFIED;
1936
1937 return etnaviv_gpu_clk_disable(gpu);
1938 }
1939
etnaviv_gpu_rpm_resume(struct device * dev)1940 static int etnaviv_gpu_rpm_resume(struct device *dev)
1941 {
1942 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1943 int ret;
1944
1945 ret = etnaviv_gpu_clk_enable(gpu);
1946 if (ret)
1947 return ret;
1948
1949 /* Re-initialise the basic hardware state */
1950 if (gpu->state == ETNA_GPU_STATE_IDENTIFIED) {
1951 ret = etnaviv_gpu_hw_resume(gpu);
1952 if (ret) {
1953 etnaviv_gpu_clk_disable(gpu);
1954 return ret;
1955 }
1956 }
1957
1958 return 0;
1959 }
1960
1961 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1962 RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, NULL)
1963 };
1964
1965 struct platform_driver etnaviv_gpu_driver = {
1966 .driver = {
1967 .name = "etnaviv-gpu",
1968 .owner = THIS_MODULE,
1969 .pm = pm_ptr(&etnaviv_gpu_pm_ops),
1970 .of_match_table = etnaviv_gpu_match,
1971 },
1972 .probe = etnaviv_gpu_platform_probe,
1973 .remove = etnaviv_gpu_platform_remove,
1974 .id_table = gpu_ids,
1975 };
1976