1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Timesys Corporation
4 * Copyright 2015 General Electric Company
5 * Copyright 2012 Freescale Semiconductor, Inc.
6 */
7
8 #include <asm/arch/clock.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <linux/errno.h>
13 #include <asm/gpio.h>
14 #include <asm/mach-imx/mxc_i2c.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/video.h>
18 #include <mmc.h>
19 #include <fsl_esdhc.h>
20 #include <miiphy.h>
21 #include <net.h>
22 #include <netdev.h>
23 #include <asm/arch/mxc_hdmi.h>
24 #include <asm/arch/crm_regs.h>
25 #include <asm/io.h>
26 #include <asm/arch/sys_proto.h>
27 #include <i2c.h>
28 #include <input.h>
29 #include <pwm.h>
30 #include <stdlib.h>
31 #include "../common/ge_common.h"
32 #include "../common/vpd_reader.h"
33 #include "../../../drivers/net/e1000.h"
34 DECLARE_GLOBAL_DATA_PTR;
35
36 static int confidx = 3; /* Default to b850v3. */
37 static struct vpd_cache vpd;
38
39 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
40 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
41 PAD_CTL_HYS)
42
43 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
44 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
45 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46
47 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
48 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
49 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
50
51 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
52 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
53
54 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
55 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
56
57 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
58 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
59
60 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
61 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
62
63 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
64 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
65 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
66
67 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
68
dram_init(void)69 int dram_init(void)
70 {
71 gd->ram_size = imx_ddr_size();
72
73 return 0;
74 }
75
76 static iomux_v3_cfg_t const uart3_pads[] = {
77 MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
78 MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
79 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
80 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
81 };
82
83 static iomux_v3_cfg_t const uart4_pads[] = {
84 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
85 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
86 };
87
88 static iomux_v3_cfg_t const enet_pads[] = {
89 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
94 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
95 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
96 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
97 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
98 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
99 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
100 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
101 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
102 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
103 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
104 /* AR8033 PHY Reset */
105 MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
106 };
107
setup_iomux_enet(void)108 static void setup_iomux_enet(void)
109 {
110 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
111
112 /* Reset AR8033 PHY */
113 gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
114 mdelay(10);
115 gpio_set_value(IMX_GPIO_NR(1, 28), 1);
116 mdelay(1);
117 }
118
119 static iomux_v3_cfg_t const usdhc2_pads[] = {
120 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
127 };
128
129 static iomux_v3_cfg_t const usdhc3_pads[] = {
130 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 };
142
143 static iomux_v3_cfg_t const usdhc4_pads[] = {
144 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
149 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
150 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
155 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
156 };
157
158 static iomux_v3_cfg_t const ecspi1_pads[] = {
159 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
160 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
161 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
162 MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
163 };
164
165 static struct i2c_pads_info i2c_pad_info1 = {
166 .scl = {
167 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
168 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
169 .gp = IMX_GPIO_NR(5, 27)
170 },
171 .sda = {
172 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
173 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
174 .gp = IMX_GPIO_NR(5, 26)
175 }
176 };
177
178 static struct i2c_pads_info i2c_pad_info2 = {
179 .scl = {
180 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
181 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
182 .gp = IMX_GPIO_NR(4, 12)
183 },
184 .sda = {
185 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
186 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
187 .gp = IMX_GPIO_NR(4, 13)
188 }
189 };
190
191 static struct i2c_pads_info i2c_pad_info3 = {
192 .scl = {
193 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
194 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
195 .gp = IMX_GPIO_NR(1, 3)
196 },
197 .sda = {
198 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
199 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
200 .gp = IMX_GPIO_NR(1, 6)
201 }
202 };
203
204 #ifdef CONFIG_MXC_SPI
board_spi_cs_gpio(unsigned bus,unsigned cs)205 int board_spi_cs_gpio(unsigned bus, unsigned cs)
206 {
207 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
208 }
209
setup_spi(void)210 static void setup_spi(void)
211 {
212 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
213 }
214 #endif
215
216 static iomux_v3_cfg_t const pcie_pads[] = {
217 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
218 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
219 };
220
setup_pcie(void)221 static void setup_pcie(void)
222 {
223 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
224 }
225
setup_iomux_uart(void)226 static void setup_iomux_uart(void)
227 {
228 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
229 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
230 }
231
232 #ifdef CONFIG_FSL_ESDHC
233 struct fsl_esdhc_cfg usdhc_cfg[3] = {
234 {USDHC2_BASE_ADDR},
235 {USDHC3_BASE_ADDR},
236 {USDHC4_BASE_ADDR},
237 };
238
239 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
240 #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
241
board_mmc_getcd(struct mmc * mmc)242 int board_mmc_getcd(struct mmc *mmc)
243 {
244 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
245 int ret = 0;
246
247 switch (cfg->esdhc_base) {
248 case USDHC2_BASE_ADDR:
249 ret = !gpio_get_value(USDHC2_CD_GPIO);
250 break;
251 case USDHC3_BASE_ADDR:
252 ret = 1; /* eMMC is always present */
253 break;
254 case USDHC4_BASE_ADDR:
255 ret = !gpio_get_value(USDHC4_CD_GPIO);
256 break;
257 }
258
259 return ret;
260 }
261
board_mmc_init(bd_t * bis)262 int board_mmc_init(bd_t *bis)
263 {
264 int ret;
265 int i;
266
267 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
268 switch (i) {
269 case 0:
270 imx_iomux_v3_setup_multiple_pads(
271 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
272 gpio_direction_input(USDHC2_CD_GPIO);
273 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
274 break;
275 case 1:
276 imx_iomux_v3_setup_multiple_pads(
277 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
278 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
279 break;
280 case 2:
281 imx_iomux_v3_setup_multiple_pads(
282 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
283 gpio_direction_input(USDHC4_CD_GPIO);
284 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
285 break;
286 default:
287 printf("Warning: you configured more USDHC controllers\n"
288 "(%d) then supported by the board (%d)\n",
289 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
290 return -EINVAL;
291 }
292
293 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
294 if (ret)
295 return ret;
296 }
297
298 return 0;
299 }
300 #endif
301
mx6_rgmii_rework(struct phy_device * phydev)302 static int mx6_rgmii_rework(struct phy_device *phydev)
303 {
304 /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
305 /* set device address 0x7 */
306 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
307 /* offset 0x8016: CLK_25M Clock Select */
308 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
309 /* enable register write, no post increment, address 0x7 */
310 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
311 /* set to 125 MHz from local PLL source */
312 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
313
314 /* rgmii tx clock delay enable */
315 /* set debug port address: SerDes Test and System Mode Control */
316 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
317 /* enable rgmii tx clock delay */
318 /* set the reserved bits to avoid board specific voltage peak issue*/
319 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
320
321 return 0;
322 }
323
board_phy_config(struct phy_device * phydev)324 int board_phy_config(struct phy_device *phydev)
325 {
326 mx6_rgmii_rework(phydev);
327
328 if (phydev->drv->config)
329 phydev->drv->config(phydev);
330
331 return 0;
332 }
333
334 #if defined(CONFIG_VIDEO_IPUV3)
335 static iomux_v3_cfg_t const backlight_pads[] = {
336 /* Power for LVDS Display */
337 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
338 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
339 /* Backlight enable for LVDS display */
340 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
341 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
342 /* backlight PWM brightness control */
343 MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
344 };
345
do_enable_hdmi(struct display_info_t const * dev)346 static void do_enable_hdmi(struct display_info_t const *dev)
347 {
348 imx_enable_hdmi_phy();
349 }
350
board_cfb_skip(void)351 int board_cfb_skip(void)
352 {
353 gpio_direction_output(LVDS_POWER_GP, 1);
354
355 return 0;
356 }
357
is_b850v3(void)358 static int is_b850v3(void)
359 {
360 return confidx == 3;
361 }
362
detect_lcd(struct display_info_t const * dev)363 static int detect_lcd(struct display_info_t const *dev)
364 {
365 return !is_b850v3();
366 }
367
368 struct display_info_t const displays[] = {{
369 .bus = -1,
370 .addr = -1,
371 .pixfmt = IPU_PIX_FMT_RGB24,
372 .detect = detect_lcd,
373 .enable = NULL,
374 .mode = {
375 .name = "G121X1-L03",
376 .refresh = 60,
377 .xres = 1024,
378 .yres = 768,
379 .pixclock = 15385,
380 .left_margin = 20,
381 .right_margin = 300,
382 .upper_margin = 30,
383 .lower_margin = 8,
384 .hsync_len = 1,
385 .vsync_len = 1,
386 .sync = FB_SYNC_EXT,
387 .vmode = FB_VMODE_NONINTERLACED
388 } }, {
389 .bus = -1,
390 .addr = 3,
391 .pixfmt = IPU_PIX_FMT_RGB24,
392 .detect = detect_hdmi,
393 .enable = do_enable_hdmi,
394 .mode = {
395 .name = "HDMI",
396 .refresh = 60,
397 .xres = 1024,
398 .yres = 768,
399 .pixclock = 15385,
400 .left_margin = 220,
401 .right_margin = 40,
402 .upper_margin = 21,
403 .lower_margin = 7,
404 .hsync_len = 60,
405 .vsync_len = 10,
406 .sync = FB_SYNC_EXT,
407 .vmode = FB_VMODE_NONINTERLACED
408 } } };
409 size_t display_count = ARRAY_SIZE(displays);
410
enable_videopll(void)411 static void enable_videopll(void)
412 {
413 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
414 s32 timeout = 100000;
415
416 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
417
418 /* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2)
419 * |
420 * PLL5
421 * |
422 * CS2CDR[LDB_DI0_CLK_SEL]
423 * |
424 * +----> LDB_DI0_SERIAL_CLK_ROOT
425 * |
426 * +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz
427 */
428
429 clrsetbits_le32(&ccm->analog_pll_video,
430 BM_ANADIG_PLL_VIDEO_DIV_SELECT |
431 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
432 BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
433 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
434
435 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
436 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
437
438 clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
439
440 while (timeout--)
441 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
442 break;
443
444 if (timeout < 0)
445 printf("Warning: video pll lock timeout!\n");
446
447 clrsetbits_le32(&ccm->analog_pll_video,
448 BM_ANADIG_PLL_VIDEO_BYPASS,
449 BM_ANADIG_PLL_VIDEO_ENABLE);
450 }
451
setup_display_b850v3(void)452 static void setup_display_b850v3(void)
453 {
454 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
455 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
456
457 enable_videopll();
458
459 /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
460 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
461
462 imx_setup_hdmi();
463
464 /* Set LDB_DI0 as clock source for IPU_DI0 */
465 clrsetbits_le32(&mxc_ccm->chsccdr,
466 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
467 (CHSCCDR_CLK_SEL_LDB_DI0 <<
468 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
469
470 /* Turn on IPU LDB DI0 clocks */
471 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
472
473 enable_ipu_clock();
474
475 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
476 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
477 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
478 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
479 IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
480 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
481 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
482 IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
483 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
484 IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
485 &iomux->gpr[2]);
486
487 clrbits_le32(&iomux->gpr[3],
488 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
489 IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
490 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
491 }
492
setup_display_bx50v3(void)493 static void setup_display_bx50v3(void)
494 {
495 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
496 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
497
498 enable_videopll();
499
500 /* When a reset/reboot is performed the display power needs to be turned
501 * off for atleast 500ms. The boot time is ~300ms, we need to wait for
502 * an additional 200ms here. Unfortunately we use external PMIC for
503 * doing the reset, so can not differentiate between POR vs soft reset
504 */
505 mdelay(200);
506
507 /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
508 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
509
510 /* Set LDB_DI0 as clock source for IPU_DI0 */
511 clrsetbits_le32(&mxc_ccm->chsccdr,
512 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
513 (CHSCCDR_CLK_SEL_LDB_DI0 <<
514 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
515
516 /* Turn on IPU LDB DI0 clocks */
517 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
518
519 enable_ipu_clock();
520
521 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
522 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
523 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
524 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
525 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
526 &iomux->gpr[2]);
527
528 clrsetbits_le32(&iomux->gpr[3],
529 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
530 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
531 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
532
533 /* backlights off until needed */
534 imx_iomux_v3_setup_multiple_pads(backlight_pads,
535 ARRAY_SIZE(backlight_pads));
536 gpio_direction_input(LVDS_POWER_GP);
537 gpio_direction_input(LVDS_BACKLIGHT_GP);
538 }
539 #endif /* CONFIG_VIDEO_IPUV3 */
540
541 /*
542 * Do not overwrite the console
543 * Use always serial for U-Boot console
544 */
overwrite_console(void)545 int overwrite_console(void)
546 {
547 return 1;
548 }
549
550 #define VPD_TYPE_INVALID 0x00
551 #define VPD_BLOCK_NETWORK 0x20
552 #define VPD_BLOCK_HWID 0x44
553 #define VPD_PRODUCT_B850 1
554 #define VPD_PRODUCT_B650 2
555 #define VPD_PRODUCT_B450 3
556 #define VPD_HAS_MAC1 0x1
557 #define VPD_HAS_MAC2 0x2
558 #define VPD_MAC_ADDRESS_LENGTH 6
559
560 struct vpd_cache {
561 bool is_read;
562 u8 product_id;
563 u8 has;
564 unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
565 unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
566 };
567
568 /*
569 * Extracts MAC and product information from the VPD.
570 */
vpd_callback(struct vpd_cache * vpd,u8 id,u8 version,u8 type,size_t size,u8 const * data)571 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
572 size_t size, u8 const *data)
573 {
574 if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
575 size >= 1) {
576 vpd->product_id = data[0];
577 } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
578 type != VPD_TYPE_INVALID) {
579 if (size >= 6) {
580 vpd->has |= VPD_HAS_MAC1;
581 memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
582 }
583 if (size >= 12) {
584 vpd->has |= VPD_HAS_MAC2;
585 memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
586 }
587 }
588
589 return 0;
590 }
591
process_vpd(struct vpd_cache * vpd)592 static void process_vpd(struct vpd_cache *vpd)
593 {
594 int fec_index = -1;
595 int i210_index = -1;
596
597 if (!vpd->is_read) {
598 printf("VPD wasn't read");
599 return;
600 }
601
602 switch (vpd->product_id) {
603 case VPD_PRODUCT_B450:
604 env_set("confidx", "1");
605 i210_index = 0;
606 fec_index = 1;
607 break;
608 case VPD_PRODUCT_B650:
609 env_set("confidx", "2");
610 i210_index = 0;
611 fec_index = 1;
612 break;
613 case VPD_PRODUCT_B850:
614 env_set("confidx", "3");
615 i210_index = 1;
616 fec_index = 2;
617 break;
618 }
619
620 if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
621 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
622
623 if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
624 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
625 }
626
board_eth_init(bd_t * bis)627 int board_eth_init(bd_t *bis)
628 {
629 setup_iomux_enet();
630 setup_pcie();
631
632 e1000_initialize(bis);
633
634 return cpu_eth_init(bis);
635 }
636
637 static iomux_v3_cfg_t const misc_pads[] = {
638 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
639 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
640 MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
641 MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
642 MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
643 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
644 MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
645 MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL),
646 };
647 #define SUS_S3_OUT IMX_GPIO_NR(4, 11)
648 #define WIFI_EN IMX_GPIO_NR(6, 14)
649
board_early_init_f(void)650 int board_early_init_f(void)
651 {
652 imx_iomux_v3_setup_multiple_pads(misc_pads,
653 ARRAY_SIZE(misc_pads));
654
655 setup_iomux_uart();
656
657 #if defined(CONFIG_VIDEO_IPUV3)
658 /* Set LDB clock to Video PLL */
659 select_ldb_di_clock_source(MXC_PLL5_CLK);
660 #endif
661 return 0;
662 }
663
set_confidx(const struct vpd_cache * vpd)664 static void set_confidx(const struct vpd_cache* vpd)
665 {
666 switch (vpd->product_id) {
667 case VPD_PRODUCT_B450:
668 confidx = 1;
669 break;
670 case VPD_PRODUCT_B650:
671 confidx = 2;
672 break;
673 case VPD_PRODUCT_B850:
674 confidx = 3;
675 break;
676 }
677 }
678
board_init(void)679 int board_init(void)
680 {
681 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
682 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
683 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
684
685 if (!read_vpd(&vpd, vpd_callback)) {
686 vpd.is_read = true;
687 set_confidx(&vpd);
688 }
689
690 gpio_direction_output(SUS_S3_OUT, 1);
691 gpio_direction_output(WIFI_EN, 1);
692 #if defined(CONFIG_VIDEO_IPUV3)
693 if (is_b850v3())
694 setup_display_b850v3();
695 else
696 setup_display_bx50v3();
697 #endif
698 /* address of boot parameters */
699 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
700
701 #ifdef CONFIG_MXC_SPI
702 setup_spi();
703 #endif
704 return 0;
705 }
706
707 #ifdef CONFIG_CMD_BMODE
708 static const struct boot_mode board_boot_modes[] = {
709 /* 4 bit bus width */
710 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
711 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
712 {NULL, 0},
713 };
714 #endif
715
pmic_init(void)716 void pmic_init(void)
717 {
718 #define I2C_PMIC 0x2
719 #define DA9063_I2C_ADDR 0x58
720 #define DA9063_REG_BCORE2_CFG 0x9D
721 #define DA9063_REG_BCORE1_CFG 0x9E
722 #define DA9063_REG_BPRO_CFG 0x9F
723 #define DA9063_REG_BIO_CFG 0xA0
724 #define DA9063_REG_BMEM_CFG 0xA1
725 #define DA9063_REG_BPERI_CFG 0xA2
726 #define DA9063_BUCK_MODE_MASK 0xC0
727 #define DA9063_BUCK_MODE_MANUAL 0x00
728 #define DA9063_BUCK_MODE_SLEEP 0x40
729 #define DA9063_BUCK_MODE_SYNC 0x80
730 #define DA9063_BUCK_MODE_AUTO 0xC0
731
732 uchar val;
733
734 i2c_set_bus_num(I2C_PMIC);
735
736 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
737 val &= ~DA9063_BUCK_MODE_MASK;
738 val |= DA9063_BUCK_MODE_SYNC;
739 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
740
741 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
742 val &= ~DA9063_BUCK_MODE_MASK;
743 val |= DA9063_BUCK_MODE_SYNC;
744 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
745
746 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
747 val &= ~DA9063_BUCK_MODE_MASK;
748 val |= DA9063_BUCK_MODE_SYNC;
749 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
750
751 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
752 val &= ~DA9063_BUCK_MODE_MASK;
753 val |= DA9063_BUCK_MODE_SYNC;
754 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
755
756 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
757 val &= ~DA9063_BUCK_MODE_MASK;
758 val |= DA9063_BUCK_MODE_SYNC;
759 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
760
761 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
762 val &= ~DA9063_BUCK_MODE_MASK;
763 val |= DA9063_BUCK_MODE_SYNC;
764 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
765 }
766
board_late_init(void)767 int board_late_init(void)
768 {
769 process_vpd(&vpd);
770
771 #ifdef CONFIG_CMD_BMODE
772 add_board_boot_modes(board_boot_modes);
773 #endif
774
775 if (is_b850v3())
776 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
777 else
778 env_set("videoargs", "video=LVDS-1:1024x768@65");
779
780 /* board specific pmic init */
781 pmic_init();
782
783 check_time();
784
785 return 0;
786 }
787
788 /*
789 * Removes the 'eth[0-9]*addr' environment variable with the given index
790 *
791 * @param index [in] the index of the eth_device whose variable is to be removed
792 */
remove_ethaddr_env_var(int index)793 static void remove_ethaddr_env_var(int index)
794 {
795 char env_var_name[9];
796
797 sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
798 env_set(env_var_name, NULL);
799 }
800
last_stage_init(void)801 int last_stage_init(void)
802 {
803 int i;
804
805 /*
806 * Remove first three ethaddr which may have been created by
807 * function process_vpd().
808 */
809 for (i = 0; i < 3; ++i)
810 remove_ethaddr_env_var(i);
811
812 return 0;
813 }
814
checkboard(void)815 int checkboard(void)
816 {
817 printf("BOARD: %s\n", CONFIG_BOARD_NAME);
818 return 0;
819 }
820
do_backlight_enable(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])821 static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
822 {
823 #ifdef CONFIG_VIDEO_IPUV3
824 /* We need at least 200ms between power on and backlight on
825 * as per specifications from CHI MEI */
826 mdelay(250);
827
828 /* enable backlight PWM 1 */
829 pwm_init(0, 0, 0);
830
831 /* duty cycle 5000000ns, period: 5000000ns */
832 pwm_config(0, 5000000, 5000000);
833
834 /* Backlight Power */
835 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
836
837 pwm_enable(0);
838 #endif
839
840 return 0;
841 }
842
843 U_BOOT_CMD(
844 bx50_backlight_enable, 1, 1, do_backlight_enable,
845 "enable Bx50 backlight",
846 ""
847 );
848