xref: /openbmc/u-boot/arch/arm/mach-imx/imx8m/soc.c (revision 7e40d0a3)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2017 NXP
4  *
5  * Peng Fan <peng.fan@nxp.com>
6  */
7 
8 #include <common.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/mach-imx/hab.h>
14 #include <asm/mach-imx/boot_mode.h>
15 #include <asm/mach-imx/syscounter.h>
16 #include <asm/armv8/mmu.h>
17 #include <errno.h>
18 #include <fdt_support.h>
19 #include <fsl_wdog.h>
20 #include <imx_sip.h>
21 
22 DECLARE_GLOBAL_DATA_PTR;
23 
24 #if defined(CONFIG_SECURE_BOOT)
25 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
26 	.bank = 1,
27 	.word = 3,
28 };
29 #endif
30 
timer_init(void)31 int timer_init(void)
32 {
33 #ifdef CONFIG_SPL_BUILD
34 	struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
35 	unsigned long freq = readl(&sctr->cntfid0);
36 
37 	/* Update with accurate clock frequency */
38 	asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
39 
40 	clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
41 			SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
42 #endif
43 
44 	gd->arch.tbl = 0;
45 	gd->arch.tbu = 0;
46 
47 	return 0;
48 }
49 
enable_tzc380(void)50 void enable_tzc380(void)
51 {
52 	struct iomuxc_gpr_base_regs *gpr =
53 		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
54 
55 	/* Enable TZASC and lock setting */
56 	setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
57 	setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
58 }
59 
set_wdog_reset(struct wdog_regs * wdog)60 void set_wdog_reset(struct wdog_regs *wdog)
61 {
62 	/*
63 	 * Output WDOG_B signal to reset external pmic or POR_B decided by
64 	 * the board design. Without external reset, the peripherals/DDR/
65 	 * PMIC are not reset, that may cause system working abnormal.
66 	 * WDZST bit is write-once only bit. Align this bit in kernel,
67 	 * otherwise kernel code will have no chance to set this bit.
68 	 */
69 	setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
70 }
71 
72 static struct mm_region imx8m_mem_map[] = {
73 	{
74 		/* ROM */
75 		.virt = 0x0UL,
76 		.phys = 0x0UL,
77 		.size = 0x100000UL,
78 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
79 			 PTE_BLOCK_OUTER_SHARE
80 	}, {
81 		/* CAAM */
82 		.virt = 0x100000UL,
83 		.phys = 0x100000UL,
84 		.size = 0x8000UL,
85 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
86 			 PTE_BLOCK_NON_SHARE |
87 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
88 	}, {
89 		/* TCM */
90 		.virt = 0x7C0000UL,
91 		.phys = 0x7C0000UL,
92 		.size = 0x80000UL,
93 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
94 			 PTE_BLOCK_NON_SHARE |
95 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
96 	}, {
97 		/* OCRAM */
98 		.virt = 0x900000UL,
99 		.phys = 0x900000UL,
100 		.size = 0x200000UL,
101 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
102 			 PTE_BLOCK_OUTER_SHARE
103 	}, {
104 		/* AIPS */
105 		.virt = 0xB00000UL,
106 		.phys = 0xB00000UL,
107 		.size = 0x3f500000UL,
108 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
109 			 PTE_BLOCK_NON_SHARE |
110 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
111 	}, {
112 		/* DRAM1 */
113 		.virt = 0x40000000UL,
114 		.phys = 0x40000000UL,
115 		.size = 0xC0000000UL,
116 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
117 			 PTE_BLOCK_OUTER_SHARE
118 	}, {
119 		/* DRAM2 */
120 		.virt = 0x100000000UL,
121 		.phys = 0x100000000UL,
122 		.size = 0x040000000UL,
123 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
124 			 PTE_BLOCK_OUTER_SHARE
125 	}, {
126 		/* List terminator */
127 		0,
128 	}
129 };
130 
131 struct mm_region *mem_map = imx8m_mem_map;
132 
get_cpu_rev(void)133 u32 get_cpu_rev(void)
134 {
135 	struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
136 	u32 reg = readl(&ana_pll->digprog);
137 	u32 type = (reg >> 16) & 0xff;
138 	u32 rom_version;
139 
140 	reg &= 0xff;
141 
142 	if (reg == CHIP_REV_1_0) {
143 		/*
144 		 * For B0 chip, the DIGPROG is not updated, still TO1.0.
145 		 * we have to check ROM version further
146 		 */
147 		rom_version = readl((void __iomem *)ROM_VERSION_A0);
148 		if (rom_version != CHIP_REV_1_0) {
149 			rom_version = readl((void __iomem *)ROM_VERSION_B0);
150 			if (rom_version >= CHIP_REV_2_0)
151 				reg = CHIP_REV_2_0;
152 		}
153 	}
154 
155 	return (type << 12) | reg;
156 }
157 
imx_set_wdog_powerdown(bool enable)158 static void imx_set_wdog_powerdown(bool enable)
159 {
160 	struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
161 	struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
162 	struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
163 
164 	/* Write to the PDE (Power Down Enable) bit */
165 	writew(enable, &wdog1->wmcr);
166 	writew(enable, &wdog2->wmcr);
167 	writew(enable, &wdog3->wmcr);
168 }
169 
arch_cpu_init(void)170 int arch_cpu_init(void)
171 {
172 	/*
173 	 * Init timer at very early state, because sscg pll setting
174 	 * will use it
175 	 */
176 	timer_init();
177 
178 	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
179 		clock_init();
180 		imx_set_wdog_powerdown(false);
181 	}
182 
183 	return 0;
184 }
185 
is_usb_boot(void)186 bool is_usb_boot(void)
187 {
188 	return get_boot_device() == USB_BOOT;
189 }
190 
191 #ifdef CONFIG_OF_SYSTEM_SETUP
ft_system_setup(void * blob,bd_t * bd)192 int ft_system_setup(void *blob, bd_t *bd)
193 {
194 	int i = 0;
195 	int rc;
196 	int nodeoff;
197 
198 	/* Disable the CPU idle for A0 chip since the HW does not support it */
199 	if (is_soc_rev(CHIP_REV_1_0)) {
200 		static const char * const nodes_path[] = {
201 			"/cpus/cpu@0",
202 			"/cpus/cpu@1",
203 			"/cpus/cpu@2",
204 			"/cpus/cpu@3",
205 		};
206 
207 		for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
208 			nodeoff = fdt_path_offset(blob, nodes_path[i]);
209 			if (nodeoff < 0)
210 				continue; /* Not found, skip it */
211 
212 			printf("Found %s node\n", nodes_path[i]);
213 
214 			rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
215 			if (rc) {
216 				printf("Unable to update property %s:%s, err=%s\n",
217 				       nodes_path[i], "status", fdt_strerror(rc));
218 				return rc;
219 			}
220 
221 			printf("Remove %s:%s\n", nodes_path[i],
222 			       "cpu-idle-states");
223 		}
224 	}
225 
226 	return 0;
227 }
228 #endif
229 
reset_cpu(ulong addr)230 void reset_cpu(ulong addr)
231 {
232 	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
233 
234 	/* Clear WDA to trigger WDOG_B immediately */
235 	writew((WCR_WDE | WCR_SRS), &wdog->wcr);
236 
237 	while (1) {
238 		/*
239 		 * spin for .5 seconds before reset
240 		 */
241 	}
242 }
243