xref: /openbmc/qemu/include/hw/misc/aspeed_sbc.h (revision 54ee5641)
1 /*
2  * ASPEED Secure Boot Controller
3  *
4  * Copyright (C) 2021-2022 IBM Corp.
5  *
6  * SPDX-License-Identifier: GPL-2.0-or-later
7  */
8 
9 #ifndef ASPEED_SBC_H
10 #define ASPEED_SBC_H
11 
12 #include "hw/sysbus.h"
13 
14 #define TYPE_ASPEED_SBC "aspeed.sbc"
15 #define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600"
16 OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPEED_SBC)
17 
18 #define ASPEED_SBC_NR_REGS (0x93c >> 2)
19 
20 #define QSR_AES                     BIT(27)
21 #define QSR_RSA1024                 (0x0 << 12)
22 #define QSR_RSA2048                 (0x1 << 12)
23 #define QSR_RSA3072                 (0x2 << 12)
24 #define QSR_RSA4096                 (0x3 << 12)
25 #define QSR_SHA224                  (0x0 << 10)
26 #define QSR_SHA256                  (0x1 << 10)
27 #define QSR_SHA384                  (0x2 << 10)
28 #define QSR_SHA512                  (0x3 << 10)
29 
30 struct AspeedSBCState {
31     SysBusDevice parent;
32 
33     bool emmc_abr;
34     uint32_t signing_settings;
35 
36     MemoryRegion iomem;
37 
38     uint32_t regs[ASPEED_SBC_NR_REGS];
39 };
40 
41 struct AspeedSBCClass {
42     SysBusDeviceClass parent_class;
43 };
44 
45 #endif /* ASPEED_SBC_H */
46