1 /*
2 * Copyright 2022 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 #include "priv.h"
23
24 static void
gp102_flcn_pio_emem_rd(struct nvkm_falcon * falcon,u8 port,const u8 * img,int len)25 gp102_flcn_pio_emem_rd(struct nvkm_falcon *falcon, u8 port, const u8 *img, int len)
26 {
27 while (len >= 4) {
28 *(u32 *)img = nvkm_falcon_rd32(falcon, 0xac4 + (port * 8));
29 img += 4;
30 len -= 4;
31 }
32 }
33
34 static void
gp102_flcn_pio_emem_rd_init(struct nvkm_falcon * falcon,u8 port,u32 dmem_base)35 gp102_flcn_pio_emem_rd_init(struct nvkm_falcon *falcon, u8 port, u32 dmem_base)
36 {
37 nvkm_falcon_wr32(falcon, 0xac0 + (port * 8), BIT(25) | dmem_base);
38 }
39
40 static void
gp102_flcn_pio_emem_wr(struct nvkm_falcon * falcon,u8 port,const u8 * img,int len,u16 tag)41 gp102_flcn_pio_emem_wr(struct nvkm_falcon *falcon, u8 port, const u8 *img, int len, u16 tag)
42 {
43 while (len >= 4) {
44 nvkm_falcon_wr32(falcon, 0xac4 + (port * 8), *(u32 *)img);
45 img += 4;
46 len -= 4;
47 }
48 }
49
50 static void
gp102_flcn_pio_emem_wr_init(struct nvkm_falcon * falcon,u8 port,bool sec,u32 emem_base)51 gp102_flcn_pio_emem_wr_init(struct nvkm_falcon *falcon, u8 port, bool sec, u32 emem_base)
52 {
53 nvkm_falcon_wr32(falcon, 0xac0 + (port * 8), BIT(24) | emem_base);
54 }
55
56 const struct nvkm_falcon_func_pio
57 gp102_flcn_emem_pio = {
58 .min = 4,
59 .max = 0x100,
60 .wr_init = gp102_flcn_pio_emem_wr_init,
61 .wr = gp102_flcn_pio_emem_wr,
62 .rd_init = gp102_flcn_pio_emem_rd_init,
63 .rd = gp102_flcn_pio_emem_rd,
64 };
65
66 int
gp102_flcn_reset_eng(struct nvkm_falcon * falcon)67 gp102_flcn_reset_eng(struct nvkm_falcon *falcon)
68 {
69 int ret;
70
71 if (falcon->func->reset_prep) {
72 ret = falcon->func->reset_prep(falcon);
73 if (ret)
74 return ret;
75 }
76
77 nvkm_falcon_mask(falcon, 0x3c0, 0x00000001, 0x00000001);
78 udelay(10);
79 nvkm_falcon_mask(falcon, 0x3c0, 0x00000001, 0x00000000);
80
81 return falcon->func->reset_wait_mem_scrubbing(falcon);
82 }
83