1 /**
2 * QEMU RTL8139 emulation
3 *
4 * Copyright (c) 2006 Igor Kovalenko
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23
24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
26 *
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
29 *
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for
47 * Darwin)
48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
49 */
50
51 #include "qemu/osdep.h"
52 #include <zlib.h> /* for crc32 */
53
54 #include "hw/pci/pci_device.h"
55 #include "hw/qdev-properties.h"
56 #include "migration/vmstate.h"
57 #include "system/dma.h"
58 #include "qemu/module.h"
59 #include "qemu/timer.h"
60 #include "qemu/bswap.h"
61 #include "net/net.h"
62 #include "net/eth.h"
63 #include "system/system.h"
64 #include "qom/object.h"
65
66 /* debug RTL8139 card */
67 //#define DEBUG_RTL8139 1
68
69 #define PCI_PERIOD 30 /* 30 ns period = 33.333333 Mhz frequency */
70
71 #define SET_MASKED(input, mask, curr) \
72 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
73
74 /* arg % size for size which is a power of 2 */
75 #define MOD2(input, size) \
76 ( ( input ) & ( size - 1 ) )
77
78 #define ETHER_TYPE_LEN 2
79
80 #define VLAN_TCI_LEN 2
81 #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
82
83 #if defined (DEBUG_RTL8139)
84 # define DPRINTF(fmt, ...) \
85 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
86 #else
DPRINTF(const char * fmt,...)87 static inline G_GNUC_PRINTF(1, 2) int DPRINTF(const char *fmt, ...)
88 {
89 return 0;
90 }
91 #endif
92
93 #define TYPE_RTL8139 "rtl8139"
94
95 OBJECT_DECLARE_SIMPLE_TYPE(RTL8139State, RTL8139)
96
97 /* Symbolic offsets to registers. */
98 enum RTL8139_registers {
99 MAC0 = 0, /* Ethernet hardware address. */
100 MAR0 = 8, /* Multicast filter. */
101 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
102 /* Dump Tally Counter control register(64bit). C+ mode only */
103 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
104 RxBuf = 0x30,
105 ChipCmd = 0x37,
106 RxBufPtr = 0x38,
107 RxBufAddr = 0x3A,
108 IntrMask = 0x3C,
109 IntrStatus = 0x3E,
110 TxConfig = 0x40,
111 RxConfig = 0x44,
112 Timer = 0x48, /* A general-purpose counter. */
113 RxMissed = 0x4C, /* 24 bits valid, write clears. */
114 Cfg9346 = 0x50,
115 Config0 = 0x51,
116 Config1 = 0x52,
117 FlashReg = 0x54,
118 MediaStatus = 0x58,
119 Config3 = 0x59,
120 Config4 = 0x5A, /* absent on RTL-8139A */
121 HltClk = 0x5B,
122 MultiIntr = 0x5C,
123 PCIRevisionID = 0x5E,
124 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
125 BasicModeCtrl = 0x62,
126 BasicModeStatus = 0x64,
127 NWayAdvert = 0x66,
128 NWayLPAR = 0x68,
129 NWayExpansion = 0x6A,
130 /* Undocumented registers, but required for proper operation. */
131 FIFOTMS = 0x70, /* FIFO Control and test. */
132 CSCR = 0x74, /* Chip Status and Configuration Register. */
133 PARA78 = 0x78,
134 PARA7c = 0x7c, /* Magic transceiver parameter register. */
135 Config5 = 0xD8, /* absent on RTL-8139A */
136 /* C+ mode */
137 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
138 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
139 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
140 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
141 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
142 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
143 TxThresh = 0xEC, /* Early Tx threshold */
144 };
145
146 enum ClearBitMasks {
147 MultiIntrClear = 0xF000,
148 ChipCmdClear = 0xE2,
149 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
150 };
151
152 enum ChipCmdBits {
153 CmdReset = 0x10,
154 CmdRxEnb = 0x08,
155 CmdTxEnb = 0x04,
156 RxBufEmpty = 0x01,
157 };
158
159 /* C+ mode */
160 enum CplusCmdBits {
161 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
162 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
163 CPlusRxEnb = 0x0002,
164 CPlusTxEnb = 0x0001,
165 };
166
167 /* Interrupt register bits, using my own meaningful names. */
168 enum IntrStatusBits {
169 PCIErr = 0x8000,
170 PCSTimeout = 0x4000,
171 RxFIFOOver = 0x40,
172 RxUnderrun = 0x20, /* Packet Underrun / Link Change */
173 RxOverflow = 0x10,
174 TxErr = 0x08,
175 TxOK = 0x04,
176 RxErr = 0x02,
177 RxOK = 0x01,
178
179 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
180 };
181
182 enum TxStatusBits {
183 TxHostOwns = 0x2000,
184 TxUnderrun = 0x4000,
185 TxStatOK = 0x8000,
186 TxOutOfWindow = 0x20000000,
187 TxAborted = 0x40000000,
188 TxCarrierLost = 0x80000000,
189 };
190 enum RxStatusBits {
191 RxMulticast = 0x8000,
192 RxPhysical = 0x4000,
193 RxBroadcast = 0x2000,
194 RxBadSymbol = 0x0020,
195 RxRunt = 0x0010,
196 RxTooLong = 0x0008,
197 RxCRCErr = 0x0004,
198 RxBadAlign = 0x0002,
199 RxStatusOK = 0x0001,
200 };
201
202 /* Bits in RxConfig. */
203 enum rx_mode_bits {
204 AcceptErr = 0x20,
205 AcceptRunt = 0x10,
206 AcceptBroadcast = 0x08,
207 AcceptMulticast = 0x04,
208 AcceptMyPhys = 0x02,
209 AcceptAllPhys = 0x01,
210 };
211
212 /* Bits in TxConfig. */
213 enum tx_config_bits {
214
215 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
216 TxIFGShift = 24,
217 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
218 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
219 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
220 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
221
222 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
223 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
224 TxClearAbt = (1 << 0), /* Clear abort (WO) */
225 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
226 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
227
228 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
229 };
230
231
232 /* Transmit Status of All Descriptors (TSAD) Register */
233 enum TSAD_bits {
234 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
235 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
236 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
237 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
238 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
239 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
240 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
241 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
242 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
243 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
244 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
245 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
246 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
247 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
248 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
249 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
250 };
251
252
253 /* Bits in Config1 */
254 enum Config1Bits {
255 Cfg1_PM_Enable = 0x01,
256 Cfg1_VPD_Enable = 0x02,
257 Cfg1_PIO = 0x04,
258 Cfg1_MMIO = 0x08,
259 LWAKE = 0x10, /* not on 8139, 8139A */
260 Cfg1_Driver_Load = 0x20,
261 Cfg1_LED0 = 0x40,
262 Cfg1_LED1 = 0x80,
263 SLEEP = (1 << 1), /* only on 8139, 8139A */
264 PWRDN = (1 << 0), /* only on 8139, 8139A */
265 };
266
267 /* Bits in Config3 */
268 enum Config3Bits {
269 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
270 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
271 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
272 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
273 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
274 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
275 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
276 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
277 };
278
279 /* Bits in Config4 */
280 enum Config4Bits {
281 LWPTN = (1 << 2), /* not on 8139, 8139A */
282 };
283
284 /* Bits in Config5 */
285 enum Config5Bits {
286 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
287 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
288 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
289 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
290 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
291 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
292 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
293 };
294
295 enum RxConfigBits {
296 /* rx fifo threshold */
297 RxCfgFIFOShift = 13,
298 RxCfgFIFONone = (7 << RxCfgFIFOShift),
299
300 /* Max DMA burst */
301 RxCfgDMAShift = 8,
302 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
303
304 /* rx ring buffer length */
305 RxCfgRcv8K = 0,
306 RxCfgRcv16K = (1 << 11),
307 RxCfgRcv32K = (1 << 12),
308 RxCfgRcv64K = (1 << 11) | (1 << 12),
309
310 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
311 RxNoWrap = (1 << 7),
312 };
313
314 /* Twister tuning parameters from RealTek.
315 Completely undocumented, but required to tune bad links on some boards. */
316 /*
317 enum CSCRBits {
318 CSCR_LinkOKBit = 0x0400,
319 CSCR_LinkChangeBit = 0x0800,
320 CSCR_LinkStatusBits = 0x0f000,
321 CSCR_LinkDownOffCmd = 0x003c0,
322 CSCR_LinkDownCmd = 0x0f3c0,
323 */
324 enum CSCRBits {
325 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
326 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
327 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
328 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
329 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
330 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
331 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
332 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
333 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
334 };
335
336 enum Cfg9346Bits {
337 Cfg9346_Normal = 0x00,
338 Cfg9346_Autoload = 0x40,
339 Cfg9346_Programming = 0x80,
340 Cfg9346_ConfigWrite = 0xC0,
341 };
342
343 typedef enum {
344 CH_8139 = 0,
345 CH_8139_K,
346 CH_8139A,
347 CH_8139A_G,
348 CH_8139B,
349 CH_8130,
350 CH_8139C,
351 CH_8100,
352 CH_8100B_8139D,
353 CH_8101,
354 } chip_t;
355
356 enum chip_flags {
357 HasHltClk = (1 << 0),
358 HasLWake = (1 << 1),
359 };
360
361 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
362 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
363 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
364
365 #define RTL8139_PCI_REVID_8139 0x10
366 #define RTL8139_PCI_REVID_8139CPLUS 0x20
367
368 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
369
370 /* Size is 64 * 16bit words */
371 #define EEPROM_9346_ADDR_BITS 6
372 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
373 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
374
375 enum Chip9346Operation
376 {
377 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
378 Chip9346_op_read = 0x80, /* 10 AAAAAA */
379 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
380 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
381 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
382 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
383 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
384 };
385
386 enum Chip9346Mode
387 {
388 Chip9346_none = 0,
389 Chip9346_enter_command_mode,
390 Chip9346_read_command,
391 Chip9346_data_read, /* from output register */
392 Chip9346_data_write, /* to input register, then to contents at specified address */
393 Chip9346_data_write_all, /* to input register, then filling contents */
394 };
395
396 typedef struct EEprom9346
397 {
398 uint16_t contents[EEPROM_9346_SIZE];
399 int mode;
400 uint32_t tick;
401 uint8_t address;
402 uint16_t input;
403 uint16_t output;
404
405 uint8_t eecs;
406 uint8_t eesk;
407 uint8_t eedi;
408 uint8_t eedo;
409 } EEprom9346;
410
411 typedef struct RTL8139TallyCounters
412 {
413 /* Tally counters */
414 uint64_t TxOk;
415 uint64_t RxOk;
416 uint64_t TxERR;
417 uint32_t RxERR;
418 uint16_t MissPkt;
419 uint16_t FAE;
420 uint32_t Tx1Col;
421 uint32_t TxMCol;
422 uint64_t RxOkPhy;
423 uint64_t RxOkBrd;
424 uint32_t RxOkMul;
425 uint16_t TxAbt;
426 uint16_t TxUndrn;
427 } RTL8139TallyCounters;
428
429 /* Clears all tally counters */
430 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
431
432 struct RTL8139State {
433 /*< private >*/
434 PCIDevice parent_obj;
435 /*< public >*/
436
437 uint8_t phys[8]; /* mac address */
438 uint8_t mult[8]; /* multicast mask array */
439
440 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
441 uint32_t TxAddr[4]; /* TxAddr0 */
442 uint32_t RxBuf; /* Receive buffer */
443 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
444 uint32_t RxBufPtr;
445 uint32_t RxBufAddr;
446
447 uint16_t IntrStatus;
448 uint16_t IntrMask;
449
450 uint32_t TxConfig;
451 uint32_t RxConfig;
452 uint32_t RxMissed;
453
454 uint16_t CSCR;
455
456 uint8_t Cfg9346;
457 uint8_t Config0;
458 uint8_t Config1;
459 uint8_t Config3;
460 uint8_t Config4;
461 uint8_t Config5;
462
463 uint8_t clock_enabled;
464 uint8_t bChipCmdState;
465
466 uint16_t MultiIntr;
467
468 uint16_t BasicModeCtrl;
469 uint16_t BasicModeStatus;
470 uint16_t NWayAdvert;
471 uint16_t NWayLPAR;
472 uint16_t NWayExpansion;
473
474 uint16_t CpCmd;
475 uint8_t TxThresh;
476
477 NICState *nic;
478 NICConf conf;
479
480 /* C ring mode */
481 uint32_t currTxDesc;
482
483 /* C+ mode */
484 uint32_t cplus_enabled;
485
486 uint32_t currCPlusRxDesc;
487 uint32_t currCPlusTxDesc;
488
489 uint32_t RxRingAddrLO;
490 uint32_t RxRingAddrHI;
491
492 EEprom9346 eeprom;
493
494 uint32_t TCTR;
495 uint32_t TimerInt;
496 int64_t TCTR_base;
497
498 /* Tally counters */
499 RTL8139TallyCounters tally_counters;
500
501 /* Non-persistent data */
502 uint8_t *cplus_txbuffer;
503 int cplus_txbuffer_len;
504 int cplus_txbuffer_offset;
505
506 /* PCI interrupt timer */
507 QEMUTimer *timer;
508
509 MemoryRegion bar_io;
510 MemoryRegion bar_mem;
511
512 /* Support migration to/from old versions */
513 int rtl8139_mmio_io_addr_dummy;
514 };
515
516 /* Writes tally counters to memory via DMA */
517 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr);
518
519 static void rtl8139_set_next_tctr_time(RTL8139State *s);
520
prom9346_decode_command(EEprom9346 * eeprom,uint8_t command)521 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
522 {
523 DPRINTF("eeprom command 0x%02x\n", command);
524
525 switch (command & Chip9346_op_mask)
526 {
527 case Chip9346_op_read:
528 {
529 eeprom->address = command & EEPROM_9346_ADDR_MASK;
530 eeprom->output = eeprom->contents[eeprom->address];
531 eeprom->eedo = 0;
532 eeprom->tick = 0;
533 eeprom->mode = Chip9346_data_read;
534 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
535 eeprom->address, eeprom->output);
536 }
537 break;
538
539 case Chip9346_op_write:
540 {
541 eeprom->address = command & EEPROM_9346_ADDR_MASK;
542 eeprom->input = 0;
543 eeprom->tick = 0;
544 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
545 DPRINTF("eeprom begin write to address 0x%02x\n",
546 eeprom->address);
547 }
548 break;
549 default:
550 eeprom->mode = Chip9346_none;
551 switch (command & Chip9346_op_ext_mask)
552 {
553 case Chip9346_op_write_enable:
554 DPRINTF("eeprom write enabled\n");
555 break;
556 case Chip9346_op_write_all:
557 DPRINTF("eeprom begin write all\n");
558 break;
559 case Chip9346_op_write_disable:
560 DPRINTF("eeprom write disabled\n");
561 break;
562 }
563 break;
564 }
565 }
566
prom9346_shift_clock(EEprom9346 * eeprom)567 static void prom9346_shift_clock(EEprom9346 *eeprom)
568 {
569 int bit = eeprom->eedi?1:0;
570
571 ++ eeprom->tick;
572
573 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
574 eeprom->eedo);
575
576 switch (eeprom->mode)
577 {
578 case Chip9346_enter_command_mode:
579 if (bit)
580 {
581 eeprom->mode = Chip9346_read_command;
582 eeprom->tick = 0;
583 eeprom->input = 0;
584 DPRINTF("eeprom: +++ synchronized, begin command read\n");
585 }
586 break;
587
588 case Chip9346_read_command:
589 eeprom->input = (eeprom->input << 1) | (bit & 1);
590 if (eeprom->tick == 8)
591 {
592 prom9346_decode_command(eeprom, eeprom->input & 0xff);
593 }
594 break;
595
596 case Chip9346_data_read:
597 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
598 eeprom->output <<= 1;
599 if (eeprom->tick == 16)
600 {
601 #if 1
602 // the FreeBSD drivers (rl and re) don't explicitly toggle
603 // CS between reads (or does setting Cfg9346 to 0 count too?),
604 // so we need to enter wait-for-command state here
605 eeprom->mode = Chip9346_enter_command_mode;
606 eeprom->input = 0;
607 eeprom->tick = 0;
608
609 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
610 #else
611 // original behaviour
612 ++eeprom->address;
613 eeprom->address &= EEPROM_9346_ADDR_MASK;
614 eeprom->output = eeprom->contents[eeprom->address];
615 eeprom->tick = 0;
616
617 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
618 eeprom->address, eeprom->output);
619 #endif
620 }
621 break;
622
623 case Chip9346_data_write:
624 eeprom->input = (eeprom->input << 1) | (bit & 1);
625 if (eeprom->tick == 16)
626 {
627 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
628 eeprom->address, eeprom->input);
629
630 eeprom->contents[eeprom->address] = eeprom->input;
631 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
632 eeprom->tick = 0;
633 eeprom->input = 0;
634 }
635 break;
636
637 case Chip9346_data_write_all:
638 eeprom->input = (eeprom->input << 1) | (bit & 1);
639 if (eeprom->tick == 16)
640 {
641 int i;
642 for (i = 0; i < EEPROM_9346_SIZE; i++)
643 {
644 eeprom->contents[i] = eeprom->input;
645 }
646 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
647
648 eeprom->mode = Chip9346_enter_command_mode;
649 eeprom->tick = 0;
650 eeprom->input = 0;
651 }
652 break;
653
654 default:
655 break;
656 }
657 }
658
prom9346_get_wire(RTL8139State * s)659 static int prom9346_get_wire(RTL8139State *s)
660 {
661 EEprom9346 *eeprom = &s->eeprom;
662 if (!eeprom->eecs)
663 return 0;
664
665 return eeprom->eedo;
666 }
667
668 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */
prom9346_set_wire(RTL8139State * s,int eecs,int eesk,int eedi)669 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
670 {
671 EEprom9346 *eeprom = &s->eeprom;
672 uint8_t old_eecs = eeprom->eecs;
673 uint8_t old_eesk = eeprom->eesk;
674
675 eeprom->eecs = eecs;
676 eeprom->eesk = eesk;
677 eeprom->eedi = eedi;
678
679 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
680 eeprom->eesk, eeprom->eedi, eeprom->eedo);
681
682 if (!old_eecs && eecs)
683 {
684 /* Synchronize start */
685 eeprom->tick = 0;
686 eeprom->input = 0;
687 eeprom->output = 0;
688 eeprom->mode = Chip9346_enter_command_mode;
689
690 DPRINTF("=== eeprom: begin access, enter command mode\n");
691 }
692
693 if (!eecs)
694 {
695 DPRINTF("=== eeprom: end access\n");
696 return;
697 }
698
699 if (!old_eesk && eesk)
700 {
701 /* SK front rules */
702 prom9346_shift_clock(eeprom);
703 }
704 }
705
rtl8139_update_irq(RTL8139State * s)706 static void rtl8139_update_irq(RTL8139State *s)
707 {
708 PCIDevice *d = PCI_DEVICE(s);
709 int isr;
710 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
711
712 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
713 s->IntrMask);
714
715 pci_set_irq(d, (isr != 0));
716 }
717
rtl8139_RxWrap(RTL8139State * s)718 static int rtl8139_RxWrap(RTL8139State *s)
719 {
720 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
721 return (s->RxConfig & (1 << 7));
722 }
723
rtl8139_receiver_enabled(RTL8139State * s)724 static int rtl8139_receiver_enabled(RTL8139State *s)
725 {
726 return s->bChipCmdState & CmdRxEnb;
727 }
728
rtl8139_transmitter_enabled(RTL8139State * s)729 static int rtl8139_transmitter_enabled(RTL8139State *s)
730 {
731 return s->bChipCmdState & CmdTxEnb;
732 }
733
rtl8139_cp_receiver_enabled(RTL8139State * s)734 static int rtl8139_cp_receiver_enabled(RTL8139State *s)
735 {
736 return s->CpCmd & CPlusRxEnb;
737 }
738
rtl8139_cp_transmitter_enabled(RTL8139State * s)739 static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
740 {
741 return s->CpCmd & CPlusTxEnb;
742 }
743
rtl8139_write_buffer(RTL8139State * s,const void * buf,int size)744 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
745 {
746 PCIDevice *d = PCI_DEVICE(s);
747
748 if (s->RxBufAddr + size > s->RxBufferSize)
749 {
750 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
751
752 /* write packet data */
753 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
754 {
755 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
756
757 if (size > wrapped)
758 {
759 pci_dma_write(d, s->RxBuf + s->RxBufAddr,
760 buf, size-wrapped);
761 }
762
763 /* reset buffer pointer */
764 s->RxBufAddr = 0;
765
766 pci_dma_write(d, s->RxBuf + s->RxBufAddr,
767 buf + (size-wrapped), wrapped);
768
769 s->RxBufAddr = wrapped;
770
771 return;
772 }
773 }
774
775 /* non-wrapping path or overwrapping enabled */
776 pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size);
777
778 s->RxBufAddr += size;
779 }
780
781 #define MIN_BUF_SIZE 60
rtl8139_addr64(uint32_t low,uint32_t high)782 static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
783 {
784 return low | ((uint64_t)high << 32);
785 }
786
787 /* Workaround for buggy guest driver such as linux who allocates rx
788 * rings after the receiver were enabled. */
rtl8139_cp_rx_valid(RTL8139State * s)789 static bool rtl8139_cp_rx_valid(RTL8139State *s)
790 {
791 return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0);
792 }
793
rtl8139_can_receive(NetClientState * nc)794 static bool rtl8139_can_receive(NetClientState *nc)
795 {
796 RTL8139State *s = qemu_get_nic_opaque(nc);
797 int avail;
798
799 /* Receive (drop) packets if card is disabled. */
800 if (!s->clock_enabled) {
801 return true;
802 }
803 if (!rtl8139_receiver_enabled(s)) {
804 return true;
805 }
806
807 if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) {
808 /* ??? Flow control not implemented in c+ mode.
809 This is a hack to work around slirp deficiencies anyway. */
810 return true;
811 }
812
813 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
814 s->RxBufferSize);
815 return avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow);
816 }
817
rtl8139_do_receive(NetClientState * nc,const uint8_t * buf,size_t size_,int do_interrupt)818 static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
819 {
820 RTL8139State *s = qemu_get_nic_opaque(nc);
821 PCIDevice *d = PCI_DEVICE(s);
822 /* size is the length of the buffer passed to the driver */
823 size_t size = size_;
824 const uint8_t *dot1q_buf = NULL;
825
826 uint32_t packet_header = 0;
827
828 static const uint8_t broadcast_macaddr[6] =
829 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
830
831 DPRINTF(">>> received len=%zu\n", size);
832
833 /* test if board clock is stopped */
834 if (!s->clock_enabled)
835 {
836 DPRINTF("stopped ==========================\n");
837 return -1;
838 }
839
840 /* first check if receiver is enabled */
841
842 if (!rtl8139_receiver_enabled(s))
843 {
844 DPRINTF("receiver disabled ================\n");
845 return -1;
846 }
847
848 /* XXX: check this */
849 if (s->RxConfig & AcceptAllPhys) {
850 /* promiscuous: receive all */
851 DPRINTF(">>> packet received in promiscuous mode\n");
852
853 } else {
854 if (!memcmp(buf, broadcast_macaddr, 6)) {
855 /* broadcast address */
856 if (!(s->RxConfig & AcceptBroadcast))
857 {
858 DPRINTF(">>> broadcast packet rejected\n");
859
860 /* update tally counter */
861 ++s->tally_counters.RxERR;
862
863 return size;
864 }
865
866 packet_header |= RxBroadcast;
867
868 DPRINTF(">>> broadcast packet received\n");
869
870 /* update tally counter */
871 ++s->tally_counters.RxOkBrd;
872
873 } else if (buf[0] & 0x01) {
874 /* multicast */
875 if (!(s->RxConfig & AcceptMulticast))
876 {
877 DPRINTF(">>> multicast packet rejected\n");
878
879 /* update tally counter */
880 ++s->tally_counters.RxERR;
881
882 return size;
883 }
884
885 int mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
886
887 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
888 {
889 DPRINTF(">>> multicast address mismatch\n");
890
891 /* update tally counter */
892 ++s->tally_counters.RxERR;
893
894 return size;
895 }
896
897 packet_header |= RxMulticast;
898
899 DPRINTF(">>> multicast packet received\n");
900
901 /* update tally counter */
902 ++s->tally_counters.RxOkMul;
903
904 } else if (s->phys[0] == buf[0] &&
905 s->phys[1] == buf[1] &&
906 s->phys[2] == buf[2] &&
907 s->phys[3] == buf[3] &&
908 s->phys[4] == buf[4] &&
909 s->phys[5] == buf[5]) {
910 /* match */
911 if (!(s->RxConfig & AcceptMyPhys))
912 {
913 DPRINTF(">>> rejecting physical address matching packet\n");
914
915 /* update tally counter */
916 ++s->tally_counters.RxERR;
917
918 return size;
919 }
920
921 packet_header |= RxPhysical;
922
923 DPRINTF(">>> physical address matching packet received\n");
924
925 /* update tally counter */
926 ++s->tally_counters.RxOkPhy;
927
928 } else {
929
930 DPRINTF(">>> unknown packet\n");
931
932 /* update tally counter */
933 ++s->tally_counters.RxERR;
934
935 return size;
936 }
937 }
938
939 if (rtl8139_cp_receiver_enabled(s))
940 {
941 if (!rtl8139_cp_rx_valid(s)) {
942 return size;
943 }
944
945 DPRINTF("in C+ Rx mode ================\n");
946
947 /* begin C+ receiver mode */
948
949 /* w0 ownership flag */
950 #define CP_RX_OWN (1<<31)
951 /* w0 end of ring flag */
952 #define CP_RX_EOR (1<<30)
953 /* w0 bits 0...12 : buffer size */
954 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
955 /* w1 tag available flag */
956 #define CP_RX_TAVA (1<<16)
957 /* w1 bits 0...15 : VLAN tag */
958 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
959 /* w2 low 32bit of Rx buffer ptr */
960 /* w3 high 32bit of Rx buffer ptr */
961
962 int descriptor = s->currCPlusRxDesc;
963 dma_addr_t cplus_rx_ring_desc;
964
965 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
966 cplus_rx_ring_desc += 16 * descriptor;
967
968 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
969 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,
970 s->RxRingAddrLO, cplus_rx_ring_desc);
971
972 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
973
974 pci_dma_read(d, cplus_rx_ring_desc, &val, 4);
975 rxdw0 = le32_to_cpu(val);
976 pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4);
977 rxdw1 = le32_to_cpu(val);
978 pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4);
979 rxbufLO = le32_to_cpu(val);
980 pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4);
981 rxbufHI = le32_to_cpu(val);
982
983 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
984 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
985
986 if (!(rxdw0 & CP_RX_OWN))
987 {
988 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
989 descriptor);
990
991 s->IntrStatus |= RxOverflow;
992 ++s->RxMissed;
993
994 /* update tally counter */
995 ++s->tally_counters.RxERR;
996 ++s->tally_counters.MissPkt;
997
998 rtl8139_update_irq(s);
999 return size_;
1000 }
1001
1002 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1003
1004 /* write VLAN info to descriptor variables. */
1005 if (s->CpCmd & CPlusRxVLAN &&
1006 lduw_be_p(&buf[ETH_ALEN * 2]) == ETH_P_VLAN) {
1007 dot1q_buf = &buf[ETH_ALEN * 2];
1008 size -= VLAN_HLEN;
1009 /* if too small buffer, use the tailroom added duing expansion */
1010 if (size < MIN_BUF_SIZE) {
1011 size = MIN_BUF_SIZE;
1012 }
1013
1014 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1015 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1016 rxdw1 |= CP_RX_TAVA | lduw_le_p(&dot1q_buf[ETHER_TYPE_LEN]);
1017
1018 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
1019 lduw_be_p(&dot1q_buf[ETHER_TYPE_LEN]));
1020 } else {
1021 /* reset VLAN tag flag */
1022 rxdw1 &= ~CP_RX_TAVA;
1023 }
1024
1025 /* TODO: scatter the packet over available receive ring descriptors space */
1026
1027 if (size+4 > rx_space)
1028 {
1029 DPRINTF("C+ Rx mode : descriptor %d size %d received %zu + 4\n",
1030 descriptor, rx_space, size);
1031
1032 s->IntrStatus |= RxOverflow;
1033 ++s->RxMissed;
1034
1035 /* update tally counter */
1036 ++s->tally_counters.RxERR;
1037 ++s->tally_counters.MissPkt;
1038
1039 rtl8139_update_irq(s);
1040 return size_;
1041 }
1042
1043 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1044
1045 /* receive/copy to target memory */
1046 if (dot1q_buf) {
1047 pci_dma_write(d, rx_addr, buf, 2 * ETH_ALEN);
1048 pci_dma_write(d, rx_addr + 2 * ETH_ALEN,
1049 buf + 2 * ETH_ALEN + VLAN_HLEN,
1050 size - 2 * ETH_ALEN);
1051 } else {
1052 pci_dma_write(d, rx_addr, buf, size);
1053 }
1054
1055 if (s->CpCmd & CPlusRxChkSum)
1056 {
1057 /* do some packet checksumming */
1058 }
1059
1060 /* write checksum */
1061 val = cpu_to_le32(crc32(0, buf, size_));
1062 pci_dma_write(d, rx_addr+size, (uint8_t *)&val, 4);
1063
1064 /* first segment of received packet flag */
1065 #define CP_RX_STATUS_FS (1<<29)
1066 /* last segment of received packet flag */
1067 #define CP_RX_STATUS_LS (1<<28)
1068 /* multicast packet flag */
1069 #define CP_RX_STATUS_MAR (1<<26)
1070 /* physical-matching packet flag */
1071 #define CP_RX_STATUS_PAM (1<<25)
1072 /* broadcast packet flag */
1073 #define CP_RX_STATUS_BAR (1<<24)
1074 /* runt packet flag */
1075 #define CP_RX_STATUS_RUNT (1<<19)
1076 /* crc error flag */
1077 #define CP_RX_STATUS_CRC (1<<18)
1078 /* IP checksum error flag */
1079 #define CP_RX_STATUS_IPF (1<<15)
1080 /* UDP checksum error flag */
1081 #define CP_RX_STATUS_UDPF (1<<14)
1082 /* TCP checksum error flag */
1083 #define CP_RX_STATUS_TCPF (1<<13)
1084
1085 /* transfer ownership to target */
1086 rxdw0 &= ~CP_RX_OWN;
1087
1088 /* set first segment bit */
1089 rxdw0 |= CP_RX_STATUS_FS;
1090
1091 /* set last segment bit */
1092 rxdw0 |= CP_RX_STATUS_LS;
1093
1094 /* set received packet type flags */
1095 if (packet_header & RxBroadcast)
1096 rxdw0 |= CP_RX_STATUS_BAR;
1097 if (packet_header & RxMulticast)
1098 rxdw0 |= CP_RX_STATUS_MAR;
1099 if (packet_header & RxPhysical)
1100 rxdw0 |= CP_RX_STATUS_PAM;
1101
1102 /* set received size */
1103 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1104 rxdw0 |= (size+4);
1105
1106 /* update ring data */
1107 val = cpu_to_le32(rxdw0);
1108 pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4);
1109 val = cpu_to_le32(rxdw1);
1110 pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1111
1112 /* update tally counter */
1113 ++s->tally_counters.RxOk;
1114
1115 /* seek to next Rx descriptor */
1116 if (rxdw0 & CP_RX_EOR)
1117 {
1118 s->currCPlusRxDesc = 0;
1119 }
1120 else
1121 {
1122 ++s->currCPlusRxDesc;
1123 }
1124
1125 DPRINTF("done C+ Rx mode ----------------\n");
1126
1127 }
1128 else
1129 {
1130 DPRINTF("in ring Rx mode ================\n");
1131
1132 /* begin ring receiver mode */
1133 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1134
1135 /* if receiver buffer is empty then avail == 0 */
1136
1137 #define RX_ALIGN(x) (((x) + 3) & ~0x3)
1138
1139 if (avail != 0 && RX_ALIGN(size + 8) >= avail)
1140 {
1141 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1142 "read 0x%04x === available 0x%04x need 0x%04zx\n",
1143 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
1144
1145 s->IntrStatus |= RxOverflow;
1146 ++s->RxMissed;
1147 rtl8139_update_irq(s);
1148 return 0;
1149 }
1150
1151 packet_header |= RxStatusOK;
1152
1153 packet_header |= (((size+4) << 16) & 0xffff0000);
1154
1155 /* write header */
1156 uint32_t val = cpu_to_le32(packet_header);
1157
1158 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1159
1160 rtl8139_write_buffer(s, buf, size);
1161
1162 /* write checksum */
1163 val = cpu_to_le32(crc32(0, buf, size));
1164 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1165
1166 /* correct buffer write pointer */
1167 s->RxBufAddr = MOD2(RX_ALIGN(s->RxBufAddr), s->RxBufferSize);
1168
1169 /* now we can signal we have received something */
1170
1171 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1172 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
1173 }
1174
1175 s->IntrStatus |= RxOK;
1176
1177 if (do_interrupt)
1178 {
1179 rtl8139_update_irq(s);
1180 }
1181
1182 return size_;
1183 }
1184
rtl8139_receive(NetClientState * nc,const uint8_t * buf,size_t size)1185 static ssize_t rtl8139_receive(NetClientState *nc, const uint8_t *buf, size_t size)
1186 {
1187 return rtl8139_do_receive(nc, buf, size, 1);
1188 }
1189
rtl8139_reset_rxring(RTL8139State * s,uint32_t bufferSize)1190 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1191 {
1192 s->RxBufferSize = bufferSize;
1193 s->RxBufPtr = 0;
1194 s->RxBufAddr = 0;
1195 }
1196
rtl8139_reset_phy(RTL8139State * s)1197 static void rtl8139_reset_phy(RTL8139State *s)
1198 {
1199 s->BasicModeStatus = 0x7809;
1200 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1201 /* preserve link state */
1202 s->BasicModeStatus |= qemu_get_queue(s->nic)->link_down ? 0 : 0x04;
1203
1204 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1205 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1206 s->NWayExpansion = 0x0001; /* autonegotiation supported */
1207
1208 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1209 }
1210
rtl8139_reset(DeviceState * d)1211 static void rtl8139_reset(DeviceState *d)
1212 {
1213 RTL8139State *s = RTL8139(d);
1214 int i;
1215
1216 /* restore MAC address */
1217 memcpy(s->phys, s->conf.macaddr.a, 6);
1218 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys);
1219
1220 /* reset interrupt mask */
1221 s->IntrStatus = 0;
1222 s->IntrMask = 0;
1223
1224 rtl8139_update_irq(s);
1225
1226 /* mark all status registers as owned by host */
1227 for (i = 0; i < 4; ++i)
1228 {
1229 s->TxStatus[i] = TxHostOwns;
1230 }
1231
1232 s->currTxDesc = 0;
1233 s->currCPlusRxDesc = 0;
1234 s->currCPlusTxDesc = 0;
1235
1236 s->RxRingAddrLO = 0;
1237 s->RxRingAddrHI = 0;
1238
1239 s->RxBuf = 0;
1240
1241 rtl8139_reset_rxring(s, 8192);
1242
1243 /* ACK the reset */
1244 s->TxConfig = 0;
1245
1246 #if 0
1247 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1248 s->clock_enabled = 0;
1249 #else
1250 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1251 s->clock_enabled = 1;
1252 #endif
1253
1254 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1255
1256 /* set initial state data */
1257 s->Config0 = 0x0; /* No boot ROM */
1258 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1259 s->Config3 = 0x1; /* fast back-to-back compatible */
1260 s->Config5 = 0x0;
1261
1262 s->CpCmd = 0x0; /* reset C+ mode */
1263 s->cplus_enabled = 0;
1264
1265 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1266 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1267 s->BasicModeCtrl = 0x1000; // autonegotiation
1268
1269 rtl8139_reset_phy(s);
1270
1271 /* also reset timer and disable timer interrupt */
1272 s->TCTR = 0;
1273 s->TimerInt = 0;
1274 s->TCTR_base = 0;
1275 rtl8139_set_next_tctr_time(s);
1276
1277 /* reset tally counters */
1278 RTL8139TallyCounters_clear(&s->tally_counters);
1279 }
1280
RTL8139TallyCounters_clear(RTL8139TallyCounters * counters)1281 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1282 {
1283 counters->TxOk = 0;
1284 counters->RxOk = 0;
1285 counters->TxERR = 0;
1286 counters->RxERR = 0;
1287 counters->MissPkt = 0;
1288 counters->FAE = 0;
1289 counters->Tx1Col = 0;
1290 counters->TxMCol = 0;
1291 counters->RxOkPhy = 0;
1292 counters->RxOkBrd = 0;
1293 counters->RxOkMul = 0;
1294 counters->TxAbt = 0;
1295 counters->TxUndrn = 0;
1296 }
1297
RTL8139TallyCounters_dma_write(RTL8139State * s,dma_addr_t tc_addr)1298 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
1299 {
1300 PCIDevice *d = PCI_DEVICE(s);
1301 RTL8139TallyCounters *tally_counters = &s->tally_counters;
1302 uint16_t val16;
1303 uint32_t val32;
1304 uint64_t val64;
1305
1306 val64 = cpu_to_le64(tally_counters->TxOk);
1307 pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8);
1308
1309 val64 = cpu_to_le64(tally_counters->RxOk);
1310 pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8);
1311
1312 val64 = cpu_to_le64(tally_counters->TxERR);
1313 pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8);
1314
1315 val32 = cpu_to_le32(tally_counters->RxERR);
1316 pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4);
1317
1318 val16 = cpu_to_le16(tally_counters->MissPkt);
1319 pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2);
1320
1321 val16 = cpu_to_le16(tally_counters->FAE);
1322 pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2);
1323
1324 val32 = cpu_to_le32(tally_counters->Tx1Col);
1325 pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4);
1326
1327 val32 = cpu_to_le32(tally_counters->TxMCol);
1328 pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4);
1329
1330 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1331 pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8);
1332
1333 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1334 pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8);
1335
1336 val32 = cpu_to_le32(tally_counters->RxOkMul);
1337 pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4);
1338
1339 val16 = cpu_to_le16(tally_counters->TxAbt);
1340 pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2);
1341
1342 val16 = cpu_to_le16(tally_counters->TxUndrn);
1343 pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2);
1344 }
1345
rtl8139_ChipCmd_write(RTL8139State * s,uint32_t val)1346 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1347 {
1348 DeviceState *d = DEVICE(s);
1349
1350 val &= 0xff;
1351
1352 DPRINTF("ChipCmd write val=0x%08x\n", val);
1353
1354 if (val & CmdReset)
1355 {
1356 DPRINTF("ChipCmd reset\n");
1357 rtl8139_reset(d);
1358 }
1359 if (val & CmdRxEnb)
1360 {
1361 DPRINTF("ChipCmd enable receiver\n");
1362
1363 s->currCPlusRxDesc = 0;
1364 }
1365 if (val & CmdTxEnb)
1366 {
1367 DPRINTF("ChipCmd enable transmitter\n");
1368
1369 s->currCPlusTxDesc = 0;
1370 }
1371
1372 /* mask unwritable bits */
1373 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1374
1375 /* Deassert reset pin before next read */
1376 val &= ~CmdReset;
1377
1378 s->bChipCmdState = val;
1379 }
1380
rtl8139_RxBufferEmpty(RTL8139State * s)1381 static int rtl8139_RxBufferEmpty(RTL8139State *s)
1382 {
1383 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1384
1385 if (unread != 0)
1386 {
1387 DPRINTF("receiver buffer data available 0x%04x\n", unread);
1388 return 0;
1389 }
1390
1391 DPRINTF("receiver buffer is empty\n");
1392
1393 return 1;
1394 }
1395
rtl8139_ChipCmd_read(RTL8139State * s)1396 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1397 {
1398 uint32_t ret = s->bChipCmdState;
1399
1400 if (rtl8139_RxBufferEmpty(s))
1401 ret |= RxBufEmpty;
1402
1403 DPRINTF("ChipCmd read val=0x%04x\n", ret);
1404
1405 return ret;
1406 }
1407
rtl8139_CpCmd_write(RTL8139State * s,uint32_t val)1408 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1409 {
1410 val &= 0xffff;
1411
1412 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
1413
1414 s->cplus_enabled = 1;
1415
1416 /* mask unwritable bits */
1417 val = SET_MASKED(val, 0xff84, s->CpCmd);
1418
1419 s->CpCmd = val;
1420 }
1421
rtl8139_CpCmd_read(RTL8139State * s)1422 static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1423 {
1424 uint32_t ret = s->CpCmd;
1425
1426 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
1427
1428 return ret;
1429 }
1430
rtl8139_IntrMitigate_write(RTL8139State * s,uint32_t val)1431 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1432 {
1433 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
1434 }
1435
rtl8139_IntrMitigate_read(RTL8139State * s)1436 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1437 {
1438 uint32_t ret = 0;
1439
1440 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
1441
1442 return ret;
1443 }
1444
rtl8139_config_writable(RTL8139State * s)1445 static int rtl8139_config_writable(RTL8139State *s)
1446 {
1447 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite)
1448 {
1449 return 1;
1450 }
1451
1452 DPRINTF("Configuration registers are write-protected\n");
1453
1454 return 0;
1455 }
1456
rtl8139_BasicModeCtrl_write(RTL8139State * s,uint32_t val)1457 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1458 {
1459 val &= 0xffff;
1460
1461 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
1462
1463 /* mask unwritable bits */
1464 uint32_t mask = 0xccff;
1465
1466 if (1 || !rtl8139_config_writable(s))
1467 {
1468 /* Speed setting and autonegotiation enable bits are read-only */
1469 mask |= 0x3000;
1470 /* Duplex mode setting is read-only */
1471 mask |= 0x0100;
1472 }
1473
1474 if (val & 0x8000) {
1475 /* Reset PHY */
1476 rtl8139_reset_phy(s);
1477 }
1478
1479 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1480
1481 s->BasicModeCtrl = val;
1482 }
1483
rtl8139_BasicModeCtrl_read(RTL8139State * s)1484 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1485 {
1486 uint32_t ret = s->BasicModeCtrl;
1487
1488 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
1489
1490 return ret;
1491 }
1492
rtl8139_BasicModeStatus_write(RTL8139State * s,uint32_t val)1493 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1494 {
1495 val &= 0xffff;
1496
1497 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
1498
1499 /* mask unwritable bits */
1500 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1501
1502 s->BasicModeStatus = val;
1503 }
1504
rtl8139_BasicModeStatus_read(RTL8139State * s)1505 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1506 {
1507 uint32_t ret = s->BasicModeStatus;
1508
1509 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
1510
1511 return ret;
1512 }
1513
rtl8139_Cfg9346_write(RTL8139State * s,uint32_t val)1514 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1515 {
1516 DeviceState *d = DEVICE(s);
1517
1518 val &= 0xff;
1519
1520 DPRINTF("Cfg9346 write val=0x%02x\n", val);
1521
1522 /* mask unwritable bits */
1523 val = SET_MASKED(val, 0x31, s->Cfg9346);
1524
1525 uint32_t opmode = val & 0xc0;
1526 uint32_t eeprom_val = val & 0xf;
1527
1528 if (opmode == 0x80) {
1529 /* eeprom access */
1530 int eecs = (eeprom_val & 0x08)?1:0;
1531 int eesk = (eeprom_val & 0x04)?1:0;
1532 int eedi = (eeprom_val & 0x02)?1:0;
1533 prom9346_set_wire(s, eecs, eesk, eedi);
1534 } else if (opmode == 0x40) {
1535 /* Reset. */
1536 val = 0;
1537 rtl8139_reset(d);
1538 }
1539
1540 s->Cfg9346 = val;
1541 }
1542
rtl8139_Cfg9346_read(RTL8139State * s)1543 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1544 {
1545 uint32_t ret = s->Cfg9346;
1546
1547 uint32_t opmode = ret & 0xc0;
1548
1549 if (opmode == 0x80)
1550 {
1551 /* eeprom access */
1552 int eedo = prom9346_get_wire(s);
1553 if (eedo)
1554 {
1555 ret |= 0x01;
1556 }
1557 else
1558 {
1559 ret &= ~0x01;
1560 }
1561 }
1562
1563 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
1564
1565 return ret;
1566 }
1567
rtl8139_Config0_write(RTL8139State * s,uint32_t val)1568 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1569 {
1570 val &= 0xff;
1571
1572 DPRINTF("Config0 write val=0x%02x\n", val);
1573
1574 if (!rtl8139_config_writable(s)) {
1575 return;
1576 }
1577
1578 /* mask unwritable bits */
1579 val = SET_MASKED(val, 0xf8, s->Config0);
1580
1581 s->Config0 = val;
1582 }
1583
rtl8139_Config0_read(RTL8139State * s)1584 static uint32_t rtl8139_Config0_read(RTL8139State *s)
1585 {
1586 uint32_t ret = s->Config0;
1587
1588 DPRINTF("Config0 read val=0x%02x\n", ret);
1589
1590 return ret;
1591 }
1592
rtl8139_Config1_write(RTL8139State * s,uint32_t val)1593 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1594 {
1595 val &= 0xff;
1596
1597 DPRINTF("Config1 write val=0x%02x\n", val);
1598
1599 if (!rtl8139_config_writable(s)) {
1600 return;
1601 }
1602
1603 /* mask unwritable bits */
1604 val = SET_MASKED(val, 0xC, s->Config1);
1605
1606 s->Config1 = val;
1607 }
1608
rtl8139_Config1_read(RTL8139State * s)1609 static uint32_t rtl8139_Config1_read(RTL8139State *s)
1610 {
1611 uint32_t ret = s->Config1;
1612
1613 DPRINTF("Config1 read val=0x%02x\n", ret);
1614
1615 return ret;
1616 }
1617
rtl8139_Config3_write(RTL8139State * s,uint32_t val)1618 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1619 {
1620 val &= 0xff;
1621
1622 DPRINTF("Config3 write val=0x%02x\n", val);
1623
1624 if (!rtl8139_config_writable(s)) {
1625 return;
1626 }
1627
1628 /* mask unwritable bits */
1629 val = SET_MASKED(val, 0x8F, s->Config3);
1630
1631 s->Config3 = val;
1632 }
1633
rtl8139_Config3_read(RTL8139State * s)1634 static uint32_t rtl8139_Config3_read(RTL8139State *s)
1635 {
1636 uint32_t ret = s->Config3;
1637
1638 DPRINTF("Config3 read val=0x%02x\n", ret);
1639
1640 return ret;
1641 }
1642
rtl8139_Config4_write(RTL8139State * s,uint32_t val)1643 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1644 {
1645 val &= 0xff;
1646
1647 DPRINTF("Config4 write val=0x%02x\n", val);
1648
1649 if (!rtl8139_config_writable(s)) {
1650 return;
1651 }
1652
1653 /* mask unwritable bits */
1654 val = SET_MASKED(val, 0x0a, s->Config4);
1655
1656 s->Config4 = val;
1657 }
1658
rtl8139_Config4_read(RTL8139State * s)1659 static uint32_t rtl8139_Config4_read(RTL8139State *s)
1660 {
1661 uint32_t ret = s->Config4;
1662
1663 DPRINTF("Config4 read val=0x%02x\n", ret);
1664
1665 return ret;
1666 }
1667
rtl8139_Config5_write(RTL8139State * s,uint32_t val)1668 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1669 {
1670 val &= 0xff;
1671
1672 DPRINTF("Config5 write val=0x%02x\n", val);
1673
1674 /* mask unwritable bits */
1675 val = SET_MASKED(val, 0x80, s->Config5);
1676
1677 s->Config5 = val;
1678 }
1679
rtl8139_Config5_read(RTL8139State * s)1680 static uint32_t rtl8139_Config5_read(RTL8139State *s)
1681 {
1682 uint32_t ret = s->Config5;
1683
1684 DPRINTF("Config5 read val=0x%02x\n", ret);
1685
1686 return ret;
1687 }
1688
rtl8139_TxConfig_write(RTL8139State * s,uint32_t val)1689 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1690 {
1691 if (!rtl8139_transmitter_enabled(s))
1692 {
1693 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
1694 return;
1695 }
1696
1697 DPRINTF("TxConfig write val=0x%08x\n", val);
1698
1699 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1700
1701 s->TxConfig = val;
1702 }
1703
rtl8139_TxConfig_writeb(RTL8139State * s,uint32_t val)1704 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1705 {
1706 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
1707
1708 uint32_t tc = s->TxConfig;
1709 tc &= 0xFFFFFF00;
1710 tc |= (val & 0x000000FF);
1711 rtl8139_TxConfig_write(s, tc);
1712 }
1713
rtl8139_TxConfig_read(RTL8139State * s)1714 static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1715 {
1716 uint32_t ret = s->TxConfig;
1717
1718 DPRINTF("TxConfig read val=0x%04x\n", ret);
1719
1720 return ret;
1721 }
1722
rtl8139_RxConfig_write(RTL8139State * s,uint32_t val)1723 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1724 {
1725 DPRINTF("RxConfig write val=0x%08x\n", val);
1726
1727 /* mask unwritable bits */
1728 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1729
1730 s->RxConfig = val;
1731
1732 /* reset buffer size and read/write pointers */
1733 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1734
1735 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
1736 }
1737
rtl8139_RxConfig_read(RTL8139State * s)1738 static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1739 {
1740 uint32_t ret = s->RxConfig;
1741
1742 DPRINTF("RxConfig read val=0x%08x\n", ret);
1743
1744 return ret;
1745 }
1746
rtl8139_transfer_frame(RTL8139State * s,uint8_t * buf,int size,int do_interrupt,const uint8_t * dot1q_buf)1747 static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1748 int do_interrupt, const uint8_t *dot1q_buf)
1749 {
1750 struct iovec *iov = NULL;
1751 struct iovec vlan_iov[3];
1752
1753 if (!size)
1754 {
1755 DPRINTF("+++ empty ethernet frame\n");
1756 return;
1757 }
1758
1759 if (dot1q_buf && size >= ETH_ALEN * 2) {
1760 iov = (struct iovec[3]) {
1761 { .iov_base = buf, .iov_len = ETH_ALEN * 2 },
1762 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1763 { .iov_base = buf + ETH_ALEN * 2,
1764 .iov_len = size - ETH_ALEN * 2 },
1765 };
1766
1767 memcpy(vlan_iov, iov, sizeof(vlan_iov));
1768 iov = vlan_iov;
1769 }
1770
1771 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1772 {
1773 size_t buf2_size;
1774 uint8_t *buf2;
1775
1776 if (iov) {
1777 buf2_size = iov_size(iov, 3);
1778 buf2 = g_malloc(buf2_size);
1779 iov_to_buf(iov, 3, 0, buf2, buf2_size);
1780 buf = buf2;
1781 }
1782
1783 DPRINTF("+++ transmit loopback mode\n");
1784 qemu_receive_packet(qemu_get_queue(s->nic), buf, size);
1785
1786 if (iov) {
1787 g_free(buf2);
1788 }
1789 }
1790 else
1791 {
1792 if (iov) {
1793 qemu_sendv_packet(qemu_get_queue(s->nic), iov, 3);
1794 } else {
1795 qemu_send_packet(qemu_get_queue(s->nic), buf, size);
1796 }
1797 }
1798 }
1799
rtl8139_transmit_one(RTL8139State * s,int descriptor)1800 static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1801 {
1802 if (!rtl8139_transmitter_enabled(s))
1803 {
1804 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1805 "disabled\n", descriptor);
1806 return 0;
1807 }
1808
1809 if (s->TxStatus[descriptor] & TxHostOwns)
1810 {
1811 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1812 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
1813 return 0;
1814 }
1815
1816 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
1817
1818 PCIDevice *d = PCI_DEVICE(s);
1819 int txsize = s->TxStatus[descriptor] & 0x1fff;
1820 QEMU_UNINITIALIZED uint8_t txbuffer[0x2000];
1821
1822 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1823 txsize, s->TxAddr[descriptor]);
1824
1825 pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize);
1826
1827 /* Mark descriptor as transferred */
1828 s->TxStatus[descriptor] |= TxHostOwns;
1829 s->TxStatus[descriptor] |= TxStatOK;
1830
1831 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
1832
1833 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1834 descriptor);
1835
1836 /* update interrupt */
1837 s->IntrStatus |= TxOK;
1838 rtl8139_update_irq(s);
1839
1840 return 1;
1841 }
1842
1843 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1844
1845 /* produces ones' complement sum of data */
ones_complement_sum(uint8_t * data,size_t len)1846 static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1847 {
1848 uint32_t result = 0;
1849
1850 for (; len > 1; data+=2, len-=2)
1851 {
1852 result += *(uint16_t*)data;
1853 }
1854
1855 /* add the remainder byte */
1856 if (len)
1857 {
1858 uint8_t odd[2] = {*data, 0};
1859 result += *(uint16_t*)odd;
1860 }
1861
1862 while (result>>16)
1863 result = (result & 0xffff) + (result >> 16);
1864
1865 return result;
1866 }
1867
ip_checksum(void * data,size_t len)1868 static uint16_t ip_checksum(void *data, size_t len)
1869 {
1870 return ~ones_complement_sum((uint8_t*)data, len);
1871 }
1872
rtl8139_cplus_transmit_one(RTL8139State * s)1873 static int rtl8139_cplus_transmit_one(RTL8139State *s)
1874 {
1875 if (!rtl8139_transmitter_enabled(s))
1876 {
1877 DPRINTF("+++ C+ mode: transmitter disabled\n");
1878 return 0;
1879 }
1880
1881 if (!rtl8139_cp_transmitter_enabled(s))
1882 {
1883 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
1884 return 0 ;
1885 }
1886
1887 PCIDevice *d = PCI_DEVICE(s);
1888 int descriptor = s->currCPlusTxDesc;
1889
1890 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1891
1892 /* Normal priority ring */
1893 cplus_tx_ring_desc += 16 * descriptor;
1894
1895 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
1896 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
1897 s->TxAddr[0], cplus_tx_ring_desc);
1898
1899 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1900
1901 pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
1902 txdw0 = le32_to_cpu(val);
1903 pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1904 txdw1 = le32_to_cpu(val);
1905 pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1906 txbufLO = le32_to_cpu(val);
1907 pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1908 txbufHI = le32_to_cpu(val);
1909
1910 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1911 txdw0, txdw1, txbufLO, txbufHI);
1912
1913 /* w0 ownership flag */
1914 #define CP_TX_OWN (1<<31)
1915 /* w0 end of ring flag */
1916 #define CP_TX_EOR (1<<30)
1917 /* first segment of received packet flag */
1918 #define CP_TX_FS (1<<29)
1919 /* last segment of received packet flag */
1920 #define CP_TX_LS (1<<28)
1921 /* large send packet flag */
1922 #define CP_TX_LGSEN (1<<27)
1923 /* large send MSS mask, bits 16...26 */
1924 #define CP_TC_LGSEN_MSS_SHIFT 16
1925 #define CP_TC_LGSEN_MSS_MASK ((1 << 11) - 1)
1926
1927 /* IP checksum offload flag */
1928 #define CP_TX_IPCS (1<<18)
1929 /* UDP checksum offload flag */
1930 #define CP_TX_UDPCS (1<<17)
1931 /* TCP checksum offload flag */
1932 #define CP_TX_TCPCS (1<<16)
1933
1934 /* w0 bits 0...15 : buffer size */
1935 #define CP_TX_BUFFER_SIZE (1<<16)
1936 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1937 /* w1 add tag flag */
1938 #define CP_TX_TAGC (1<<17)
1939 /* w1 bits 0...15 : VLAN tag (big endian) */
1940 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1941 /* w2 low 32bit of Rx buffer ptr */
1942 /* w3 high 32bit of Rx buffer ptr */
1943
1944 /* set after transmission */
1945 /* FIFO underrun flag */
1946 #define CP_TX_STATUS_UNF (1<<25)
1947 /* transmit error summary flag, valid if set any of three below */
1948 #define CP_TX_STATUS_TES (1<<23)
1949 /* out-of-window collision flag */
1950 #define CP_TX_STATUS_OWC (1<<22)
1951 /* link failure flag */
1952 #define CP_TX_STATUS_LNKF (1<<21)
1953 /* excessive collisions flag */
1954 #define CP_TX_STATUS_EXC (1<<20)
1955
1956 if (!(txdw0 & CP_TX_OWN))
1957 {
1958 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
1959 return 0 ;
1960 }
1961
1962 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
1963
1964 if (txdw0 & CP_TX_FS)
1965 {
1966 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
1967 "descriptor\n", descriptor);
1968
1969 /* reset internal buffer offset */
1970 s->cplus_txbuffer_offset = 0;
1971 }
1972
1973 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
1974 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
1975
1976 /* make sure we have enough space to assemble the packet */
1977 if (!s->cplus_txbuffer)
1978 {
1979 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
1980 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
1981 s->cplus_txbuffer_offset = 0;
1982
1983 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
1984 s->cplus_txbuffer_len);
1985 }
1986
1987 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
1988 {
1989 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
1990 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
1991 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
1992 "length to %d\n", txsize);
1993 }
1994
1995 /* append more data to the packet */
1996
1997 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
1998 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
1999 s->cplus_txbuffer_offset);
2000
2001 pci_dma_read(d, tx_addr,
2002 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2003 s->cplus_txbuffer_offset += txsize;
2004
2005 /* seek to next Rx descriptor */
2006 if (txdw0 & CP_TX_EOR)
2007 {
2008 s->currCPlusTxDesc = 0;
2009 }
2010 else
2011 {
2012 ++s->currCPlusTxDesc;
2013 if (s->currCPlusTxDesc >= 64)
2014 s->currCPlusTxDesc = 0;
2015 }
2016
2017 /* Build the Tx Status Descriptor */
2018 uint32_t tx_status = txdw0;
2019
2020 /* transfer ownership to target */
2021 tx_status &= ~CP_TX_OWN;
2022
2023 /* reset error indicator bits */
2024 tx_status &= ~CP_TX_STATUS_UNF;
2025 tx_status &= ~CP_TX_STATUS_TES;
2026 tx_status &= ~CP_TX_STATUS_OWC;
2027 tx_status &= ~CP_TX_STATUS_LNKF;
2028 tx_status &= ~CP_TX_STATUS_EXC;
2029
2030 /* update ring data */
2031 val = cpu_to_le32(tx_status);
2032 pci_dma_write(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
2033
2034 /* Now decide if descriptor being processed is holding the last segment of packet */
2035 if (txdw0 & CP_TX_LS)
2036 {
2037 uint8_t dot1q_buffer_space[VLAN_HLEN];
2038 uint16_t *dot1q_buffer;
2039
2040 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2041 descriptor);
2042
2043 /* can transfer fully assembled packet */
2044
2045 uint8_t *saved_buffer = s->cplus_txbuffer;
2046 int saved_size = s->cplus_txbuffer_offset;
2047 int saved_buffer_len = s->cplus_txbuffer_len;
2048
2049 /* create vlan tag */
2050 if (txdw1 & CP_TX_TAGC) {
2051 /* the vlan tag is in BE byte order in the descriptor
2052 * BE + le_to_cpu() + ~swap()~ = cpu */
2053 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2054 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
2055
2056 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2057 dot1q_buffer[0] = cpu_to_be16(ETH_P_VLAN);
2058 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2059 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2060 } else {
2061 dot1q_buffer = NULL;
2062 }
2063
2064 /* reset the card space to protect from recursive call */
2065 s->cplus_txbuffer = NULL;
2066 s->cplus_txbuffer_offset = 0;
2067 s->cplus_txbuffer_len = 0;
2068
2069 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
2070 {
2071 DPRINTF("+++ C+ mode offloaded task checksum\n");
2072
2073 /* Large enough for Ethernet and IP headers? */
2074 if (saved_size < ETH_HLEN + sizeof(struct ip_header)) {
2075 goto skip_offload;
2076 }
2077
2078 /* ip packet header */
2079 struct ip_header *ip = NULL;
2080 int hlen = 0;
2081 uint8_t ip_protocol = 0;
2082 uint16_t ip_data_len = 0;
2083
2084 uint8_t *eth_payload_data = NULL;
2085 size_t eth_payload_len = 0;
2086
2087 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
2088 if (proto != ETH_P_IP)
2089 {
2090 goto skip_offload;
2091 }
2092
2093 DPRINTF("+++ C+ mode has IP packet\n");
2094
2095 /* Note on memory alignment: eth_payload_data is 16-bit aligned
2096 * since saved_buffer is allocated with g_malloc() and ETH_HLEN is
2097 * even. 32-bit accesses must use ldl/stl wrappers to avoid
2098 * unaligned accesses.
2099 */
2100 eth_payload_data = saved_buffer + ETH_HLEN;
2101 eth_payload_len = saved_size - ETH_HLEN;
2102
2103 ip = (struct ip_header*)eth_payload_data;
2104
2105 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2106 DPRINTF("+++ C+ mode packet has bad IP version %d "
2107 "expected %d\n", IP_HEADER_VERSION(ip),
2108 IP_HEADER_VERSION_4);
2109 goto skip_offload;
2110 }
2111
2112 hlen = IP_HDR_GET_LEN(ip);
2113 if (hlen < sizeof(struct ip_header) || hlen > eth_payload_len) {
2114 goto skip_offload;
2115 }
2116
2117 ip_protocol = ip->ip_p;
2118
2119 ip_data_len = be16_to_cpu(ip->ip_len);
2120 if (ip_data_len < hlen || ip_data_len > eth_payload_len) {
2121 goto skip_offload;
2122 }
2123 ip_data_len -= hlen;
2124
2125 if (!(txdw0 & CP_TX_LGSEN) && (txdw0 & CP_TX_IPCS))
2126 {
2127 DPRINTF("+++ C+ mode need IP checksum\n");
2128
2129 ip->ip_sum = 0;
2130 ip->ip_sum = ip_checksum(ip, hlen);
2131 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2132 hlen, ip->ip_sum);
2133 }
2134
2135 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2136 {
2137 /* Large enough for the TCP header? */
2138 if (ip_data_len < sizeof(tcp_header)) {
2139 goto skip_offload;
2140 }
2141
2142 int large_send_mss = (txdw0 >> CP_TC_LGSEN_MSS_SHIFT) &
2143 CP_TC_LGSEN_MSS_MASK;
2144 if (large_send_mss == 0) {
2145 goto skip_offload;
2146 }
2147
2148 DPRINTF("+++ C+ mode offloaded task TSO IP data %d "
2149 "frame data %d specified MSS=%d\n",
2150 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
2151
2152 int tcp_send_offset = 0;
2153
2154 /* maximum IP header length is 60 bytes */
2155 uint8_t saved_ip_header[60];
2156
2157 /* save IP header template; data area is used in tcp checksum calculation */
2158 memcpy(saved_ip_header, eth_payload_data, hlen);
2159
2160 /* a placeholder for checksum calculation routine in tcp case */
2161 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2162 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2163
2164 /* pointer to TCP header */
2165 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2166
2167 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2168
2169 /* Invalid TCP data offset? */
2170 if (tcp_hlen < sizeof(tcp_header) || tcp_hlen > ip_data_len) {
2171 goto skip_offload;
2172 }
2173
2174 int tcp_data_len = ip_data_len - tcp_hlen;
2175
2176 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2177 "data len %d\n", ip_data_len, tcp_hlen, tcp_data_len);
2178
2179 /* note the cycle below overwrites IP header data,
2180 but restores it from saved_ip_header before sending packet */
2181
2182 int is_last_frame = 0;
2183
2184 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += large_send_mss)
2185 {
2186 uint16_t chunk_size = large_send_mss;
2187
2188 /* check if this is the last frame */
2189 if (tcp_send_offset + large_send_mss >= tcp_data_len)
2190 {
2191 is_last_frame = 1;
2192 chunk_size = tcp_data_len - tcp_send_offset;
2193 }
2194
2195 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2196 ldl_be_p(&p_tcp_hdr->th_seq));
2197
2198 /* add 4 TCP pseudoheader fields */
2199 /* copy IP source and destination fields */
2200 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2201
2202 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2203 "packet with %d bytes data\n", tcp_hlen +
2204 chunk_size);
2205
2206 if (tcp_send_offset)
2207 {
2208 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2209 }
2210
2211 /* keep PUSH and FIN flags only for the last frame */
2212 if (!is_last_frame)
2213 {
2214 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TH_PUSH | TH_FIN);
2215 }
2216
2217 /* recalculate TCP checksum */
2218 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2219 p_tcpip_hdr->zeros = 0;
2220 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2221 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2222
2223 p_tcp_hdr->th_sum = 0;
2224
2225 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2226 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2227 tcp_checksum);
2228
2229 p_tcp_hdr->th_sum = tcp_checksum;
2230
2231 /* restore IP header */
2232 memcpy(eth_payload_data, saved_ip_header, hlen);
2233
2234 /* set IP data length and recalculate IP checksum */
2235 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2236
2237 /* increment IP id for subsequent frames */
2238 ip->ip_id = cpu_to_be16(tcp_send_offset/large_send_mss + be16_to_cpu(ip->ip_id));
2239
2240 ip->ip_sum = 0;
2241 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2242 DPRINTF("+++ C+ mode TSO IP header len=%d "
2243 "checksum=%04x\n", hlen, ip->ip_sum);
2244
2245 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2246 DPRINTF("+++ C+ mode TSO transferring packet size "
2247 "%d\n", tso_send_size);
2248 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2249 0, (uint8_t *) dot1q_buffer);
2250
2251 /* add transferred count to TCP sequence number */
2252 stl_be_p(&p_tcp_hdr->th_seq,
2253 chunk_size + ldl_be_p(&p_tcp_hdr->th_seq));
2254 }
2255
2256 /* Stop sending this frame */
2257 saved_size = 0;
2258 }
2259 else if (!(txdw0 & CP_TX_LGSEN) && (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS)))
2260 {
2261 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
2262
2263 /* maximum IP header length is 60 bytes */
2264 uint8_t saved_ip_header[60];
2265 memcpy(saved_ip_header, eth_payload_data, hlen);
2266
2267 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2268 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2269
2270 /* add 4 TCP pseudoheader fields */
2271 /* copy IP source and destination fields */
2272 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2273
2274 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2275 {
2276 DPRINTF("+++ C+ mode calculating TCP checksum for "
2277 "packet with %d bytes data\n", ip_data_len);
2278
2279 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2280 p_tcpip_hdr->zeros = 0;
2281 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2282 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2283
2284 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2285
2286 p_tcp_hdr->th_sum = 0;
2287
2288 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2289 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2290 tcp_checksum);
2291
2292 p_tcp_hdr->th_sum = tcp_checksum;
2293 }
2294 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2295 {
2296 DPRINTF("+++ C+ mode calculating UDP checksum for "
2297 "packet with %d bytes data\n", ip_data_len);
2298
2299 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2300 p_udpip_hdr->zeros = 0;
2301 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2302 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2303
2304 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2305
2306 p_udp_hdr->uh_sum = 0;
2307
2308 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2309 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2310 udp_checksum);
2311
2312 p_udp_hdr->uh_sum = udp_checksum;
2313 }
2314
2315 /* restore IP header */
2316 memcpy(eth_payload_data, saved_ip_header, hlen);
2317 }
2318 }
2319
2320 skip_offload:
2321 /* update tally counter */
2322 ++s->tally_counters.TxOk;
2323
2324 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
2325
2326 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2327 (uint8_t *) dot1q_buffer);
2328
2329 /* restore card space if there was no recursion and reset offset */
2330 if (!s->cplus_txbuffer)
2331 {
2332 s->cplus_txbuffer = saved_buffer;
2333 s->cplus_txbuffer_len = saved_buffer_len;
2334 s->cplus_txbuffer_offset = 0;
2335 }
2336 else
2337 {
2338 g_free(saved_buffer);
2339 }
2340 }
2341 else
2342 {
2343 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
2344 }
2345
2346 return 1;
2347 }
2348
rtl8139_cplus_transmit(RTL8139State * s)2349 static void rtl8139_cplus_transmit(RTL8139State *s)
2350 {
2351 int txcount = 0;
2352
2353 while (txcount < 64 && rtl8139_cplus_transmit_one(s))
2354 {
2355 ++txcount;
2356 }
2357
2358 /* Mark transfer completed */
2359 if (!txcount)
2360 {
2361 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2362 s->currCPlusTxDesc);
2363 }
2364 else
2365 {
2366 /* update interrupt status */
2367 s->IntrStatus |= TxOK;
2368 rtl8139_update_irq(s);
2369 }
2370 }
2371
rtl8139_transmit(RTL8139State * s)2372 static void rtl8139_transmit(RTL8139State *s)
2373 {
2374 int descriptor = s->currTxDesc, txcount = 0;
2375
2376 /*while*/
2377 if (rtl8139_transmit_one(s, descriptor))
2378 {
2379 ++s->currTxDesc;
2380 s->currTxDesc %= 4;
2381 ++txcount;
2382 }
2383
2384 /* Mark transfer completed */
2385 if (!txcount)
2386 {
2387 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2388 s->currTxDesc);
2389 }
2390 }
2391
rtl8139_TxStatus_write(RTL8139State * s,uint32_t txRegOffset,uint32_t val)2392 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2393 {
2394
2395 int descriptor = txRegOffset/4;
2396
2397 /* handle C+ transmit mode register configuration */
2398
2399 if (s->cplus_enabled)
2400 {
2401 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2402 "descriptor=%d\n", txRegOffset, val, descriptor);
2403
2404 /* handle Dump Tally Counters command */
2405 s->TxStatus[descriptor] = val;
2406
2407 if (descriptor == 0 && (val & 0x8))
2408 {
2409 hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2410
2411 /* dump tally counters to specified memory location */
2412 RTL8139TallyCounters_dma_write(s, tc_addr);
2413
2414 /* mark dump completed */
2415 s->TxStatus[0] &= ~0x8;
2416 }
2417
2418 return;
2419 }
2420
2421 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2422 txRegOffset, val, descriptor);
2423
2424 /* mask only reserved bits */
2425 val &= ~0xff00c000; /* these bits are reset on write */
2426 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2427
2428 s->TxStatus[descriptor] = val;
2429
2430 /* attempt to start transmission */
2431 rtl8139_transmit(s);
2432 }
2433
rtl8139_TxStatus_TxAddr_read(RTL8139State * s,uint32_t regs[],uint32_t base,uint8_t addr,int size)2434 static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[],
2435 uint32_t base, uint8_t addr,
2436 int size)
2437 {
2438 uint32_t reg = (addr - base) / 4;
2439 uint32_t offset = addr & 0x3;
2440 uint32_t ret = 0;
2441
2442 if (addr & (size - 1)) {
2443 DPRINTF("not implemented read for TxStatus/TxAddr "
2444 "addr=0x%x size=0x%x\n", addr, size);
2445 return ret;
2446 }
2447
2448 switch (size) {
2449 case 1: /* fall through */
2450 case 2: /* fall through */
2451 case 4:
2452 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1);
2453 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n",
2454 reg, addr, size, ret);
2455 break;
2456 default:
2457 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size);
2458 break;
2459 }
2460
2461 return ret;
2462 }
2463
rtl8139_TSAD_read(RTL8139State * s)2464 static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2465 {
2466 uint16_t ret = 0;
2467
2468 /* Simulate TSAD, it is read only anyway */
2469
2470 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2471 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2472 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2473 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2474
2475 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2476 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2477 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2478 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2479
2480 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2481 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2482 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2483 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2484
2485 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2486 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2487 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2488 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2489
2490
2491 DPRINTF("TSAD read val=0x%04x\n", ret);
2492
2493 return ret;
2494 }
2495
rtl8139_CSCR_read(RTL8139State * s)2496 static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2497 {
2498 uint16_t ret = s->CSCR;
2499
2500 DPRINTF("CSCR read val=0x%04x\n", ret);
2501
2502 return ret;
2503 }
2504
rtl8139_TxAddr_write(RTL8139State * s,uint32_t txAddrOffset,uint32_t val)2505 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2506 {
2507 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
2508
2509 s->TxAddr[txAddrOffset/4] = val;
2510 }
2511
rtl8139_TxAddr_read(RTL8139State * s,uint32_t txAddrOffset)2512 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2513 {
2514 uint32_t ret = s->TxAddr[txAddrOffset/4];
2515
2516 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
2517
2518 return ret;
2519 }
2520
rtl8139_RxBufPtr_write(RTL8139State * s,uint32_t val)2521 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2522 {
2523 DPRINTF("RxBufPtr write val=0x%04x\n", val);
2524
2525 /* this value is off by 16 */
2526 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2527
2528 /* more buffer space may be available so try to receive */
2529 qemu_flush_queued_packets(qemu_get_queue(s->nic));
2530
2531 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2532 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
2533 }
2534
rtl8139_RxBufPtr_read(RTL8139State * s)2535 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2536 {
2537 /* this value is off by 16 */
2538 uint32_t ret = s->RxBufPtr - 0x10;
2539
2540 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
2541
2542 return ret;
2543 }
2544
rtl8139_RxBufAddr_read(RTL8139State * s)2545 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2546 {
2547 /* this value is NOT off by 16 */
2548 uint32_t ret = s->RxBufAddr;
2549
2550 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
2551
2552 return ret;
2553 }
2554
rtl8139_RxBuf_write(RTL8139State * s,uint32_t val)2555 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2556 {
2557 DPRINTF("RxBuf write val=0x%08x\n", val);
2558
2559 s->RxBuf = val;
2560
2561 /* may need to reset rxring here */
2562 }
2563
rtl8139_RxBuf_read(RTL8139State * s)2564 static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2565 {
2566 uint32_t ret = s->RxBuf;
2567
2568 DPRINTF("RxBuf read val=0x%08x\n", ret);
2569
2570 return ret;
2571 }
2572
rtl8139_IntrMask_write(RTL8139State * s,uint32_t val)2573 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2574 {
2575 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
2576
2577 /* mask unwritable bits */
2578 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2579
2580 s->IntrMask = val;
2581
2582 rtl8139_update_irq(s);
2583
2584 }
2585
rtl8139_IntrMask_read(RTL8139State * s)2586 static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2587 {
2588 uint32_t ret = s->IntrMask;
2589
2590 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
2591
2592 return ret;
2593 }
2594
rtl8139_IntrStatus_write(RTL8139State * s,uint32_t val)2595 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2596 {
2597 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
2598
2599 #if 0
2600
2601 /* writing to ISR has no effect */
2602
2603 return;
2604
2605 #else
2606 uint16_t newStatus = s->IntrStatus & ~val;
2607
2608 /* mask unwritable bits */
2609 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2610
2611 /* writing 1 to interrupt status register bit clears it */
2612 s->IntrStatus = 0;
2613 rtl8139_update_irq(s);
2614
2615 s->IntrStatus = newStatus;
2616 rtl8139_set_next_tctr_time(s);
2617 rtl8139_update_irq(s);
2618
2619 #endif
2620 }
2621
rtl8139_IntrStatus_read(RTL8139State * s)2622 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2623 {
2624 uint32_t ret = s->IntrStatus;
2625
2626 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
2627
2628 #if 0
2629
2630 /* reading ISR clears all interrupts */
2631 s->IntrStatus = 0;
2632
2633 rtl8139_update_irq(s);
2634
2635 #endif
2636
2637 return ret;
2638 }
2639
rtl8139_MultiIntr_write(RTL8139State * s,uint32_t val)2640 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2641 {
2642 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
2643
2644 /* mask unwritable bits */
2645 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2646
2647 s->MultiIntr = val;
2648 }
2649
rtl8139_MultiIntr_read(RTL8139State * s)2650 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2651 {
2652 uint32_t ret = s->MultiIntr;
2653
2654 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
2655
2656 return ret;
2657 }
2658
rtl8139_io_writeb(void * opaque,uint8_t addr,uint32_t val)2659 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2660 {
2661 RTL8139State *s = opaque;
2662
2663 switch (addr)
2664 {
2665 case MAC0 ... MAC0+4:
2666 s->phys[addr - MAC0] = val;
2667 break;
2668 case MAC0+5:
2669 s->phys[addr - MAC0] = val;
2670 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys);
2671 break;
2672 case MAC0+6 ... MAC0+7:
2673 /* reserved */
2674 break;
2675 case MAR0 ... MAR0+7:
2676 s->mult[addr - MAR0] = val;
2677 break;
2678 case ChipCmd:
2679 rtl8139_ChipCmd_write(s, val);
2680 break;
2681 case Cfg9346:
2682 rtl8139_Cfg9346_write(s, val);
2683 break;
2684 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2685 rtl8139_TxConfig_writeb(s, val);
2686 break;
2687 case Config0:
2688 rtl8139_Config0_write(s, val);
2689 break;
2690 case Config1:
2691 rtl8139_Config1_write(s, val);
2692 break;
2693 case Config3:
2694 rtl8139_Config3_write(s, val);
2695 break;
2696 case Config4:
2697 rtl8139_Config4_write(s, val);
2698 break;
2699 case Config5:
2700 rtl8139_Config5_write(s, val);
2701 break;
2702 case MediaStatus:
2703 /* ignore */
2704 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2705 val);
2706 break;
2707
2708 case HltClk:
2709 DPRINTF("HltClk write val=0x%08x\n", val);
2710 if (val == 'R')
2711 {
2712 s->clock_enabled = 1;
2713 }
2714 else if (val == 'H')
2715 {
2716 s->clock_enabled = 0;
2717 }
2718 break;
2719
2720 case TxThresh:
2721 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
2722 s->TxThresh = val;
2723 break;
2724
2725 case TxPoll:
2726 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
2727 if (val & (1 << 7))
2728 {
2729 DPRINTF("C+ TxPoll high priority transmission (not "
2730 "implemented)\n");
2731 //rtl8139_cplus_transmit(s);
2732 }
2733 if (val & (1 << 6))
2734 {
2735 DPRINTF("C+ TxPoll normal priority transmission\n");
2736 rtl8139_cplus_transmit(s);
2737 }
2738
2739 break;
2740 case RxConfig:
2741 DPRINTF("RxConfig write(b) val=0x%02x\n", val);
2742 rtl8139_RxConfig_write(s,
2743 (rtl8139_RxConfig_read(s) & 0xFFFFFF00) | val);
2744 break;
2745 default:
2746 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2747 val);
2748 break;
2749 }
2750 }
2751
rtl8139_io_writew(void * opaque,uint8_t addr,uint32_t val)2752 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2753 {
2754 RTL8139State *s = opaque;
2755
2756 switch (addr)
2757 {
2758 case IntrMask:
2759 rtl8139_IntrMask_write(s, val);
2760 break;
2761
2762 case IntrStatus:
2763 rtl8139_IntrStatus_write(s, val);
2764 break;
2765
2766 case MultiIntr:
2767 rtl8139_MultiIntr_write(s, val);
2768 break;
2769
2770 case RxBufPtr:
2771 rtl8139_RxBufPtr_write(s, val);
2772 break;
2773
2774 case BasicModeCtrl:
2775 rtl8139_BasicModeCtrl_write(s, val);
2776 break;
2777 case BasicModeStatus:
2778 rtl8139_BasicModeStatus_write(s, val);
2779 break;
2780 case NWayAdvert:
2781 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
2782 s->NWayAdvert = val;
2783 break;
2784 case NWayLPAR:
2785 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
2786 break;
2787 case NWayExpansion:
2788 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
2789 s->NWayExpansion = val;
2790 break;
2791
2792 case CpCmd:
2793 rtl8139_CpCmd_write(s, val);
2794 break;
2795
2796 case IntrMitigate:
2797 rtl8139_IntrMitigate_write(s, val);
2798 break;
2799
2800 default:
2801 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2802 addr, val);
2803
2804 rtl8139_io_writeb(opaque, addr, val & 0xff);
2805 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2806 break;
2807 }
2808 }
2809
rtl8139_set_next_tctr_time(RTL8139State * s)2810 static void rtl8139_set_next_tctr_time(RTL8139State *s)
2811 {
2812 const uint64_t ns_per_period = (uint64_t)PCI_PERIOD << 32;
2813
2814 DPRINTF("entered rtl8139_set_next_tctr_time\n");
2815
2816 /* This function is called at least once per period, so it is a good
2817 * place to update the timer base.
2818 *
2819 * After one iteration of this loop the value in the Timer register does
2820 * not change, but the device model is counting up by 2^32 ticks (approx.
2821 * 130 seconds).
2822 */
2823 while (s->TCTR_base + ns_per_period <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
2824 s->TCTR_base += ns_per_period;
2825 }
2826
2827 if (!s->TimerInt) {
2828 timer_del(s->timer);
2829 } else {
2830 uint64_t delta = (uint64_t)s->TimerInt * PCI_PERIOD;
2831 if (s->TCTR_base + delta <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
2832 delta += ns_per_period;
2833 }
2834 timer_mod(s->timer, s->TCTR_base + delta);
2835 }
2836 }
2837
rtl8139_io_writel(void * opaque,uint8_t addr,uint32_t val)2838 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2839 {
2840 RTL8139State *s = opaque;
2841
2842 switch (addr)
2843 {
2844 case RxMissed:
2845 DPRINTF("RxMissed clearing on write\n");
2846 s->RxMissed = 0;
2847 break;
2848
2849 case TxConfig:
2850 rtl8139_TxConfig_write(s, val);
2851 break;
2852
2853 case RxConfig:
2854 rtl8139_RxConfig_write(s, val);
2855 break;
2856
2857 case TxStatus0 ... TxStatus0+4*4-1:
2858 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2859 break;
2860
2861 case TxAddr0 ... TxAddr0+4*4-1:
2862 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2863 break;
2864
2865 case RxBuf:
2866 rtl8139_RxBuf_write(s, val);
2867 break;
2868
2869 case RxRingAddrLO:
2870 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
2871 s->RxRingAddrLO = val;
2872 break;
2873
2874 case RxRingAddrHI:
2875 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
2876 s->RxRingAddrHI = val;
2877 break;
2878
2879 case Timer:
2880 DPRINTF("TCTR Timer reset on write\n");
2881 s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2882 rtl8139_set_next_tctr_time(s);
2883 break;
2884
2885 case FlashReg:
2886 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
2887 if (s->TimerInt != val) {
2888 s->TimerInt = val;
2889 rtl8139_set_next_tctr_time(s);
2890 }
2891 break;
2892
2893 default:
2894 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2895 addr, val);
2896 rtl8139_io_writeb(opaque, addr, val & 0xff);
2897 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2898 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2899 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2900 break;
2901 }
2902 }
2903
rtl8139_io_readb(void * opaque,uint8_t addr)2904 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2905 {
2906 RTL8139State *s = opaque;
2907 int ret;
2908
2909 switch (addr)
2910 {
2911 case MAC0 ... MAC0+5:
2912 ret = s->phys[addr - MAC0];
2913 break;
2914 case MAC0+6 ... MAC0+7:
2915 ret = 0;
2916 break;
2917 case MAR0 ... MAR0+7:
2918 ret = s->mult[addr - MAR0];
2919 break;
2920 case TxStatus0 ... TxStatus0+4*4-1:
2921 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
2922 addr, 1);
2923 break;
2924 case ChipCmd:
2925 ret = rtl8139_ChipCmd_read(s);
2926 break;
2927 case Cfg9346:
2928 ret = rtl8139_Cfg9346_read(s);
2929 break;
2930 case Config0:
2931 ret = rtl8139_Config0_read(s);
2932 break;
2933 case Config1:
2934 ret = rtl8139_Config1_read(s);
2935 break;
2936 case Config3:
2937 ret = rtl8139_Config3_read(s);
2938 break;
2939 case Config4:
2940 ret = rtl8139_Config4_read(s);
2941 break;
2942 case Config5:
2943 ret = rtl8139_Config5_read(s);
2944 break;
2945
2946 case MediaStatus:
2947 /* The LinkDown bit of MediaStatus is inverse with link status */
2948 ret = 0xd0 | (~s->BasicModeStatus & 0x04);
2949 DPRINTF("MediaStatus read 0x%x\n", ret);
2950 break;
2951
2952 case HltClk:
2953 ret = s->clock_enabled;
2954 DPRINTF("HltClk read 0x%x\n", ret);
2955 break;
2956
2957 case PCIRevisionID:
2958 ret = RTL8139_PCI_REVID;
2959 DPRINTF("PCI Revision ID read 0x%x\n", ret);
2960 break;
2961
2962 case TxThresh:
2963 ret = s->TxThresh;
2964 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
2965 break;
2966
2967 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2968 ret = s->TxConfig >> 24;
2969 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
2970 break;
2971
2972 default:
2973 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
2974 ret = 0;
2975 break;
2976 }
2977
2978 return ret;
2979 }
2980
rtl8139_io_readw(void * opaque,uint8_t addr)2981 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2982 {
2983 RTL8139State *s = opaque;
2984 uint32_t ret;
2985
2986 switch (addr)
2987 {
2988 case TxAddr0 ... TxAddr0+4*4-1:
2989 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2);
2990 break;
2991 case IntrMask:
2992 ret = rtl8139_IntrMask_read(s);
2993 break;
2994
2995 case IntrStatus:
2996 ret = rtl8139_IntrStatus_read(s);
2997 break;
2998
2999 case MultiIntr:
3000 ret = rtl8139_MultiIntr_read(s);
3001 break;
3002
3003 case RxBufPtr:
3004 ret = rtl8139_RxBufPtr_read(s);
3005 break;
3006
3007 case RxBufAddr:
3008 ret = rtl8139_RxBufAddr_read(s);
3009 break;
3010
3011 case BasicModeCtrl:
3012 ret = rtl8139_BasicModeCtrl_read(s);
3013 break;
3014 case BasicModeStatus:
3015 ret = rtl8139_BasicModeStatus_read(s);
3016 break;
3017 case NWayAdvert:
3018 ret = s->NWayAdvert;
3019 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
3020 break;
3021 case NWayLPAR:
3022 ret = s->NWayLPAR;
3023 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
3024 break;
3025 case NWayExpansion:
3026 ret = s->NWayExpansion;
3027 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
3028 break;
3029
3030 case CpCmd:
3031 ret = rtl8139_CpCmd_read(s);
3032 break;
3033
3034 case IntrMitigate:
3035 ret = rtl8139_IntrMitigate_read(s);
3036 break;
3037
3038 case TxSummary:
3039 ret = rtl8139_TSAD_read(s);
3040 break;
3041
3042 case CSCR:
3043 ret = rtl8139_CSCR_read(s);
3044 break;
3045
3046 default:
3047 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
3048
3049 ret = rtl8139_io_readb(opaque, addr);
3050 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3051
3052 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
3053 break;
3054 }
3055
3056 return ret;
3057 }
3058
rtl8139_io_readl(void * opaque,uint8_t addr)3059 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3060 {
3061 RTL8139State *s = opaque;
3062 uint32_t ret;
3063
3064 switch (addr)
3065 {
3066 case RxMissed:
3067 ret = s->RxMissed;
3068
3069 DPRINTF("RxMissed read val=0x%08x\n", ret);
3070 break;
3071
3072 case TxConfig:
3073 ret = rtl8139_TxConfig_read(s);
3074 break;
3075
3076 case RxConfig:
3077 ret = rtl8139_RxConfig_read(s);
3078 break;
3079
3080 case TxStatus0 ... TxStatus0+4*4-1:
3081 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
3082 addr, 4);
3083 break;
3084
3085 case TxAddr0 ... TxAddr0+4*4-1:
3086 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3087 break;
3088
3089 case RxBuf:
3090 ret = rtl8139_RxBuf_read(s);
3091 break;
3092
3093 case RxRingAddrLO:
3094 ret = s->RxRingAddrLO;
3095 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
3096 break;
3097
3098 case RxRingAddrHI:
3099 ret = s->RxRingAddrHI;
3100 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
3101 break;
3102
3103 case Timer:
3104 ret = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base) /
3105 PCI_PERIOD;
3106 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
3107 break;
3108
3109 case FlashReg:
3110 ret = s->TimerInt;
3111 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
3112 break;
3113
3114 default:
3115 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
3116
3117 ret = rtl8139_io_readb(opaque, addr);
3118 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3119 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3120 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3121
3122 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
3123 break;
3124 }
3125
3126 return ret;
3127 }
3128
3129 /* */
3130
rtl8139_post_load(void * opaque,int version_id)3131 static int rtl8139_post_load(void *opaque, int version_id)
3132 {
3133 RTL8139State* s = opaque;
3134 rtl8139_set_next_tctr_time(s);
3135 if (version_id < 4) {
3136 s->cplus_enabled = s->CpCmd != 0;
3137 }
3138
3139 /* nc.link_down can't be migrated, so infer link_down according
3140 * to link status bit in BasicModeStatus */
3141 qemu_get_queue(s->nic)->link_down = (s->BasicModeStatus & 0x04) == 0;
3142
3143 return 0;
3144 }
3145
rtl8139_hotplug_ready_needed(void * opaque)3146 static bool rtl8139_hotplug_ready_needed(void *opaque)
3147 {
3148 return qdev_machine_modified();
3149 }
3150
3151 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3152 .name = "rtl8139/hotplug_ready",
3153 .version_id = 1,
3154 .minimum_version_id = 1,
3155 .needed = rtl8139_hotplug_ready_needed,
3156 .fields = (const VMStateField[]) {
3157 VMSTATE_END_OF_LIST()
3158 }
3159 };
3160
rtl8139_pre_save(void * opaque)3161 static int rtl8139_pre_save(void *opaque)
3162 {
3163 RTL8139State* s = opaque;
3164 int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
3165
3166 /* for migration to older versions */
3167 s->TCTR = (current_time - s->TCTR_base) / PCI_PERIOD;
3168 s->rtl8139_mmio_io_addr_dummy = 0;
3169
3170 return 0;
3171 }
3172
3173 static const VMStateDescription vmstate_rtl8139 = {
3174 .name = "rtl8139",
3175 .version_id = 5,
3176 .minimum_version_id = 3,
3177 .post_load = rtl8139_post_load,
3178 .pre_save = rtl8139_pre_save,
3179 .fields = (const VMStateField[]) {
3180 VMSTATE_PCI_DEVICE(parent_obj, RTL8139State),
3181 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3182 VMSTATE_BUFFER(mult, RTL8139State),
3183 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3184 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3185
3186 VMSTATE_UINT32(RxBuf, RTL8139State),
3187 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3188 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3189 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3190
3191 VMSTATE_UINT16(IntrStatus, RTL8139State),
3192 VMSTATE_UINT16(IntrMask, RTL8139State),
3193
3194 VMSTATE_UINT32(TxConfig, RTL8139State),
3195 VMSTATE_UINT32(RxConfig, RTL8139State),
3196 VMSTATE_UINT32(RxMissed, RTL8139State),
3197 VMSTATE_UINT16(CSCR, RTL8139State),
3198
3199 VMSTATE_UINT8(Cfg9346, RTL8139State),
3200 VMSTATE_UINT8(Config0, RTL8139State),
3201 VMSTATE_UINT8(Config1, RTL8139State),
3202 VMSTATE_UINT8(Config3, RTL8139State),
3203 VMSTATE_UINT8(Config4, RTL8139State),
3204 VMSTATE_UINT8(Config5, RTL8139State),
3205
3206 VMSTATE_UINT8(clock_enabled, RTL8139State),
3207 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3208
3209 VMSTATE_UINT16(MultiIntr, RTL8139State),
3210
3211 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3212 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3213 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3214 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3215 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3216
3217 VMSTATE_UINT16(CpCmd, RTL8139State),
3218 VMSTATE_UINT8(TxThresh, RTL8139State),
3219
3220 VMSTATE_UNUSED(4),
3221 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
3222 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
3223
3224 VMSTATE_UINT32(currTxDesc, RTL8139State),
3225 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3226 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3227 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3228 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3229
3230 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3231 VMSTATE_INT32(eeprom.mode, RTL8139State),
3232 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3233 VMSTATE_UINT8(eeprom.address, RTL8139State),
3234 VMSTATE_UINT16(eeprom.input, RTL8139State),
3235 VMSTATE_UINT16(eeprom.output, RTL8139State),
3236
3237 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3238 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3239 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3240 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3241
3242 VMSTATE_UINT32(TCTR, RTL8139State),
3243 VMSTATE_UINT32(TimerInt, RTL8139State),
3244 VMSTATE_INT64(TCTR_base, RTL8139State),
3245
3246 VMSTATE_UINT64(tally_counters.TxOk, RTL8139State),
3247 VMSTATE_UINT64(tally_counters.RxOk, RTL8139State),
3248 VMSTATE_UINT64(tally_counters.TxERR, RTL8139State),
3249 VMSTATE_UINT32(tally_counters.RxERR, RTL8139State),
3250 VMSTATE_UINT16(tally_counters.MissPkt, RTL8139State),
3251 VMSTATE_UINT16(tally_counters.FAE, RTL8139State),
3252 VMSTATE_UINT32(tally_counters.Tx1Col, RTL8139State),
3253 VMSTATE_UINT32(tally_counters.TxMCol, RTL8139State),
3254 VMSTATE_UINT64(tally_counters.RxOkPhy, RTL8139State),
3255 VMSTATE_UINT64(tally_counters.RxOkBrd, RTL8139State),
3256 VMSTATE_UINT32_V(tally_counters.RxOkMul, RTL8139State, 5),
3257 VMSTATE_UINT16(tally_counters.TxAbt, RTL8139State),
3258 VMSTATE_UINT16(tally_counters.TxUndrn, RTL8139State),
3259
3260 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3261 VMSTATE_END_OF_LIST()
3262 },
3263 .subsections = (const VMStateDescription * const []) {
3264 &vmstate_rtl8139_hotplug_ready,
3265 NULL
3266 }
3267 };
3268
3269 /***********************************************************/
3270 /* PCI RTL8139 definitions */
3271
rtl8139_ioport_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)3272 static void rtl8139_ioport_write(void *opaque, hwaddr addr,
3273 uint64_t val, unsigned size)
3274 {
3275 switch (size) {
3276 case 1:
3277 rtl8139_io_writeb(opaque, addr, val);
3278 break;
3279 case 2:
3280 rtl8139_io_writew(opaque, addr, val);
3281 break;
3282 case 4:
3283 rtl8139_io_writel(opaque, addr, val);
3284 break;
3285 }
3286 }
3287
rtl8139_ioport_read(void * opaque,hwaddr addr,unsigned size)3288 static uint64_t rtl8139_ioport_read(void *opaque, hwaddr addr,
3289 unsigned size)
3290 {
3291 switch (size) {
3292 case 1:
3293 return rtl8139_io_readb(opaque, addr);
3294 case 2:
3295 return rtl8139_io_readw(opaque, addr);
3296 case 4:
3297 return rtl8139_io_readl(opaque, addr);
3298 }
3299
3300 return -1;
3301 }
3302
3303 static const MemoryRegionOps rtl8139_io_ops = {
3304 .read = rtl8139_ioport_read,
3305 .write = rtl8139_ioport_write,
3306 .impl = {
3307 .min_access_size = 1,
3308 .max_access_size = 4,
3309 },
3310 .endianness = DEVICE_LITTLE_ENDIAN,
3311 };
3312
rtl8139_timer(void * opaque)3313 static void rtl8139_timer(void *opaque)
3314 {
3315 RTL8139State *s = opaque;
3316
3317 if (!s->clock_enabled)
3318 {
3319 DPRINTF(">>> timer: clock is not running\n");
3320 return;
3321 }
3322
3323 s->IntrStatus |= PCSTimeout;
3324 rtl8139_update_irq(s);
3325 rtl8139_set_next_tctr_time(s);
3326 }
3327
pci_rtl8139_uninit(PCIDevice * dev)3328 static void pci_rtl8139_uninit(PCIDevice *dev)
3329 {
3330 RTL8139State *s = RTL8139(dev);
3331
3332 g_free(s->cplus_txbuffer);
3333 s->cplus_txbuffer = NULL;
3334 timer_free(s->timer);
3335 qemu_del_nic(s->nic);
3336 }
3337
rtl8139_set_link_status(NetClientState * nc)3338 static void rtl8139_set_link_status(NetClientState *nc)
3339 {
3340 RTL8139State *s = qemu_get_nic_opaque(nc);
3341
3342 if (nc->link_down) {
3343 s->BasicModeStatus &= ~0x04;
3344 } else {
3345 s->BasicModeStatus |= 0x04;
3346 }
3347
3348 s->IntrStatus |= RxUnderrun;
3349 rtl8139_update_irq(s);
3350 }
3351
3352 static NetClientInfo net_rtl8139_info = {
3353 .type = NET_CLIENT_DRIVER_NIC,
3354 .size = sizeof(NICState),
3355 .can_receive = rtl8139_can_receive,
3356 .receive = rtl8139_receive,
3357 .link_status_changed = rtl8139_set_link_status,
3358 };
3359
pci_rtl8139_realize(PCIDevice * dev,Error ** errp)3360 static void pci_rtl8139_realize(PCIDevice *dev, Error **errp)
3361 {
3362 RTL8139State *s = RTL8139(dev);
3363 DeviceState *d = DEVICE(dev);
3364 uint8_t *pci_conf;
3365
3366 pci_conf = dev->config;
3367 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
3368 /* TODO: start of capability list, but no capability
3369 * list bit in status register, and offset 0xdc seems unused. */
3370 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
3371
3372 memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s,
3373 "rtl8139", 0x100);
3374 memory_region_init_alias(&s->bar_mem, OBJECT(s), "rtl8139-mem", &s->bar_io,
3375 0, 0x100);
3376
3377 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
3378 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
3379
3380 qemu_macaddr_default_if_unset(&s->conf.macaddr);
3381
3382 /* prepare eeprom */
3383 s->eeprom.contents[0] = 0x8129;
3384 #if 1
3385 /* PCI vendor and device ID should be mirrored here */
3386 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3387 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3388 #endif
3389 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3390 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3391 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3392
3393 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
3394 object_get_typename(OBJECT(dev)), d->id,
3395 &d->mem_reentrancy_guard, s);
3396 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
3397
3398 s->cplus_txbuffer = NULL;
3399 s->cplus_txbuffer_len = 0;
3400 s->cplus_txbuffer_offset = 0;
3401
3402 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s);
3403 }
3404
rtl8139_instance_init(Object * obj)3405 static void rtl8139_instance_init(Object *obj)
3406 {
3407 RTL8139State *s = RTL8139(obj);
3408
3409 device_add_bootindex_property(obj, &s->conf.bootindex,
3410 "bootindex", "/ethernet-phy@0",
3411 DEVICE(obj));
3412 }
3413
3414 static const Property rtl8139_properties[] = {
3415 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3416 };
3417
rtl8139_class_init(ObjectClass * klass,const void * data)3418 static void rtl8139_class_init(ObjectClass *klass, const void *data)
3419 {
3420 DeviceClass *dc = DEVICE_CLASS(klass);
3421 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3422
3423 k->realize = pci_rtl8139_realize;
3424 k->exit = pci_rtl8139_uninit;
3425 k->romfile = "efi-rtl8139.rom";
3426 k->vendor_id = PCI_VENDOR_ID_REALTEK;
3427 k->device_id = PCI_DEVICE_ID_REALTEK_8139;
3428 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
3429 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
3430 device_class_set_legacy_reset(dc, rtl8139_reset);
3431 dc->vmsd = &vmstate_rtl8139;
3432 device_class_set_props(dc, rtl8139_properties);
3433 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
3434 }
3435
3436 static const TypeInfo rtl8139_info = {
3437 .name = TYPE_RTL8139,
3438 .parent = TYPE_PCI_DEVICE,
3439 .instance_size = sizeof(RTL8139State),
3440 .class_init = rtl8139_class_init,
3441 .instance_init = rtl8139_instance_init,
3442 .interfaces = (const InterfaceInfo[]) {
3443 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
3444 { },
3445 },
3446 };
3447
rtl8139_register_types(void)3448 static void rtl8139_register_types(void)
3449 {
3450 type_register_static(&rtl8139_info);
3451 }
3452
3453 type_init(rtl8139_register_types)
3454