xref: /openbmc/linux/drivers/dma/fsl-edma-common.h (revision ed4543328f7108e1047b83b96ca7f7208747d930) 
1  /* SPDX-License-Identifier: GPL-2.0+ */
2  /*
3   * Copyright 2013-2014 Freescale Semiconductor, Inc.
4   * Copyright 2018 Angelo Dureghello <angelo@sysam.it>
5   */
6  #ifndef _FSL_EDMA_COMMON_H_
7  #define _FSL_EDMA_COMMON_H_
8  
9  #include <linux/dma-direction.h>
10  #include <linux/platform_device.h>
11  #include "virt-dma.h"
12  
13  #define EDMA_CR_EDBG		BIT(1)
14  #define EDMA_CR_ERCA		BIT(2)
15  #define EDMA_CR_ERGA		BIT(3)
16  #define EDMA_CR_HOE		BIT(4)
17  #define EDMA_CR_HALT		BIT(5)
18  #define EDMA_CR_CLM		BIT(6)
19  #define EDMA_CR_EMLM		BIT(7)
20  #define EDMA_CR_ECX		BIT(16)
21  #define EDMA_CR_CX		BIT(17)
22  
23  #define EDMA_SEEI_SEEI(x)	((x) & GENMASK(4, 0))
24  #define EDMA_CEEI_CEEI(x)	((x) & GENMASK(4, 0))
25  #define EDMA_CINT_CINT(x)	((x) & GENMASK(4, 0))
26  #define EDMA_CERR_CERR(x)	((x) & GENMASK(4, 0))
27  
28  #define EDMA_TCD_ATTR_DSIZE(x)		(((x) & GENMASK(2, 0)))
29  #define EDMA_TCD_ATTR_DMOD(x)		(((x) & GENMASK(4, 0)) << 3)
30  #define EDMA_TCD_ATTR_SSIZE(x)		(((x) & GENMASK(2, 0)) << 8)
31  #define EDMA_TCD_ATTR_SMOD(x)		(((x) & GENMASK(4, 0)) << 11)
32  
33  #define EDMA_TCD_ITER_MASK		GENMASK(14, 0)
34  #define EDMA_TCD_CITER_CITER(x)		((x) & EDMA_TCD_ITER_MASK)
35  #define EDMA_TCD_BITER_BITER(x)		((x) & EDMA_TCD_ITER_MASK)
36  
37  #define EDMA_TCD_CSR_START		BIT(0)
38  #define EDMA_TCD_CSR_INT_MAJOR		BIT(1)
39  #define EDMA_TCD_CSR_INT_HALF		BIT(2)
40  #define EDMA_TCD_CSR_D_REQ		BIT(3)
41  #define EDMA_TCD_CSR_E_SG		BIT(4)
42  #define EDMA_TCD_CSR_E_LINK		BIT(5)
43  #define EDMA_TCD_CSR_ACTIVE		BIT(6)
44  #define EDMA_TCD_CSR_DONE		BIT(7)
45  
46  #define EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(x) ((x) & GENMASK(9, 0))
47  #define EDMA_V3_TCD_NBYTES_MLOFF(x)        (x << 10)
48  #define EDMA_V3_TCD_NBYTES_DMLOE           (1 << 30)
49  #define EDMA_V3_TCD_NBYTES_SMLOE           (1 << 31)
50  
51  #define EDMAMUX_CHCFG_DIS		0x0
52  #define EDMAMUX_CHCFG_ENBL		0x80
53  #define EDMAMUX_CHCFG_SOURCE(n)		((n) & 0x3F)
54  
55  #define DMAMUX_NR	2
56  
57  #define EDMA_TCD                0x1000
58  
59  #define FSL_EDMA_BUSWIDTHS	(BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
60  				 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
61  				 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
62  				 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
63  
64  #define EDMA_V3_CH_SBR_RD          BIT(22)
65  #define EDMA_V3_CH_SBR_WR          BIT(21)
66  #define EDMA_V3_CH_CSR_ERQ         BIT(0)
67  #define EDMA_V3_CH_CSR_EARQ        BIT(1)
68  #define EDMA_V3_CH_CSR_EEI         BIT(2)
69  #define EDMA_V3_CH_CSR_DONE        BIT(30)
70  #define EDMA_V3_CH_CSR_ACTIVE      BIT(31)
71  
72  enum fsl_edma_pm_state {
73  	RUNNING = 0,
74  	SUSPENDED,
75  };
76  
77  struct fsl_edma_hw_tcd {
78  	__le32	saddr;
79  	__le16	soff;
80  	__le16	attr;
81  	__le32	nbytes;
82  	__le32	slast;
83  	__le32	daddr;
84  	__le16	doff;
85  	__le16	citer;
86  	__le32	dlast_sga;
87  	__le16	csr;
88  	__le16	biter;
89  };
90  
91  struct fsl_edma3_ch_reg {
92  	__le32	ch_csr;
93  	__le32	ch_es;
94  	__le32	ch_int;
95  	__le32	ch_sbr;
96  	__le32	ch_pri;
97  	__le32	ch_mux;
98  	__le32  ch_mattr; /* edma4, reserved for edma3 */
99  	__le32  ch_reserved;
100  	struct fsl_edma_hw_tcd tcd;
101  } __packed;
102  
103  /*
104   * These are iomem pointers, for both v32 and v64.
105   */
106  struct edma_regs {
107  	void __iomem *cr;
108  	void __iomem *es;
109  	void __iomem *erqh;
110  	void __iomem *erql;	/* aka erq on v32 */
111  	void __iomem *eeih;
112  	void __iomem *eeil;	/* aka eei on v32 */
113  	void __iomem *seei;
114  	void __iomem *ceei;
115  	void __iomem *serq;
116  	void __iomem *cerq;
117  	void __iomem *cint;
118  	void __iomem *cerr;
119  	void __iomem *ssrt;
120  	void __iomem *cdne;
121  	void __iomem *inth;
122  	void __iomem *intl;
123  	void __iomem *errh;
124  	void __iomem *errl;
125  };
126  
127  struct fsl_edma_sw_tcd {
128  	dma_addr_t			ptcd;
129  	struct fsl_edma_hw_tcd		*vtcd;
130  };
131  
132  struct fsl_edma_chan {
133  	struct virt_dma_chan		vchan;
134  	enum dma_status			status;
135  	enum fsl_edma_pm_state		pm_state;
136  	bool				idle;
137  	u32				slave_id;
138  	struct fsl_edma_engine		*edma;
139  	struct fsl_edma_desc		*edesc;
140  	struct dma_slave_config		cfg;
141  	u32				attr;
142  	bool                            is_sw;
143  	struct dma_pool			*tcd_pool;
144  	dma_addr_t			dma_dev_addr;
145  	u32				dma_dev_size;
146  	enum dma_data_direction		dma_dir;
147  	char				chan_name[32];
148  	struct fsl_edma_hw_tcd __iomem *tcd;
149  	void __iomem			*mux_addr;
150  	u32				real_count;
151  	struct work_struct		issue_worker;
152  	struct platform_device		*pdev;
153  	struct device			*pd_dev;
154  	struct device_link		*pd_dev_link;
155  	u32				srcid;
156  	struct clk			*clk;
157  	int                             priority;
158  	int				hw_chanid;
159  	int				txirq;
160  	bool				is_rxchan;
161  	bool				is_remote;
162  	bool				is_multi_fifo;
163  };
164  
165  struct fsl_edma_desc {
166  	struct virt_dma_desc		vdesc;
167  	struct fsl_edma_chan		*echan;
168  	bool				iscyclic;
169  	enum dma_transfer_direction	dirn;
170  	unsigned int			n_tcds;
171  	struct fsl_edma_sw_tcd		tcd[];
172  };
173  
174  #define FSL_EDMA_DRV_HAS_DMACLK		BIT(0)
175  #define FSL_EDMA_DRV_MUX_SWAP		BIT(1)
176  #define FSL_EDMA_DRV_CONFIG32		BIT(2)
177  #define FSL_EDMA_DRV_WRAP_IO		BIT(3)
178  #define FSL_EDMA_DRV_EDMA64		BIT(4)
179  #define FSL_EDMA_DRV_HAS_PD		BIT(5)
180  #define FSL_EDMA_DRV_HAS_CHCLK		BIT(6)
181  #define FSL_EDMA_DRV_HAS_CHMUX		BIT(7)
182  #define FSL_EDMA_DRV_MEM_REMOTE		BIT(8)
183  /* control and status register is in tcd address space, edma3 reg layout */
184  #define FSL_EDMA_DRV_SPLIT_REG		BIT(9)
185  #define FSL_EDMA_DRV_BUS_8BYTE		BIT(10)
186  #define FSL_EDMA_DRV_DEV_TO_DEV		BIT(11)
187  #define FSL_EDMA_DRV_ALIGN_64BYTE	BIT(12)
188  /* Need clean CHn_CSR DONE before enable TCD's ESG */
189  #define FSL_EDMA_DRV_CLEAR_DONE_E_SG	BIT(13)
190  /* Need clean CHn_CSR DONE before enable TCD's MAJORELINK */
191  #define FSL_EDMA_DRV_CLEAR_DONE_E_LINK	BIT(14)
192  
193  #define FSL_EDMA_DRV_EDMA3	(FSL_EDMA_DRV_SPLIT_REG |	\
194  				 FSL_EDMA_DRV_BUS_8BYTE |	\
195  				 FSL_EDMA_DRV_DEV_TO_DEV |	\
196  				 FSL_EDMA_DRV_ALIGN_64BYTE |	\
197  				 FSL_EDMA_DRV_CLEAR_DONE_E_SG |	\
198  				 FSL_EDMA_DRV_CLEAR_DONE_E_LINK)
199  
200  #define FSL_EDMA_DRV_EDMA4	(FSL_EDMA_DRV_SPLIT_REG |	\
201  				 FSL_EDMA_DRV_BUS_8BYTE |	\
202  				 FSL_EDMA_DRV_DEV_TO_DEV |	\
203  				 FSL_EDMA_DRV_ALIGN_64BYTE |	\
204  				 FSL_EDMA_DRV_CLEAR_DONE_E_LINK)
205  
206  struct fsl_edma_drvdata {
207  	u32			dmamuxs; /* only used before v3 */
208  	u32			chreg_off;
209  	u32			chreg_space_sz;
210  	u32			flags;
211  	u32			mux_off;	/* channel mux register offset */
212  	u32			mux_skip;	/* how much skip for each channel */
213  	int			(*setup_irq)(struct platform_device *pdev,
214  					     struct fsl_edma_engine *fsl_edma);
215  };
216  
217  struct fsl_edma_engine {
218  	struct dma_device	dma_dev;
219  	void __iomem		*membase;
220  	void __iomem		*muxbase[DMAMUX_NR];
221  	struct clk		*muxclk[DMAMUX_NR];
222  	struct clk		*dmaclk;
223  	struct clk		*chclk;
224  	struct mutex		fsl_edma_mutex;
225  	const struct fsl_edma_drvdata *drvdata;
226  	u32			n_chans;
227  	int			txirq;
228  	int			errirq;
229  	bool			big_endian;
230  	struct edma_regs	regs;
231  	u64			chan_masked;
232  	struct fsl_edma_chan	chans[];
233  };
234  
235  #define edma_read_tcdreg(chan, __name)				\
236  (sizeof(chan->tcd->__name) == sizeof(u32) ?			\
237  	edma_readl(chan->edma, &chan->tcd->__name) :		\
238  	edma_readw(chan->edma, &chan->tcd->__name))
239  
240  #define edma_write_tcdreg(chan, val, __name)			\
241  (sizeof(chan->tcd->__name) == sizeof(u32) ?			\
242  	edma_writel(chan->edma, (u32 __force)val, &chan->tcd->__name) :	\
243  	edma_writew(chan->edma, (u16 __force)val, &chan->tcd->__name))
244  
245  #define edma_readl_chreg(chan, __name)				\
246  	edma_readl(chan->edma,					\
247  		   (void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name))
248  
249  #define edma_writel_chreg(chan, val,  __name)			\
250  	edma_writel(chan->edma, val,				\
251  		   (void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name))
252  
253  /*
254   * R/W functions for big- or little-endian registers:
255   * The eDMA controller's endian is independent of the CPU core's endian.
256   * For the big-endian IP module, the offset for 8-bit or 16-bit registers
257   * should also be swapped opposite to that in little-endian IP.
258   */
edma_readl(struct fsl_edma_engine * edma,void __iomem * addr)259  static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
260  {
261  	if (edma->big_endian)
262  		return ioread32be(addr);
263  	else
264  		return ioread32(addr);
265  }
266  
edma_readw(struct fsl_edma_engine * edma,void __iomem * addr)267  static inline u16 edma_readw(struct fsl_edma_engine *edma, void __iomem *addr)
268  {
269  	if (edma->big_endian)
270  		return ioread16be(addr);
271  	else
272  		return ioread16(addr);
273  }
274  
edma_writeb(struct fsl_edma_engine * edma,u8 val,void __iomem * addr)275  static inline void edma_writeb(struct fsl_edma_engine *edma,
276  			       u8 val, void __iomem *addr)
277  {
278  	/* swap the reg offset for these in big-endian mode */
279  	if (edma->big_endian)
280  		iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
281  	else
282  		iowrite8(val, addr);
283  }
284  
edma_writew(struct fsl_edma_engine * edma,u16 val,void __iomem * addr)285  static inline void edma_writew(struct fsl_edma_engine *edma,
286  			       u16 val, void __iomem *addr)
287  {
288  	/* swap the reg offset for these in big-endian mode */
289  	if (edma->big_endian)
290  		iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
291  	else
292  		iowrite16(val, addr);
293  }
294  
edma_writel(struct fsl_edma_engine * edma,u32 val,void __iomem * addr)295  static inline void edma_writel(struct fsl_edma_engine *edma,
296  			       u32 val, void __iomem *addr)
297  {
298  	if (edma->big_endian)
299  		iowrite32be(val, addr);
300  	else
301  		iowrite32(val, addr);
302  }
303  
to_fsl_edma_chan(struct dma_chan * chan)304  static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
305  {
306  	return container_of(chan, struct fsl_edma_chan, vchan.chan);
307  }
308  
fsl_edma_drvflags(struct fsl_edma_chan * fsl_chan)309  static inline u32 fsl_edma_drvflags(struct fsl_edma_chan *fsl_chan)
310  {
311  	return fsl_chan->edma->drvdata->flags;
312  }
313  
to_fsl_edma_desc(struct virt_dma_desc * vd)314  static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
315  {
316  	return container_of(vd, struct fsl_edma_desc, vdesc);
317  }
318  
fsl_edma_err_chan_handler(struct fsl_edma_chan * fsl_chan)319  static inline void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan)
320  {
321  	fsl_chan->status = DMA_ERROR;
322  	fsl_chan->idle = true;
323  }
324  
325  void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan);
326  void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
327  void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
328  			unsigned int slot, bool enable);
329  void fsl_edma_free_desc(struct virt_dma_desc *vdesc);
330  int fsl_edma_terminate_all(struct dma_chan *chan);
331  int fsl_edma_pause(struct dma_chan *chan);
332  int fsl_edma_resume(struct dma_chan *chan);
333  int fsl_edma_slave_config(struct dma_chan *chan,
334  				 struct dma_slave_config *cfg);
335  enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
336  		dma_cookie_t cookie, struct dma_tx_state *txstate);
337  struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
338  		struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
339  		size_t period_len, enum dma_transfer_direction direction,
340  		unsigned long flags);
341  struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
342  		struct dma_chan *chan, struct scatterlist *sgl,
343  		unsigned int sg_len, enum dma_transfer_direction direction,
344  		unsigned long flags, void *context);
345  struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(
346  		struct dma_chan *chan, dma_addr_t dma_dst, dma_addr_t dma_src,
347  		size_t len, unsigned long flags);
348  void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan);
349  void fsl_edma_issue_pending(struct dma_chan *chan);
350  int fsl_edma_alloc_chan_resources(struct dma_chan *chan);
351  void fsl_edma_free_chan_resources(struct dma_chan *chan);
352  void fsl_edma_cleanup_vchan(struct dma_device *dmadev);
353  void fsl_edma_setup_regs(struct fsl_edma_engine *edma);
354  
355  #endif /* _FSL_EDMA_COMMON_H_ */
356