1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2020 Intel Corporation
4  */
5 
6 #include "g4x_dp.h"
7 #include "i915_drv.h"
8 #include "i915_reg.h"
9 #include "intel_de.h"
10 #include "intel_display_power_well.h"
11 #include "intel_display_types.h"
12 #include "intel_dp.h"
13 #include "intel_dpio_phy.h"
14 #include "intel_dpll.h"
15 #include "intel_lvds.h"
16 #include "intel_lvds_regs.h"
17 #include "intel_pps.h"
18 #include "intel_pps_regs.h"
19 #include "intel_quirks.h"
20 
21 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
22 				      enum pipe pipe);
23 
24 static void pps_init_delays(struct intel_dp *intel_dp);
25 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
26 
pps_name(struct drm_i915_private * i915,struct intel_pps * pps)27 static const char *pps_name(struct drm_i915_private *i915,
28 			    struct intel_pps *pps)
29 {
30 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
31 		switch (pps->pps_pipe) {
32 		case INVALID_PIPE:
33 			/*
34 			 * FIXME would be nice if we can guarantee
35 			 * to always have a valid PPS when calling this.
36 			 */
37 			return "PPS <none>";
38 		case PIPE_A:
39 			return "PPS A";
40 		case PIPE_B:
41 			return "PPS B";
42 		default:
43 			MISSING_CASE(pps->pps_pipe);
44 			break;
45 		}
46 	} else {
47 		switch (pps->pps_idx) {
48 		case 0:
49 			return "PPS 0";
50 		case 1:
51 			return "PPS 1";
52 		default:
53 			MISSING_CASE(pps->pps_idx);
54 			break;
55 		}
56 	}
57 
58 	return "PPS <invalid>";
59 }
60 
intel_pps_lock(struct intel_dp * intel_dp)61 intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
62 {
63 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
64 	intel_wakeref_t wakeref;
65 
66 	/*
67 	 * See intel_pps_reset_all() why we need a power domain reference here.
68 	 */
69 	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
70 	mutex_lock(&dev_priv->display.pps.mutex);
71 
72 	return wakeref;
73 }
74 
intel_pps_unlock(struct intel_dp * intel_dp,intel_wakeref_t wakeref)75 intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
76 				 intel_wakeref_t wakeref)
77 {
78 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
79 
80 	mutex_unlock(&dev_priv->display.pps.mutex);
81 	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
82 
83 	return 0;
84 }
85 
86 static void
vlv_power_sequencer_kick(struct intel_dp * intel_dp)87 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
88 {
89 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
90 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
91 	enum pipe pipe = intel_dp->pps.pps_pipe;
92 	bool pll_enabled, release_cl_override = false;
93 	enum dpio_phy phy = DPIO_PHY(pipe);
94 	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
95 	u32 DP;
96 
97 	if (drm_WARN(&dev_priv->drm,
98 		     intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
99 		     "skipping %s kick due to [ENCODER:%d:%s] being active\n",
100 		     pps_name(dev_priv, &intel_dp->pps),
101 		     dig_port->base.base.base.id, dig_port->base.base.name))
102 		return;
103 
104 	drm_dbg_kms(&dev_priv->drm,
105 		    "kicking %s for [ENCODER:%d:%s]\n",
106 		    pps_name(dev_priv, &intel_dp->pps),
107 		    dig_port->base.base.base.id, dig_port->base.base.name);
108 
109 	/* Preserve the BIOS-computed detected bit. This is
110 	 * supposed to be read-only.
111 	 */
112 	DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
113 	DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
114 	DP |= DP_PORT_WIDTH(1);
115 	DP |= DP_LINK_TRAIN_PAT_1;
116 
117 	if (IS_CHERRYVIEW(dev_priv))
118 		DP |= DP_PIPE_SEL_CHV(pipe);
119 	else
120 		DP |= DP_PIPE_SEL(pipe);
121 
122 	pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
123 
124 	/*
125 	 * The DPLL for the pipe must be enabled for this to work.
126 	 * So enable temporarily it if it's not already enabled.
127 	 */
128 	if (!pll_enabled) {
129 		release_cl_override = IS_CHERRYVIEW(dev_priv) &&
130 			!chv_phy_powergate_ch(dev_priv, phy, ch, true);
131 
132 		if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
133 			drm_err(&dev_priv->drm,
134 				"Failed to force on PLL for pipe %c!\n",
135 				pipe_name(pipe));
136 			return;
137 		}
138 	}
139 
140 	/*
141 	 * Similar magic as in intel_dp_enable_port().
142 	 * We _must_ do this port enable + disable trick
143 	 * to make this power sequencer lock onto the port.
144 	 * Otherwise even VDD force bit won't work.
145 	 */
146 	intel_de_write(dev_priv, intel_dp->output_reg, DP);
147 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
148 
149 	intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
150 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
151 
152 	intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
153 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
154 
155 	if (!pll_enabled) {
156 		vlv_force_pll_off(dev_priv, pipe);
157 
158 		if (release_cl_override)
159 			chv_phy_powergate_ch(dev_priv, phy, ch, false);
160 	}
161 }
162 
vlv_find_free_pps(struct drm_i915_private * dev_priv)163 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
164 {
165 	struct intel_encoder *encoder;
166 	unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
167 
168 	/*
169 	 * We don't have power sequencer currently.
170 	 * Pick one that's not used by other ports.
171 	 */
172 	for_each_intel_dp(&dev_priv->drm, encoder) {
173 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
174 
175 		if (encoder->type == INTEL_OUTPUT_EDP) {
176 			drm_WARN_ON(&dev_priv->drm,
177 				    intel_dp->pps.active_pipe != INVALID_PIPE &&
178 				    intel_dp->pps.active_pipe !=
179 				    intel_dp->pps.pps_pipe);
180 
181 			if (intel_dp->pps.pps_pipe != INVALID_PIPE)
182 				pipes &= ~(1 << intel_dp->pps.pps_pipe);
183 		} else {
184 			drm_WARN_ON(&dev_priv->drm,
185 				    intel_dp->pps.pps_pipe != INVALID_PIPE);
186 
187 			if (intel_dp->pps.active_pipe != INVALID_PIPE)
188 				pipes &= ~(1 << intel_dp->pps.active_pipe);
189 		}
190 	}
191 
192 	if (pipes == 0)
193 		return INVALID_PIPE;
194 
195 	return ffs(pipes) - 1;
196 }
197 
198 static enum pipe
vlv_power_sequencer_pipe(struct intel_dp * intel_dp)199 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
200 {
201 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
202 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
203 	enum pipe pipe;
204 
205 	lockdep_assert_held(&dev_priv->display.pps.mutex);
206 
207 	/* We should never land here with regular DP ports */
208 	drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
209 
210 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE &&
211 		    intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe);
212 
213 	if (intel_dp->pps.pps_pipe != INVALID_PIPE)
214 		return intel_dp->pps.pps_pipe;
215 
216 	pipe = vlv_find_free_pps(dev_priv);
217 
218 	/*
219 	 * Didn't find one. This should not happen since there
220 	 * are two power sequencers and up to two eDP ports.
221 	 */
222 	if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
223 		pipe = PIPE_A;
224 
225 	vlv_steal_power_sequencer(dev_priv, pipe);
226 	intel_dp->pps.pps_pipe = pipe;
227 
228 	drm_dbg_kms(&dev_priv->drm,
229 		    "picked %s for [ENCODER:%d:%s]\n",
230 		    pps_name(dev_priv, &intel_dp->pps),
231 		    dig_port->base.base.base.id, dig_port->base.base.name);
232 
233 	/* init power sequencer on this pipe and port */
234 	pps_init_delays(intel_dp);
235 	pps_init_registers(intel_dp, true);
236 
237 	/*
238 	 * Even vdd force doesn't work until we've made
239 	 * the power sequencer lock in on the port.
240 	 */
241 	vlv_power_sequencer_kick(intel_dp);
242 
243 	return intel_dp->pps.pps_pipe;
244 }
245 
246 static int
bxt_power_sequencer_idx(struct intel_dp * intel_dp)247 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
248 {
249 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
250 	int pps_idx = intel_dp->pps.pps_idx;
251 
252 	lockdep_assert_held(&dev_priv->display.pps.mutex);
253 
254 	/* We should never land here with regular DP ports */
255 	drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
256 
257 	if (!intel_dp->pps.pps_reset)
258 		return pps_idx;
259 
260 	intel_dp->pps.pps_reset = false;
261 
262 	/*
263 	 * Only the HW needs to be reprogrammed, the SW state is fixed and
264 	 * has been setup during connector init.
265 	 */
266 	pps_init_registers(intel_dp, false);
267 
268 	return pps_idx;
269 }
270 
271 typedef bool (*pps_check)(struct drm_i915_private *dev_priv, int pps_idx);
272 
pps_has_pp_on(struct drm_i915_private * dev_priv,int pps_idx)273 static bool pps_has_pp_on(struct drm_i915_private *dev_priv, int pps_idx)
274 {
275 	return intel_de_read(dev_priv, PP_STATUS(pps_idx)) & PP_ON;
276 }
277 
pps_has_vdd_on(struct drm_i915_private * dev_priv,int pps_idx)278 static bool pps_has_vdd_on(struct drm_i915_private *dev_priv, int pps_idx)
279 {
280 	return intel_de_read(dev_priv, PP_CONTROL(pps_idx)) & EDP_FORCE_VDD;
281 }
282 
pps_any(struct drm_i915_private * dev_priv,int pps_idx)283 static bool pps_any(struct drm_i915_private *dev_priv, int pps_idx)
284 {
285 	return true;
286 }
287 
288 static enum pipe
vlv_initial_pps_pipe(struct drm_i915_private * dev_priv,enum port port,pps_check check)289 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
290 		     enum port port, pps_check check)
291 {
292 	enum pipe pipe;
293 
294 	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
295 		u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
296 			PANEL_PORT_SELECT_MASK;
297 
298 		if (port_sel != PANEL_PORT_SELECT_VLV(port))
299 			continue;
300 
301 		if (!check(dev_priv, pipe))
302 			continue;
303 
304 		return pipe;
305 	}
306 
307 	return INVALID_PIPE;
308 }
309 
310 static void
vlv_initial_power_sequencer_setup(struct intel_dp * intel_dp)311 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
312 {
313 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
314 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
315 	enum port port = dig_port->base.port;
316 
317 	lockdep_assert_held(&dev_priv->display.pps.mutex);
318 
319 	/* try to find a pipe with this port selected */
320 	/* first pick one where the panel is on */
321 	intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
322 						      pps_has_pp_on);
323 	/* didn't find one? pick one where vdd is on */
324 	if (intel_dp->pps.pps_pipe == INVALID_PIPE)
325 		intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
326 							      pps_has_vdd_on);
327 	/* didn't find one? pick one with just the correct port */
328 	if (intel_dp->pps.pps_pipe == INVALID_PIPE)
329 		intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
330 							      pps_any);
331 
332 	/* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
333 	if (intel_dp->pps.pps_pipe == INVALID_PIPE) {
334 		drm_dbg_kms(&dev_priv->drm,
335 			    "[ENCODER:%d:%s] no initial power sequencer\n",
336 			    dig_port->base.base.base.id, dig_port->base.base.name);
337 		return;
338 	}
339 
340 	drm_dbg_kms(&dev_priv->drm,
341 		    "[ENCODER:%d:%s] initial power sequencer: %s\n",
342 		    dig_port->base.base.base.id, dig_port->base.base.name,
343 		    pps_name(dev_priv, &intel_dp->pps));
344 }
345 
intel_num_pps(struct drm_i915_private * i915)346 static int intel_num_pps(struct drm_i915_private *i915)
347 {
348 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
349 		return 2;
350 
351 	if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
352 		return 2;
353 
354 	if (INTEL_PCH_TYPE(i915) >= PCH_DG1)
355 		return 1;
356 
357 	if (INTEL_PCH_TYPE(i915) >= PCH_ICP)
358 		return 2;
359 
360 	return 1;
361 }
362 
intel_pps_is_valid(struct intel_dp * intel_dp)363 static bool intel_pps_is_valid(struct intel_dp *intel_dp)
364 {
365 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
366 
367 	if (intel_dp->pps.pps_idx == 1 &&
368 	    INTEL_PCH_TYPE(i915) >= PCH_ICP &&
369 	    INTEL_PCH_TYPE(i915) < PCH_MTP)
370 		return intel_de_read(i915, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;
371 
372 	return true;
373 }
374 
375 static int
bxt_initial_pps_idx(struct drm_i915_private * i915,pps_check check)376 bxt_initial_pps_idx(struct drm_i915_private *i915, pps_check check)
377 {
378 	int pps_idx, pps_num = intel_num_pps(i915);
379 
380 	for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
381 		if (check(i915, pps_idx))
382 			return pps_idx;
383 	}
384 
385 	return -1;
386 }
387 
388 static bool
pps_initial_setup(struct intel_dp * intel_dp)389 pps_initial_setup(struct intel_dp *intel_dp)
390 {
391 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
392 	struct intel_connector *connector = intel_dp->attached_connector;
393 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
394 
395 	lockdep_assert_held(&i915->display.pps.mutex);
396 
397 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
398 		vlv_initial_power_sequencer_setup(intel_dp);
399 		return true;
400 	}
401 
402 	/* first ask the VBT */
403 	if (intel_num_pps(i915) > 1)
404 		intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;
405 	else
406 		intel_dp->pps.pps_idx = 0;
407 
408 	if (drm_WARN_ON(&i915->drm, intel_dp->pps.pps_idx >= intel_num_pps(i915)))
409 		intel_dp->pps.pps_idx = -1;
410 
411 	/* VBT wasn't parsed yet? pick one where the panel is on */
412 	if (intel_dp->pps.pps_idx < 0)
413 		intel_dp->pps.pps_idx = bxt_initial_pps_idx(i915, pps_has_pp_on);
414 	/* didn't find one? pick one where vdd is on */
415 	if (intel_dp->pps.pps_idx < 0)
416 		intel_dp->pps.pps_idx = bxt_initial_pps_idx(i915, pps_has_vdd_on);
417 	/* didn't find one? pick any */
418 	if (intel_dp->pps.pps_idx < 0) {
419 		intel_dp->pps.pps_idx = bxt_initial_pps_idx(i915, pps_any);
420 
421 		drm_dbg_kms(&i915->drm,
422 			    "[ENCODER:%d:%s] no initial power sequencer, assuming %s\n",
423 			    encoder->base.base.id, encoder->base.name,
424 			    pps_name(i915, &intel_dp->pps));
425 	} else {
426 		drm_dbg_kms(&i915->drm,
427 			    "[ENCODER:%d:%s] initial power sequencer: %s\n",
428 			    encoder->base.base.id, encoder->base.name,
429 			    pps_name(i915, &intel_dp->pps));
430 	}
431 
432 	return intel_pps_is_valid(intel_dp);
433 }
434 
intel_pps_reset_all(struct drm_i915_private * dev_priv)435 void intel_pps_reset_all(struct drm_i915_private *dev_priv)
436 {
437 	struct intel_encoder *encoder;
438 
439 	if (drm_WARN_ON(&dev_priv->drm, !IS_LP(dev_priv)))
440 		return;
441 
442 	if (!HAS_DISPLAY(dev_priv))
443 		return;
444 
445 	/*
446 	 * We can't grab pps_mutex here due to deadlock with power_domain
447 	 * mutex when power_domain functions are called while holding pps_mutex.
448 	 * That also means that in order to use pps_pipe the code needs to
449 	 * hold both a power domain reference and pps_mutex, and the power domain
450 	 * reference get/put must be done while _not_ holding pps_mutex.
451 	 * pps_{lock,unlock}() do these steps in the correct order, so one
452 	 * should use them always.
453 	 */
454 
455 	for_each_intel_dp(&dev_priv->drm, encoder) {
456 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
457 
458 		drm_WARN_ON(&dev_priv->drm,
459 			    intel_dp->pps.active_pipe != INVALID_PIPE);
460 
461 		if (encoder->type != INTEL_OUTPUT_EDP)
462 			continue;
463 
464 		if (DISPLAY_VER(dev_priv) >= 9)
465 			intel_dp->pps.pps_reset = true;
466 		else
467 			intel_dp->pps.pps_pipe = INVALID_PIPE;
468 	}
469 }
470 
471 struct pps_registers {
472 	i915_reg_t pp_ctrl;
473 	i915_reg_t pp_stat;
474 	i915_reg_t pp_on;
475 	i915_reg_t pp_off;
476 	i915_reg_t pp_div;
477 };
478 
intel_pps_get_registers(struct intel_dp * intel_dp,struct pps_registers * regs)479 static void intel_pps_get_registers(struct intel_dp *intel_dp,
480 				    struct pps_registers *regs)
481 {
482 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
483 	int pps_idx;
484 
485 	memset(regs, 0, sizeof(*regs));
486 
487 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
488 		pps_idx = vlv_power_sequencer_pipe(intel_dp);
489 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
490 		pps_idx = bxt_power_sequencer_idx(intel_dp);
491 	else
492 		pps_idx = intel_dp->pps.pps_idx;
493 
494 	regs->pp_ctrl = PP_CONTROL(pps_idx);
495 	regs->pp_stat = PP_STATUS(pps_idx);
496 	regs->pp_on = PP_ON_DELAYS(pps_idx);
497 	regs->pp_off = PP_OFF_DELAYS(pps_idx);
498 
499 	/* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
500 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
501 	    INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
502 		regs->pp_div = INVALID_MMIO_REG;
503 	else
504 		regs->pp_div = PP_DIVISOR(pps_idx);
505 }
506 
507 static i915_reg_t
_pp_ctrl_reg(struct intel_dp * intel_dp)508 _pp_ctrl_reg(struct intel_dp *intel_dp)
509 {
510 	struct pps_registers regs;
511 
512 	intel_pps_get_registers(intel_dp, &regs);
513 
514 	return regs.pp_ctrl;
515 }
516 
517 static i915_reg_t
_pp_stat_reg(struct intel_dp * intel_dp)518 _pp_stat_reg(struct intel_dp *intel_dp)
519 {
520 	struct pps_registers regs;
521 
522 	intel_pps_get_registers(intel_dp, &regs);
523 
524 	return regs.pp_stat;
525 }
526 
edp_have_panel_power(struct intel_dp * intel_dp)527 static bool edp_have_panel_power(struct intel_dp *intel_dp)
528 {
529 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
530 
531 	lockdep_assert_held(&dev_priv->display.pps.mutex);
532 
533 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
534 	    intel_dp->pps.pps_pipe == INVALID_PIPE)
535 		return false;
536 
537 	return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
538 }
539 
edp_have_panel_vdd(struct intel_dp * intel_dp)540 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
541 {
542 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
543 
544 	lockdep_assert_held(&dev_priv->display.pps.mutex);
545 
546 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
547 	    intel_dp->pps.pps_pipe == INVALID_PIPE)
548 		return false;
549 
550 	return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
551 }
552 
intel_pps_check_power_unlocked(struct intel_dp * intel_dp)553 void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
554 {
555 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
556 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
557 
558 	if (!intel_dp_is_edp(intel_dp))
559 		return;
560 
561 	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
562 		drm_WARN(&dev_priv->drm, 1,
563 			 "[ENCODER:%d:%s] %s powered off while attempting AUX CH communication.\n",
564 			 dig_port->base.base.base.id, dig_port->base.base.name,
565 			 pps_name(dev_priv, &intel_dp->pps));
566 		drm_dbg_kms(&dev_priv->drm,
567 			    "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
568 			    dig_port->base.base.base.id, dig_port->base.base.name,
569 			    pps_name(dev_priv, &intel_dp->pps),
570 			    intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
571 			    intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
572 	}
573 }
574 
575 #define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
576 #define IDLE_ON_VALUE		(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
577 
578 #define IDLE_OFF_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
579 #define IDLE_OFF_VALUE		(0     | PP_SEQUENCE_NONE | 0                     | 0)
580 
581 #define IDLE_CYCLE_MASK		(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
582 #define IDLE_CYCLE_VALUE	(0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
583 
584 static void intel_pps_verify_state(struct intel_dp *intel_dp);
585 
wait_panel_status(struct intel_dp * intel_dp,u32 mask,u32 value)586 static void wait_panel_status(struct intel_dp *intel_dp,
587 			      u32 mask, u32 value)
588 {
589 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
590 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
591 	i915_reg_t pp_stat_reg, pp_ctrl_reg;
592 
593 	lockdep_assert_held(&dev_priv->display.pps.mutex);
594 
595 	intel_pps_verify_state(intel_dp);
596 
597 	pp_stat_reg = _pp_stat_reg(intel_dp);
598 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
599 
600 	drm_dbg_kms(&dev_priv->drm,
601 		    "[ENCODER:%d:%s] %s mask: 0x%08x value: 0x%08x PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
602 		    dig_port->base.base.base.id, dig_port->base.base.name,
603 		    pps_name(dev_priv, &intel_dp->pps),
604 		    mask, value,
605 		    intel_de_read(dev_priv, pp_stat_reg),
606 		    intel_de_read(dev_priv, pp_ctrl_reg));
607 
608 	if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
609 				       mask, value, 5000))
610 		drm_err(&dev_priv->drm,
611 			"[ENCODER:%d:%s] %s panel status timeout: PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
612 			dig_port->base.base.base.id, dig_port->base.base.name,
613 			pps_name(dev_priv, &intel_dp->pps),
614 			intel_de_read(dev_priv, pp_stat_reg),
615 			intel_de_read(dev_priv, pp_ctrl_reg));
616 
617 	drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
618 }
619 
wait_panel_on(struct intel_dp * intel_dp)620 static void wait_panel_on(struct intel_dp *intel_dp)
621 {
622 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
623 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
624 
625 	drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] %s wait for panel power on\n",
626 		    dig_port->base.base.base.id, dig_port->base.base.name,
627 		    pps_name(i915, &intel_dp->pps));
628 	wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
629 }
630 
wait_panel_off(struct intel_dp * intel_dp)631 static void wait_panel_off(struct intel_dp *intel_dp)
632 {
633 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
634 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
635 
636 	drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] %s wait for panel power off time\n",
637 		    dig_port->base.base.base.id, dig_port->base.base.name,
638 		    pps_name(i915, &intel_dp->pps));
639 	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
640 }
641 
wait_panel_power_cycle(struct intel_dp * intel_dp)642 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
643 {
644 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
645 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
646 	ktime_t panel_power_on_time;
647 	s64 panel_power_off_duration;
648 
649 	drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] %s wait for panel power cycle\n",
650 		    dig_port->base.base.base.id, dig_port->base.base.name,
651 		    pps_name(i915, &intel_dp->pps));
652 
653 	/* take the difference of current time and panel power off time
654 	 * and then make panel wait for t11_t12 if needed. */
655 	panel_power_on_time = ktime_get_boottime();
656 	panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);
657 
658 	/* When we disable the VDD override bit last we have to do the manual
659 	 * wait. */
660 	if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay)
661 		wait_remaining_ms_from_jiffies(jiffies,
662 				       intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);
663 
664 	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
665 }
666 
intel_pps_wait_power_cycle(struct intel_dp * intel_dp)667 void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
668 {
669 	intel_wakeref_t wakeref;
670 
671 	if (!intel_dp_is_edp(intel_dp))
672 		return;
673 
674 	with_intel_pps_lock(intel_dp, wakeref)
675 		wait_panel_power_cycle(intel_dp);
676 }
677 
wait_backlight_on(struct intel_dp * intel_dp)678 static void wait_backlight_on(struct intel_dp *intel_dp)
679 {
680 	wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,
681 				       intel_dp->pps.backlight_on_delay);
682 }
683 
edp_wait_backlight_off(struct intel_dp * intel_dp)684 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
685 {
686 	wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,
687 				       intel_dp->pps.backlight_off_delay);
688 }
689 
690 /* Read the current pp_control value, unlocking the register if it
691  * is locked
692  */
693 
ilk_get_pp_control(struct intel_dp * intel_dp)694 static  u32 ilk_get_pp_control(struct intel_dp *intel_dp)
695 {
696 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
697 	u32 control;
698 
699 	lockdep_assert_held(&dev_priv->display.pps.mutex);
700 
701 	control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
702 	if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
703 			(control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
704 		control &= ~PANEL_UNLOCK_MASK;
705 		control |= PANEL_UNLOCK_REGS;
706 	}
707 	return control;
708 }
709 
710 /*
711  * Must be paired with intel_pps_vdd_off_unlocked().
712  * Must hold pps_mutex around the whole on/off sequence.
713  * Can be nested with intel_pps_vdd_{on,off}() calls.
714  */
intel_pps_vdd_on_unlocked(struct intel_dp * intel_dp)715 bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
716 {
717 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
718 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
719 	u32 pp;
720 	i915_reg_t pp_stat_reg, pp_ctrl_reg;
721 	bool need_to_disable = !intel_dp->pps.want_panel_vdd;
722 
723 	lockdep_assert_held(&dev_priv->display.pps.mutex);
724 
725 	if (!intel_dp_is_edp(intel_dp))
726 		return false;
727 
728 	cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
729 	intel_dp->pps.want_panel_vdd = true;
730 
731 	if (edp_have_panel_vdd(intel_dp))
732 		return need_to_disable;
733 
734 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
735 	intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
736 							    intel_aux_power_domain(dig_port));
737 
738 	pp_stat_reg = _pp_stat_reg(intel_dp);
739 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
740 
741 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s turning VDD on\n",
742 		    dig_port->base.base.base.id, dig_port->base.base.name,
743 		    pps_name(dev_priv, &intel_dp->pps));
744 
745 	if (!edp_have_panel_power(intel_dp))
746 		wait_panel_power_cycle(intel_dp);
747 
748 	pp = ilk_get_pp_control(intel_dp);
749 	pp |= EDP_FORCE_VDD;
750 
751 	intel_de_write(dev_priv, pp_ctrl_reg, pp);
752 	intel_de_posting_read(dev_priv, pp_ctrl_reg);
753 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
754 		    dig_port->base.base.base.id, dig_port->base.base.name,
755 		    pps_name(dev_priv, &intel_dp->pps),
756 		    intel_de_read(dev_priv, pp_stat_reg),
757 		    intel_de_read(dev_priv, pp_ctrl_reg));
758 	/*
759 	 * If the panel wasn't on, delay before accessing aux channel
760 	 */
761 	if (!edp_have_panel_power(intel_dp)) {
762 		drm_dbg_kms(&dev_priv->drm,
763 			    "[ENCODER:%d:%s] %s panel power wasn't enabled\n",
764 			    dig_port->base.base.base.id, dig_port->base.base.name,
765 			    pps_name(dev_priv, &intel_dp->pps));
766 		msleep(intel_dp->pps.panel_power_up_delay);
767 	}
768 
769 	return need_to_disable;
770 }
771 
772 /*
773  * Must be paired with intel_pps_off().
774  * Nested calls to these functions are not allowed since
775  * we drop the lock. Caller must use some higher level
776  * locking to prevent nested calls from other threads.
777  */
intel_pps_vdd_on(struct intel_dp * intel_dp)778 void intel_pps_vdd_on(struct intel_dp *intel_dp)
779 {
780 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
781 	intel_wakeref_t wakeref;
782 	bool vdd;
783 
784 	if (!intel_dp_is_edp(intel_dp))
785 		return;
786 
787 	vdd = false;
788 	with_intel_pps_lock(intel_dp, wakeref)
789 		vdd = intel_pps_vdd_on_unlocked(intel_dp);
790 	I915_STATE_WARN(i915, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n",
791 			dp_to_dig_port(intel_dp)->base.base.base.id,
792 			dp_to_dig_port(intel_dp)->base.base.name,
793 			pps_name(i915, &intel_dp->pps));
794 }
795 
intel_pps_vdd_off_sync_unlocked(struct intel_dp * intel_dp)796 static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
797 {
798 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
799 	struct intel_digital_port *dig_port =
800 		dp_to_dig_port(intel_dp);
801 	u32 pp;
802 	i915_reg_t pp_stat_reg, pp_ctrl_reg;
803 
804 	lockdep_assert_held(&dev_priv->display.pps.mutex);
805 
806 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd);
807 
808 	if (!edp_have_panel_vdd(intel_dp))
809 		return;
810 
811 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s turning VDD off\n",
812 		    dig_port->base.base.base.id, dig_port->base.base.name,
813 		    pps_name(dev_priv, &intel_dp->pps));
814 
815 	pp = ilk_get_pp_control(intel_dp);
816 	pp &= ~EDP_FORCE_VDD;
817 
818 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
819 	pp_stat_reg = _pp_stat_reg(intel_dp);
820 
821 	intel_de_write(dev_priv, pp_ctrl_reg, pp);
822 	intel_de_posting_read(dev_priv, pp_ctrl_reg);
823 
824 	/* Make sure sequencer is idle before allowing subsequent activity */
825 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
826 		    dig_port->base.base.base.id, dig_port->base.base.name,
827 		    pps_name(dev_priv, &intel_dp->pps),
828 		    intel_de_read(dev_priv, pp_stat_reg),
829 		    intel_de_read(dev_priv, pp_ctrl_reg));
830 
831 	if ((pp & PANEL_POWER_ON) == 0)
832 		intel_dp->pps.panel_power_off_time = ktime_get_boottime();
833 
834 	intel_display_power_put(dev_priv,
835 				intel_aux_power_domain(dig_port),
836 				fetch_and_zero(&intel_dp->pps.vdd_wakeref));
837 }
838 
intel_pps_vdd_off_sync(struct intel_dp * intel_dp)839 void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
840 {
841 	intel_wakeref_t wakeref;
842 
843 	if (!intel_dp_is_edp(intel_dp))
844 		return;
845 
846 	cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);
847 	/*
848 	 * vdd might still be enabled due to the delayed vdd off.
849 	 * Make sure vdd is actually turned off here.
850 	 */
851 	with_intel_pps_lock(intel_dp, wakeref)
852 		intel_pps_vdd_off_sync_unlocked(intel_dp);
853 }
854 
edp_panel_vdd_work(struct work_struct * __work)855 static void edp_panel_vdd_work(struct work_struct *__work)
856 {
857 	struct intel_pps *pps = container_of(to_delayed_work(__work),
858 					     struct intel_pps, panel_vdd_work);
859 	struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);
860 	intel_wakeref_t wakeref;
861 
862 	with_intel_pps_lock(intel_dp, wakeref) {
863 		if (!intel_dp->pps.want_panel_vdd)
864 			intel_pps_vdd_off_sync_unlocked(intel_dp);
865 	}
866 }
867 
edp_panel_vdd_schedule_off(struct intel_dp * intel_dp)868 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
869 {
870 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
871 	unsigned long delay;
872 
873 	/*
874 	 * We may not yet know the real power sequencing delays,
875 	 * so keep VDD enabled until we're done with init.
876 	 */
877 	if (intel_dp->pps.initializing)
878 		return;
879 
880 	/*
881 	 * Queue the timer to fire a long time from now (relative to the power
882 	 * down delay) to keep the panel power up across a sequence of
883 	 * operations.
884 	 */
885 	delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);
886 	queue_delayed_work(i915->unordered_wq,
887 			   &intel_dp->pps.panel_vdd_work, delay);
888 }
889 
890 /*
891  * Must be paired with edp_panel_vdd_on().
892  * Must hold pps_mutex around the whole on/off sequence.
893  * Can be nested with intel_pps_vdd_{on,off}() calls.
894  */
intel_pps_vdd_off_unlocked(struct intel_dp * intel_dp,bool sync)895 void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
896 {
897 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
898 
899 	lockdep_assert_held(&dev_priv->display.pps.mutex);
900 
901 	if (!intel_dp_is_edp(intel_dp))
902 		return;
903 
904 	I915_STATE_WARN(dev_priv, !intel_dp->pps.want_panel_vdd,
905 			"[ENCODER:%d:%s] %s VDD not forced on",
906 			dp_to_dig_port(intel_dp)->base.base.base.id,
907 			dp_to_dig_port(intel_dp)->base.base.name,
908 			pps_name(dev_priv, &intel_dp->pps));
909 
910 	intel_dp->pps.want_panel_vdd = false;
911 
912 	if (sync)
913 		intel_pps_vdd_off_sync_unlocked(intel_dp);
914 	else
915 		edp_panel_vdd_schedule_off(intel_dp);
916 }
917 
intel_pps_on_unlocked(struct intel_dp * intel_dp)918 void intel_pps_on_unlocked(struct intel_dp *intel_dp)
919 {
920 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
921 	u32 pp;
922 	i915_reg_t pp_ctrl_reg;
923 
924 	lockdep_assert_held(&dev_priv->display.pps.mutex);
925 
926 	if (!intel_dp_is_edp(intel_dp))
927 		return;
928 
929 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s turn panel power on\n",
930 		    dp_to_dig_port(intel_dp)->base.base.base.id,
931 		    dp_to_dig_port(intel_dp)->base.base.name,
932 		    pps_name(dev_priv, &intel_dp->pps));
933 
934 	if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
935 		     "[ENCODER:%d:%s] %s panel power already on\n",
936 		     dp_to_dig_port(intel_dp)->base.base.base.id,
937 		     dp_to_dig_port(intel_dp)->base.base.name,
938 		     pps_name(dev_priv, &intel_dp->pps)))
939 		return;
940 
941 	wait_panel_power_cycle(intel_dp);
942 
943 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
944 	pp = ilk_get_pp_control(intel_dp);
945 	if (IS_IRONLAKE(dev_priv)) {
946 		/* ILK workaround: disable reset around power sequence */
947 		pp &= ~PANEL_POWER_RESET;
948 		intel_de_write(dev_priv, pp_ctrl_reg, pp);
949 		intel_de_posting_read(dev_priv, pp_ctrl_reg);
950 	}
951 
952 	pp |= PANEL_POWER_ON;
953 	if (!IS_IRONLAKE(dev_priv))
954 		pp |= PANEL_POWER_RESET;
955 
956 	intel_de_write(dev_priv, pp_ctrl_reg, pp);
957 	intel_de_posting_read(dev_priv, pp_ctrl_reg);
958 
959 	wait_panel_on(intel_dp);
960 	intel_dp->pps.last_power_on = jiffies;
961 
962 	if (IS_IRONLAKE(dev_priv)) {
963 		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
964 		intel_de_write(dev_priv, pp_ctrl_reg, pp);
965 		intel_de_posting_read(dev_priv, pp_ctrl_reg);
966 	}
967 }
968 
intel_pps_on(struct intel_dp * intel_dp)969 void intel_pps_on(struct intel_dp *intel_dp)
970 {
971 	intel_wakeref_t wakeref;
972 
973 	if (!intel_dp_is_edp(intel_dp))
974 		return;
975 
976 	with_intel_pps_lock(intel_dp, wakeref)
977 		intel_pps_on_unlocked(intel_dp);
978 }
979 
intel_pps_off_unlocked(struct intel_dp * intel_dp)980 void intel_pps_off_unlocked(struct intel_dp *intel_dp)
981 {
982 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
983 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
984 	u32 pp;
985 	i915_reg_t pp_ctrl_reg;
986 
987 	lockdep_assert_held(&dev_priv->display.pps.mutex);
988 
989 	if (!intel_dp_is_edp(intel_dp))
990 		return;
991 
992 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] %s turn panel power off\n",
993 		    dig_port->base.base.base.id, dig_port->base.base.name,
994 		    pps_name(dev_priv, &intel_dp->pps));
995 
996 	drm_WARN(&dev_priv->drm, !intel_dp->pps.want_panel_vdd,
997 		 "[ENCODER:%d:%s] %s need VDD to turn off panel\n",
998 		 dig_port->base.base.base.id, dig_port->base.base.name,
999 		 pps_name(dev_priv, &intel_dp->pps));
1000 
1001 	pp = ilk_get_pp_control(intel_dp);
1002 	/* We need to switch off panel power _and_ force vdd, for otherwise some
1003 	 * panels get very unhappy and cease to work. */
1004 	pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1005 		EDP_BLC_ENABLE);
1006 
1007 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1008 
1009 	intel_dp->pps.want_panel_vdd = false;
1010 
1011 	intel_de_write(dev_priv, pp_ctrl_reg, pp);
1012 	intel_de_posting_read(dev_priv, pp_ctrl_reg);
1013 
1014 	wait_panel_off(intel_dp);
1015 	intel_dp->pps.panel_power_off_time = ktime_get_boottime();
1016 
1017 	/* We got a reference when we enabled the VDD. */
1018 	intel_display_power_put(dev_priv,
1019 				intel_aux_power_domain(dig_port),
1020 				fetch_and_zero(&intel_dp->pps.vdd_wakeref));
1021 }
1022 
intel_pps_off(struct intel_dp * intel_dp)1023 void intel_pps_off(struct intel_dp *intel_dp)
1024 {
1025 	intel_wakeref_t wakeref;
1026 
1027 	if (!intel_dp_is_edp(intel_dp))
1028 		return;
1029 
1030 	with_intel_pps_lock(intel_dp, wakeref)
1031 		intel_pps_off_unlocked(intel_dp);
1032 }
1033 
1034 /* Enable backlight in the panel power control. */
intel_pps_backlight_on(struct intel_dp * intel_dp)1035 void intel_pps_backlight_on(struct intel_dp *intel_dp)
1036 {
1037 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1038 	intel_wakeref_t wakeref;
1039 
1040 	/*
1041 	 * If we enable the backlight right away following a panel power
1042 	 * on, we may see slight flicker as the panel syncs with the eDP
1043 	 * link.  So delay a bit to make sure the image is solid before
1044 	 * allowing it to appear.
1045 	 */
1046 	wait_backlight_on(intel_dp);
1047 
1048 	with_intel_pps_lock(intel_dp, wakeref) {
1049 		i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1050 		u32 pp;
1051 
1052 		pp = ilk_get_pp_control(intel_dp);
1053 		pp |= EDP_BLC_ENABLE;
1054 
1055 		intel_de_write(dev_priv, pp_ctrl_reg, pp);
1056 		intel_de_posting_read(dev_priv, pp_ctrl_reg);
1057 	}
1058 }
1059 
1060 /* Disable backlight in the panel power control. */
intel_pps_backlight_off(struct intel_dp * intel_dp)1061 void intel_pps_backlight_off(struct intel_dp *intel_dp)
1062 {
1063 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1064 	intel_wakeref_t wakeref;
1065 
1066 	if (!intel_dp_is_edp(intel_dp))
1067 		return;
1068 
1069 	with_intel_pps_lock(intel_dp, wakeref) {
1070 		i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1071 		u32 pp;
1072 
1073 		pp = ilk_get_pp_control(intel_dp);
1074 		pp &= ~EDP_BLC_ENABLE;
1075 
1076 		intel_de_write(dev_priv, pp_ctrl_reg, pp);
1077 		intel_de_posting_read(dev_priv, pp_ctrl_reg);
1078 	}
1079 
1080 	intel_dp->pps.last_backlight_off = jiffies;
1081 	edp_wait_backlight_off(intel_dp);
1082 }
1083 
1084 /*
1085  * Hook for controlling the panel power control backlight through the bl_power
1086  * sysfs attribute. Take care to handle multiple calls.
1087  */
intel_pps_backlight_power(struct intel_connector * connector,bool enable)1088 void intel_pps_backlight_power(struct intel_connector *connector, bool enable)
1089 {
1090 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
1091 	struct intel_dp *intel_dp = intel_attached_dp(connector);
1092 	intel_wakeref_t wakeref;
1093 	bool is_enabled;
1094 
1095 	is_enabled = false;
1096 	with_intel_pps_lock(intel_dp, wakeref)
1097 		is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1098 	if (is_enabled == enable)
1099 		return;
1100 
1101 	drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
1102 		    enable ? "enable" : "disable");
1103 
1104 	if (enable)
1105 		intel_pps_backlight_on(intel_dp);
1106 	else
1107 		intel_pps_backlight_off(intel_dp);
1108 }
1109 
vlv_detach_power_sequencer(struct intel_dp * intel_dp)1110 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
1111 {
1112 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1113 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1114 	enum pipe pipe = intel_dp->pps.pps_pipe;
1115 	i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
1116 
1117 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
1118 
1119 	if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
1120 		return;
1121 
1122 	intel_pps_vdd_off_sync_unlocked(intel_dp);
1123 
1124 	/*
1125 	 * VLV seems to get confused when multiple power sequencers
1126 	 * have the same port selected (even if only one has power/vdd
1127 	 * enabled). The failure manifests as vlv_wait_port_ready() failing
1128 	 * CHV on the other hand doesn't seem to mind having the same port
1129 	 * selected in multiple power sequencers, but let's clear the
1130 	 * port select always when logically disconnecting a power sequencer
1131 	 * from a port.
1132 	 */
1133 	drm_dbg_kms(&dev_priv->drm,
1134 		    "detaching %s from [ENCODER:%d:%s]\n",
1135 		    pps_name(dev_priv, &intel_dp->pps),
1136 		    dig_port->base.base.base.id, dig_port->base.base.name);
1137 	intel_de_write(dev_priv, pp_on_reg, 0);
1138 	intel_de_posting_read(dev_priv, pp_on_reg);
1139 
1140 	intel_dp->pps.pps_pipe = INVALID_PIPE;
1141 }
1142 
vlv_steal_power_sequencer(struct drm_i915_private * dev_priv,enum pipe pipe)1143 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
1144 				      enum pipe pipe)
1145 {
1146 	struct intel_encoder *encoder;
1147 
1148 	lockdep_assert_held(&dev_priv->display.pps.mutex);
1149 
1150 	for_each_intel_dp(&dev_priv->drm, encoder) {
1151 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1152 
1153 		drm_WARN(&dev_priv->drm, intel_dp->pps.active_pipe == pipe,
1154 			 "stealing PPS %c from active [ENCODER:%d:%s]\n",
1155 			 pipe_name(pipe), encoder->base.base.id,
1156 			 encoder->base.name);
1157 
1158 		if (intel_dp->pps.pps_pipe != pipe)
1159 			continue;
1160 
1161 		drm_dbg_kms(&dev_priv->drm,
1162 			    "stealing PPS %c from [ENCODER:%d:%s]\n",
1163 			    pipe_name(pipe), encoder->base.base.id,
1164 			    encoder->base.name);
1165 
1166 		/* make sure vdd is off before we steal it */
1167 		vlv_detach_power_sequencer(intel_dp);
1168 	}
1169 }
1170 
vlv_pps_init(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1171 void vlv_pps_init(struct intel_encoder *encoder,
1172 		  const struct intel_crtc_state *crtc_state)
1173 {
1174 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1175 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1176 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1177 
1178 	lockdep_assert_held(&dev_priv->display.pps.mutex);
1179 
1180 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
1181 
1182 	if (intel_dp->pps.pps_pipe != INVALID_PIPE &&
1183 	    intel_dp->pps.pps_pipe != crtc->pipe) {
1184 		/*
1185 		 * If another power sequencer was being used on this
1186 		 * port previously make sure to turn off vdd there while
1187 		 * we still have control of it.
1188 		 */
1189 		vlv_detach_power_sequencer(intel_dp);
1190 	}
1191 
1192 	/*
1193 	 * We may be stealing the power
1194 	 * sequencer from another port.
1195 	 */
1196 	vlv_steal_power_sequencer(dev_priv, crtc->pipe);
1197 
1198 	intel_dp->pps.active_pipe = crtc->pipe;
1199 
1200 	if (!intel_dp_is_edp(intel_dp))
1201 		return;
1202 
1203 	/* now it's all ours */
1204 	intel_dp->pps.pps_pipe = crtc->pipe;
1205 
1206 	drm_dbg_kms(&dev_priv->drm,
1207 		    "initializing %s for [ENCODER:%d:%s]\n",
1208 		    pps_name(dev_priv, &intel_dp->pps),
1209 		    encoder->base.base.id, encoder->base.name);
1210 
1211 	/* init power sequencer on this pipe and port */
1212 	pps_init_delays(intel_dp);
1213 	pps_init_registers(intel_dp, true);
1214 }
1215 
pps_vdd_init(struct intel_dp * intel_dp)1216 static void pps_vdd_init(struct intel_dp *intel_dp)
1217 {
1218 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1219 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1220 
1221 	lockdep_assert_held(&dev_priv->display.pps.mutex);
1222 
1223 	if (!edp_have_panel_vdd(intel_dp))
1224 		return;
1225 
1226 	/*
1227 	 * The VDD bit needs a power domain reference, so if the bit is
1228 	 * already enabled when we boot or resume, grab this reference and
1229 	 * schedule a vdd off, so we don't hold on to the reference
1230 	 * indefinitely.
1231 	 */
1232 	drm_dbg_kms(&dev_priv->drm,
1233 		    "[ENCODER:%d:%s] %s VDD left on by BIOS, adjusting state tracking\n",
1234 		    dig_port->base.base.base.id, dig_port->base.base.name,
1235 		    pps_name(dev_priv, &intel_dp->pps));
1236 	drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
1237 	intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
1238 							    intel_aux_power_domain(dig_port));
1239 }
1240 
intel_pps_have_panel_power_or_vdd(struct intel_dp * intel_dp)1241 bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp)
1242 {
1243 	intel_wakeref_t wakeref;
1244 	bool have_power = false;
1245 
1246 	with_intel_pps_lock(intel_dp, wakeref) {
1247 		have_power = edp_have_panel_power(intel_dp) ||
1248 			     edp_have_panel_vdd(intel_dp);
1249 	}
1250 
1251 	return have_power;
1252 }
1253 
pps_init_timestamps(struct intel_dp * intel_dp)1254 static void pps_init_timestamps(struct intel_dp *intel_dp)
1255 {
1256 	/*
1257 	 * Initialize panel power off time to 0, assuming panel power could have
1258 	 * been toggled between kernel boot and now only by a previously loaded
1259 	 * and removed i915, which has already ensured sufficient power off
1260 	 * delay at module remove.
1261 	 */
1262 	intel_dp->pps.panel_power_off_time = 0;
1263 	intel_dp->pps.last_power_on = jiffies;
1264 	intel_dp->pps.last_backlight_off = jiffies;
1265 }
1266 
1267 static void
intel_pps_readout_hw_state(struct intel_dp * intel_dp,struct edp_power_seq * seq)1268 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
1269 {
1270 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1271 	u32 pp_on, pp_off, pp_ctl;
1272 	struct pps_registers regs;
1273 
1274 	intel_pps_get_registers(intel_dp, &regs);
1275 
1276 	pp_ctl = ilk_get_pp_control(intel_dp);
1277 
1278 	/* Ensure PPS is unlocked */
1279 	if (!HAS_DDI(dev_priv))
1280 		intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
1281 
1282 	pp_on = intel_de_read(dev_priv, regs.pp_on);
1283 	pp_off = intel_de_read(dev_priv, regs.pp_off);
1284 
1285 	/* Pull timing values out of registers */
1286 	seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
1287 	seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
1288 	seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
1289 	seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
1290 
1291 	if (i915_mmio_reg_valid(regs.pp_div)) {
1292 		u32 pp_div;
1293 
1294 		pp_div = intel_de_read(dev_priv, regs.pp_div);
1295 
1296 		seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
1297 	} else {
1298 		seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
1299 	}
1300 }
1301 
1302 static void
intel_pps_dump_state(struct intel_dp * intel_dp,const char * state_name,const struct edp_power_seq * seq)1303 intel_pps_dump_state(struct intel_dp *intel_dp, const char *state_name,
1304 		     const struct edp_power_seq *seq)
1305 {
1306 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1307 
1308 	drm_dbg_kms(&i915->drm, "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
1309 		    state_name,
1310 		    seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
1311 }
1312 
1313 static void
intel_pps_verify_state(struct intel_dp * intel_dp)1314 intel_pps_verify_state(struct intel_dp *intel_dp)
1315 {
1316 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1317 	struct edp_power_seq hw;
1318 	struct edp_power_seq *sw = &intel_dp->pps.pps_delays;
1319 
1320 	intel_pps_readout_hw_state(intel_dp, &hw);
1321 
1322 	if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
1323 	    hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
1324 		drm_err(&i915->drm, "PPS state mismatch\n");
1325 		intel_pps_dump_state(intel_dp, "sw", sw);
1326 		intel_pps_dump_state(intel_dp, "hw", &hw);
1327 	}
1328 }
1329 
pps_delays_valid(struct edp_power_seq * delays)1330 static bool pps_delays_valid(struct edp_power_seq *delays)
1331 {
1332 	return delays->t1_t3 || delays->t8 || delays->t9 ||
1333 		delays->t10 || delays->t11_t12;
1334 }
1335 
pps_init_delays_bios(struct intel_dp * intel_dp,struct edp_power_seq * bios)1336 static void pps_init_delays_bios(struct intel_dp *intel_dp,
1337 				 struct edp_power_seq *bios)
1338 {
1339 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1340 
1341 	lockdep_assert_held(&dev_priv->display.pps.mutex);
1342 
1343 	if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays))
1344 		intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays);
1345 
1346 	*bios = intel_dp->pps.bios_pps_delays;
1347 
1348 	intel_pps_dump_state(intel_dp, "bios", bios);
1349 }
1350 
pps_init_delays_vbt(struct intel_dp * intel_dp,struct edp_power_seq * vbt)1351 static void pps_init_delays_vbt(struct intel_dp *intel_dp,
1352 				struct edp_power_seq *vbt)
1353 {
1354 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1355 	struct intel_connector *connector = intel_dp->attached_connector;
1356 
1357 	*vbt = connector->panel.vbt.edp.pps;
1358 
1359 	if (!pps_delays_valid(vbt))
1360 		return;
1361 
1362 	/* On Toshiba Satellite P50-C-18C system the VBT T12 delay
1363 	 * of 500ms appears to be too short. Ocassionally the panel
1364 	 * just fails to power back on. Increasing the delay to 800ms
1365 	 * seems sufficient to avoid this problem.
1366 	 */
1367 	if (intel_has_quirk(dev_priv, QUIRK_INCREASE_T12_DELAY)) {
1368 		vbt->t11_t12 = max_t(u16, vbt->t11_t12, 1300 * 10);
1369 		drm_dbg_kms(&dev_priv->drm,
1370 			    "Increasing T12 panel delay as per the quirk to %d\n",
1371 			    vbt->t11_t12);
1372 	}
1373 
1374 	/* T11_T12 delay is special and actually in units of 100ms, but zero
1375 	 * based in the hw (so we need to add 100 ms). But the sw vbt
1376 	 * table multiplies it with 1000 to make it in units of 100usec,
1377 	 * too. */
1378 	vbt->t11_t12 += 100 * 10;
1379 
1380 	intel_pps_dump_state(intel_dp, "vbt", vbt);
1381 }
1382 
pps_init_delays_spec(struct intel_dp * intel_dp,struct edp_power_seq * spec)1383 static void pps_init_delays_spec(struct intel_dp *intel_dp,
1384 				 struct edp_power_seq *spec)
1385 {
1386 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1387 
1388 	lockdep_assert_held(&dev_priv->display.pps.mutex);
1389 
1390 	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
1391 	 * our hw here, which are all in 100usec. */
1392 	spec->t1_t3 = 210 * 10;
1393 	spec->t8 = 50 * 10; /* no limit for t8, use t7 instead */
1394 	spec->t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
1395 	spec->t10 = 500 * 10;
1396 	/* This one is special and actually in units of 100ms, but zero
1397 	 * based in the hw (so we need to add 100 ms). But the sw vbt
1398 	 * table multiplies it with 1000 to make it in units of 100usec,
1399 	 * too. */
1400 	spec->t11_t12 = (510 + 100) * 10;
1401 
1402 	intel_pps_dump_state(intel_dp, "spec", spec);
1403 }
1404 
pps_init_delays(struct intel_dp * intel_dp)1405 static void pps_init_delays(struct intel_dp *intel_dp)
1406 {
1407 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1408 	struct edp_power_seq cur, vbt, spec,
1409 		*final = &intel_dp->pps.pps_delays;
1410 
1411 	lockdep_assert_held(&dev_priv->display.pps.mutex);
1412 
1413 	/* already initialized? */
1414 	if (pps_delays_valid(final))
1415 		return;
1416 
1417 	pps_init_delays_bios(intel_dp, &cur);
1418 	pps_init_delays_vbt(intel_dp, &vbt);
1419 	pps_init_delays_spec(intel_dp, &spec);
1420 
1421 	/* Use the max of the register settings and vbt. If both are
1422 	 * unset, fall back to the spec limits. */
1423 #define assign_final(field)	final->field = (max(cur.field, vbt.field) == 0 ? \
1424 				       spec.field : \
1425 				       max(cur.field, vbt.field))
1426 	assign_final(t1_t3);
1427 	assign_final(t8);
1428 	assign_final(t9);
1429 	assign_final(t10);
1430 	assign_final(t11_t12);
1431 #undef assign_final
1432 
1433 #define get_delay(field)	(DIV_ROUND_UP(final->field, 10))
1434 	intel_dp->pps.panel_power_up_delay = get_delay(t1_t3);
1435 	intel_dp->pps.backlight_on_delay = get_delay(t8);
1436 	intel_dp->pps.backlight_off_delay = get_delay(t9);
1437 	intel_dp->pps.panel_power_down_delay = get_delay(t10);
1438 	intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12);
1439 #undef get_delay
1440 
1441 	drm_dbg_kms(&dev_priv->drm,
1442 		    "panel power up delay %d, power down delay %d, power cycle delay %d\n",
1443 		    intel_dp->pps.panel_power_up_delay,
1444 		    intel_dp->pps.panel_power_down_delay,
1445 		    intel_dp->pps.panel_power_cycle_delay);
1446 
1447 	drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
1448 		    intel_dp->pps.backlight_on_delay,
1449 		    intel_dp->pps.backlight_off_delay);
1450 
1451 	/*
1452 	 * We override the HW backlight delays to 1 because we do manual waits
1453 	 * on them. For T8, even BSpec recommends doing it. For T9, if we
1454 	 * don't do this, we'll end up waiting for the backlight off delay
1455 	 * twice: once when we do the manual sleep, and once when we disable
1456 	 * the panel and wait for the PP_STATUS bit to become zero.
1457 	 */
1458 	final->t8 = 1;
1459 	final->t9 = 1;
1460 
1461 	/*
1462 	 * HW has only a 100msec granularity for t11_t12 so round it up
1463 	 * accordingly.
1464 	 */
1465 	final->t11_t12 = roundup(final->t11_t12, 100 * 10);
1466 }
1467 
pps_init_registers(struct intel_dp * intel_dp,bool force_disable_vdd)1468 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd)
1469 {
1470 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1471 	u32 pp_on, pp_off, port_sel = 0;
1472 	int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
1473 	struct pps_registers regs;
1474 	enum port port = dp_to_dig_port(intel_dp)->base.port;
1475 	const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
1476 
1477 	lockdep_assert_held(&dev_priv->display.pps.mutex);
1478 
1479 	intel_pps_get_registers(intel_dp, &regs);
1480 
1481 	/*
1482 	 * On some VLV machines the BIOS can leave the VDD
1483 	 * enabled even on power sequencers which aren't
1484 	 * hooked up to any port. This would mess up the
1485 	 * power domain tracking the first time we pick
1486 	 * one of these power sequencers for use since
1487 	 * intel_pps_vdd_on_unlocked() would notice that the VDD was
1488 	 * already on and therefore wouldn't grab the power
1489 	 * domain reference. Disable VDD first to avoid this.
1490 	 * This also avoids spuriously turning the VDD on as
1491 	 * soon as the new power sequencer gets initialized.
1492 	 */
1493 	if (force_disable_vdd) {
1494 		u32 pp = ilk_get_pp_control(intel_dp);
1495 
1496 		drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
1497 			 "Panel power already on\n");
1498 
1499 		if (pp & EDP_FORCE_VDD)
1500 			drm_dbg_kms(&dev_priv->drm,
1501 				    "VDD already on, disabling first\n");
1502 
1503 		pp &= ~EDP_FORCE_VDD;
1504 
1505 		intel_de_write(dev_priv, regs.pp_ctrl, pp);
1506 	}
1507 
1508 	pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
1509 		REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
1510 	pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
1511 		REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
1512 
1513 	/* Haswell doesn't have any port selection bits for the panel
1514 	 * power sequencer any more. */
1515 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1516 		port_sel = PANEL_PORT_SELECT_VLV(port);
1517 	} else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
1518 		switch (port) {
1519 		case PORT_A:
1520 			port_sel = PANEL_PORT_SELECT_DPA;
1521 			break;
1522 		case PORT_C:
1523 			port_sel = PANEL_PORT_SELECT_DPC;
1524 			break;
1525 		case PORT_D:
1526 			port_sel = PANEL_PORT_SELECT_DPD;
1527 			break;
1528 		default:
1529 			MISSING_CASE(port);
1530 			break;
1531 		}
1532 	}
1533 
1534 	pp_on |= port_sel;
1535 
1536 	intel_de_write(dev_priv, regs.pp_on, pp_on);
1537 	intel_de_write(dev_priv, regs.pp_off, pp_off);
1538 
1539 	/*
1540 	 * Compute the divisor for the pp clock, simply match the Bspec formula.
1541 	 */
1542 	if (i915_mmio_reg_valid(regs.pp_div))
1543 		intel_de_write(dev_priv, regs.pp_div,
1544 			       REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
1545 	else
1546 		intel_de_rmw(dev_priv, regs.pp_ctrl, BXT_POWER_CYCLE_DELAY_MASK,
1547 			     REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK,
1548 					    DIV_ROUND_UP(seq->t11_t12, 1000)));
1549 
1550 	drm_dbg_kms(&dev_priv->drm,
1551 		    "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
1552 		    intel_de_read(dev_priv, regs.pp_on),
1553 		    intel_de_read(dev_priv, regs.pp_off),
1554 		    i915_mmio_reg_valid(regs.pp_div) ?
1555 		    intel_de_read(dev_priv, regs.pp_div) :
1556 		    (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
1557 }
1558 
intel_pps_encoder_reset(struct intel_dp * intel_dp)1559 void intel_pps_encoder_reset(struct intel_dp *intel_dp)
1560 {
1561 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1562 	intel_wakeref_t wakeref;
1563 
1564 	if (!intel_dp_is_edp(intel_dp))
1565 		return;
1566 
1567 	with_intel_pps_lock(intel_dp, wakeref) {
1568 		/*
1569 		 * Reinit the power sequencer also on the resume path, in case
1570 		 * BIOS did something nasty with it.
1571 		 */
1572 		if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1573 			vlv_initial_power_sequencer_setup(intel_dp);
1574 
1575 		pps_init_delays(intel_dp);
1576 		pps_init_registers(intel_dp, false);
1577 		pps_vdd_init(intel_dp);
1578 
1579 		if (edp_have_panel_vdd(intel_dp))
1580 			edp_panel_vdd_schedule_off(intel_dp);
1581 	}
1582 }
1583 
intel_pps_init(struct intel_dp * intel_dp)1584 bool intel_pps_init(struct intel_dp *intel_dp)
1585 {
1586 	intel_wakeref_t wakeref;
1587 	bool ret;
1588 
1589 	intel_dp->pps.initializing = true;
1590 	INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
1591 
1592 	pps_init_timestamps(intel_dp);
1593 
1594 	with_intel_pps_lock(intel_dp, wakeref) {
1595 		ret = pps_initial_setup(intel_dp);
1596 
1597 		pps_init_delays(intel_dp);
1598 		pps_init_registers(intel_dp, false);
1599 		pps_vdd_init(intel_dp);
1600 	}
1601 
1602 	return ret;
1603 }
1604 
pps_init_late(struct intel_dp * intel_dp)1605 static void pps_init_late(struct intel_dp *intel_dp)
1606 {
1607 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1608 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1609 	struct intel_connector *connector = intel_dp->attached_connector;
1610 
1611 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1612 		return;
1613 
1614 	if (intel_num_pps(i915) < 2)
1615 		return;
1616 
1617 	drm_WARN(&i915->drm, connector->panel.vbt.backlight.controller >= 0 &&
1618 		 intel_dp->pps.pps_idx != connector->panel.vbt.backlight.controller,
1619 		 "[ENCODER:%d:%s] power sequencer mismatch: %d (initial) vs. %d (VBT)\n",
1620 		 encoder->base.base.id, encoder->base.name,
1621 		 intel_dp->pps.pps_idx, connector->panel.vbt.backlight.controller);
1622 
1623 	if (connector->panel.vbt.backlight.controller >= 0)
1624 		intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;
1625 }
1626 
intel_pps_init_late(struct intel_dp * intel_dp)1627 void intel_pps_init_late(struct intel_dp *intel_dp)
1628 {
1629 	intel_wakeref_t wakeref;
1630 
1631 	with_intel_pps_lock(intel_dp, wakeref) {
1632 		/* Reinit delays after per-panel info has been parsed from VBT */
1633 		pps_init_late(intel_dp);
1634 
1635 		memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays));
1636 		pps_init_delays(intel_dp);
1637 		pps_init_registers(intel_dp, false);
1638 
1639 		intel_dp->pps.initializing = false;
1640 
1641 		if (edp_have_panel_vdd(intel_dp))
1642 			edp_panel_vdd_schedule_off(intel_dp);
1643 	}
1644 }
1645 
intel_pps_unlock_regs_wa(struct drm_i915_private * dev_priv)1646 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
1647 {
1648 	int pps_num;
1649 	int pps_idx;
1650 
1651 	if (!HAS_DISPLAY(dev_priv) || HAS_DDI(dev_priv))
1652 		return;
1653 	/*
1654 	 * This w/a is needed at least on CPT/PPT, but to be sure apply it
1655 	 * everywhere where registers can be write protected.
1656 	 */
1657 	pps_num = intel_num_pps(dev_priv);
1658 
1659 	for (pps_idx = 0; pps_idx < pps_num; pps_idx++)
1660 		intel_de_rmw(dev_priv, PP_CONTROL(pps_idx),
1661 			     PANEL_UNLOCK_MASK, PANEL_UNLOCK_REGS);
1662 }
1663 
intel_pps_setup(struct drm_i915_private * i915)1664 void intel_pps_setup(struct drm_i915_private *i915)
1665 {
1666 	if (HAS_PCH_SPLIT(i915) || IS_GEMINILAKE(i915) || IS_BROXTON(i915))
1667 		i915->display.pps.mmio_base = PCH_PPS_BASE;
1668 	else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1669 		i915->display.pps.mmio_base = VLV_PPS_BASE;
1670 	else
1671 		i915->display.pps.mmio_base = PPS_BASE;
1672 }
1673 
assert_pps_unlocked(struct drm_i915_private * dev_priv,enum pipe pipe)1674 void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1675 {
1676 	i915_reg_t pp_reg;
1677 	u32 val;
1678 	enum pipe panel_pipe = INVALID_PIPE;
1679 	bool locked = true;
1680 
1681 	if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
1682 		return;
1683 
1684 	if (HAS_PCH_SPLIT(dev_priv)) {
1685 		u32 port_sel;
1686 
1687 		pp_reg = PP_CONTROL(0);
1688 		port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1689 
1690 		switch (port_sel) {
1691 		case PANEL_PORT_SELECT_LVDS:
1692 			intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1693 			break;
1694 		case PANEL_PORT_SELECT_DPA:
1695 			g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1696 			break;
1697 		case PANEL_PORT_SELECT_DPC:
1698 			g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1699 			break;
1700 		case PANEL_PORT_SELECT_DPD:
1701 			g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1702 			break;
1703 		default:
1704 			MISSING_CASE(port_sel);
1705 			break;
1706 		}
1707 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1708 		/* presumably write lock depends on pipe, not port select */
1709 		pp_reg = PP_CONTROL(pipe);
1710 		panel_pipe = pipe;
1711 	} else {
1712 		u32 port_sel;
1713 
1714 		pp_reg = PP_CONTROL(0);
1715 		port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1716 
1717 		drm_WARN_ON(&dev_priv->drm,
1718 			    port_sel != PANEL_PORT_SELECT_LVDS);
1719 		intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1720 	}
1721 
1722 	val = intel_de_read(dev_priv, pp_reg);
1723 	if (!(val & PANEL_POWER_ON) ||
1724 	    ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1725 		locked = false;
1726 
1727 	I915_STATE_WARN(dev_priv, panel_pipe == pipe && locked,
1728 			"panel assertion failure, pipe %c regs locked\n",
1729 			pipe_name(pipe));
1730 }
1731