xref: /openbmc/qemu/hw/net/e1000e_core.c (revision 4cadf102)
1 /*
2  * Core code for QEMU e1000e emulation
3  *
4  * Software developer's manuals:
5  * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
6  *
7  * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
8  * Developed by Daynix Computing LTD (http://www.daynix.com)
9  *
10  * Authors:
11  * Dmitry Fleytman <dmitry@daynix.com>
12  * Leonid Bloch <leonid@daynix.com>
13  * Yan Vugenfirer <yan@daynix.com>
14  *
15  * Based on work done by:
16  * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
17  * Copyright (c) 2008 Qumranet
18  * Based on work done by:
19  * Copyright (c) 2007 Dan Aloni
20  * Copyright (c) 2004 Antony T Curtis
21  *
22  * This library is free software; you can redistribute it and/or
23  * modify it under the terms of the GNU Lesser General Public
24  * License as published by the Free Software Foundation; either
25  * version 2.1 of the License, or (at your option) any later version.
26  *
27  * This library is distributed in the hope that it will be useful,
28  * but WITHOUT ANY WARRANTY; without even the implied warranty of
29  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
30  * Lesser General Public License for more details.
31  *
32  * You should have received a copy of the GNU Lesser General Public
33  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
34  */
35 
36 #include "qemu/osdep.h"
37 #include "qemu/log.h"
38 #include "net/net.h"
39 #include "net/tap.h"
40 #include "hw/net/mii.h"
41 #include "hw/pci/msi.h"
42 #include "hw/pci/msix.h"
43 #include "sysemu/runstate.h"
44 
45 #include "net_tx_pkt.h"
46 #include "net_rx_pkt.h"
47 
48 #include "e1000_common.h"
49 #include "e1000x_common.h"
50 #include "e1000e_core.h"
51 
52 #include "trace.h"
53 
54 /* No more then 7813 interrupts per second according to spec 10.2.4.2 */
55 #define E1000E_MIN_XITR     (500)
56 
57 #define E1000E_MAX_TX_FRAGS (64)
58 
59 union e1000_rx_desc_union {
60     struct e1000_rx_desc legacy;
61     union e1000_rx_desc_extended extended;
62     union e1000_rx_desc_packet_split packet_split;
63 };
64 
65 static ssize_t
66 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt,
67                         bool has_vnet);
68 
69 static inline void
70 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val);
71 
72 static void e1000e_reset(E1000ECore *core, bool sw);
73 
74 static inline void
e1000e_process_ts_option(E1000ECore * core,struct e1000_tx_desc * dp)75 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp)
76 {
77     if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) {
78         trace_e1000e_wrn_no_ts_support();
79     }
80 }
81 
82 static inline void
e1000e_process_snap_option(E1000ECore * core,uint32_t cmd_and_length)83 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length)
84 {
85     if (cmd_and_length & E1000_TXD_CMD_SNAP) {
86         trace_e1000e_wrn_no_snap_support();
87     }
88 }
89 
90 static inline void
e1000e_raise_legacy_irq(E1000ECore * core)91 e1000e_raise_legacy_irq(E1000ECore *core)
92 {
93     trace_e1000e_irq_legacy_notify(true);
94     e1000x_inc_reg_if_not_full(core->mac, IAC);
95     pci_set_irq(core->owner, 1);
96 }
97 
98 static inline void
e1000e_lower_legacy_irq(E1000ECore * core)99 e1000e_lower_legacy_irq(E1000ECore *core)
100 {
101     trace_e1000e_irq_legacy_notify(false);
102     pci_set_irq(core->owner, 0);
103 }
104 
105 static inline void
e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer * timer)106 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer)
107 {
108     int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] *
109                                  timer->delay_resolution_ns;
110 
111     trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns);
112 
113     timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns);
114 
115     timer->running = true;
116 }
117 
118 static void
e1000e_intmgr_timer_resume(E1000IntrDelayTimer * timer)119 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer)
120 {
121     if (timer->running) {
122         e1000e_intrmgr_rearm_timer(timer);
123     }
124 }
125 
126 static inline void
e1000e_intrmgr_stop_timer(E1000IntrDelayTimer * timer)127 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer)
128 {
129     if (timer->running) {
130         timer_del(timer->timer);
131         timer->running = false;
132     }
133 }
134 
135 static inline void
e1000e_intrmgr_fire_delayed_interrupts(E1000ECore * core)136 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core)
137 {
138     trace_e1000e_irq_fire_delayed_interrupts();
139     e1000e_set_interrupt_cause(core, 0);
140 }
141 
142 static void
e1000e_intrmgr_on_timer(void * opaque)143 e1000e_intrmgr_on_timer(void *opaque)
144 {
145     E1000IntrDelayTimer *timer = opaque;
146 
147     trace_e1000e_irq_throttling_timer(timer->delay_reg << 2);
148 
149     timer->running = false;
150     e1000e_intrmgr_fire_delayed_interrupts(timer->core);
151 }
152 
153 static void
e1000e_intrmgr_on_throttling_timer(void * opaque)154 e1000e_intrmgr_on_throttling_timer(void *opaque)
155 {
156     E1000IntrDelayTimer *timer = opaque;
157 
158     timer->running = false;
159 
160     if (timer->core->mac[IMS] & timer->core->mac[ICR]) {
161         if (msi_enabled(timer->core->owner)) {
162             trace_e1000e_irq_msi_notify_postponed();
163             msi_notify(timer->core->owner, 0);
164         } else {
165             trace_e1000e_irq_legacy_notify_postponed();
166             e1000e_raise_legacy_irq(timer->core);
167         }
168     }
169 }
170 
171 static void
e1000e_intrmgr_on_msix_throttling_timer(void * opaque)172 e1000e_intrmgr_on_msix_throttling_timer(void *opaque)
173 {
174     E1000IntrDelayTimer *timer = opaque;
175     int idx = timer - &timer->core->eitr[0];
176 
177     timer->running = false;
178 
179     trace_e1000e_irq_msix_notify_postponed_vec(idx);
180     msix_notify(timer->core->owner, idx);
181 }
182 
183 static void
e1000e_intrmgr_initialize_all_timers(E1000ECore * core,bool create)184 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create)
185 {
186     int i;
187 
188     core->radv.delay_reg = RADV;
189     core->rdtr.delay_reg = RDTR;
190     core->raid.delay_reg = RAID;
191     core->tadv.delay_reg = TADV;
192     core->tidv.delay_reg = TIDV;
193 
194     core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
195     core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
196     core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
197     core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
198     core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
199 
200     core->radv.core = core;
201     core->rdtr.core = core;
202     core->raid.core = core;
203     core->tadv.core = core;
204     core->tidv.core = core;
205 
206     core->itr.core = core;
207     core->itr.delay_reg = ITR;
208     core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
209 
210     for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
211         core->eitr[i].core = core;
212         core->eitr[i].delay_reg = EITR + i;
213         core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
214     }
215 
216     if (!create) {
217         return;
218     }
219 
220     core->radv.timer =
221         timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv);
222     core->rdtr.timer =
223         timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr);
224     core->raid.timer =
225         timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid);
226 
227     core->tadv.timer =
228         timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv);
229     core->tidv.timer =
230         timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv);
231 
232     core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
233                                    e1000e_intrmgr_on_throttling_timer,
234                                    &core->itr);
235 
236     for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
237         core->eitr[i].timer =
238             timer_new_ns(QEMU_CLOCK_VIRTUAL,
239                          e1000e_intrmgr_on_msix_throttling_timer,
240                          &core->eitr[i]);
241     }
242 }
243 
244 static inline void
e1000e_intrmgr_stop_delay_timers(E1000ECore * core)245 e1000e_intrmgr_stop_delay_timers(E1000ECore *core)
246 {
247     e1000e_intrmgr_stop_timer(&core->radv);
248     e1000e_intrmgr_stop_timer(&core->rdtr);
249     e1000e_intrmgr_stop_timer(&core->raid);
250     e1000e_intrmgr_stop_timer(&core->tidv);
251     e1000e_intrmgr_stop_timer(&core->tadv);
252 }
253 
254 static bool
e1000e_intrmgr_delay_rx_causes(E1000ECore * core,uint32_t * causes)255 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes)
256 {
257     uint32_t delayable_causes;
258     uint32_t rdtr = core->mac[RDTR];
259     uint32_t radv = core->mac[RADV];
260     uint32_t raid = core->mac[RAID];
261 
262     if (msix_enabled(core->owner)) {
263         return false;
264     }
265 
266     delayable_causes = E1000_ICR_RXQ0 |
267                        E1000_ICR_RXQ1 |
268                        E1000_ICR_RXT0;
269 
270     if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) {
271         delayable_causes |= E1000_ICR_ACK;
272     }
273 
274     /* Clean up all causes that may be delayed */
275     core->delayed_causes |= *causes & delayable_causes;
276     *causes &= ~delayable_causes;
277 
278     /*
279      * Check if delayed RX interrupts disabled by client
280      * or if there are causes that cannot be delayed
281      */
282     if ((rdtr == 0) || (*causes != 0)) {
283         return false;
284     }
285 
286     /*
287      * Check if delayed RX ACK interrupts disabled by client
288      * and there is an ACK packet received
289      */
290     if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) {
291         return false;
292     }
293 
294     /* All causes delayed */
295     e1000e_intrmgr_rearm_timer(&core->rdtr);
296 
297     if (!core->radv.running && (radv != 0)) {
298         e1000e_intrmgr_rearm_timer(&core->radv);
299     }
300 
301     if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) {
302         e1000e_intrmgr_rearm_timer(&core->raid);
303     }
304 
305     return true;
306 }
307 
308 static bool
e1000e_intrmgr_delay_tx_causes(E1000ECore * core,uint32_t * causes)309 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes)
310 {
311     static const uint32_t delayable_causes = E1000_ICR_TXQ0 |
312                                              E1000_ICR_TXQ1 |
313                                              E1000_ICR_TXQE |
314                                              E1000_ICR_TXDW;
315 
316     if (msix_enabled(core->owner)) {
317         return false;
318     }
319 
320     /* Clean up all causes that may be delayed */
321     core->delayed_causes |= *causes & delayable_causes;
322     *causes &= ~delayable_causes;
323 
324     /* If there are causes that cannot be delayed */
325     if (*causes != 0) {
326         return false;
327     }
328 
329     /* All causes delayed */
330     e1000e_intrmgr_rearm_timer(&core->tidv);
331 
332     if (!core->tadv.running && (core->mac[TADV] != 0)) {
333         e1000e_intrmgr_rearm_timer(&core->tadv);
334     }
335 
336     return true;
337 }
338 
339 static uint32_t
e1000e_intmgr_collect_delayed_causes(E1000ECore * core)340 e1000e_intmgr_collect_delayed_causes(E1000ECore *core)
341 {
342     uint32_t res;
343 
344     if (msix_enabled(core->owner)) {
345         assert(core->delayed_causes == 0);
346         return 0;
347     }
348 
349     res = core->delayed_causes;
350     core->delayed_causes = 0;
351 
352     e1000e_intrmgr_stop_delay_timers(core);
353 
354     return res;
355 }
356 
357 static void
e1000e_intrmgr_fire_all_timers(E1000ECore * core)358 e1000e_intrmgr_fire_all_timers(E1000ECore *core)
359 {
360     int i;
361 
362     if (core->itr.running) {
363         timer_del(core->itr.timer);
364         e1000e_intrmgr_on_throttling_timer(&core->itr);
365     }
366 
367     for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
368         if (core->eitr[i].running) {
369             timer_del(core->eitr[i].timer);
370             e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]);
371         }
372     }
373 }
374 
375 static void
e1000e_intrmgr_resume(E1000ECore * core)376 e1000e_intrmgr_resume(E1000ECore *core)
377 {
378     int i;
379 
380     e1000e_intmgr_timer_resume(&core->radv);
381     e1000e_intmgr_timer_resume(&core->rdtr);
382     e1000e_intmgr_timer_resume(&core->raid);
383     e1000e_intmgr_timer_resume(&core->tidv);
384     e1000e_intmgr_timer_resume(&core->tadv);
385 
386     e1000e_intmgr_timer_resume(&core->itr);
387 
388     for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
389         e1000e_intmgr_timer_resume(&core->eitr[i]);
390     }
391 }
392 
393 static void
e1000e_intrmgr_reset(E1000ECore * core)394 e1000e_intrmgr_reset(E1000ECore *core)
395 {
396     int i;
397 
398     core->delayed_causes = 0;
399 
400     e1000e_intrmgr_stop_delay_timers(core);
401 
402     e1000e_intrmgr_stop_timer(&core->itr);
403 
404     for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
405         e1000e_intrmgr_stop_timer(&core->eitr[i]);
406     }
407 }
408 
409 static void
e1000e_intrmgr_pci_unint(E1000ECore * core)410 e1000e_intrmgr_pci_unint(E1000ECore *core)
411 {
412     int i;
413 
414     timer_free(core->radv.timer);
415     timer_free(core->rdtr.timer);
416     timer_free(core->raid.timer);
417 
418     timer_free(core->tadv.timer);
419     timer_free(core->tidv.timer);
420 
421     timer_free(core->itr.timer);
422 
423     for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
424         timer_free(core->eitr[i].timer);
425     }
426 }
427 
428 static void
e1000e_intrmgr_pci_realize(E1000ECore * core)429 e1000e_intrmgr_pci_realize(E1000ECore *core)
430 {
431     e1000e_intrmgr_initialize_all_timers(core, true);
432 }
433 
434 static inline bool
e1000e_rx_csum_enabled(E1000ECore * core)435 e1000e_rx_csum_enabled(E1000ECore *core)
436 {
437     return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true;
438 }
439 
440 static inline bool
e1000e_rx_use_legacy_descriptor(E1000ECore * core)441 e1000e_rx_use_legacy_descriptor(E1000ECore *core)
442 {
443     return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true;
444 }
445 
446 static inline bool
e1000e_rx_use_ps_descriptor(E1000ECore * core)447 e1000e_rx_use_ps_descriptor(E1000ECore *core)
448 {
449     return !e1000e_rx_use_legacy_descriptor(core) &&
450            (core->mac[RCTL] & E1000_RCTL_DTYP_PS);
451 }
452 
453 static inline bool
e1000e_rss_enabled(E1000ECore * core)454 e1000e_rss_enabled(E1000ECore *core)
455 {
456     return E1000_MRQC_ENABLED(core->mac[MRQC]) &&
457            !e1000e_rx_csum_enabled(core) &&
458            !e1000e_rx_use_legacy_descriptor(core);
459 }
460 
461 typedef struct E1000E_RSSInfo_st {
462     bool enabled;
463     uint32_t hash;
464     uint32_t queue;
465     uint32_t type;
466 } E1000E_RSSInfo;
467 
468 static uint32_t
e1000e_rss_get_hash_type(E1000ECore * core,struct NetRxPkt * pkt)469 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt)
470 {
471     bool hasip4, hasip6;
472     EthL4HdrProto l4hdr_proto;
473 
474     assert(e1000e_rss_enabled(core));
475 
476     net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
477 
478     if (hasip4) {
479         trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC],
480                                 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]),
481                                 E1000_MRQC_EN_IPV4(core->mac[MRQC]));
482 
483         if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
484             E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) {
485             return E1000_MRQ_RSS_TYPE_IPV4TCP;
486         }
487 
488         if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) {
489             return E1000_MRQ_RSS_TYPE_IPV4;
490         }
491     } else if (hasip6) {
492         eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt);
493 
494         bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS;
495         bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS;
496 
497         /*
498          * Following two traces must not be combined because resulting
499          * event will have 11 arguments totally and some trace backends
500          * (at least "ust") have limitation of maximum 10 arguments per
501          * event. Events with more arguments fail to compile for
502          * backends like these.
503          */
504         trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]);
505         trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto,
506                                 ip6info->has_ext_hdrs,
507                                 ip6info->rss_ex_dst_valid,
508                                 ip6info->rss_ex_src_valid,
509                                 core->mac[MRQC],
510                                 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC]),
511                                 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]),
512                                 E1000_MRQC_EN_IPV6(core->mac[MRQC]));
513 
514         if ((!ex_dis || !ip6info->has_ext_hdrs) &&
515             (!new_ex_dis || !(ip6info->rss_ex_dst_valid ||
516                               ip6info->rss_ex_src_valid))) {
517 
518             if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
519                 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC])) {
520                 return E1000_MRQ_RSS_TYPE_IPV6TCPEX;
521             }
522 
523             if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) {
524                 return E1000_MRQ_RSS_TYPE_IPV6EX;
525             }
526 
527         }
528 
529         if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) {
530             return E1000_MRQ_RSS_TYPE_IPV6;
531         }
532 
533     }
534 
535     return E1000_MRQ_RSS_TYPE_NONE;
536 }
537 
538 static uint32_t
e1000e_rss_calc_hash(E1000ECore * core,struct NetRxPkt * pkt,E1000E_RSSInfo * info)539 e1000e_rss_calc_hash(E1000ECore *core,
540                      struct NetRxPkt *pkt,
541                      E1000E_RSSInfo *info)
542 {
543     NetRxPktRssType type;
544 
545     assert(e1000e_rss_enabled(core));
546 
547     switch (info->type) {
548     case E1000_MRQ_RSS_TYPE_IPV4:
549         type = NetPktRssIpV4;
550         break;
551     case E1000_MRQ_RSS_TYPE_IPV4TCP:
552         type = NetPktRssIpV4Tcp;
553         break;
554     case E1000_MRQ_RSS_TYPE_IPV6TCPEX:
555         type = NetPktRssIpV6TcpEx;
556         break;
557     case E1000_MRQ_RSS_TYPE_IPV6:
558         type = NetPktRssIpV6;
559         break;
560     case E1000_MRQ_RSS_TYPE_IPV6EX:
561         type = NetPktRssIpV6Ex;
562         break;
563     default:
564         assert(false);
565         return 0;
566     }
567 
568     return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]);
569 }
570 
571 static void
e1000e_rss_parse_packet(E1000ECore * core,struct NetRxPkt * pkt,E1000E_RSSInfo * info)572 e1000e_rss_parse_packet(E1000ECore *core,
573                         struct NetRxPkt *pkt,
574                         E1000E_RSSInfo *info)
575 {
576     trace_e1000e_rx_rss_started();
577 
578     if (!e1000e_rss_enabled(core)) {
579         info->enabled = false;
580         info->hash = 0;
581         info->queue = 0;
582         info->type = 0;
583         trace_e1000e_rx_rss_disabled();
584         return;
585     }
586 
587     info->enabled = true;
588 
589     info->type = e1000e_rss_get_hash_type(core, pkt);
590 
591     trace_e1000e_rx_rss_type(info->type);
592 
593     if (info->type == E1000_MRQ_RSS_TYPE_NONE) {
594         info->hash = 0;
595         info->queue = 0;
596         return;
597     }
598 
599     info->hash = e1000e_rss_calc_hash(core, pkt, info);
600     info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash);
601 }
602 
603 static bool
e1000e_setup_tx_offloads(E1000ECore * core,struct e1000e_tx * tx)604 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx)
605 {
606     if (tx->props.tse && tx->cptse) {
607         if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss)) {
608             return false;
609         }
610 
611         net_tx_pkt_update_ip_checksums(tx->tx_pkt);
612         e1000x_inc_reg_if_not_full(core->mac, TSCTC);
613         return true;
614     }
615 
616     if (tx->sum_needed & E1000_TXD_POPTS_TXSM) {
617         if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) {
618             return false;
619         }
620     }
621 
622     if (tx->sum_needed & E1000_TXD_POPTS_IXSM) {
623         net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt);
624     }
625 
626     return true;
627 }
628 
e1000e_tx_pkt_callback(void * core,const struct iovec * iov,int iovcnt,const struct iovec * virt_iov,int virt_iovcnt)629 static void e1000e_tx_pkt_callback(void *core,
630                                    const struct iovec *iov,
631                                    int iovcnt,
632                                    const struct iovec *virt_iov,
633                                    int virt_iovcnt)
634 {
635     e1000e_receive_internal(core, virt_iov, virt_iovcnt, true);
636 }
637 
638 static bool
e1000e_tx_pkt_send(E1000ECore * core,struct e1000e_tx * tx,int queue_index)639 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index)
640 {
641     int target_queue = MIN(core->max_queue_num, queue_index);
642     NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue);
643 
644     if (!e1000e_setup_tx_offloads(core, tx)) {
645         return false;
646     }
647 
648     net_tx_pkt_dump(tx->tx_pkt);
649 
650     if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) ||
651         ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) {
652         return net_tx_pkt_send_custom(tx->tx_pkt, false,
653                                       e1000e_tx_pkt_callback, core);
654     } else {
655         return net_tx_pkt_send(tx->tx_pkt, queue);
656     }
657 }
658 
659 static void
e1000e_on_tx_done_update_stats(E1000ECore * core,struct NetTxPkt * tx_pkt)660 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt)
661 {
662     static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
663                                     PTC1023, PTC1522 };
664 
665     size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4;
666 
667     e1000x_increase_size_stats(core->mac, PTCregs, tot_len);
668     e1000x_inc_reg_if_not_full(core->mac, TPT);
669     e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len);
670 
671     switch (net_tx_pkt_get_packet_type(tx_pkt)) {
672     case ETH_PKT_BCAST:
673         e1000x_inc_reg_if_not_full(core->mac, BPTC);
674         break;
675     case ETH_PKT_MCAST:
676         e1000x_inc_reg_if_not_full(core->mac, MPTC);
677         break;
678     case ETH_PKT_UCAST:
679         break;
680     default:
681         g_assert_not_reached();
682     }
683 
684     e1000x_inc_reg_if_not_full(core->mac, GPTC);
685     e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len);
686 }
687 
688 static void
e1000e_process_tx_desc(E1000ECore * core,struct e1000e_tx * tx,struct e1000_tx_desc * dp,int queue_index)689 e1000e_process_tx_desc(E1000ECore *core,
690                        struct e1000e_tx *tx,
691                        struct e1000_tx_desc *dp,
692                        int queue_index)
693 {
694     uint32_t txd_lower = le32_to_cpu(dp->lower.data);
695     uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
696     unsigned int split_size = txd_lower & 0xffff;
697     uint64_t addr;
698     struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
699     bool eop = txd_lower & E1000_TXD_CMD_EOP;
700 
701     if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */
702         e1000x_read_tx_ctx_descr(xp, &tx->props);
703         e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length));
704         return;
705     } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
706         /* data descriptor */
707         tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
708         tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0;
709         e1000e_process_ts_option(core, dp);
710     } else {
711         /* legacy descriptor */
712         e1000e_process_ts_option(core, dp);
713         tx->cptse = 0;
714     }
715 
716     addr = le64_to_cpu(dp->buffer_addr);
717 
718     if (!tx->skip_cp) {
719         if (!net_tx_pkt_add_raw_fragment_pci(tx->tx_pkt, core->owner,
720                                              addr, split_size)) {
721             tx->skip_cp = true;
722         }
723     }
724 
725     if (eop) {
726         if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) {
727             if (e1000x_vlan_enabled(core->mac) &&
728                 e1000x_is_vlan_txd(txd_lower)) {
729                 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt,
730                     le16_to_cpu(dp->upper.fields.special), core->mac[VET]);
731             }
732             if (e1000e_tx_pkt_send(core, tx, queue_index)) {
733                 e1000e_on_tx_done_update_stats(core, tx->tx_pkt);
734             }
735         }
736 
737         tx->skip_cp = false;
738         net_tx_pkt_reset(tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner);
739 
740         tx->sum_needed = 0;
741         tx->cptse = 0;
742     }
743 }
744 
745 static inline uint32_t
e1000e_tx_wb_interrupt_cause(E1000ECore * core,int queue_idx)746 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx)
747 {
748     if (!msix_enabled(core->owner)) {
749         return E1000_ICR_TXDW;
750     }
751 
752     return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1;
753 }
754 
755 static inline uint32_t
e1000e_rx_wb_interrupt_cause(E1000ECore * core,int queue_idx,bool min_threshold_hit)756 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx,
757                              bool min_threshold_hit)
758 {
759     if (!msix_enabled(core->owner)) {
760         return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0);
761     }
762 
763     return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1;
764 }
765 
766 static uint32_t
e1000e_txdesc_writeback(E1000ECore * core,dma_addr_t base,struct e1000_tx_desc * dp,bool * ide,int queue_idx)767 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base,
768                         struct e1000_tx_desc *dp, bool *ide, int queue_idx)
769 {
770     uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
771 
772     if (!(txd_lower & E1000_TXD_CMD_RS) &&
773         !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) {
774         return 0;
775     }
776 
777     *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false;
778 
779     txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD;
780 
781     dp->upper.data = cpu_to_le32(txd_upper);
782     pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp),
783                   &dp->upper, sizeof(dp->upper));
784     return e1000e_tx_wb_interrupt_cause(core, queue_idx);
785 }
786 
787 typedef struct E1000ERingInfo {
788     int dbah;
789     int dbal;
790     int dlen;
791     int dh;
792     int dt;
793     int idx;
794 } E1000ERingInfo;
795 
796 static inline bool
e1000e_ring_empty(E1000ECore * core,const E1000ERingInfo * r)797 e1000e_ring_empty(E1000ECore *core, const E1000ERingInfo *r)
798 {
799     return core->mac[r->dh] == core->mac[r->dt] ||
800                 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN;
801 }
802 
803 static inline uint64_t
e1000e_ring_base(E1000ECore * core,const E1000ERingInfo * r)804 e1000e_ring_base(E1000ECore *core, const E1000ERingInfo *r)
805 {
806     uint64_t bah = core->mac[r->dbah];
807     uint64_t bal = core->mac[r->dbal];
808 
809     return (bah << 32) + bal;
810 }
811 
812 static inline uint64_t
e1000e_ring_head_descr(E1000ECore * core,const E1000ERingInfo * r)813 e1000e_ring_head_descr(E1000ECore *core, const E1000ERingInfo *r)
814 {
815     return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh];
816 }
817 
818 static inline void
e1000e_ring_advance(E1000ECore * core,const E1000ERingInfo * r,uint32_t count)819 e1000e_ring_advance(E1000ECore *core, const E1000ERingInfo *r, uint32_t count)
820 {
821     core->mac[r->dh] += count;
822 
823     if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) {
824         core->mac[r->dh] = 0;
825     }
826 }
827 
828 static inline uint32_t
e1000e_ring_free_descr_num(E1000ECore * core,const E1000ERingInfo * r)829 e1000e_ring_free_descr_num(E1000ECore *core, const E1000ERingInfo *r)
830 {
831     trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen],
832                                  core->mac[r->dh],  core->mac[r->dt]);
833 
834     if (core->mac[r->dh] <= core->mac[r->dt]) {
835         return core->mac[r->dt] - core->mac[r->dh];
836     }
837 
838     if (core->mac[r->dh] > core->mac[r->dt]) {
839         return core->mac[r->dlen] / E1000_RING_DESC_LEN +
840                core->mac[r->dt] - core->mac[r->dh];
841     }
842 
843     g_assert_not_reached();
844     return 0;
845 }
846 
847 static inline bool
e1000e_ring_enabled(E1000ECore * core,const E1000ERingInfo * r)848 e1000e_ring_enabled(E1000ECore *core, const E1000ERingInfo *r)
849 {
850     return core->mac[r->dlen] > 0;
851 }
852 
853 static inline uint32_t
e1000e_ring_len(E1000ECore * core,const E1000ERingInfo * r)854 e1000e_ring_len(E1000ECore *core, const E1000ERingInfo *r)
855 {
856     return core->mac[r->dlen];
857 }
858 
859 typedef struct E1000E_TxRing_st {
860     const E1000ERingInfo *i;
861     struct e1000e_tx *tx;
862 } E1000E_TxRing;
863 
864 static inline int
e1000e_mq_queue_idx(int base_reg_idx,int reg_idx)865 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx)
866 {
867     return (reg_idx - base_reg_idx) / (0x100 >> 2);
868 }
869 
870 static inline void
e1000e_tx_ring_init(E1000ECore * core,E1000E_TxRing * txr,int idx)871 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx)
872 {
873     static const E1000ERingInfo i[E1000E_NUM_QUEUES] = {
874         { TDBAH,  TDBAL,  TDLEN,  TDH,  TDT, 0 },
875         { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 }
876     };
877 
878     assert(idx < ARRAY_SIZE(i));
879 
880     txr->i     = &i[idx];
881     txr->tx    = &core->tx[idx];
882 }
883 
884 typedef struct E1000E_RxRing_st {
885     const E1000ERingInfo *i;
886 } E1000E_RxRing;
887 
888 static inline void
e1000e_rx_ring_init(E1000ECore * core,E1000E_RxRing * rxr,int idx)889 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx)
890 {
891     static const E1000ERingInfo i[E1000E_NUM_QUEUES] = {
892         { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 },
893         { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 }
894     };
895 
896     assert(idx < ARRAY_SIZE(i));
897 
898     rxr->i      = &i[idx];
899 }
900 
901 static void
e1000e_start_xmit(E1000ECore * core,const E1000E_TxRing * txr)902 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr)
903 {
904     dma_addr_t base;
905     struct e1000_tx_desc desc;
906     bool ide = false;
907     const E1000ERingInfo *txi = txr->i;
908     uint32_t cause = E1000_ICS_TXQE;
909 
910     if (!(core->mac[TCTL] & E1000_TCTL_EN)) {
911         trace_e1000e_tx_disabled();
912         return;
913     }
914 
915     while (!e1000e_ring_empty(core, txi)) {
916         base = e1000e_ring_head_descr(core, txi);
917 
918         pci_dma_read(core->owner, base, &desc, sizeof(desc));
919 
920         trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr,
921                               desc.lower.data, desc.upper.data);
922 
923         e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx);
924         cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx);
925 
926         e1000e_ring_advance(core, txi, 1);
927     }
928 
929     if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) {
930         e1000e_set_interrupt_cause(core, cause);
931     }
932 
933     net_tx_pkt_reset(txr->tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner);
934 }
935 
936 static bool
e1000e_has_rxbufs(E1000ECore * core,const E1000ERingInfo * r,size_t total_size)937 e1000e_has_rxbufs(E1000ECore *core, const E1000ERingInfo *r,
938                   size_t total_size)
939 {
940     uint32_t bufs = e1000e_ring_free_descr_num(core, r);
941 
942     trace_e1000e_rx_has_buffers(r->idx, bufs, total_size,
943                                 core->rx_desc_buf_size);
944 
945     return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) *
946                          core->rx_desc_buf_size;
947 }
948 
949 void
e1000e_start_recv(E1000ECore * core)950 e1000e_start_recv(E1000ECore *core)
951 {
952     int i;
953 
954     trace_e1000e_rx_start_recv();
955 
956     for (i = 0; i <= core->max_queue_num; i++) {
957         qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i));
958     }
959 }
960 
961 bool
e1000e_can_receive(E1000ECore * core)962 e1000e_can_receive(E1000ECore *core)
963 {
964     int i;
965 
966     if (!e1000x_rx_ready(core->owner, core->mac)) {
967         return false;
968     }
969 
970     for (i = 0; i < E1000E_NUM_QUEUES; i++) {
971         E1000E_RxRing rxr;
972 
973         e1000e_rx_ring_init(core, &rxr, i);
974         if (e1000e_ring_enabled(core, rxr.i) &&
975             e1000e_has_rxbufs(core, rxr.i, 1)) {
976             trace_e1000e_rx_can_recv();
977             return true;
978         }
979     }
980 
981     trace_e1000e_rx_can_recv_rings_full();
982     return false;
983 }
984 
985 ssize_t
e1000e_receive(E1000ECore * core,const uint8_t * buf,size_t size)986 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size)
987 {
988     const struct iovec iov = {
989         .iov_base = (uint8_t *)buf,
990         .iov_len = size
991     };
992 
993     return e1000e_receive_iov(core, &iov, 1);
994 }
995 
996 static inline bool
e1000e_rx_l3_cso_enabled(E1000ECore * core)997 e1000e_rx_l3_cso_enabled(E1000ECore *core)
998 {
999     return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD);
1000 }
1001 
1002 static inline bool
e1000e_rx_l4_cso_enabled(E1000ECore * core)1003 e1000e_rx_l4_cso_enabled(E1000ECore *core)
1004 {
1005     return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD);
1006 }
1007 
1008 static bool
e1000e_receive_filter(E1000ECore * core,const void * buf)1009 e1000e_receive_filter(E1000ECore *core, const void *buf)
1010 {
1011     return (!e1000x_is_vlan_packet(buf, core->mac[VET]) ||
1012             e1000x_rx_vlan_filter(core->mac, PKT_GET_VLAN_HDR(buf))) &&
1013            e1000x_rx_group_filter(core->mac, buf);
1014 }
1015 
1016 static inline void
e1000e_read_lgcy_rx_descr(E1000ECore * core,struct e1000_rx_desc * desc,hwaddr * buff_addr)1017 e1000e_read_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc,
1018                           hwaddr *buff_addr)
1019 {
1020     *buff_addr = le64_to_cpu(desc->buffer_addr);
1021 }
1022 
1023 static inline void
e1000e_read_ext_rx_descr(E1000ECore * core,union e1000_rx_desc_extended * desc,hwaddr * buff_addr)1024 e1000e_read_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc,
1025                          hwaddr *buff_addr)
1026 {
1027     *buff_addr = le64_to_cpu(desc->read.buffer_addr);
1028 }
1029 
1030 static inline void
e1000e_read_ps_rx_descr(E1000ECore * core,union e1000_rx_desc_packet_split * desc,hwaddr buff_addr[MAX_PS_BUFFERS])1031 e1000e_read_ps_rx_descr(E1000ECore *core,
1032                         union e1000_rx_desc_packet_split *desc,
1033                         hwaddr buff_addr[MAX_PS_BUFFERS])
1034 {
1035     int i;
1036 
1037     for (i = 0; i < MAX_PS_BUFFERS; i++) {
1038         buff_addr[i] = le64_to_cpu(desc->read.buffer_addr[i]);
1039     }
1040 
1041     trace_e1000e_rx_desc_ps_read(buff_addr[0], buff_addr[1],
1042                                  buff_addr[2], buff_addr[3]);
1043 }
1044 
1045 static inline void
e1000e_read_rx_descr(E1000ECore * core,union e1000_rx_desc_union * desc,hwaddr buff_addr[MAX_PS_BUFFERS])1046 e1000e_read_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc,
1047                      hwaddr buff_addr[MAX_PS_BUFFERS])
1048 {
1049     if (e1000e_rx_use_legacy_descriptor(core)) {
1050         e1000e_read_lgcy_rx_descr(core, &desc->legacy, &buff_addr[0]);
1051         buff_addr[1] = buff_addr[2] = buff_addr[3] = 0;
1052     } else {
1053         if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1054             e1000e_read_ps_rx_descr(core, &desc->packet_split, buff_addr);
1055         } else {
1056             e1000e_read_ext_rx_descr(core, &desc->extended, &buff_addr[0]);
1057             buff_addr[1] = buff_addr[2] = buff_addr[3] = 0;
1058         }
1059     }
1060 }
1061 
1062 static void
e1000e_verify_csum_in_sw(E1000ECore * core,struct NetRxPkt * pkt,uint32_t * status_flags,EthL4HdrProto l4hdr_proto)1063 e1000e_verify_csum_in_sw(E1000ECore *core,
1064                          struct NetRxPkt *pkt,
1065                          uint32_t *status_flags,
1066                          EthL4HdrProto l4hdr_proto)
1067 {
1068     bool csum_valid;
1069     uint32_t csum_error;
1070 
1071     if (e1000e_rx_l3_cso_enabled(core)) {
1072         if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) {
1073             trace_e1000e_rx_metadata_l3_csum_validation_failed();
1074         } else {
1075             csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE;
1076             *status_flags |= E1000_RXD_STAT_IPCS | csum_error;
1077         }
1078     } else {
1079         trace_e1000e_rx_metadata_l3_cso_disabled();
1080     }
1081 
1082     if (!e1000e_rx_l4_cso_enabled(core)) {
1083         trace_e1000e_rx_metadata_l4_cso_disabled();
1084         return;
1085     }
1086 
1087     if (l4hdr_proto != ETH_L4_HDR_PROTO_TCP &&
1088         l4hdr_proto != ETH_L4_HDR_PROTO_UDP) {
1089         return;
1090     }
1091 
1092     if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
1093         trace_e1000e_rx_metadata_l4_csum_validation_failed();
1094         return;
1095     }
1096 
1097     csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE;
1098     *status_flags |= E1000_RXD_STAT_TCPCS | csum_error;
1099 
1100     if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1101         *status_flags |= E1000_RXD_STAT_UDPCS;
1102     }
1103 }
1104 
1105 static inline bool
e1000e_is_tcp_ack(E1000ECore * core,struct NetRxPkt * rx_pkt)1106 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt)
1107 {
1108     if (!net_rx_pkt_is_tcp_ack(rx_pkt)) {
1109         return false;
1110     }
1111 
1112     if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) {
1113         return !net_rx_pkt_has_tcp_data(rx_pkt);
1114     }
1115 
1116     return true;
1117 }
1118 
1119 static void
e1000e_build_rx_metadata(E1000ECore * core,struct NetRxPkt * pkt,bool is_eop,const E1000E_RSSInfo * rss_info,uint32_t * rss,uint32_t * mrq,uint32_t * status_flags,uint16_t * ip_id,uint16_t * vlan_tag)1120 e1000e_build_rx_metadata(E1000ECore *core,
1121                          struct NetRxPkt *pkt,
1122                          bool is_eop,
1123                          const E1000E_RSSInfo *rss_info,
1124                          uint32_t *rss, uint32_t *mrq,
1125                          uint32_t *status_flags,
1126                          uint16_t *ip_id,
1127                          uint16_t *vlan_tag)
1128 {
1129     struct virtio_net_hdr *vhdr;
1130     bool hasip4, hasip6;
1131     EthL4HdrProto l4hdr_proto;
1132     uint32_t pkt_type;
1133 
1134     *status_flags = E1000_RXD_STAT_DD;
1135 
1136     /* No additional metadata needed for non-EOP descriptors */
1137     if (!is_eop) {
1138         goto func_exit;
1139     }
1140 
1141     *status_flags |= E1000_RXD_STAT_EOP;
1142 
1143     net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
1144     trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto);
1145 
1146     /* VLAN state */
1147     if (net_rx_pkt_is_vlan_stripped(pkt)) {
1148         *status_flags |= E1000_RXD_STAT_VP;
1149         *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt));
1150         trace_e1000e_rx_metadata_vlan(*vlan_tag);
1151     }
1152 
1153     /* Packet parsing results */
1154     if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) {
1155         if (rss_info->enabled) {
1156             *rss = cpu_to_le32(rss_info->hash);
1157             *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8));
1158             trace_e1000e_rx_metadata_rss(*rss, *mrq);
1159         }
1160     } else if (hasip4) {
1161             *status_flags |= E1000_RXD_STAT_IPIDV;
1162             *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt));
1163             trace_e1000e_rx_metadata_ip_id(*ip_id);
1164     }
1165 
1166     if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && e1000e_is_tcp_ack(core, pkt)) {
1167         *status_flags |= E1000_RXD_STAT_ACK;
1168         trace_e1000e_rx_metadata_ack();
1169     }
1170 
1171     if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) {
1172         trace_e1000e_rx_metadata_ipv6_filtering_disabled();
1173         pkt_type = E1000_RXD_PKT_MAC;
1174     } else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP ||
1175                l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1176         pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP;
1177     } else if (hasip4 || hasip6) {
1178         pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6;
1179     } else {
1180         pkt_type = E1000_RXD_PKT_MAC;
1181     }
1182 
1183     *status_flags |= E1000_RXD_PKT_TYPE(pkt_type);
1184     trace_e1000e_rx_metadata_pkt_type(pkt_type);
1185 
1186     /* RX CSO information */
1187     if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) {
1188         trace_e1000e_rx_metadata_ipv6_sum_disabled();
1189         goto func_exit;
1190     }
1191 
1192     vhdr = net_rx_pkt_get_vhdr(pkt);
1193 
1194     if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) &&
1195         !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
1196         trace_e1000e_rx_metadata_virthdr_no_csum_info();
1197         e1000e_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto);
1198         goto func_exit;
1199     }
1200 
1201     if (e1000e_rx_l3_cso_enabled(core)) {
1202         *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0;
1203     } else {
1204         trace_e1000e_rx_metadata_l3_cso_disabled();
1205     }
1206 
1207     if (e1000e_rx_l4_cso_enabled(core)) {
1208         switch (l4hdr_proto) {
1209         case ETH_L4_HDR_PROTO_TCP:
1210             *status_flags |= E1000_RXD_STAT_TCPCS;
1211             break;
1212 
1213         case ETH_L4_HDR_PROTO_UDP:
1214             *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS;
1215             break;
1216 
1217         default:
1218             break;
1219         }
1220     } else {
1221         trace_e1000e_rx_metadata_l4_cso_disabled();
1222     }
1223 
1224 func_exit:
1225     trace_e1000e_rx_metadata_status_flags(*status_flags);
1226     *status_flags = cpu_to_le32(*status_flags);
1227 }
1228 
1229 static inline void
e1000e_write_lgcy_rx_descr(E1000ECore * core,struct e1000_rx_desc * desc,struct NetRxPkt * pkt,const E1000E_RSSInfo * rss_info,uint16_t length)1230 e1000e_write_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc,
1231                            struct NetRxPkt *pkt,
1232                            const E1000E_RSSInfo *rss_info,
1233                            uint16_t length)
1234 {
1235     uint32_t status_flags, rss, mrq;
1236     uint16_t ip_id;
1237 
1238     assert(!rss_info->enabled);
1239 
1240     desc->length = cpu_to_le16(length);
1241     desc->csum = 0;
1242 
1243     e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1244                              rss_info,
1245                              &rss, &mrq,
1246                              &status_flags, &ip_id,
1247                              &desc->special);
1248     desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24);
1249     desc->status = (uint8_t) le32_to_cpu(status_flags);
1250 }
1251 
1252 static inline void
e1000e_write_ext_rx_descr(E1000ECore * core,union e1000_rx_desc_extended * desc,struct NetRxPkt * pkt,const E1000E_RSSInfo * rss_info,uint16_t length)1253 e1000e_write_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc,
1254                           struct NetRxPkt *pkt,
1255                           const E1000E_RSSInfo *rss_info,
1256                           uint16_t length)
1257 {
1258     memset(&desc->wb, 0, sizeof(desc->wb));
1259 
1260     desc->wb.upper.length = cpu_to_le16(length);
1261 
1262     e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1263                              rss_info,
1264                              &desc->wb.lower.hi_dword.rss,
1265                              &desc->wb.lower.mrq,
1266                              &desc->wb.upper.status_error,
1267                              &desc->wb.lower.hi_dword.csum_ip.ip_id,
1268                              &desc->wb.upper.vlan);
1269 }
1270 
1271 static inline void
e1000e_write_ps_rx_descr(E1000ECore * core,union e1000_rx_desc_packet_split * desc,struct NetRxPkt * pkt,const E1000E_RSSInfo * rss_info,size_t ps_hdr_len,uint16_t (* written)[MAX_PS_BUFFERS])1272 e1000e_write_ps_rx_descr(E1000ECore *core,
1273                          union e1000_rx_desc_packet_split *desc,
1274                          struct NetRxPkt *pkt,
1275                          const E1000E_RSSInfo *rss_info,
1276                          size_t ps_hdr_len,
1277                          uint16_t(*written)[MAX_PS_BUFFERS])
1278 {
1279     int i;
1280 
1281     memset(&desc->wb, 0, sizeof(desc->wb));
1282 
1283     desc->wb.middle.length0 = cpu_to_le16((*written)[0]);
1284 
1285     for (i = 0; i < PS_PAGE_BUFFERS; i++) {
1286         desc->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]);
1287     }
1288 
1289     e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1290                              rss_info,
1291                              &desc->wb.lower.hi_dword.rss,
1292                              &desc->wb.lower.mrq,
1293                              &desc->wb.middle.status_error,
1294                              &desc->wb.lower.hi_dword.csum_ip.ip_id,
1295                              &desc->wb.middle.vlan);
1296 
1297     desc->wb.upper.header_status =
1298         cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0));
1299 
1300     trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1],
1301                                   (*written)[2], (*written)[3]);
1302 }
1303 
1304 static inline void
e1000e_write_rx_descr(E1000ECore * core,union e1000_rx_desc_union * desc,struct NetRxPkt * pkt,const E1000E_RSSInfo * rss_info,size_t ps_hdr_len,uint16_t (* written)[MAX_PS_BUFFERS])1305 e1000e_write_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc,
1306 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info,
1307     size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS])
1308 {
1309     if (e1000e_rx_use_legacy_descriptor(core)) {
1310         assert(ps_hdr_len == 0);
1311         e1000e_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info,
1312                                    (*written)[0]);
1313     } else {
1314         if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1315             e1000e_write_ps_rx_descr(core, &desc->packet_split, pkt, rss_info,
1316                                       ps_hdr_len, written);
1317         } else {
1318             assert(ps_hdr_len == 0);
1319             e1000e_write_ext_rx_descr(core, &desc->extended, pkt, rss_info,
1320                                        (*written)[0]);
1321         }
1322     }
1323 }
1324 
1325 static inline void
e1000e_pci_dma_write_rx_desc(E1000ECore * core,dma_addr_t addr,union e1000_rx_desc_union * desc,dma_addr_t len)1326 e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr,
1327                              union e1000_rx_desc_union *desc, dma_addr_t len)
1328 {
1329     PCIDevice *dev = core->owner;
1330 
1331     if (e1000e_rx_use_legacy_descriptor(core)) {
1332         struct e1000_rx_desc *d = &desc->legacy;
1333         size_t offset = offsetof(struct e1000_rx_desc, status);
1334         uint8_t status = d->status;
1335 
1336         d->status &= ~E1000_RXD_STAT_DD;
1337         pci_dma_write(dev, addr, desc, len);
1338 
1339         if (status & E1000_RXD_STAT_DD) {
1340             d->status = status;
1341             pci_dma_write(dev, addr + offset, &status, sizeof(status));
1342         }
1343     } else {
1344         if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1345             union e1000_rx_desc_packet_split *d = &desc->packet_split;
1346             size_t offset = offsetof(union e1000_rx_desc_packet_split,
1347                 wb.middle.status_error);
1348             uint32_t status = d->wb.middle.status_error;
1349 
1350             d->wb.middle.status_error &= ~E1000_RXD_STAT_DD;
1351             pci_dma_write(dev, addr, desc, len);
1352 
1353             if (status & E1000_RXD_STAT_DD) {
1354                 d->wb.middle.status_error = status;
1355                 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1356             }
1357         } else {
1358             union e1000_rx_desc_extended *d = &desc->extended;
1359             size_t offset = offsetof(union e1000_rx_desc_extended,
1360                 wb.upper.status_error);
1361             uint32_t status = d->wb.upper.status_error;
1362 
1363             d->wb.upper.status_error &= ~E1000_RXD_STAT_DD;
1364             pci_dma_write(dev, addr, desc, len);
1365 
1366             if (status & E1000_RXD_STAT_DD) {
1367                 d->wb.upper.status_error = status;
1368                 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1369             }
1370         }
1371     }
1372 }
1373 
1374 typedef struct E1000EBAState {
1375     uint16_t written[MAX_PS_BUFFERS];
1376     uint8_t cur_idx;
1377 } E1000EBAState;
1378 
1379 static inline void
e1000e_write_hdr_frag_to_rx_buffers(E1000ECore * core,hwaddr ba[MAX_PS_BUFFERS],E1000EBAState * bastate,const char * data,dma_addr_t data_len)1380 e1000e_write_hdr_frag_to_rx_buffers(E1000ECore *core,
1381                                     hwaddr ba[MAX_PS_BUFFERS],
1382                                     E1000EBAState *bastate,
1383                                     const char *data,
1384                                     dma_addr_t data_len)
1385 {
1386     assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]);
1387 
1388     pci_dma_write(core->owner, ba[0] + bastate->written[0], data, data_len);
1389     bastate->written[0] += data_len;
1390 
1391     bastate->cur_idx = 1;
1392 }
1393 
1394 static void
e1000e_write_payload_frag_to_rx_buffers(E1000ECore * core,hwaddr ba[MAX_PS_BUFFERS],E1000EBAState * bastate,const char * data,dma_addr_t data_len)1395 e1000e_write_payload_frag_to_rx_buffers(E1000ECore *core,
1396                                         hwaddr ba[MAX_PS_BUFFERS],
1397                                         E1000EBAState *bastate,
1398                                         const char *data,
1399                                         dma_addr_t data_len)
1400 {
1401     while (data_len > 0) {
1402         uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx];
1403         uint32_t cur_buf_bytes_left = cur_buf_len -
1404                                       bastate->written[bastate->cur_idx];
1405         uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left);
1406 
1407         trace_e1000e_rx_desc_buff_write(bastate->cur_idx,
1408                                         ba[bastate->cur_idx],
1409                                         bastate->written[bastate->cur_idx],
1410                                         data,
1411                                         bytes_to_write);
1412 
1413         pci_dma_write(core->owner,
1414             ba[bastate->cur_idx] + bastate->written[bastate->cur_idx],
1415             data, bytes_to_write);
1416 
1417         bastate->written[bastate->cur_idx] += bytes_to_write;
1418         data += bytes_to_write;
1419         data_len -= bytes_to_write;
1420 
1421         if (bastate->written[bastate->cur_idx] == cur_buf_len) {
1422             bastate->cur_idx++;
1423         }
1424 
1425         assert(bastate->cur_idx < MAX_PS_BUFFERS);
1426     }
1427 }
1428 
1429 static void
e1000e_update_rx_stats(E1000ECore * core,size_t pkt_size,size_t pkt_fcs_size)1430 e1000e_update_rx_stats(E1000ECore *core, size_t pkt_size, size_t pkt_fcs_size)
1431 {
1432     eth_pkt_types_e pkt_type = net_rx_pkt_get_packet_type(core->rx_pkt);
1433     e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size);
1434 }
1435 
1436 static inline bool
e1000e_rx_descr_threshold_hit(E1000ECore * core,const E1000ERingInfo * rxi)1437 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000ERingInfo *rxi)
1438 {
1439     return e1000e_ring_free_descr_num(core, rxi) ==
1440            e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift;
1441 }
1442 
1443 static bool
e1000e_do_ps(E1000ECore * core,struct NetRxPkt * pkt,size_t * hdr_len)1444 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len)
1445 {
1446     bool hasip4, hasip6;
1447     EthL4HdrProto l4hdr_proto;
1448     bool fragment;
1449 
1450     if (!e1000e_rx_use_ps_descriptor(core)) {
1451         return false;
1452     }
1453 
1454     net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
1455 
1456     if (hasip4) {
1457         fragment = net_rx_pkt_get_ip4_info(pkt)->fragment;
1458     } else if (hasip6) {
1459         fragment = net_rx_pkt_get_ip6_info(pkt)->fragment;
1460     } else {
1461         return false;
1462     }
1463 
1464     if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) {
1465         return false;
1466     }
1467 
1468     if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP ||
1469         l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1470         *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt);
1471     } else {
1472         *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt);
1473     }
1474 
1475     if ((*hdr_len > core->rxbuf_sizes[0]) ||
1476         (*hdr_len > net_rx_pkt_get_total_len(pkt))) {
1477         return false;
1478     }
1479 
1480     return true;
1481 }
1482 
1483 static void
e1000e_write_packet_to_guest(E1000ECore * core,struct NetRxPkt * pkt,const E1000E_RxRing * rxr,const E1000E_RSSInfo * rss_info)1484 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt,
1485                              const E1000E_RxRing *rxr,
1486                              const E1000E_RSSInfo *rss_info)
1487 {
1488     PCIDevice *d = core->owner;
1489     dma_addr_t base;
1490     union e1000_rx_desc_union desc;
1491     size_t desc_size;
1492     size_t desc_offset = 0;
1493     size_t iov_ofs = 0;
1494 
1495     struct iovec *iov = net_rx_pkt_get_iovec(pkt);
1496     size_t size = net_rx_pkt_get_total_len(pkt);
1497     size_t total_size = size + e1000x_fcs_len(core->mac);
1498     const E1000ERingInfo *rxi;
1499     size_t ps_hdr_len = 0;
1500     bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len);
1501     bool is_first = true;
1502 
1503     rxi = rxr->i;
1504 
1505     do {
1506         hwaddr ba[MAX_PS_BUFFERS];
1507         E1000EBAState bastate = { { 0 } };
1508         bool is_last = false;
1509 
1510         desc_size = total_size - desc_offset;
1511 
1512         if (desc_size > core->rx_desc_buf_size) {
1513             desc_size = core->rx_desc_buf_size;
1514         }
1515 
1516         if (e1000e_ring_empty(core, rxi)) {
1517             return;
1518         }
1519 
1520         base = e1000e_ring_head_descr(core, rxi);
1521 
1522         pci_dma_read(d, base, &desc, core->rx_desc_len);
1523 
1524         trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len);
1525 
1526         e1000e_read_rx_descr(core, &desc, ba);
1527 
1528         if (ba[0]) {
1529             if (desc_offset < size) {
1530                 static const uint32_t fcs_pad;
1531                 size_t iov_copy;
1532                 size_t copy_size = size - desc_offset;
1533                 if (copy_size > core->rx_desc_buf_size) {
1534                     copy_size = core->rx_desc_buf_size;
1535                 }
1536 
1537                 /* For PS mode copy the packet header first */
1538                 if (do_ps) {
1539                     if (is_first) {
1540                         size_t ps_hdr_copied = 0;
1541                         do {
1542                             iov_copy = MIN(ps_hdr_len - ps_hdr_copied,
1543                                            iov->iov_len - iov_ofs);
1544 
1545                             e1000e_write_hdr_frag_to_rx_buffers(core, ba,
1546                                                                 &bastate,
1547                                                                 iov->iov_base,
1548                                                                 iov_copy);
1549 
1550                             copy_size -= iov_copy;
1551                             ps_hdr_copied += iov_copy;
1552 
1553                             iov_ofs += iov_copy;
1554                             if (iov_ofs == iov->iov_len) {
1555                                 iov++;
1556                                 iov_ofs = 0;
1557                             }
1558                         } while (ps_hdr_copied < ps_hdr_len);
1559 
1560                         is_first = false;
1561                     } else {
1562                         /* Leave buffer 0 of each descriptor except first */
1563                         /* empty as per spec 7.1.5.1                      */
1564                         e1000e_write_hdr_frag_to_rx_buffers(core, ba, &bastate,
1565                                                             NULL, 0);
1566                     }
1567                 }
1568 
1569                 /* Copy packet payload */
1570                 while (copy_size) {
1571                     iov_copy = MIN(copy_size, iov->iov_len - iov_ofs);
1572 
1573                     e1000e_write_payload_frag_to_rx_buffers(core, ba, &bastate,
1574                                                             iov->iov_base +
1575                                                             iov_ofs,
1576                                                             iov_copy);
1577 
1578                     copy_size -= iov_copy;
1579                     iov_ofs += iov_copy;
1580                     if (iov_ofs == iov->iov_len) {
1581                         iov++;
1582                         iov_ofs = 0;
1583                     }
1584                 }
1585 
1586                 if (desc_offset + desc_size >= total_size) {
1587                     /* Simulate FCS checksum presence in the last descriptor */
1588                     e1000e_write_payload_frag_to_rx_buffers(core, ba, &bastate,
1589                           (const char *) &fcs_pad, e1000x_fcs_len(core->mac));
1590                 }
1591             }
1592         } else { /* as per intel docs; skip descriptors with null buf addr */
1593             trace_e1000e_rx_null_descriptor();
1594         }
1595         desc_offset += desc_size;
1596         if (desc_offset >= total_size) {
1597             is_last = true;
1598         }
1599 
1600         e1000e_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL,
1601                            rss_info, do_ps ? ps_hdr_len : 0, &bastate.written);
1602         e1000e_pci_dma_write_rx_desc(core, base, &desc, core->rx_desc_len);
1603 
1604         e1000e_ring_advance(core, rxi,
1605                             core->rx_desc_len / E1000_MIN_RX_DESC_LEN);
1606 
1607     } while (desc_offset < total_size);
1608 
1609     e1000e_update_rx_stats(core, size, total_size);
1610 }
1611 
1612 static inline void
e1000e_rx_fix_l4_csum(E1000ECore * core,struct NetRxPkt * pkt)1613 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt)
1614 {
1615     struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt);
1616 
1617     if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
1618         net_rx_pkt_fix_l4_csum(pkt);
1619     }
1620 }
1621 
1622 ssize_t
e1000e_receive_iov(E1000ECore * core,const struct iovec * iov,int iovcnt)1623 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt)
1624 {
1625     return e1000e_receive_internal(core, iov, iovcnt, core->has_vnet);
1626 }
1627 
1628 static ssize_t
e1000e_receive_internal(E1000ECore * core,const struct iovec * iov,int iovcnt,bool has_vnet)1629 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt,
1630                         bool has_vnet)
1631 {
1632     uint32_t causes = 0;
1633     uint8_t buf[ETH_ZLEN];
1634     struct iovec min_iov;
1635     size_t size, orig_size;
1636     size_t iov_ofs = 0;
1637     E1000E_RxRing rxr;
1638     E1000E_RSSInfo rss_info;
1639     size_t total_size;
1640     ssize_t retval;
1641     bool rdmts_hit;
1642 
1643     trace_e1000e_rx_receive_iov(iovcnt);
1644 
1645     if (!e1000x_hw_rx_enabled(core->mac)) {
1646         return -1;
1647     }
1648 
1649     /* Pull virtio header in */
1650     if (has_vnet) {
1651         net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt);
1652         iov_ofs = sizeof(struct virtio_net_hdr);
1653     } else {
1654         net_rx_pkt_unset_vhdr(core->rx_pkt);
1655     }
1656 
1657     orig_size = iov_size(iov, iovcnt);
1658     size = orig_size - iov_ofs;
1659 
1660     /* Pad to minimum Ethernet frame length */
1661     if (size < sizeof(buf)) {
1662         iov_to_buf(iov, iovcnt, iov_ofs, buf, size);
1663         memset(&buf[size], 0, sizeof(buf) - size);
1664         e1000x_inc_reg_if_not_full(core->mac, RUC);
1665         min_iov.iov_base = buf;
1666         min_iov.iov_len = size = sizeof(buf);
1667         iovcnt = 1;
1668         iov = &min_iov;
1669         iov_ofs = 0;
1670     } else {
1671         iov_to_buf(iov, iovcnt, iov_ofs, buf, ETH_HLEN + 4);
1672     }
1673 
1674     /* Discard oversized packets if !LPE and !SBP. */
1675     if (e1000x_is_oversized(core->mac, size)) {
1676         return orig_size;
1677     }
1678 
1679     net_rx_pkt_set_packet_type(core->rx_pkt,
1680         get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
1681 
1682     if (!e1000e_receive_filter(core, buf)) {
1683         trace_e1000e_rx_flt_dropped();
1684         return orig_size;
1685     }
1686 
1687     net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
1688                                e1000x_vlan_enabled(core->mac) ? 0 : -1,
1689                                core->mac[VET], 0);
1690 
1691     e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info);
1692     e1000e_rx_ring_init(core, &rxr, rss_info.queue);
1693 
1694     total_size = net_rx_pkt_get_total_len(core->rx_pkt) +
1695         e1000x_fcs_len(core->mac);
1696 
1697     if (e1000e_has_rxbufs(core, rxr.i, total_size)) {
1698         e1000e_rx_fix_l4_csum(core, core->rx_pkt);
1699 
1700         e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info);
1701 
1702         retval = orig_size;
1703 
1704         /* Perform small receive detection (RSRPD) */
1705         if (total_size < core->mac[RSRPD]) {
1706             causes |= E1000_ICS_SRPD;
1707         }
1708 
1709         /* Perform ACK receive detection */
1710         if  (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) &&
1711              (e1000e_is_tcp_ack(core, core->rx_pkt))) {
1712             causes |= E1000_ICS_ACK;
1713         }
1714 
1715         /* Check if receive descriptor minimum threshold hit */
1716         rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i);
1717         causes |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit);
1718 
1719         trace_e1000e_rx_written_to_guest(rxr.i->idx);
1720     } else {
1721         causes |= E1000_ICS_RXO;
1722         retval = 0;
1723 
1724         trace_e1000e_rx_not_written_to_guest(rxr.i->idx);
1725     }
1726 
1727     if (!e1000e_intrmgr_delay_rx_causes(core, &causes)) {
1728         trace_e1000e_rx_interrupt_set(causes);
1729         e1000e_set_interrupt_cause(core, causes);
1730     } else {
1731         trace_e1000e_rx_interrupt_delayed(causes);
1732     }
1733 
1734     return retval;
1735 }
1736 
1737 static inline bool
e1000e_have_autoneg(E1000ECore * core)1738 e1000e_have_autoneg(E1000ECore *core)
1739 {
1740     return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN;
1741 }
1742 
e1000e_update_flowctl_status(E1000ECore * core)1743 static void e1000e_update_flowctl_status(E1000ECore *core)
1744 {
1745     if (e1000e_have_autoneg(core) &&
1746         core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) {
1747         trace_e1000e_link_autoneg_flowctl(true);
1748         core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE;
1749     } else {
1750         trace_e1000e_link_autoneg_flowctl(false);
1751     }
1752 }
1753 
1754 static inline void
e1000e_link_down(E1000ECore * core)1755 e1000e_link_down(E1000ECore *core)
1756 {
1757     e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1758     e1000e_update_flowctl_status(core);
1759 }
1760 
1761 static inline void
e1000e_set_phy_ctrl(E1000ECore * core,int index,uint16_t val)1762 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val)
1763 {
1764     /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */
1765     core->phy[0][MII_BMCR] = val & ~(0x3f |
1766                                      MII_BMCR_RESET |
1767                                      MII_BMCR_ANRESTART);
1768 
1769     if ((val & MII_BMCR_ANRESTART) &&
1770         e1000e_have_autoneg(core)) {
1771         e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1772     }
1773 }
1774 
1775 static void
e1000e_set_phy_oem_bits(E1000ECore * core,int index,uint16_t val)1776 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val)
1777 {
1778     core->phy[0][PHY_OEM_BITS] = val & ~BIT(10);
1779 
1780     if (val & BIT(10)) {
1781         e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1782     }
1783 }
1784 
1785 static void
e1000e_set_phy_page(E1000ECore * core,int index,uint16_t val)1786 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val)
1787 {
1788     core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK;
1789 }
1790 
1791 void
e1000e_core_set_link_status(E1000ECore * core)1792 e1000e_core_set_link_status(E1000ECore *core)
1793 {
1794     NetClientState *nc = qemu_get_queue(core->owner_nic);
1795     uint32_t old_status = core->mac[STATUS];
1796 
1797     trace_e1000e_link_status_changed(nc->link_down ? false : true);
1798 
1799     if (nc->link_down) {
1800         e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1801     } else {
1802         if (e1000e_have_autoneg(core) &&
1803             !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) {
1804             e1000x_restart_autoneg(core->mac, core->phy[0],
1805                                    core->autoneg_timer);
1806         } else {
1807             e1000x_update_regs_on_link_up(core->mac, core->phy[0]);
1808             e1000e_start_recv(core);
1809         }
1810     }
1811 
1812     if (core->mac[STATUS] != old_status) {
1813         e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
1814     }
1815 }
1816 
1817 static void
e1000e_set_ctrl(E1000ECore * core,int index,uint32_t val)1818 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val)
1819 {
1820     trace_e1000e_core_ctrl_write(index, val);
1821 
1822     /* RST is self clearing */
1823     core->mac[CTRL] = val & ~E1000_CTRL_RST;
1824     core->mac[CTRL_DUP] = core->mac[CTRL];
1825 
1826     trace_e1000e_link_set_params(
1827         !!(val & E1000_CTRL_ASDE),
1828         (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
1829         !!(val & E1000_CTRL_FRCSPD),
1830         !!(val & E1000_CTRL_FRCDPX),
1831         !!(val & E1000_CTRL_RFCE),
1832         !!(val & E1000_CTRL_TFCE));
1833 
1834     if (val & E1000_CTRL_RST) {
1835         trace_e1000e_core_ctrl_sw_reset();
1836         e1000e_reset(core, true);
1837     }
1838 
1839     if (val & E1000_CTRL_PHY_RST) {
1840         trace_e1000e_core_ctrl_phy_reset();
1841         core->mac[STATUS] |= E1000_STATUS_PHYRA;
1842     }
1843 }
1844 
1845 static void
e1000e_set_rfctl(E1000ECore * core,int index,uint32_t val)1846 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val)
1847 {
1848     trace_e1000e_rx_set_rfctl(val);
1849 
1850     if (!(val & E1000_RFCTL_ISCSI_DIS)) {
1851         trace_e1000e_wrn_iscsi_filtering_not_supported();
1852     }
1853 
1854     if (!(val & E1000_RFCTL_NFSW_DIS)) {
1855         trace_e1000e_wrn_nfsw_filtering_not_supported();
1856     }
1857 
1858     if (!(val & E1000_RFCTL_NFSR_DIS)) {
1859         trace_e1000e_wrn_nfsr_filtering_not_supported();
1860     }
1861 
1862     core->mac[RFCTL] = val;
1863 }
1864 
1865 static void
e1000e_calc_per_desc_buf_size(E1000ECore * core)1866 e1000e_calc_per_desc_buf_size(E1000ECore *core)
1867 {
1868     int i;
1869     core->rx_desc_buf_size = 0;
1870 
1871     for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) {
1872         core->rx_desc_buf_size += core->rxbuf_sizes[i];
1873     }
1874 }
1875 
1876 static void
e1000e_parse_rxbufsize(E1000ECore * core)1877 e1000e_parse_rxbufsize(E1000ECore *core)
1878 {
1879     uint32_t rctl = core->mac[RCTL];
1880 
1881     memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes));
1882 
1883     if (rctl & E1000_RCTL_DTYP_MASK) {
1884         uint32_t bsize;
1885 
1886         bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK;
1887         core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128;
1888 
1889         bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK;
1890         core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024;
1891 
1892         bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK;
1893         core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024;
1894 
1895         bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK;
1896         core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024;
1897     } else if (rctl & E1000_RCTL_FLXBUF_MASK) {
1898         int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK;
1899         core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024;
1900     } else {
1901         core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl);
1902     }
1903 
1904     trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1],
1905                                     core->rxbuf_sizes[2], core->rxbuf_sizes[3]);
1906 
1907     e1000e_calc_per_desc_buf_size(core);
1908 }
1909 
1910 static void
e1000e_calc_rxdesclen(E1000ECore * core)1911 e1000e_calc_rxdesclen(E1000ECore *core)
1912 {
1913     if (e1000e_rx_use_legacy_descriptor(core)) {
1914         core->rx_desc_len = sizeof(struct e1000_rx_desc);
1915     } else {
1916         if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1917             core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split);
1918         } else {
1919             core->rx_desc_len = sizeof(union e1000_rx_desc_extended);
1920         }
1921     }
1922     trace_e1000e_rx_desc_len(core->rx_desc_len);
1923 }
1924 
1925 static void
e1000e_set_rx_control(E1000ECore * core,int index,uint32_t val)1926 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val)
1927 {
1928     core->mac[RCTL] = val;
1929     trace_e1000e_rx_set_rctl(core->mac[RCTL]);
1930 
1931     if (val & E1000_RCTL_EN) {
1932         e1000e_parse_rxbufsize(core);
1933         e1000e_calc_rxdesclen(core);
1934         core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 +
1935                                 E1000_RING_DESC_LEN_SHIFT;
1936 
1937         e1000e_start_recv(core);
1938     }
1939 }
1940 
1941 static
1942 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE])
1943 (E1000ECore *, int, uint16_t) = {
1944     [0] = {
1945         [MII_BMCR]     = e1000e_set_phy_ctrl,
1946         [PHY_PAGE]     = e1000e_set_phy_page,
1947         [PHY_OEM_BITS] = e1000e_set_phy_oem_bits
1948     }
1949 };
1950 
1951 static inline bool
e1000e_postpone_interrupt(E1000IntrDelayTimer * timer)1952 e1000e_postpone_interrupt(E1000IntrDelayTimer *timer)
1953 {
1954     if (timer->running) {
1955         trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2);
1956 
1957         return true;
1958     }
1959 
1960     if (timer->core->mac[timer->delay_reg] != 0) {
1961         e1000e_intrmgr_rearm_timer(timer);
1962     }
1963 
1964     return false;
1965 }
1966 
1967 static inline bool
e1000e_itr_should_postpone(E1000ECore * core)1968 e1000e_itr_should_postpone(E1000ECore *core)
1969 {
1970     return e1000e_postpone_interrupt(&core->itr);
1971 }
1972 
1973 static inline bool
e1000e_eitr_should_postpone(E1000ECore * core,int idx)1974 e1000e_eitr_should_postpone(E1000ECore *core, int idx)
1975 {
1976     return e1000e_postpone_interrupt(&core->eitr[idx]);
1977 }
1978 
1979 static void
e1000e_msix_notify_one(E1000ECore * core,uint32_t cause,uint32_t int_cfg)1980 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
1981 {
1982     uint32_t effective_eiac;
1983 
1984     if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
1985         uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
1986         if (vec < E1000E_MSIX_VEC_NUM) {
1987             if (!e1000e_eitr_should_postpone(core, vec)) {
1988                 trace_e1000e_irq_msix_notify_vec(vec);
1989                 msix_notify(core->owner, vec);
1990             }
1991         } else {
1992             trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
1993         }
1994     } else {
1995         trace_e1000e_wrn_msix_invalid(cause, int_cfg);
1996     }
1997 
1998     if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) {
1999         trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause);
2000         core->mac[IAM] &= ~cause;
2001     }
2002 
2003     trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]);
2004 
2005     effective_eiac = core->mac[EIAC] & cause;
2006 
2007     core->mac[ICR] &= ~effective_eiac;
2008 
2009     if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2010         core->mac[IMS] &= ~effective_eiac;
2011     }
2012 }
2013 
2014 static void
e1000e_msix_notify(E1000ECore * core,uint32_t causes)2015 e1000e_msix_notify(E1000ECore *core, uint32_t causes)
2016 {
2017     if (causes & E1000_ICR_RXQ0) {
2018         e1000e_msix_notify_one(core, E1000_ICR_RXQ0,
2019                                E1000_IVAR_RXQ0(core->mac[IVAR]));
2020     }
2021 
2022     if (causes & E1000_ICR_RXQ1) {
2023         e1000e_msix_notify_one(core, E1000_ICR_RXQ1,
2024                                E1000_IVAR_RXQ1(core->mac[IVAR]));
2025     }
2026 
2027     if (causes & E1000_ICR_TXQ0) {
2028         e1000e_msix_notify_one(core, E1000_ICR_TXQ0,
2029                                E1000_IVAR_TXQ0(core->mac[IVAR]));
2030     }
2031 
2032     if (causes & E1000_ICR_TXQ1) {
2033         e1000e_msix_notify_one(core, E1000_ICR_TXQ1,
2034                                E1000_IVAR_TXQ1(core->mac[IVAR]));
2035     }
2036 
2037     if (causes & E1000_ICR_OTHER) {
2038         e1000e_msix_notify_one(core, E1000_ICR_OTHER,
2039                                E1000_IVAR_OTHER(core->mac[IVAR]));
2040     }
2041 }
2042 
2043 static void
e1000e_msix_clear_one(E1000ECore * core,uint32_t cause,uint32_t int_cfg)2044 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
2045 {
2046     if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
2047         uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
2048         if (vec < E1000E_MSIX_VEC_NUM) {
2049             trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec);
2050             msix_clr_pending(core->owner, vec);
2051         } else {
2052             trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2053         }
2054     } else {
2055         trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2056     }
2057 }
2058 
2059 static void
e1000e_msix_clear(E1000ECore * core,uint32_t causes)2060 e1000e_msix_clear(E1000ECore *core, uint32_t causes)
2061 {
2062     if (causes & E1000_ICR_RXQ0) {
2063         e1000e_msix_clear_one(core, E1000_ICR_RXQ0,
2064                               E1000_IVAR_RXQ0(core->mac[IVAR]));
2065     }
2066 
2067     if (causes & E1000_ICR_RXQ1) {
2068         e1000e_msix_clear_one(core, E1000_ICR_RXQ1,
2069                               E1000_IVAR_RXQ1(core->mac[IVAR]));
2070     }
2071 
2072     if (causes & E1000_ICR_TXQ0) {
2073         e1000e_msix_clear_one(core, E1000_ICR_TXQ0,
2074                               E1000_IVAR_TXQ0(core->mac[IVAR]));
2075     }
2076 
2077     if (causes & E1000_ICR_TXQ1) {
2078         e1000e_msix_clear_one(core, E1000_ICR_TXQ1,
2079                               E1000_IVAR_TXQ1(core->mac[IVAR]));
2080     }
2081 
2082     if (causes & E1000_ICR_OTHER) {
2083         e1000e_msix_clear_one(core, E1000_ICR_OTHER,
2084                               E1000_IVAR_OTHER(core->mac[IVAR]));
2085     }
2086 }
2087 
2088 static inline void
e1000e_fix_icr_asserted(E1000ECore * core)2089 e1000e_fix_icr_asserted(E1000ECore *core)
2090 {
2091     core->mac[ICR] &= ~E1000_ICR_ASSERTED;
2092     if (core->mac[ICR]) {
2093         core->mac[ICR] |= E1000_ICR_ASSERTED;
2094     }
2095 
2096     trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]);
2097 }
2098 
e1000e_raise_interrupts(E1000ECore * core,size_t index,uint32_t causes)2099 static void e1000e_raise_interrupts(E1000ECore *core,
2100                                     size_t index, uint32_t causes)
2101 {
2102     bool is_msix = msix_enabled(core->owner);
2103     uint32_t old_causes = core->mac[IMS] & core->mac[ICR];
2104     uint32_t raised_causes;
2105 
2106     trace_e1000e_irq_set(index << 2,
2107                          core->mac[index], core->mac[index] | causes);
2108 
2109     core->mac[index] |= causes;
2110 
2111     /* Set ICR[OTHER] for MSI-X */
2112     if (is_msix) {
2113         if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) {
2114             core->mac[ICR] |= E1000_ICR_OTHER;
2115             trace_e1000e_irq_add_msi_other(core->mac[ICR]);
2116         }
2117     }
2118 
2119     e1000e_fix_icr_asserted(core);
2120 
2121     /*
2122      * Make sure ICR and ICS registers have the same value.
2123      * The spec says that the ICS register is write-only.  However in practice,
2124      * on real hardware ICS is readable, and for reads it has the same value as
2125      * ICR (except that ICS does not have the clear on read behaviour of ICR).
2126      *
2127      * The VxWorks PRO/1000 driver uses this behaviour.
2128      */
2129     core->mac[ICS] = core->mac[ICR];
2130 
2131     trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
2132                                         core->mac[ICR], core->mac[IMS]);
2133 
2134     raised_causes = core->mac[IMS] & core->mac[ICR] & ~old_causes;
2135     if (!raised_causes) {
2136         return;
2137     }
2138 
2139     if (is_msix) {
2140         e1000e_msix_notify(core, raised_causes & ~E1000_ICR_ASSERTED);
2141     } else if (!e1000e_itr_should_postpone(core)) {
2142         if (msi_enabled(core->owner)) {
2143             trace_e1000e_irq_msi_notify(raised_causes);
2144             msi_notify(core->owner, 0);
2145         } else {
2146             e1000e_raise_legacy_irq(core);
2147         }
2148     }
2149 }
2150 
e1000e_lower_interrupts(E1000ECore * core,size_t index,uint32_t causes)2151 static void e1000e_lower_interrupts(E1000ECore *core,
2152                                     size_t index, uint32_t causes)
2153 {
2154     trace_e1000e_irq_clear(index << 2,
2155                            core->mac[index], core->mac[index] & ~causes);
2156 
2157     core->mac[index] &= ~causes;
2158 
2159     /*
2160      * Make sure ICR and ICS registers have the same value.
2161      * The spec says that the ICS register is write-only.  However in practice,
2162      * on real hardware ICS is readable, and for reads it has the same value as
2163      * ICR (except that ICS does not have the clear on read behaviour of ICR).
2164      *
2165      * The VxWorks PRO/1000 driver uses this behaviour.
2166      */
2167     core->mac[ICS] = core->mac[ICR];
2168 
2169     trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
2170                                         core->mac[ICR], core->mac[IMS]);
2171 
2172     if (!(core->mac[IMS] & core->mac[ICR]) &&
2173         !msix_enabled(core->owner) && !msi_enabled(core->owner)) {
2174         e1000e_lower_legacy_irq(core);
2175     }
2176 }
2177 
2178 static void
e1000e_set_interrupt_cause(E1000ECore * core,uint32_t val)2179 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val)
2180 {
2181     val |= e1000e_intmgr_collect_delayed_causes(core);
2182     e1000e_raise_interrupts(core, ICR, val);
2183 }
2184 
2185 static inline void
e1000e_autoneg_timer(void * opaque)2186 e1000e_autoneg_timer(void *opaque)
2187 {
2188     E1000ECore *core = opaque;
2189     if (!qemu_get_queue(core->owner_nic)->link_down) {
2190         e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]);
2191         e1000e_start_recv(core);
2192 
2193         e1000e_update_flowctl_status(core);
2194         /* signal link status change to the guest */
2195         e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
2196     }
2197 }
2198 
2199 static inline uint16_t
e1000e_get_reg_index_with_offset(const uint16_t * mac_reg_access,hwaddr addr)2200 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr)
2201 {
2202     uint16_t index = (addr & 0x1ffff) >> 2;
2203     return index + (mac_reg_access[index] & 0xfffe);
2204 }
2205 
2206 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = {
2207     [0] = {
2208         [MII_BMCR]              = PHY_ANYPAGE | PHY_RW,
2209         [MII_BMSR]              = PHY_ANYPAGE | PHY_R,
2210         [MII_PHYID1]            = PHY_ANYPAGE | PHY_R,
2211         [MII_PHYID2]            = PHY_ANYPAGE | PHY_R,
2212         [MII_ANAR]              = PHY_ANYPAGE | PHY_RW,
2213         [MII_ANLPAR]            = PHY_ANYPAGE | PHY_R,
2214         [MII_ANER]              = PHY_ANYPAGE | PHY_R,
2215         [MII_ANNP]              = PHY_ANYPAGE | PHY_RW,
2216         [MII_ANLPRNP]           = PHY_ANYPAGE | PHY_R,
2217         [MII_CTRL1000]          = PHY_ANYPAGE | PHY_RW,
2218         [MII_STAT1000]          = PHY_ANYPAGE | PHY_R,
2219         [MII_EXTSTAT]           = PHY_ANYPAGE | PHY_R,
2220         [PHY_PAGE]              = PHY_ANYPAGE | PHY_RW,
2221 
2222         [PHY_COPPER_CTRL1]      = PHY_RW,
2223         [PHY_COPPER_STAT1]      = PHY_R,
2224         [PHY_COPPER_CTRL3]      = PHY_RW,
2225         [PHY_RX_ERR_CNTR]       = PHY_R,
2226         [PHY_OEM_BITS]          = PHY_RW,
2227         [PHY_BIAS_1]            = PHY_RW,
2228         [PHY_BIAS_2]            = PHY_RW,
2229         [PHY_COPPER_INT_ENABLE] = PHY_RW,
2230         [PHY_COPPER_STAT2]      = PHY_R,
2231         [PHY_COPPER_CTRL2]      = PHY_RW
2232     },
2233     [2] = {
2234         [PHY_MAC_CTRL1]         = PHY_RW,
2235         [PHY_MAC_INT_ENABLE]    = PHY_RW,
2236         [PHY_MAC_STAT]          = PHY_R,
2237         [PHY_MAC_CTRL2]         = PHY_RW
2238     },
2239     [3] = {
2240         [PHY_LED_03_FUNC_CTRL1] = PHY_RW,
2241         [PHY_LED_03_POL_CTRL]   = PHY_RW,
2242         [PHY_LED_TIMER_CTRL]    = PHY_RW,
2243         [PHY_LED_45_CTRL]       = PHY_RW
2244     },
2245     [5] = {
2246         [PHY_1000T_SKEW]        = PHY_R,
2247         [PHY_1000T_SWAP]        = PHY_R
2248     },
2249     [6] = {
2250         [PHY_CRC_COUNTERS]      = PHY_R
2251     }
2252 };
2253 
2254 static bool
e1000e_phy_reg_check_cap(E1000ECore * core,uint32_t addr,char cap,uint8_t * page)2255 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr,
2256                          char cap, uint8_t *page)
2257 {
2258     *page =
2259         (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0
2260                                                     : core->phy[0][PHY_PAGE];
2261 
2262     if (*page >= E1000E_PHY_PAGES) {
2263         return false;
2264     }
2265 
2266     return e1000e_phy_regcap[*page][addr] & cap;
2267 }
2268 
2269 static void
e1000e_phy_reg_write(E1000ECore * core,uint8_t page,uint32_t addr,uint16_t data)2270 e1000e_phy_reg_write(E1000ECore *core, uint8_t page,
2271                      uint32_t addr, uint16_t data)
2272 {
2273     assert(page < E1000E_PHY_PAGES);
2274     assert(addr < E1000E_PHY_PAGE_SIZE);
2275 
2276     if (e1000e_phyreg_writeops[page][addr]) {
2277         e1000e_phyreg_writeops[page][addr](core, addr, data);
2278     } else {
2279         core->phy[page][addr] = data;
2280     }
2281 }
2282 
2283 static void
e1000e_set_mdic(E1000ECore * core,int index,uint32_t val)2284 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val)
2285 {
2286     uint32_t data = val & E1000_MDIC_DATA_MASK;
2287     uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
2288     uint8_t page;
2289 
2290     if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */
2291         val = core->mac[MDIC] | E1000_MDIC_ERROR;
2292     } else if (val & E1000_MDIC_OP_READ) {
2293         if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) {
2294             trace_e1000e_core_mdic_read_unhandled(page, addr);
2295             val |= E1000_MDIC_ERROR;
2296         } else {
2297             val = (val ^ data) | core->phy[page][addr];
2298             trace_e1000e_core_mdic_read(page, addr, val);
2299         }
2300     } else if (val & E1000_MDIC_OP_WRITE) {
2301         if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) {
2302             trace_e1000e_core_mdic_write_unhandled(page, addr);
2303             val |= E1000_MDIC_ERROR;
2304         } else {
2305             trace_e1000e_core_mdic_write(page, addr, data);
2306             e1000e_phy_reg_write(core, page, addr, data);
2307         }
2308     }
2309     core->mac[MDIC] = val | E1000_MDIC_READY;
2310 
2311     if (val & E1000_MDIC_INT_EN) {
2312         e1000e_set_interrupt_cause(core, E1000_ICR_MDAC);
2313     }
2314 }
2315 
2316 static void
e1000e_set_rdt(E1000ECore * core,int index,uint32_t val)2317 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val)
2318 {
2319     core->mac[index] = val & 0xffff;
2320     trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val);
2321     e1000e_start_recv(core);
2322 }
2323 
2324 static void
e1000e_set_status(E1000ECore * core,int index,uint32_t val)2325 e1000e_set_status(E1000ECore *core, int index, uint32_t val)
2326 {
2327     if ((val & E1000_STATUS_PHYRA) == 0) {
2328         core->mac[index] &= ~E1000_STATUS_PHYRA;
2329     }
2330 }
2331 
2332 static void
e1000e_set_ctrlext(E1000ECore * core,int index,uint32_t val)2333 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val)
2334 {
2335     trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
2336                                      !!(val & E1000_CTRL_EXT_SPD_BYPS));
2337 
2338     /* Zero self-clearing bits */
2339     val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST);
2340     core->mac[CTRL_EXT] = val;
2341 }
2342 
2343 static void
e1000e_set_pbaclr(E1000ECore * core,int index,uint32_t val)2344 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val)
2345 {
2346     int i;
2347 
2348     core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK;
2349 
2350     if (!msix_enabled(core->owner)) {
2351         return;
2352     }
2353 
2354     for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
2355         if (core->mac[PBACLR] & BIT(i)) {
2356             msix_clr_pending(core->owner, i);
2357         }
2358     }
2359 }
2360 
2361 static void
e1000e_set_fcrth(E1000ECore * core,int index,uint32_t val)2362 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val)
2363 {
2364     core->mac[FCRTH] = val & 0xFFF8;
2365 }
2366 
2367 static void
e1000e_set_fcrtl(E1000ECore * core,int index,uint32_t val)2368 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val)
2369 {
2370     core->mac[FCRTL] = val & 0x8000FFF8;
2371 }
2372 
2373 #define E1000E_LOW_BITS_SET_FUNC(num)                                \
2374     static void                                                      \
2375     e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \
2376     {                                                                \
2377         core->mac[index] = val & (BIT(num) - 1);                     \
2378     }
2379 
2380 E1000E_LOW_BITS_SET_FUNC(4)
2381 E1000E_LOW_BITS_SET_FUNC(6)
2382 E1000E_LOW_BITS_SET_FUNC(11)
2383 E1000E_LOW_BITS_SET_FUNC(12)
2384 E1000E_LOW_BITS_SET_FUNC(13)
2385 E1000E_LOW_BITS_SET_FUNC(16)
2386 
2387 static void
e1000e_set_vet(E1000ECore * core,int index,uint32_t val)2388 e1000e_set_vet(E1000ECore *core, int index, uint32_t val)
2389 {
2390     core->mac[VET] = val & 0xffff;
2391     trace_e1000e_vlan_vet(core->mac[VET]);
2392 }
2393 
2394 static void
e1000e_set_dlen(E1000ECore * core,int index,uint32_t val)2395 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val)
2396 {
2397     core->mac[index] = val & E1000_XDLEN_MASK;
2398 }
2399 
2400 static void
e1000e_set_dbal(E1000ECore * core,int index,uint32_t val)2401 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val)
2402 {
2403     core->mac[index] = val & E1000_XDBAL_MASK;
2404 }
2405 
2406 static void
e1000e_set_tctl(E1000ECore * core,int index,uint32_t val)2407 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val)
2408 {
2409     E1000E_TxRing txr;
2410     core->mac[index] = val;
2411 
2412     if (core->mac[TARC0] & E1000_TARC_ENABLE) {
2413         e1000e_tx_ring_init(core, &txr, 0);
2414         e1000e_start_xmit(core, &txr);
2415     }
2416 
2417     if (core->mac[TARC1] & E1000_TARC_ENABLE) {
2418         e1000e_tx_ring_init(core, &txr, 1);
2419         e1000e_start_xmit(core, &txr);
2420     }
2421 }
2422 
2423 static void
e1000e_set_tdt(E1000ECore * core,int index,uint32_t val)2424 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val)
2425 {
2426     E1000E_TxRing txr;
2427     int qidx = e1000e_mq_queue_idx(TDT, index);
2428     uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1;
2429 
2430     core->mac[index] = val & 0xffff;
2431 
2432     if (core->mac[tarc_reg] & E1000_TARC_ENABLE) {
2433         e1000e_tx_ring_init(core, &txr, qidx);
2434         e1000e_start_xmit(core, &txr);
2435     }
2436 }
2437 
2438 static void
e1000e_set_ics(E1000ECore * core,int index,uint32_t val)2439 e1000e_set_ics(E1000ECore *core, int index, uint32_t val)
2440 {
2441     trace_e1000e_irq_write_ics(val);
2442     e1000e_set_interrupt_cause(core, val);
2443 }
2444 
2445 static void
e1000e_set_icr(E1000ECore * core,int index,uint32_t val)2446 e1000e_set_icr(E1000ECore *core, int index, uint32_t val)
2447 {
2448     if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
2449         (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2450         trace_e1000e_irq_icr_process_iame();
2451         e1000e_lower_interrupts(core, IMS, core->mac[IAM]);
2452     }
2453 
2454     /*
2455      * Windows driver expects that the "receive overrun" bit and other
2456      * ones to be cleared when the "Other" bit (#24) is cleared.
2457      */
2458     if (val & E1000_ICR_OTHER) {
2459         val |= E1000_ICR_OTHER_CAUSES;
2460     }
2461     e1000e_lower_interrupts(core, ICR, val);
2462 }
2463 
2464 static void
e1000e_set_imc(E1000ECore * core,int index,uint32_t val)2465 e1000e_set_imc(E1000ECore *core, int index, uint32_t val)
2466 {
2467     trace_e1000e_irq_ims_clear_set_imc(val);
2468     e1000e_lower_interrupts(core, IMS, val);
2469 }
2470 
2471 static void
e1000e_set_ims(E1000ECore * core,int index,uint32_t val)2472 e1000e_set_ims(E1000ECore *core, int index, uint32_t val)
2473 {
2474     static const uint32_t ims_ext_mask =
2475         E1000_IMS_RXQ0 | E1000_IMS_RXQ1 |
2476         E1000_IMS_TXQ0 | E1000_IMS_TXQ1 |
2477         E1000_IMS_OTHER;
2478 
2479     static const uint32_t ims_valid_mask =
2480         E1000_IMS_TXDW      | E1000_IMS_TXQE    | E1000_IMS_LSC  |
2481         E1000_IMS_RXDMT0    | E1000_IMS_RXO     | E1000_IMS_RXT0 |
2482         E1000_IMS_MDAC      | E1000_IMS_TXD_LOW | E1000_IMS_SRPD |
2483         E1000_IMS_ACK       | E1000_IMS_MNG     | E1000_IMS_RXQ0 |
2484         E1000_IMS_RXQ1      | E1000_IMS_TXQ0    | E1000_IMS_TXQ1 |
2485         E1000_IMS_OTHER;
2486 
2487     uint32_t valid_val = val & ims_valid_mask;
2488 
2489     if ((valid_val & ims_ext_mask) &&
2490         (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) &&
2491         msix_enabled(core->owner)) {
2492         e1000e_msix_clear(core, valid_val);
2493     }
2494 
2495     if ((valid_val == ims_valid_mask) &&
2496         (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) {
2497         trace_e1000e_irq_fire_all_timers(val);
2498         e1000e_intrmgr_fire_all_timers(core);
2499     }
2500 
2501     e1000e_raise_interrupts(core, IMS, valid_val);
2502 }
2503 
2504 static void
e1000e_set_rdtr(E1000ECore * core,int index,uint32_t val)2505 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val)
2506 {
2507     e1000e_set_16bit(core, index, val);
2508 
2509     if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) {
2510         trace_e1000e_irq_rdtr_fpd_running();
2511         e1000e_intrmgr_fire_delayed_interrupts(core);
2512     } else {
2513         trace_e1000e_irq_rdtr_fpd_not_running();
2514     }
2515 }
2516 
2517 static void
e1000e_set_tidv(E1000ECore * core,int index,uint32_t val)2518 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val)
2519 {
2520     e1000e_set_16bit(core, index, val);
2521 
2522     if ((val & E1000_TIDV_FPD) && (core->tidv.running)) {
2523         trace_e1000e_irq_tidv_fpd_running();
2524         e1000e_intrmgr_fire_delayed_interrupts(core);
2525     } else {
2526         trace_e1000e_irq_tidv_fpd_not_running();
2527     }
2528 }
2529 
2530 static uint32_t
e1000e_mac_readreg(E1000ECore * core,int index)2531 e1000e_mac_readreg(E1000ECore *core, int index)
2532 {
2533     return core->mac[index];
2534 }
2535 
2536 static uint32_t
e1000e_mac_ics_read(E1000ECore * core,int index)2537 e1000e_mac_ics_read(E1000ECore *core, int index)
2538 {
2539     trace_e1000e_irq_read_ics(core->mac[ICS]);
2540     return core->mac[ICS];
2541 }
2542 
2543 static uint32_t
e1000e_mac_ims_read(E1000ECore * core,int index)2544 e1000e_mac_ims_read(E1000ECore *core, int index)
2545 {
2546     trace_e1000e_irq_read_ims(core->mac[IMS]);
2547     return core->mac[IMS];
2548 }
2549 
2550 static uint32_t
e1000e_mac_swsm_read(E1000ECore * core,int index)2551 e1000e_mac_swsm_read(E1000ECore *core, int index)
2552 {
2553     uint32_t val = core->mac[SWSM];
2554     core->mac[SWSM] = val | E1000_SWSM_SMBI;
2555     return val;
2556 }
2557 
2558 static uint32_t
e1000e_mac_itr_read(E1000ECore * core,int index)2559 e1000e_mac_itr_read(E1000ECore *core, int index)
2560 {
2561     return core->itr_guest_value;
2562 }
2563 
2564 static uint32_t
e1000e_mac_eitr_read(E1000ECore * core,int index)2565 e1000e_mac_eitr_read(E1000ECore *core, int index)
2566 {
2567     return core->eitr_guest_value[index - EITR];
2568 }
2569 
2570 static uint32_t
e1000e_mac_icr_read(E1000ECore * core,int index)2571 e1000e_mac_icr_read(E1000ECore *core, int index)
2572 {
2573     uint32_t ret = core->mac[ICR];
2574 
2575     if (core->mac[IMS] == 0) {
2576         trace_e1000e_irq_icr_clear_zero_ims();
2577         e1000e_lower_interrupts(core, ICR, 0xffffffff);
2578     }
2579 
2580     if (!msix_enabled(core->owner)) {
2581         trace_e1000e_irq_icr_clear_nonmsix_icr_read();
2582         e1000e_lower_interrupts(core, ICR, 0xffffffff);
2583     }
2584 
2585     if (core->mac[ICR] & E1000_ICR_ASSERTED) {
2586         if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME) {
2587             trace_e1000e_irq_icr_clear_iame();
2588             e1000e_lower_interrupts(core, ICR, 0xffffffff);
2589             trace_e1000e_irq_icr_process_iame();
2590             e1000e_lower_interrupts(core, IMS, core->mac[IAM]);
2591         }
2592 
2593         /*
2594          * The datasheet does not say what happens when interrupt was asserted
2595          * (ICR.INT_ASSERT=1) and auto mask is *not* active.
2596          * However, section of 13.3.27 the PCIe* GbE Controllers Open Source
2597          * Software Developer’s Manual, which were written for older devices,
2598          * namely 631xESB/632xESB, 82563EB/82564EB, 82571EB/82572EI &
2599          * 82573E/82573V/82573L, does say:
2600          * > If IMS = 0b, then the ICR register is always clear-on-read. If IMS
2601          * > is not 0b, but some ICR bit is set where the corresponding IMS bit
2602          * > is not set, then a read does not clear the ICR register. For
2603          * > example, if IMS = 10101010b and ICR = 01010101b, then a read to the
2604          * > ICR register does not clear it. If IMS = 10101010b and
2605          * > ICR = 0101011b, then a read to the ICR register clears it entirely
2606          * > (ICR.INT_ASSERTED = 1b).
2607          *
2608          * Linux does no longer activate auto mask since commit
2609          * 0a8047ac68e50e4ccbadcfc6b6b070805b976885 and the real hardware
2610          * clears ICR even in such a case so we also should do so.
2611          */
2612         if (core->mac[ICR] & core->mac[IMS]) {
2613             trace_e1000e_irq_icr_clear_icr_bit_ims(core->mac[ICR],
2614                                                    core->mac[IMS]);
2615             e1000e_lower_interrupts(core, ICR, 0xffffffff);
2616         }
2617     }
2618 
2619     return ret;
2620 }
2621 
2622 static uint32_t
e1000e_mac_read_clr4(E1000ECore * core,int index)2623 e1000e_mac_read_clr4(E1000ECore *core, int index)
2624 {
2625     uint32_t ret = core->mac[index];
2626 
2627     core->mac[index] = 0;
2628     return ret;
2629 }
2630 
2631 static uint32_t
e1000e_mac_read_clr8(E1000ECore * core,int index)2632 e1000e_mac_read_clr8(E1000ECore *core, int index)
2633 {
2634     uint32_t ret = core->mac[index];
2635 
2636     core->mac[index] = 0;
2637     core->mac[index - 1] = 0;
2638     return ret;
2639 }
2640 
2641 static uint32_t
e1000e_get_ctrl(E1000ECore * core,int index)2642 e1000e_get_ctrl(E1000ECore *core, int index)
2643 {
2644     uint32_t val = core->mac[CTRL];
2645 
2646     trace_e1000e_link_read_params(
2647         !!(val & E1000_CTRL_ASDE),
2648         (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
2649         !!(val & E1000_CTRL_FRCSPD),
2650         !!(val & E1000_CTRL_FRCDPX),
2651         !!(val & E1000_CTRL_RFCE),
2652         !!(val & E1000_CTRL_TFCE));
2653 
2654     return val;
2655 }
2656 
2657 static uint32_t
e1000e_get_status(E1000ECore * core,int index)2658 e1000e_get_status(E1000ECore *core, int index)
2659 {
2660     uint32_t res = core->mac[STATUS];
2661 
2662     if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) {
2663         res |= E1000_STATUS_GIO_MASTER_ENABLE;
2664     }
2665 
2666     if (core->mac[CTRL] & E1000_CTRL_FRCDPX) {
2667         res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0;
2668     } else {
2669         res |= E1000_STATUS_FD;
2670     }
2671 
2672     if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) ||
2673         (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) {
2674         switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) {
2675         case E1000_CTRL_SPD_10:
2676             res |= E1000_STATUS_SPEED_10;
2677             break;
2678         case E1000_CTRL_SPD_100:
2679             res |= E1000_STATUS_SPEED_100;
2680             break;
2681         case E1000_CTRL_SPD_1000:
2682         default:
2683             res |= E1000_STATUS_SPEED_1000;
2684             break;
2685         }
2686     } else {
2687         res |= E1000_STATUS_SPEED_1000;
2688     }
2689 
2690     trace_e1000e_link_status(
2691         !!(res & E1000_STATUS_LU),
2692         !!(res & E1000_STATUS_FD),
2693         (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT,
2694         (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT);
2695 
2696     return res;
2697 }
2698 
2699 static uint32_t
e1000e_get_tarc(E1000ECore * core,int index)2700 e1000e_get_tarc(E1000ECore *core, int index)
2701 {
2702     return core->mac[index] & ((BIT(11) - 1) |
2703                                 BIT(27)      |
2704                                 BIT(28)      |
2705                                 BIT(29)      |
2706                                 BIT(30));
2707 }
2708 
2709 static void
e1000e_mac_writereg(E1000ECore * core,int index,uint32_t val)2710 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val)
2711 {
2712     core->mac[index] = val;
2713 }
2714 
2715 static void
e1000e_mac_setmacaddr(E1000ECore * core,int index,uint32_t val)2716 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val)
2717 {
2718     uint32_t macaddr[2];
2719 
2720     core->mac[index] = val;
2721 
2722     macaddr[0] = cpu_to_le32(core->mac[RA]);
2723     macaddr[1] = cpu_to_le32(core->mac[RA + 1]);
2724     qemu_format_nic_info_str(qemu_get_queue(core->owner_nic),
2725         (uint8_t *) macaddr);
2726 
2727     trace_e1000e_mac_set_sw(MAC_ARG(macaddr));
2728 }
2729 
2730 static void
e1000e_set_eecd(E1000ECore * core,int index,uint32_t val)2731 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val)
2732 {
2733     static const uint32_t ro_bits = E1000_EECD_PRES          |
2734                                     E1000_EECD_AUTO_RD       |
2735                                     E1000_EECD_SIZE_EX_MASK;
2736 
2737     core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits);
2738 }
2739 
2740 static void
e1000e_set_eerd(E1000ECore * core,int index,uint32_t val)2741 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val)
2742 {
2743     uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2744     uint32_t flags = 0;
2745     uint32_t data = 0;
2746 
2747     if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2748         data = core->eeprom[addr];
2749         flags = E1000_EERW_DONE;
2750     }
2751 
2752     core->mac[EERD] = flags                           |
2753                       (addr << E1000_EERW_ADDR_SHIFT) |
2754                       (data << E1000_EERW_DATA_SHIFT);
2755 }
2756 
2757 static void
e1000e_set_eewr(E1000ECore * core,int index,uint32_t val)2758 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val)
2759 {
2760     uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2761     uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK;
2762     uint32_t flags = 0;
2763 
2764     if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2765         core->eeprom[addr] = data;
2766         flags = E1000_EERW_DONE;
2767     }
2768 
2769     core->mac[EERD] = flags                           |
2770                       (addr << E1000_EERW_ADDR_SHIFT) |
2771                       (data << E1000_EERW_DATA_SHIFT);
2772 }
2773 
2774 static void
e1000e_set_rxdctl(E1000ECore * core,int index,uint32_t val)2775 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val)
2776 {
2777     core->mac[RXDCTL] = core->mac[RXDCTL1] = val;
2778 }
2779 
2780 static void
e1000e_set_itr(E1000ECore * core,int index,uint32_t val)2781 e1000e_set_itr(E1000ECore *core, int index, uint32_t val)
2782 {
2783     uint32_t interval = val & 0xffff;
2784 
2785     trace_e1000e_irq_itr_set(val);
2786 
2787     core->itr_guest_value = interval;
2788     core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2789 }
2790 
2791 static void
e1000e_set_eitr(E1000ECore * core,int index,uint32_t val)2792 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val)
2793 {
2794     uint32_t interval = val & 0xffff;
2795     uint32_t eitr_num = index - EITR;
2796 
2797     trace_e1000e_irq_eitr_set(eitr_num, val);
2798 
2799     core->eitr_guest_value[eitr_num] = interval;
2800     core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2801 }
2802 
2803 static void
e1000e_set_psrctl(E1000ECore * core,int index,uint32_t val)2804 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val)
2805 {
2806     if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) {
2807 
2808         if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) {
2809             qemu_log_mask(LOG_GUEST_ERROR,
2810                           "e1000e: PSRCTL.BSIZE0 cannot be zero");
2811             return;
2812         }
2813 
2814         if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) {
2815             qemu_log_mask(LOG_GUEST_ERROR,
2816                           "e1000e: PSRCTL.BSIZE1 cannot be zero");
2817             return;
2818         }
2819     }
2820 
2821     core->mac[PSRCTL] = val;
2822 }
2823 
2824 static void
e1000e_update_rx_offloads(E1000ECore * core)2825 e1000e_update_rx_offloads(E1000ECore *core)
2826 {
2827     int cso_state = e1000e_rx_l4_cso_enabled(core);
2828 
2829     trace_e1000e_rx_set_cso(cso_state);
2830 
2831     if (core->has_vnet) {
2832         qemu_set_offload(qemu_get_queue(core->owner_nic)->peer,
2833                          cso_state, 0, 0, 0, 0, 0, 0);
2834     }
2835 }
2836 
2837 static void
e1000e_set_rxcsum(E1000ECore * core,int index,uint32_t val)2838 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val)
2839 {
2840     core->mac[RXCSUM] = val;
2841     e1000e_update_rx_offloads(core);
2842 }
2843 
2844 static void
e1000e_set_gcr(E1000ECore * core,int index,uint32_t val)2845 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val)
2846 {
2847     uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS;
2848     core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits;
2849 }
2850 
e1000e_get_systiml(E1000ECore * core,int index)2851 static uint32_t e1000e_get_systiml(E1000ECore *core, int index)
2852 {
2853     e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH);
2854     return core->mac[SYSTIML];
2855 }
2856 
e1000e_get_rxsatrh(E1000ECore * core,int index)2857 static uint32_t e1000e_get_rxsatrh(E1000ECore *core, int index)
2858 {
2859     core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID;
2860     return core->mac[RXSATRH];
2861 }
2862 
e1000e_get_txstmph(E1000ECore * core,int index)2863 static uint32_t e1000e_get_txstmph(E1000ECore *core, int index)
2864 {
2865     core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID;
2866     return core->mac[TXSTMPH];
2867 }
2868 
e1000e_set_timinca(E1000ECore * core,int index,uint32_t val)2869 static void e1000e_set_timinca(E1000ECore *core, int index, uint32_t val)
2870 {
2871     e1000x_set_timinca(core->mac, &core->timadj, val);
2872 }
2873 
e1000e_set_timadjh(E1000ECore * core,int index,uint32_t val)2874 static void e1000e_set_timadjh(E1000ECore *core, int index, uint32_t val)
2875 {
2876     core->mac[TIMADJH] = val;
2877     core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32);
2878 }
2879 
2880 #define e1000e_getreg(x)    [x] = e1000e_mac_readreg
2881 typedef uint32_t (*readops)(E1000ECore *, int);
2882 static const readops e1000e_macreg_readops[] = {
2883     e1000e_getreg(PBA),
2884     e1000e_getreg(WUFC),
2885     e1000e_getreg(MANC),
2886     e1000e_getreg(TOTL),
2887     e1000e_getreg(RDT0),
2888     e1000e_getreg(RDBAH0),
2889     e1000e_getreg(TDBAL1),
2890     e1000e_getreg(RDLEN0),
2891     e1000e_getreg(RDH1),
2892     e1000e_getreg(LATECOL),
2893     e1000e_getreg(SEQEC),
2894     e1000e_getreg(XONTXC),
2895     e1000e_getreg(AIT),
2896     e1000e_getreg(TDFH),
2897     e1000e_getreg(TDFT),
2898     e1000e_getreg(TDFHS),
2899     e1000e_getreg(TDFTS),
2900     e1000e_getreg(TDFPC),
2901     e1000e_getreg(WUS),
2902     e1000e_getreg(PBS),
2903     e1000e_getreg(RDFH),
2904     e1000e_getreg(RDFT),
2905     e1000e_getreg(RDFHS),
2906     e1000e_getreg(RDFTS),
2907     e1000e_getreg(RDFPC),
2908     e1000e_getreg(GORCL),
2909     e1000e_getreg(MGTPRC),
2910     e1000e_getreg(EERD),
2911     e1000e_getreg(EIAC),
2912     e1000e_getreg(PSRCTL),
2913     e1000e_getreg(MANC2H),
2914     e1000e_getreg(RXCSUM),
2915     e1000e_getreg(GSCL_3),
2916     e1000e_getreg(GSCN_2),
2917     e1000e_getreg(RSRPD),
2918     e1000e_getreg(RDBAL1),
2919     e1000e_getreg(FCAH),
2920     e1000e_getreg(FCRTH),
2921     e1000e_getreg(FLOP),
2922     e1000e_getreg(FLASHT),
2923     e1000e_getreg(RXSTMPH),
2924     e1000e_getreg(TXSTMPL),
2925     e1000e_getreg(TIMADJL),
2926     e1000e_getreg(TXDCTL),
2927     e1000e_getreg(RDH0),
2928     e1000e_getreg(TDT1),
2929     e1000e_getreg(TNCRS),
2930     e1000e_getreg(RJC),
2931     e1000e_getreg(IAM),
2932     e1000e_getreg(GSCL_2),
2933     e1000e_getreg(RDBAH1),
2934     e1000e_getreg(FLSWDATA),
2935     e1000e_getreg(TIPG),
2936     e1000e_getreg(FLMNGCTL),
2937     e1000e_getreg(FLMNGCNT),
2938     e1000e_getreg(TSYNCTXCTL),
2939     e1000e_getreg(EXTCNF_SIZE),
2940     e1000e_getreg(EXTCNF_CTRL),
2941     e1000e_getreg(EEMNGDATA),
2942     e1000e_getreg(CTRL_EXT),
2943     e1000e_getreg(SYSTIMH),
2944     e1000e_getreg(EEMNGCTL),
2945     e1000e_getreg(FLMNGDATA),
2946     e1000e_getreg(TSYNCRXCTL),
2947     e1000e_getreg(TDH),
2948     e1000e_getreg(LEDCTL),
2949     e1000e_getreg(TCTL),
2950     e1000e_getreg(TDBAL),
2951     e1000e_getreg(TDLEN),
2952     e1000e_getreg(TDH1),
2953     e1000e_getreg(RADV),
2954     e1000e_getreg(ECOL),
2955     e1000e_getreg(DC),
2956     e1000e_getreg(RLEC),
2957     e1000e_getreg(XOFFTXC),
2958     e1000e_getreg(RFC),
2959     e1000e_getreg(RNBC),
2960     e1000e_getreg(MGTPTC),
2961     e1000e_getreg(TIMINCA),
2962     e1000e_getreg(RXCFGL),
2963     e1000e_getreg(MFUTP01),
2964     e1000e_getreg(FACTPS),
2965     e1000e_getreg(GSCL_1),
2966     e1000e_getreg(GSCN_0),
2967     e1000e_getreg(GCR2),
2968     e1000e_getreg(RDT1),
2969     e1000e_getreg(PBACLR),
2970     e1000e_getreg(FCTTV),
2971     e1000e_getreg(EEWR),
2972     e1000e_getreg(FLSWCTL),
2973     e1000e_getreg(RXDCTL1),
2974     e1000e_getreg(RXSATRL),
2975     e1000e_getreg(RXUDP),
2976     e1000e_getreg(TORL),
2977     e1000e_getreg(TDLEN1),
2978     e1000e_getreg(MCC),
2979     e1000e_getreg(WUC),
2980     e1000e_getreg(EECD),
2981     e1000e_getreg(MFUTP23),
2982     e1000e_getreg(RAID),
2983     e1000e_getreg(FCRTV),
2984     e1000e_getreg(TXDCTL1),
2985     e1000e_getreg(RCTL),
2986     e1000e_getreg(TDT),
2987     e1000e_getreg(MDIC),
2988     e1000e_getreg(FCRUC),
2989     e1000e_getreg(VET),
2990     e1000e_getreg(RDBAL0),
2991     e1000e_getreg(TDBAH1),
2992     e1000e_getreg(RDTR),
2993     e1000e_getreg(SCC),
2994     e1000e_getreg(COLC),
2995     e1000e_getreg(CEXTERR),
2996     e1000e_getreg(XOFFRXC),
2997     e1000e_getreg(IPAV),
2998     e1000e_getreg(GOTCL),
2999     e1000e_getreg(MGTPDC),
3000     e1000e_getreg(GCR),
3001     e1000e_getreg(IVAR),
3002     e1000e_getreg(POEMB),
3003     e1000e_getreg(MFVAL),
3004     e1000e_getreg(FUNCTAG),
3005     e1000e_getreg(GSCL_4),
3006     e1000e_getreg(GSCN_3),
3007     e1000e_getreg(MRQC),
3008     e1000e_getreg(RDLEN1),
3009     e1000e_getreg(FCT),
3010     e1000e_getreg(FLA),
3011     e1000e_getreg(FLOL),
3012     e1000e_getreg(RXDCTL),
3013     e1000e_getreg(RXSTMPL),
3014     e1000e_getreg(TIMADJH),
3015     e1000e_getreg(FCRTL),
3016     e1000e_getreg(TDBAH),
3017     e1000e_getreg(TADV),
3018     e1000e_getreg(XONRXC),
3019     e1000e_getreg(TSCTFC),
3020     e1000e_getreg(RFCTL),
3021     e1000e_getreg(GSCN_1),
3022     e1000e_getreg(FCAL),
3023     e1000e_getreg(FLSWCNT),
3024 
3025     [TOTH]    = e1000e_mac_read_clr8,
3026     [GOTCH]   = e1000e_mac_read_clr8,
3027     [PRC64]   = e1000e_mac_read_clr4,
3028     [PRC255]  = e1000e_mac_read_clr4,
3029     [PRC1023] = e1000e_mac_read_clr4,
3030     [PTC64]   = e1000e_mac_read_clr4,
3031     [PTC255]  = e1000e_mac_read_clr4,
3032     [PTC1023] = e1000e_mac_read_clr4,
3033     [GPRC]    = e1000e_mac_read_clr4,
3034     [TPT]     = e1000e_mac_read_clr4,
3035     [RUC]     = e1000e_mac_read_clr4,
3036     [BPRC]    = e1000e_mac_read_clr4,
3037     [MPTC]    = e1000e_mac_read_clr4,
3038     [IAC]     = e1000e_mac_read_clr4,
3039     [ICR]     = e1000e_mac_icr_read,
3040     [STATUS]  = e1000e_get_status,
3041     [TARC0]   = e1000e_get_tarc,
3042     [ICS]     = e1000e_mac_ics_read,
3043     [TORH]    = e1000e_mac_read_clr8,
3044     [GORCH]   = e1000e_mac_read_clr8,
3045     [PRC127]  = e1000e_mac_read_clr4,
3046     [PRC511]  = e1000e_mac_read_clr4,
3047     [PRC1522] = e1000e_mac_read_clr4,
3048     [PTC127]  = e1000e_mac_read_clr4,
3049     [PTC511]  = e1000e_mac_read_clr4,
3050     [PTC1522] = e1000e_mac_read_clr4,
3051     [GPTC]    = e1000e_mac_read_clr4,
3052     [TPR]     = e1000e_mac_read_clr4,
3053     [ROC]     = e1000e_mac_read_clr4,
3054     [MPRC]    = e1000e_mac_read_clr4,
3055     [BPTC]    = e1000e_mac_read_clr4,
3056     [TSCTC]   = e1000e_mac_read_clr4,
3057     [ITR]     = e1000e_mac_itr_read,
3058     [CTRL]    = e1000e_get_ctrl,
3059     [TARC1]   = e1000e_get_tarc,
3060     [SWSM]    = e1000e_mac_swsm_read,
3061     [IMS]     = e1000e_mac_ims_read,
3062     [SYSTIML] = e1000e_get_systiml,
3063     [RXSATRH] = e1000e_get_rxsatrh,
3064     [TXSTMPH] = e1000e_get_txstmph,
3065 
3066     [CRCERRS ... MPC]      = e1000e_mac_readreg,
3067     [IP6AT ... IP6AT + 3]  = e1000e_mac_readreg,
3068     [IP4AT ... IP4AT + 6]  = e1000e_mac_readreg,
3069     [RA ... RA + 31]       = e1000e_mac_readreg,
3070     [WUPM ... WUPM + 31]   = e1000e_mac_readreg,
3071     [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_readreg,
3072     [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1]  = e1000e_mac_readreg,
3073     [FFMT ... FFMT + 254]  = e1000e_mac_readreg,
3074     [FFVT ... FFVT + 254]  = e1000e_mac_readreg,
3075     [MDEF ... MDEF + 7]    = e1000e_mac_readreg,
3076     [FFLT ... FFLT + 10]   = e1000e_mac_readreg,
3077     [FTFT ... FTFT + 254]  = e1000e_mac_readreg,
3078     [PBM ... PBM + 10239]  = e1000e_mac_readreg,
3079     [RETA ... RETA + 31]   = e1000e_mac_readreg,
3080     [RSSRK ... RSSRK + 31] = e1000e_mac_readreg,
3081     [MAVTV0 ... MAVTV3]    = e1000e_mac_readreg,
3082     [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read
3083 };
3084 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) };
3085 
3086 #define e1000e_putreg(x)    [x] = e1000e_mac_writereg
3087 typedef void (*writeops)(E1000ECore *, int, uint32_t);
3088 static const writeops e1000e_macreg_writeops[] = {
3089     e1000e_putreg(PBA),
3090     e1000e_putreg(SWSM),
3091     e1000e_putreg(WUFC),
3092     e1000e_putreg(RDBAH1),
3093     e1000e_putreg(TDBAH),
3094     e1000e_putreg(TXDCTL),
3095     e1000e_putreg(RDBAH0),
3096     e1000e_putreg(LEDCTL),
3097     e1000e_putreg(FCAL),
3098     e1000e_putreg(FCRUC),
3099     e1000e_putreg(WUC),
3100     e1000e_putreg(WUS),
3101     e1000e_putreg(IPAV),
3102     e1000e_putreg(TDBAH1),
3103     e1000e_putreg(IAM),
3104     e1000e_putreg(EIAC),
3105     e1000e_putreg(IVAR),
3106     e1000e_putreg(TARC0),
3107     e1000e_putreg(TARC1),
3108     e1000e_putreg(FLSWDATA),
3109     e1000e_putreg(POEMB),
3110     e1000e_putreg(MFUTP01),
3111     e1000e_putreg(MFUTP23),
3112     e1000e_putreg(MANC),
3113     e1000e_putreg(MANC2H),
3114     e1000e_putreg(MFVAL),
3115     e1000e_putreg(EXTCNF_CTRL),
3116     e1000e_putreg(FACTPS),
3117     e1000e_putreg(FUNCTAG),
3118     e1000e_putreg(GSCL_1),
3119     e1000e_putreg(GSCL_2),
3120     e1000e_putreg(GSCL_3),
3121     e1000e_putreg(GSCL_4),
3122     e1000e_putreg(GSCN_0),
3123     e1000e_putreg(GSCN_1),
3124     e1000e_putreg(GSCN_2),
3125     e1000e_putreg(GSCN_3),
3126     e1000e_putreg(GCR2),
3127     e1000e_putreg(MRQC),
3128     e1000e_putreg(FLOP),
3129     e1000e_putreg(FLOL),
3130     e1000e_putreg(FLSWCTL),
3131     e1000e_putreg(FLSWCNT),
3132     e1000e_putreg(FLA),
3133     e1000e_putreg(RXDCTL1),
3134     e1000e_putreg(TXDCTL1),
3135     e1000e_putreg(TIPG),
3136     e1000e_putreg(RXSTMPH),
3137     e1000e_putreg(RXSTMPL),
3138     e1000e_putreg(RXSATRL),
3139     e1000e_putreg(RXSATRH),
3140     e1000e_putreg(TXSTMPL),
3141     e1000e_putreg(TXSTMPH),
3142     e1000e_putreg(SYSTIML),
3143     e1000e_putreg(SYSTIMH),
3144     e1000e_putreg(TIMADJL),
3145     e1000e_putreg(RXUDP),
3146     e1000e_putreg(RXCFGL),
3147     e1000e_putreg(TSYNCRXCTL),
3148     e1000e_putreg(TSYNCTXCTL),
3149     e1000e_putreg(EXTCNF_SIZE),
3150     e1000e_putreg(EEMNGCTL),
3151     e1000e_putreg(RA),
3152 
3153     [TDH1]     = e1000e_set_16bit,
3154     [TDT1]     = e1000e_set_tdt,
3155     [TCTL]     = e1000e_set_tctl,
3156     [TDT]      = e1000e_set_tdt,
3157     [MDIC]     = e1000e_set_mdic,
3158     [ICS]      = e1000e_set_ics,
3159     [TDH]      = e1000e_set_16bit,
3160     [RDH0]     = e1000e_set_16bit,
3161     [RDT0]     = e1000e_set_rdt,
3162     [IMC]      = e1000e_set_imc,
3163     [IMS]      = e1000e_set_ims,
3164     [ICR]      = e1000e_set_icr,
3165     [EECD]     = e1000e_set_eecd,
3166     [RCTL]     = e1000e_set_rx_control,
3167     [CTRL]     = e1000e_set_ctrl,
3168     [RDTR]     = e1000e_set_rdtr,
3169     [RADV]     = e1000e_set_16bit,
3170     [TADV]     = e1000e_set_16bit,
3171     [ITR]      = e1000e_set_itr,
3172     [EERD]     = e1000e_set_eerd,
3173     [AIT]      = e1000e_set_16bit,
3174     [TDFH]     = e1000e_set_13bit,
3175     [TDFT]     = e1000e_set_13bit,
3176     [TDFHS]    = e1000e_set_13bit,
3177     [TDFTS]    = e1000e_set_13bit,
3178     [TDFPC]    = e1000e_set_13bit,
3179     [RDFH]     = e1000e_set_13bit,
3180     [RDFHS]    = e1000e_set_13bit,
3181     [RDFT]     = e1000e_set_13bit,
3182     [RDFTS]    = e1000e_set_13bit,
3183     [RDFPC]    = e1000e_set_13bit,
3184     [PBS]      = e1000e_set_6bit,
3185     [GCR]      = e1000e_set_gcr,
3186     [PSRCTL]   = e1000e_set_psrctl,
3187     [RXCSUM]   = e1000e_set_rxcsum,
3188     [RAID]     = e1000e_set_16bit,
3189     [RSRPD]    = e1000e_set_12bit,
3190     [TIDV]     = e1000e_set_tidv,
3191     [TDLEN1]   = e1000e_set_dlen,
3192     [TDLEN]    = e1000e_set_dlen,
3193     [RDLEN0]   = e1000e_set_dlen,
3194     [RDLEN1]   = e1000e_set_dlen,
3195     [TDBAL]    = e1000e_set_dbal,
3196     [TDBAL1]   = e1000e_set_dbal,
3197     [RDBAL0]   = e1000e_set_dbal,
3198     [RDBAL1]   = e1000e_set_dbal,
3199     [RDH1]     = e1000e_set_16bit,
3200     [RDT1]     = e1000e_set_rdt,
3201     [STATUS]   = e1000e_set_status,
3202     [PBACLR]   = e1000e_set_pbaclr,
3203     [CTRL_EXT] = e1000e_set_ctrlext,
3204     [FCAH]     = e1000e_set_16bit,
3205     [FCT]      = e1000e_set_16bit,
3206     [FCTTV]    = e1000e_set_16bit,
3207     [FCRTV]    = e1000e_set_16bit,
3208     [FCRTH]    = e1000e_set_fcrth,
3209     [FCRTL]    = e1000e_set_fcrtl,
3210     [VET]      = e1000e_set_vet,
3211     [RXDCTL]   = e1000e_set_rxdctl,
3212     [FLASHT]   = e1000e_set_16bit,
3213     [EEWR]     = e1000e_set_eewr,
3214     [CTRL_DUP] = e1000e_set_ctrl,
3215     [RFCTL]    = e1000e_set_rfctl,
3216     [RA + 1]   = e1000e_mac_setmacaddr,
3217     [TIMINCA]  = e1000e_set_timinca,
3218     [TIMADJH]  = e1000e_set_timadjh,
3219 
3220     [IP6AT ... IP6AT + 3]    = e1000e_mac_writereg,
3221     [IP4AT ... IP4AT + 6]    = e1000e_mac_writereg,
3222     [RA + 2 ... RA + 31]     = e1000e_mac_writereg,
3223     [WUPM ... WUPM + 31]     = e1000e_mac_writereg,
3224     [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_writereg,
3225     [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1]    = e1000e_mac_writereg,
3226     [FFMT ... FFMT + 254]    = e1000e_set_4bit,
3227     [FFVT ... FFVT + 254]    = e1000e_mac_writereg,
3228     [PBM ... PBM + 10239]    = e1000e_mac_writereg,
3229     [MDEF ... MDEF + 7]      = e1000e_mac_writereg,
3230     [FFLT ... FFLT + 10]     = e1000e_set_11bit,
3231     [FTFT ... FTFT + 254]    = e1000e_mac_writereg,
3232     [RETA ... RETA + 31]     = e1000e_mac_writereg,
3233     [RSSRK ... RSSRK + 31]   = e1000e_mac_writereg,
3234     [MAVTV0 ... MAVTV3]      = e1000e_mac_writereg,
3235     [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr
3236 };
3237 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) };
3238 
3239 enum { MAC_ACCESS_PARTIAL = 1 };
3240 
3241 /*
3242  * The array below combines alias offsets of the index values for the
3243  * MAC registers that have aliases, with the indication of not fully
3244  * implemented registers (lowest bit). This combination is possible
3245  * because all of the offsets are even.
3246  */
3247 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = {
3248     /* Alias index offsets */
3249     [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802,
3250     [RDH0_A]  = 0x09bc, [RDT0_A]  = 0x09bc, [RDTR_A] = 0x09c6,
3251     [RDFH_A]  = 0xe904, [RDFT_A]  = 0xe904,
3252     [TDH_A]   = 0x0cf8, [TDT_A]   = 0x0cf8, [TIDV_A] = 0x0cf8,
3253     [TDFH_A]  = 0xed00, [TDFT_A]  = 0xed00,
3254     [RA_A ... RA_A + 31]      = 0x14f0,
3255     [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400,
3256     [RDBAL0_A ... RDLEN0_A] = 0x09bc,
3257     [TDBAL_A ... TDLEN_A]   = 0x0cf8,
3258     /* Access options */
3259     [RDFH]  = MAC_ACCESS_PARTIAL,    [RDFT]  = MAC_ACCESS_PARTIAL,
3260     [RDFHS] = MAC_ACCESS_PARTIAL,    [RDFTS] = MAC_ACCESS_PARTIAL,
3261     [RDFPC] = MAC_ACCESS_PARTIAL,
3262     [TDFH]  = MAC_ACCESS_PARTIAL,    [TDFT]  = MAC_ACCESS_PARTIAL,
3263     [TDFHS] = MAC_ACCESS_PARTIAL,    [TDFTS] = MAC_ACCESS_PARTIAL,
3264     [TDFPC] = MAC_ACCESS_PARTIAL,    [EECD]  = MAC_ACCESS_PARTIAL,
3265     [PBM]   = MAC_ACCESS_PARTIAL,    [FLA]   = MAC_ACCESS_PARTIAL,
3266     [FCAL]  = MAC_ACCESS_PARTIAL,    [FCAH]  = MAC_ACCESS_PARTIAL,
3267     [FCT]   = MAC_ACCESS_PARTIAL,    [FCTTV] = MAC_ACCESS_PARTIAL,
3268     [FCRTV] = MAC_ACCESS_PARTIAL,    [FCRTL] = MAC_ACCESS_PARTIAL,
3269     [FCRTH] = MAC_ACCESS_PARTIAL,    [TXDCTL] = MAC_ACCESS_PARTIAL,
3270     [TXDCTL1] = MAC_ACCESS_PARTIAL,
3271     [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL
3272 };
3273 
3274 void
e1000e_core_write(E1000ECore * core,hwaddr addr,uint64_t val,unsigned size)3275 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size)
3276 {
3277     uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3278 
3279     if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) {
3280         if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3281             trace_e1000e_wrn_regs_write_trivial(index << 2);
3282         }
3283         trace_e1000e_core_write(index << 2, size, val);
3284         e1000e_macreg_writeops[index](core, index, val);
3285     } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3286         trace_e1000e_wrn_regs_write_ro(index << 2, size, val);
3287     } else {
3288         trace_e1000e_wrn_regs_write_unknown(index << 2, size, val);
3289     }
3290 }
3291 
3292 uint64_t
e1000e_core_read(E1000ECore * core,hwaddr addr,unsigned size)3293 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size)
3294 {
3295     uint64_t val;
3296     uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3297 
3298     if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3299         if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3300             trace_e1000e_wrn_regs_read_trivial(index << 2);
3301         }
3302         val = e1000e_macreg_readops[index](core, index);
3303         trace_e1000e_core_read(index << 2, size, val);
3304         return val;
3305     } else {
3306         trace_e1000e_wrn_regs_read_unknown(index << 2, size);
3307     }
3308     return 0;
3309 }
3310 
3311 static void
e1000e_autoneg_resume(E1000ECore * core)3312 e1000e_autoneg_resume(E1000ECore *core)
3313 {
3314     if (e1000e_have_autoneg(core) &&
3315         !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) {
3316         qemu_get_queue(core->owner_nic)->link_down = false;
3317         timer_mod(core->autoneg_timer,
3318                   qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
3319     }
3320 }
3321 
3322 void
e1000e_core_pci_realize(E1000ECore * core,const uint16_t * eeprom_templ,uint32_t eeprom_size,const uint8_t * macaddr)3323 e1000e_core_pci_realize(E1000ECore     *core,
3324                         const uint16_t *eeprom_templ,
3325                         uint32_t        eeprom_size,
3326                         const uint8_t  *macaddr)
3327 {
3328     int i;
3329 
3330     core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3331                                        e1000e_autoneg_timer, core);
3332     e1000e_intrmgr_pci_realize(core);
3333 
3334     for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3335         net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS);
3336     }
3337 
3338     net_rx_pkt_init(&core->rx_pkt);
3339 
3340     e1000x_core_prepare_eeprom(core->eeprom,
3341                                eeprom_templ,
3342                                eeprom_size,
3343                                PCI_DEVICE_GET_CLASS(core->owner)->device_id,
3344                                macaddr);
3345     e1000e_update_rx_offloads(core);
3346 }
3347 
3348 void
e1000e_core_pci_uninit(E1000ECore * core)3349 e1000e_core_pci_uninit(E1000ECore *core)
3350 {
3351     int i;
3352 
3353     timer_free(core->autoneg_timer);
3354 
3355     e1000e_intrmgr_pci_unint(core);
3356 
3357     for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3358         net_tx_pkt_uninit(core->tx[i].tx_pkt);
3359     }
3360 
3361     net_rx_pkt_uninit(core->rx_pkt);
3362 }
3363 
3364 static const uint16_t
3365 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = {
3366     [0] = {
3367         [MII_BMCR] = MII_BMCR_SPEED1000 |
3368                      MII_BMCR_FD        |
3369                      MII_BMCR_AUTOEN,
3370 
3371         [MII_BMSR] = MII_BMSR_EXTCAP    |
3372                      MII_BMSR_LINK_ST   |
3373                      MII_BMSR_AUTONEG   |
3374                      MII_BMSR_MFPS      |
3375                      MII_BMSR_EXTSTAT   |
3376                      MII_BMSR_10T_HD    |
3377                      MII_BMSR_10T_FD    |
3378                      MII_BMSR_100TX_HD  |
3379                      MII_BMSR_100TX_FD,
3380 
3381         [MII_PHYID1]            = 0x141,
3382         [MII_PHYID2]            = E1000_PHY_ID2_82574x,
3383         [MII_ANAR]              = MII_ANAR_CSMACD | MII_ANAR_10 |
3384                                   MII_ANAR_10FD | MII_ANAR_TX |
3385                                   MII_ANAR_TXFD | MII_ANAR_PAUSE |
3386                                   MII_ANAR_PAUSE_ASYM,
3387         [MII_ANLPAR]            = MII_ANLPAR_10 | MII_ANLPAR_10FD |
3388                                   MII_ANLPAR_TX | MII_ANLPAR_TXFD |
3389                                   MII_ANLPAR_T4 | MII_ANLPAR_PAUSE,
3390         [MII_ANER]              = MII_ANER_NP | MII_ANER_NWAY,
3391         [MII_ANNP]              = 1 | MII_ANNP_MP,
3392         [MII_CTRL1000]          = MII_CTRL1000_HALF | MII_CTRL1000_FULL |
3393                                   MII_CTRL1000_PORT | MII_CTRL1000_MASTER,
3394         [MII_STAT1000]          = MII_STAT1000_HALF | MII_STAT1000_FULL |
3395                                   MII_STAT1000_ROK | MII_STAT1000_LOK,
3396         [MII_EXTSTAT]           = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD,
3397 
3398         [PHY_COPPER_CTRL1]      = BIT(5) | BIT(6) | BIT(8) | BIT(9) |
3399                                   BIT(12) | BIT(13),
3400         [PHY_COPPER_STAT1]      = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15)
3401     },
3402     [2] = {
3403         [PHY_MAC_CTRL1]         = BIT(3) | BIT(7),
3404         [PHY_MAC_CTRL2]         = BIT(1) | BIT(2) | BIT(6) | BIT(12)
3405     },
3406     [3] = {
3407         [PHY_LED_TIMER_CTRL]    = BIT(0) | BIT(2) | BIT(14)
3408     }
3409 };
3410 
3411 static const uint32_t e1000e_mac_reg_init[] = {
3412     [PBA]           =     0x00140014,
3413     [LEDCTL]        =  BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18),
3414     [EXTCNF_CTRL]   = BIT(3),
3415     [EEMNGCTL]      = BIT(31),
3416     [FLASHT]        = 0x2,
3417     [FLSWCTL]       = BIT(30) | BIT(31),
3418     [FLOL]          = BIT(0),
3419     [RXDCTL]        = BIT(16),
3420     [RXDCTL1]       = BIT(16),
3421     [TIPG]          = 0x8 | (0x8 << 10) | (0x6 << 20),
3422     [RXCFGL]        = 0x88F7,
3423     [RXUDP]         = 0x319,
3424     [CTRL]          = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
3425                       E1000_CTRL_SPD_1000 | E1000_CTRL_SLU |
3426                       E1000_CTRL_ADVD3WUC,
3427     [STATUS]        =  E1000_STATUS_ASDV_1000 | E1000_STATUS_LU,
3428     [PSRCTL]        = (2 << E1000_PSRCTL_BSIZE0_SHIFT) |
3429                       (4 << E1000_PSRCTL_BSIZE1_SHIFT) |
3430                       (4 << E1000_PSRCTL_BSIZE2_SHIFT),
3431     [TARC0]         = 0x3 | E1000_TARC_ENABLE,
3432     [TARC1]         = 0x3 | E1000_TARC_ENABLE,
3433     [EECD]          = E1000_EECD_AUTO_RD | E1000_EECD_PRES,
3434     [EERD]          = E1000_EERW_DONE,
3435     [EEWR]          = E1000_EERW_DONE,
3436     [GCR]           = E1000_L0S_ADJUST |
3437                       E1000_L1_ENTRY_LATENCY_MSB |
3438                       E1000_L1_ENTRY_LATENCY_LSB,
3439     [TDFH]          = 0x600,
3440     [TDFT]          = 0x600,
3441     [TDFHS]         = 0x600,
3442     [TDFTS]         = 0x600,
3443     [POEMB]         = 0x30D,
3444     [PBS]           = 0x028,
3445     [MANC]          = E1000_MANC_DIS_IP_CHK_ARP,
3446     [FACTPS]        = E1000_FACTPS_LAN0_ON | 0x20000000,
3447     [SWSM]          = 1,
3448     [RXCSUM]        = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD,
3449     [ITR]           = E1000E_MIN_XITR,
3450     [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR,
3451 };
3452 
e1000e_reset(E1000ECore * core,bool sw)3453 static void e1000e_reset(E1000ECore *core, bool sw)
3454 {
3455     int i;
3456 
3457     timer_del(core->autoneg_timer);
3458 
3459     e1000e_intrmgr_reset(core);
3460 
3461     memset(core->phy, 0, sizeof core->phy);
3462     memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init);
3463 
3464     for (i = 0; i < E1000E_MAC_SIZE; i++) {
3465         if (sw && (i == PBA || i == PBS || i == FLA)) {
3466             continue;
3467         }
3468 
3469         core->mac[i] = i < ARRAY_SIZE(e1000e_mac_reg_init) ?
3470                        e1000e_mac_reg_init[i] : 0;
3471     }
3472 
3473     core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT;
3474 
3475     if (qemu_get_queue(core->owner_nic)->link_down) {
3476         e1000e_link_down(core);
3477     }
3478 
3479     e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
3480 
3481     for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3482         memset(&core->tx[i].props, 0, sizeof(core->tx[i].props));
3483         core->tx[i].skip_cp = false;
3484     }
3485 }
3486 
3487 void
e1000e_core_reset(E1000ECore * core)3488 e1000e_core_reset(E1000ECore *core)
3489 {
3490     e1000e_reset(core, false);
3491 }
3492 
e1000e_core_pre_save(E1000ECore * core)3493 void e1000e_core_pre_save(E1000ECore *core)
3494 {
3495     int i;
3496     NetClientState *nc = qemu_get_queue(core->owner_nic);
3497 
3498     /*
3499      * If link is down and auto-negotiation is supported and ongoing,
3500      * complete auto-negotiation immediately. This allows us to look
3501      * at MII_BMSR_AN_COMP to infer link status on load.
3502      */
3503     if (nc->link_down && e1000e_have_autoneg(core)) {
3504         core->phy[0][MII_BMSR] |= MII_BMSR_AN_COMP;
3505         e1000e_update_flowctl_status(core);
3506     }
3507 
3508     for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3509         if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) {
3510             core->tx[i].skip_cp = true;
3511         }
3512     }
3513 }
3514 
3515 int
e1000e_core_post_load(E1000ECore * core)3516 e1000e_core_post_load(E1000ECore *core)
3517 {
3518     NetClientState *nc = qemu_get_queue(core->owner_nic);
3519 
3520     /*
3521      * nc.link_down can't be migrated, so infer link_down according
3522      * to link status bit in core.mac[STATUS].
3523      */
3524     nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0;
3525 
3526     /*
3527      * we need to restart intrmgr timers, as an older version of
3528      * QEMU can have stopped them before migration
3529      */
3530     e1000e_intrmgr_resume(core);
3531     e1000e_autoneg_resume(core);
3532 
3533     return 0;
3534 }
3535