1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 #include "e1000.h"
5 #include <linux/ethtool.h>
6
7 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
8 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
9 u16 *data, bool read, bool page_set);
10 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
11 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
12 u16 *data, bool read);
13
14 /* Cable length tables */
15 static const u16 e1000_m88_cable_length_table[] = {
16 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
17 };
18
19 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
20 ARRAY_SIZE(e1000_m88_cable_length_table)
21
22 static const u16 e1000_igp_2_cable_length_table[] = {
23 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
24 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
25 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
26 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
27 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
28 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
29 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
30 124
31 };
32
33 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
34 ARRAY_SIZE(e1000_igp_2_cable_length_table)
35
36 /**
37 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
38 * @hw: pointer to the HW structure
39 *
40 * Read the PHY management control register and check whether a PHY reset
41 * is blocked. If a reset is not blocked return 0, otherwise
42 * return E1000_BLK_PHY_RESET (12).
43 **/
e1000e_check_reset_block_generic(struct e1000_hw * hw)44 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
45 {
46 u32 manc;
47
48 manc = er32(MANC);
49
50 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
51 }
52
53 /**
54 * e1000e_get_phy_id - Retrieve the PHY ID and revision
55 * @hw: pointer to the HW structure
56 *
57 * Reads the PHY registers and stores the PHY ID and possibly the PHY
58 * revision in the hardware structure.
59 **/
e1000e_get_phy_id(struct e1000_hw * hw)60 s32 e1000e_get_phy_id(struct e1000_hw *hw)
61 {
62 struct e1000_phy_info *phy = &hw->phy;
63 s32 ret_val = 0;
64 u16 phy_id;
65 u16 retry_count = 0;
66
67 if (!phy->ops.read_reg)
68 return 0;
69
70 while (retry_count < 2) {
71 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
72 if (ret_val)
73 return ret_val;
74
75 phy->id = (u32)(phy_id << 16);
76 usleep_range(20, 40);
77 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
78 if (ret_val)
79 return ret_val;
80
81 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
82 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
83
84 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
85 return 0;
86
87 retry_count++;
88 }
89
90 return 0;
91 }
92
93 /**
94 * e1000e_phy_reset_dsp - Reset PHY DSP
95 * @hw: pointer to the HW structure
96 *
97 * Reset the digital signal processor.
98 **/
e1000e_phy_reset_dsp(struct e1000_hw * hw)99 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
100 {
101 s32 ret_val;
102
103 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
104 if (ret_val)
105 return ret_val;
106
107 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
108 }
109
e1000e_disable_phy_retry(struct e1000_hw * hw)110 void e1000e_disable_phy_retry(struct e1000_hw *hw)
111 {
112 hw->phy.retry_enabled = false;
113 }
114
e1000e_enable_phy_retry(struct e1000_hw * hw)115 void e1000e_enable_phy_retry(struct e1000_hw *hw)
116 {
117 hw->phy.retry_enabled = true;
118 }
119
120 /**
121 * e1000e_read_phy_reg_mdic - Read MDI control register
122 * @hw: pointer to the HW structure
123 * @offset: register offset to be read
124 * @data: pointer to the read data
125 *
126 * Reads the MDI control register in the PHY at offset and stores the
127 * information read to data.
128 **/
e1000e_read_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 * data)129 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
130 {
131 u32 i, mdic = 0, retry_counter, retry_max;
132 struct e1000_phy_info *phy = &hw->phy;
133 bool success;
134
135 if (offset > MAX_PHY_REG_ADDRESS) {
136 e_dbg("PHY Address %d is out of range\n", offset);
137 return -E1000_ERR_PARAM;
138 }
139
140 retry_max = phy->retry_enabled ? phy->retry_count : 0;
141
142 /* Set up Op-code, Phy Address, and register offset in the MDI
143 * Control register. The MAC will take care of interfacing with the
144 * PHY to retrieve the desired data.
145 */
146 for (retry_counter = 0; retry_counter <= retry_max; retry_counter++) {
147 success = true;
148
149 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
150 (phy->addr << E1000_MDIC_PHY_SHIFT) |
151 (E1000_MDIC_OP_READ));
152
153 ew32(MDIC, mdic);
154
155 /* Poll the ready bit to see if the MDI read completed
156 * Increasing the time out as testing showed failures with
157 * the lower time out
158 */
159 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
160 udelay(50);
161 mdic = er32(MDIC);
162 if (mdic & E1000_MDIC_READY)
163 break;
164 }
165 if (!(mdic & E1000_MDIC_READY)) {
166 e_dbg("MDI Read PHY Reg Address %d did not complete\n",
167 offset);
168 success = false;
169 }
170 if (mdic & E1000_MDIC_ERROR) {
171 e_dbg("MDI Read PHY Reg Address %d Error\n", offset);
172 success = false;
173 }
174 if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
175 e_dbg("MDI Read offset error - requested %d, returned %d\n",
176 offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
177 success = false;
178 }
179
180 /* Allow some time after each MDIC transaction to avoid
181 * reading duplicate data in the next MDIC transaction.
182 */
183 if (hw->mac.type == e1000_pch2lan)
184 udelay(100);
185
186 if (success) {
187 *data = (u16)mdic;
188 return 0;
189 }
190
191 if (retry_counter != retry_max) {
192 e_dbg("Perform retry on PHY transaction...\n");
193 mdelay(10);
194 }
195 }
196
197 return -E1000_ERR_PHY;
198 }
199
200 /**
201 * e1000e_write_phy_reg_mdic - Write MDI control register
202 * @hw: pointer to the HW structure
203 * @offset: register offset to write to
204 * @data: data to write to register at offset
205 *
206 * Writes data to MDI control register in the PHY at offset.
207 **/
e1000e_write_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 data)208 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
209 {
210 u32 i, mdic = 0, retry_counter, retry_max;
211 struct e1000_phy_info *phy = &hw->phy;
212 bool success;
213
214 if (offset > MAX_PHY_REG_ADDRESS) {
215 e_dbg("PHY Address %d is out of range\n", offset);
216 return -E1000_ERR_PARAM;
217 }
218
219 retry_max = phy->retry_enabled ? phy->retry_count : 0;
220
221 /* Set up Op-code, Phy Address, and register offset in the MDI
222 * Control register. The MAC will take care of interfacing with the
223 * PHY to retrieve the desired data.
224 */
225 for (retry_counter = 0; retry_counter <= retry_max; retry_counter++) {
226 success = true;
227
228 mdic = (((u32)data) |
229 (offset << E1000_MDIC_REG_SHIFT) |
230 (phy->addr << E1000_MDIC_PHY_SHIFT) |
231 (E1000_MDIC_OP_WRITE));
232
233 ew32(MDIC, mdic);
234
235 /* Poll the ready bit to see if the MDI read completed
236 * Increasing the time out as testing showed failures with
237 * the lower time out
238 */
239 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
240 udelay(50);
241 mdic = er32(MDIC);
242 if (mdic & E1000_MDIC_READY)
243 break;
244 }
245 if (!(mdic & E1000_MDIC_READY)) {
246 e_dbg("MDI Write PHY Reg Address %d did not complete\n",
247 offset);
248 success = false;
249 }
250 if (mdic & E1000_MDIC_ERROR) {
251 e_dbg("MDI Write PHY Reg Address %d Error\n", offset);
252 success = false;
253 }
254 if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
255 e_dbg("MDI Write offset error - requested %d, returned %d\n",
256 offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
257 success = false;
258 }
259
260 /* Allow some time after each MDIC transaction to avoid
261 * reading duplicate data in the next MDIC transaction.
262 */
263 if (hw->mac.type == e1000_pch2lan)
264 udelay(100);
265
266 if (success)
267 return 0;
268
269 if (retry_counter != retry_max) {
270 e_dbg("Perform retry on PHY transaction...\n");
271 mdelay(10);
272 }
273 }
274
275 return -E1000_ERR_PHY;
276 }
277
278 /**
279 * e1000e_read_phy_reg_m88 - Read m88 PHY register
280 * @hw: pointer to the HW structure
281 * @offset: register offset to be read
282 * @data: pointer to the read data
283 *
284 * Acquires semaphore, if necessary, then reads the PHY register at offset
285 * and storing the retrieved information in data. Release any acquired
286 * semaphores before exiting.
287 **/
e1000e_read_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 * data)288 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
289 {
290 s32 ret_val;
291
292 ret_val = hw->phy.ops.acquire(hw);
293 if (ret_val)
294 return ret_val;
295
296 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
297 data);
298
299 hw->phy.ops.release(hw);
300
301 return ret_val;
302 }
303
304 /**
305 * e1000e_write_phy_reg_m88 - Write m88 PHY register
306 * @hw: pointer to the HW structure
307 * @offset: register offset to write to
308 * @data: data to write at register offset
309 *
310 * Acquires semaphore, if necessary, then writes the data to PHY register
311 * at the offset. Release any acquired semaphores before exiting.
312 **/
e1000e_write_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 data)313 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
314 {
315 s32 ret_val;
316
317 ret_val = hw->phy.ops.acquire(hw);
318 if (ret_val)
319 return ret_val;
320
321 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
322 data);
323
324 hw->phy.ops.release(hw);
325
326 return ret_val;
327 }
328
329 /**
330 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
331 * @hw: pointer to the HW structure
332 * @page: page to set (shifted left when necessary)
333 *
334 * Sets PHY page required for PHY register access. Assumes semaphore is
335 * already acquired. Note, this function sets phy.addr to 1 so the caller
336 * must set it appropriately (if necessary) after this function returns.
337 **/
e1000_set_page_igp(struct e1000_hw * hw,u16 page)338 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
339 {
340 e_dbg("Setting page 0x%x\n", page);
341
342 hw->phy.addr = 1;
343
344 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
345 }
346
347 /**
348 * __e1000e_read_phy_reg_igp - Read igp PHY register
349 * @hw: pointer to the HW structure
350 * @offset: register offset to be read
351 * @data: pointer to the read data
352 * @locked: semaphore has already been acquired or not
353 *
354 * Acquires semaphore, if necessary, then reads the PHY register at offset
355 * and stores the retrieved information in data. Release any acquired
356 * semaphores before exiting.
357 **/
__e1000e_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)358 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
359 bool locked)
360 {
361 s32 ret_val = 0;
362
363 if (!locked) {
364 if (!hw->phy.ops.acquire)
365 return 0;
366
367 ret_val = hw->phy.ops.acquire(hw);
368 if (ret_val)
369 return ret_val;
370 }
371
372 if (offset > MAX_PHY_MULTI_PAGE_REG)
373 ret_val = e1000e_write_phy_reg_mdic(hw,
374 IGP01E1000_PHY_PAGE_SELECT,
375 (u16)offset);
376 if (!ret_val)
377 ret_val = e1000e_read_phy_reg_mdic(hw,
378 MAX_PHY_REG_ADDRESS & offset,
379 data);
380 if (!locked)
381 hw->phy.ops.release(hw);
382
383 return ret_val;
384 }
385
386 /**
387 * e1000e_read_phy_reg_igp - Read igp PHY register
388 * @hw: pointer to the HW structure
389 * @offset: register offset to be read
390 * @data: pointer to the read data
391 *
392 * Acquires semaphore then reads the PHY register at offset and stores the
393 * retrieved information in data.
394 * Release the acquired semaphore before exiting.
395 **/
e1000e_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data)396 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
397 {
398 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
399 }
400
401 /**
402 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
403 * @hw: pointer to the HW structure
404 * @offset: register offset to be read
405 * @data: pointer to the read data
406 *
407 * Reads the PHY register at offset and stores the retrieved information
408 * in data. Assumes semaphore already acquired.
409 **/
e1000e_read_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 * data)410 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
411 {
412 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
413 }
414
415 /**
416 * __e1000e_write_phy_reg_igp - Write igp PHY register
417 * @hw: pointer to the HW structure
418 * @offset: register offset to write to
419 * @data: data to write at register offset
420 * @locked: semaphore has already been acquired or not
421 *
422 * Acquires semaphore, if necessary, then writes the data to PHY register
423 * at the offset. Release any acquired semaphores before exiting.
424 **/
__e1000e_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data,bool locked)425 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
426 bool locked)
427 {
428 s32 ret_val = 0;
429
430 if (!locked) {
431 if (!hw->phy.ops.acquire)
432 return 0;
433
434 ret_val = hw->phy.ops.acquire(hw);
435 if (ret_val)
436 return ret_val;
437 }
438
439 if (offset > MAX_PHY_MULTI_PAGE_REG)
440 ret_val = e1000e_write_phy_reg_mdic(hw,
441 IGP01E1000_PHY_PAGE_SELECT,
442 (u16)offset);
443 if (!ret_val)
444 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
445 offset, data);
446 if (!locked)
447 hw->phy.ops.release(hw);
448
449 return ret_val;
450 }
451
452 /**
453 * e1000e_write_phy_reg_igp - Write igp PHY register
454 * @hw: pointer to the HW structure
455 * @offset: register offset to write to
456 * @data: data to write at register offset
457 *
458 * Acquires semaphore then writes the data to PHY register
459 * at the offset. Release any acquired semaphores before exiting.
460 **/
e1000e_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data)461 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
462 {
463 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
464 }
465
466 /**
467 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
468 * @hw: pointer to the HW structure
469 * @offset: register offset to write to
470 * @data: data to write at register offset
471 *
472 * Writes the data to PHY register at the offset.
473 * Assumes semaphore already acquired.
474 **/
e1000e_write_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 data)475 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
476 {
477 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
478 }
479
480 /**
481 * __e1000_read_kmrn_reg - Read kumeran register
482 * @hw: pointer to the HW structure
483 * @offset: register offset to be read
484 * @data: pointer to the read data
485 * @locked: semaphore has already been acquired or not
486 *
487 * Acquires semaphore, if necessary. Then reads the PHY register at offset
488 * using the kumeran interface. The information retrieved is stored in data.
489 * Release any acquired semaphores before exiting.
490 **/
__e1000_read_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)491 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
492 bool locked)
493 {
494 u32 kmrnctrlsta;
495
496 if (!locked) {
497 s32 ret_val = 0;
498
499 if (!hw->phy.ops.acquire)
500 return 0;
501
502 ret_val = hw->phy.ops.acquire(hw);
503 if (ret_val)
504 return ret_val;
505 }
506
507 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
508 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
509 ew32(KMRNCTRLSTA, kmrnctrlsta);
510 e1e_flush();
511
512 udelay(2);
513
514 kmrnctrlsta = er32(KMRNCTRLSTA);
515 *data = (u16)kmrnctrlsta;
516
517 if (!locked)
518 hw->phy.ops.release(hw);
519
520 return 0;
521 }
522
523 /**
524 * e1000e_read_kmrn_reg - Read kumeran register
525 * @hw: pointer to the HW structure
526 * @offset: register offset to be read
527 * @data: pointer to the read data
528 *
529 * Acquires semaphore then reads the PHY register at offset using the
530 * kumeran interface. The information retrieved is stored in data.
531 * Release the acquired semaphore before exiting.
532 **/
e1000e_read_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 * data)533 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
534 {
535 return __e1000_read_kmrn_reg(hw, offset, data, false);
536 }
537
538 /**
539 * e1000e_read_kmrn_reg_locked - Read kumeran register
540 * @hw: pointer to the HW structure
541 * @offset: register offset to be read
542 * @data: pointer to the read data
543 *
544 * Reads the PHY register at offset using the kumeran interface. The
545 * information retrieved is stored in data.
546 * Assumes semaphore already acquired.
547 **/
e1000e_read_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 * data)548 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
549 {
550 return __e1000_read_kmrn_reg(hw, offset, data, true);
551 }
552
553 /**
554 * __e1000_write_kmrn_reg - Write kumeran register
555 * @hw: pointer to the HW structure
556 * @offset: register offset to write to
557 * @data: data to write at register offset
558 * @locked: semaphore has already been acquired or not
559 *
560 * Acquires semaphore, if necessary. Then write the data to PHY register
561 * at the offset using the kumeran interface. Release any acquired semaphores
562 * before exiting.
563 **/
__e1000_write_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 data,bool locked)564 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
565 bool locked)
566 {
567 u32 kmrnctrlsta;
568
569 if (!locked) {
570 s32 ret_val = 0;
571
572 if (!hw->phy.ops.acquire)
573 return 0;
574
575 ret_val = hw->phy.ops.acquire(hw);
576 if (ret_val)
577 return ret_val;
578 }
579
580 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
581 E1000_KMRNCTRLSTA_OFFSET) | data;
582 ew32(KMRNCTRLSTA, kmrnctrlsta);
583 e1e_flush();
584
585 udelay(2);
586
587 if (!locked)
588 hw->phy.ops.release(hw);
589
590 return 0;
591 }
592
593 /**
594 * e1000e_write_kmrn_reg - Write kumeran register
595 * @hw: pointer to the HW structure
596 * @offset: register offset to write to
597 * @data: data to write at register offset
598 *
599 * Acquires semaphore then writes the data to the PHY register at the offset
600 * using the kumeran interface. Release the acquired semaphore before exiting.
601 **/
e1000e_write_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 data)602 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
603 {
604 return __e1000_write_kmrn_reg(hw, offset, data, false);
605 }
606
607 /**
608 * e1000e_write_kmrn_reg_locked - Write kumeran register
609 * @hw: pointer to the HW structure
610 * @offset: register offset to write to
611 * @data: data to write at register offset
612 *
613 * Write the data to PHY register at the offset using the kumeran interface.
614 * Assumes semaphore already acquired.
615 **/
e1000e_write_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 data)616 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
617 {
618 return __e1000_write_kmrn_reg(hw, offset, data, true);
619 }
620
621 /**
622 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
623 * @hw: pointer to the HW structure
624 *
625 * Sets up Master/slave mode
626 **/
e1000_set_master_slave_mode(struct e1000_hw * hw)627 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
628 {
629 s32 ret_val;
630 u16 phy_data;
631
632 /* Resolve Master/Slave mode */
633 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data);
634 if (ret_val)
635 return ret_val;
636
637 /* load defaults for future use */
638 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ?
639 ((phy_data & CTL1000_AS_MASTER) ?
640 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
641
642 switch (hw->phy.ms_type) {
643 case e1000_ms_force_master:
644 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
645 break;
646 case e1000_ms_force_slave:
647 phy_data |= CTL1000_ENABLE_MASTER;
648 phy_data &= ~(CTL1000_AS_MASTER);
649 break;
650 case e1000_ms_auto:
651 phy_data &= ~CTL1000_ENABLE_MASTER;
652 fallthrough;
653 default:
654 break;
655 }
656
657 return e1e_wphy(hw, MII_CTRL1000, phy_data);
658 }
659
660 /**
661 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
662 * @hw: pointer to the HW structure
663 *
664 * Sets up Carrier-sense on Transmit and downshift values.
665 **/
e1000_copper_link_setup_82577(struct e1000_hw * hw)666 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
667 {
668 s32 ret_val;
669 u16 phy_data;
670
671 /* Enable CRS on Tx. This must be set for half-duplex operation. */
672 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
673 if (ret_val)
674 return ret_val;
675
676 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
677
678 /* Enable downshift */
679 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
680
681 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
682 if (ret_val)
683 return ret_val;
684
685 /* Set MDI/MDIX mode */
686 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
687 if (ret_val)
688 return ret_val;
689 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
690 /* Options:
691 * 0 - Auto (default)
692 * 1 - MDI mode
693 * 2 - MDI-X mode
694 */
695 switch (hw->phy.mdix) {
696 case 1:
697 break;
698 case 2:
699 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
700 break;
701 case 0:
702 default:
703 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
704 break;
705 }
706 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
707 if (ret_val)
708 return ret_val;
709
710 return e1000_set_master_slave_mode(hw);
711 }
712
713 /**
714 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
715 * @hw: pointer to the HW structure
716 *
717 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
718 * and downshift values are set also.
719 **/
e1000e_copper_link_setup_m88(struct e1000_hw * hw)720 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
721 {
722 struct e1000_phy_info *phy = &hw->phy;
723 s32 ret_val;
724 u16 phy_data;
725
726 /* Enable CRS on Tx. This must be set for half-duplex operation. */
727 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
728 if (ret_val)
729 return ret_val;
730
731 /* For BM PHY this bit is downshift enable */
732 if (phy->type != e1000_phy_bm)
733 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
734
735 /* Options:
736 * MDI/MDI-X = 0 (default)
737 * 0 - Auto for all speeds
738 * 1 - MDI mode
739 * 2 - MDI-X mode
740 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
741 */
742 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
743
744 switch (phy->mdix) {
745 case 1:
746 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
747 break;
748 case 2:
749 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
750 break;
751 case 3:
752 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
753 break;
754 case 0:
755 default:
756 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
757 break;
758 }
759
760 /* Options:
761 * disable_polarity_correction = 0 (default)
762 * Automatic Correction for Reversed Cable Polarity
763 * 0 - Disabled
764 * 1 - Enabled
765 */
766 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
767 if (phy->disable_polarity_correction)
768 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
769
770 /* Enable downshift on BM (disabled by default) */
771 if (phy->type == e1000_phy_bm) {
772 /* For 82574/82583, first disable then enable downshift */
773 if (phy->id == BME1000_E_PHY_ID_R2) {
774 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
775 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
776 phy_data);
777 if (ret_val)
778 return ret_val;
779 /* Commit the changes. */
780 ret_val = phy->ops.commit(hw);
781 if (ret_val) {
782 e_dbg("Error committing the PHY changes\n");
783 return ret_val;
784 }
785 }
786
787 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
788 }
789
790 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
791 if (ret_val)
792 return ret_val;
793
794 if ((phy->type == e1000_phy_m88) &&
795 (phy->revision < E1000_REVISION_4) &&
796 (phy->id != BME1000_E_PHY_ID_R2)) {
797 /* Force TX_CLK in the Extended PHY Specific Control Register
798 * to 25MHz clock.
799 */
800 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
801 if (ret_val)
802 return ret_val;
803
804 phy_data |= M88E1000_EPSCR_TX_CLK_25;
805
806 if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) {
807 /* 82573L PHY - set the downshift counter to 5x. */
808 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
809 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
810 } else {
811 /* Configure Master and Slave downshift values */
812 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
813 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
814 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
815 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
816 }
817 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
818 if (ret_val)
819 return ret_val;
820 }
821
822 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
823 /* Set PHY page 0, register 29 to 0x0003 */
824 ret_val = e1e_wphy(hw, 29, 0x0003);
825 if (ret_val)
826 return ret_val;
827
828 /* Set PHY page 0, register 30 to 0x0000 */
829 ret_val = e1e_wphy(hw, 30, 0x0000);
830 if (ret_val)
831 return ret_val;
832 }
833
834 /* Commit the changes. */
835 if (phy->ops.commit) {
836 ret_val = phy->ops.commit(hw);
837 if (ret_val) {
838 e_dbg("Error committing the PHY changes\n");
839 return ret_val;
840 }
841 }
842
843 if (phy->type == e1000_phy_82578) {
844 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
845 if (ret_val)
846 return ret_val;
847
848 /* 82578 PHY - set the downshift count to 1x. */
849 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
850 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
851 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
852 if (ret_val)
853 return ret_val;
854 }
855
856 return 0;
857 }
858
859 /**
860 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
861 * @hw: pointer to the HW structure
862 *
863 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
864 * igp PHY's.
865 **/
e1000e_copper_link_setup_igp(struct e1000_hw * hw)866 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
867 {
868 struct e1000_phy_info *phy = &hw->phy;
869 s32 ret_val;
870 u16 data;
871
872 ret_val = e1000_phy_hw_reset(hw);
873 if (ret_val) {
874 e_dbg("Error resetting the PHY.\n");
875 return ret_val;
876 }
877
878 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
879 * timeout issues when LFS is enabled.
880 */
881 msleep(100);
882
883 /* disable lplu d0 during driver init */
884 if (hw->phy.ops.set_d0_lplu_state) {
885 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
886 if (ret_val) {
887 e_dbg("Error Disabling LPLU D0\n");
888 return ret_val;
889 }
890 }
891 /* Configure mdi-mdix settings */
892 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
893 if (ret_val)
894 return ret_val;
895
896 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
897
898 switch (phy->mdix) {
899 case 1:
900 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
901 break;
902 case 2:
903 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
904 break;
905 case 0:
906 default:
907 data |= IGP01E1000_PSCR_AUTO_MDIX;
908 break;
909 }
910 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
911 if (ret_val)
912 return ret_val;
913
914 /* set auto-master slave resolution settings */
915 if (hw->mac.autoneg) {
916 /* when autonegotiation advertisement is only 1000Mbps then we
917 * should disable SmartSpeed and enable Auto MasterSlave
918 * resolution as hardware default.
919 */
920 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
921 /* Disable SmartSpeed */
922 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
923 &data);
924 if (ret_val)
925 return ret_val;
926
927 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
928 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
929 data);
930 if (ret_val)
931 return ret_val;
932
933 /* Set auto Master/Slave resolution process */
934 ret_val = e1e_rphy(hw, MII_CTRL1000, &data);
935 if (ret_val)
936 return ret_val;
937
938 data &= ~CTL1000_ENABLE_MASTER;
939 ret_val = e1e_wphy(hw, MII_CTRL1000, data);
940 if (ret_val)
941 return ret_val;
942 }
943
944 ret_val = e1000_set_master_slave_mode(hw);
945 }
946
947 return ret_val;
948 }
949
950 /**
951 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
952 * @hw: pointer to the HW structure
953 *
954 * Reads the MII auto-neg advertisement register and/or the 1000T control
955 * register and if the PHY is already setup for auto-negotiation, then
956 * return successful. Otherwise, setup advertisement and flow control to
957 * the appropriate values for the wanted auto-negotiation.
958 **/
e1000_phy_setup_autoneg(struct e1000_hw * hw)959 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
960 {
961 struct e1000_phy_info *phy = &hw->phy;
962 s32 ret_val;
963 u16 mii_autoneg_adv_reg;
964 u16 mii_1000t_ctrl_reg = 0;
965
966 phy->autoneg_advertised &= phy->autoneg_mask;
967
968 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
969 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg);
970 if (ret_val)
971 return ret_val;
972
973 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
974 /* Read the MII 1000Base-T Control Register (Address 9). */
975 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg);
976 if (ret_val)
977 return ret_val;
978 }
979
980 /* Need to parse both autoneg_advertised and fc and set up
981 * the appropriate PHY registers. First we will parse for
982 * autoneg_advertised software override. Since we can advertise
983 * a plethora of combinations, we need to check each bit
984 * individually.
985 */
986
987 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
988 * Advertisement Register (Address 4) and the 1000 mb speed bits in
989 * the 1000Base-T Control Register (Address 9).
990 */
991 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL |
992 ADVERTISE_100HALF |
993 ADVERTISE_10FULL | ADVERTISE_10HALF);
994 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
995
996 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
997
998 /* Do we want to advertise 10 Mb Half Duplex? */
999 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1000 e_dbg("Advertise 10mb Half duplex\n");
1001 mii_autoneg_adv_reg |= ADVERTISE_10HALF;
1002 }
1003
1004 /* Do we want to advertise 10 Mb Full Duplex? */
1005 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1006 e_dbg("Advertise 10mb Full duplex\n");
1007 mii_autoneg_adv_reg |= ADVERTISE_10FULL;
1008 }
1009
1010 /* Do we want to advertise 100 Mb Half Duplex? */
1011 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1012 e_dbg("Advertise 100mb Half duplex\n");
1013 mii_autoneg_adv_reg |= ADVERTISE_100HALF;
1014 }
1015
1016 /* Do we want to advertise 100 Mb Full Duplex? */
1017 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1018 e_dbg("Advertise 100mb Full duplex\n");
1019 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
1020 }
1021
1022 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1023 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1024 e_dbg("Advertise 1000mb Half duplex request denied!\n");
1025
1026 /* Do we want to advertise 1000 Mb Full Duplex? */
1027 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1028 e_dbg("Advertise 1000mb Full duplex\n");
1029 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
1030 }
1031
1032 /* Check for a software override of the flow control settings, and
1033 * setup the PHY advertisement registers accordingly. If
1034 * auto-negotiation is enabled, then software will have to set the
1035 * "PAUSE" bits to the correct value in the Auto-Negotiation
1036 * Advertisement Register (MII_ADVERTISE) and re-start auto-
1037 * negotiation.
1038 *
1039 * The possible values of the "fc" parameter are:
1040 * 0: Flow control is completely disabled
1041 * 1: Rx flow control is enabled (we can receive pause frames
1042 * but not send pause frames).
1043 * 2: Tx flow control is enabled (we can send pause frames
1044 * but we do not support receiving pause frames).
1045 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1046 * other: No software override. The flow control configuration
1047 * in the EEPROM is used.
1048 */
1049 switch (hw->fc.current_mode) {
1050 case e1000_fc_none:
1051 /* Flow control (Rx & Tx) is completely disabled by a
1052 * software over-ride.
1053 */
1054 mii_autoneg_adv_reg &=
1055 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1056 phy->autoneg_advertised &=
1057 ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1058 break;
1059 case e1000_fc_rx_pause:
1060 /* Rx Flow control is enabled, and Tx Flow control is
1061 * disabled, by a software over-ride.
1062 *
1063 * Since there really isn't a way to advertise that we are
1064 * capable of Rx Pause ONLY, we will advertise that we
1065 * support both symmetric and asymmetric Rx PAUSE. Later
1066 * (in e1000e_config_fc_after_link_up) we will disable the
1067 * hw's ability to send PAUSE frames.
1068 */
1069 mii_autoneg_adv_reg |=
1070 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1071 phy->autoneg_advertised |=
1072 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1073 break;
1074 case e1000_fc_tx_pause:
1075 /* Tx Flow control is enabled, and Rx Flow control is
1076 * disabled, by a software over-ride.
1077 */
1078 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM;
1079 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP;
1080 phy->autoneg_advertised |= ADVERTISED_Asym_Pause;
1081 phy->autoneg_advertised &= ~ADVERTISED_Pause;
1082 break;
1083 case e1000_fc_full:
1084 /* Flow control (both Rx and Tx) is enabled by a software
1085 * over-ride.
1086 */
1087 mii_autoneg_adv_reg |=
1088 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1089 phy->autoneg_advertised |=
1090 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1091 break;
1092 default:
1093 e_dbg("Flow control param set incorrectly\n");
1094 return -E1000_ERR_CONFIG;
1095 }
1096
1097 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1098 if (ret_val)
1099 return ret_val;
1100
1101 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1102
1103 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1104 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
1105
1106 return ret_val;
1107 }
1108
1109 /**
1110 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1111 * @hw: pointer to the HW structure
1112 *
1113 * Performs initial bounds checking on autoneg advertisement parameter, then
1114 * configure to advertise the full capability. Setup the PHY to autoneg
1115 * and restart the negotiation process between the link partner. If
1116 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1117 **/
e1000_copper_link_autoneg(struct e1000_hw * hw)1118 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1119 {
1120 struct e1000_phy_info *phy = &hw->phy;
1121 s32 ret_val;
1122 u16 phy_ctrl;
1123
1124 /* Perform some bounds checking on the autoneg advertisement
1125 * parameter.
1126 */
1127 phy->autoneg_advertised &= phy->autoneg_mask;
1128
1129 /* If autoneg_advertised is zero, we assume it was not defaulted
1130 * by the calling code so we set to advertise full capability.
1131 */
1132 if (!phy->autoneg_advertised)
1133 phy->autoneg_advertised = phy->autoneg_mask;
1134
1135 e_dbg("Reconfiguring auto-neg advertisement params\n");
1136 ret_val = e1000_phy_setup_autoneg(hw);
1137 if (ret_val) {
1138 e_dbg("Error Setting up Auto-Negotiation\n");
1139 return ret_val;
1140 }
1141 e_dbg("Restarting Auto-Neg\n");
1142
1143 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1144 * the Auto Neg Restart bit in the PHY control register.
1145 */
1146 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
1147 if (ret_val)
1148 return ret_val;
1149
1150 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1151 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
1152 if (ret_val)
1153 return ret_val;
1154
1155 /* Does the user want to wait for Auto-Neg to complete here, or
1156 * check at a later time (for example, callback routine).
1157 */
1158 if (phy->autoneg_wait_to_complete) {
1159 ret_val = e1000_wait_autoneg(hw);
1160 if (ret_val) {
1161 e_dbg("Error while waiting for autoneg to complete\n");
1162 return ret_val;
1163 }
1164 }
1165
1166 hw->mac.get_link_status = true;
1167
1168 return ret_val;
1169 }
1170
1171 /**
1172 * e1000e_setup_copper_link - Configure copper link settings
1173 * @hw: pointer to the HW structure
1174 *
1175 * Calls the appropriate function to configure the link for auto-neg or forced
1176 * speed and duplex. Then we check for link, once link is established calls
1177 * to configure collision distance and flow control are called. If link is
1178 * not established, we return -E1000_ERR_PHY (-2).
1179 **/
e1000e_setup_copper_link(struct e1000_hw * hw)1180 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1181 {
1182 s32 ret_val;
1183 bool link;
1184
1185 if (hw->mac.autoneg) {
1186 /* Setup autoneg and flow control advertisement and perform
1187 * autonegotiation.
1188 */
1189 ret_val = e1000_copper_link_autoneg(hw);
1190 if (ret_val)
1191 return ret_val;
1192 } else {
1193 /* PHY will be set to 10H, 10F, 100H or 100F
1194 * depending on user settings.
1195 */
1196 e_dbg("Forcing Speed and Duplex\n");
1197 ret_val = hw->phy.ops.force_speed_duplex(hw);
1198 if (ret_val) {
1199 e_dbg("Error Forcing Speed and Duplex\n");
1200 return ret_val;
1201 }
1202 }
1203
1204 /* Check link status. Wait up to 100 microseconds for link to become
1205 * valid.
1206 */
1207 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1208 &link);
1209 if (ret_val)
1210 return ret_val;
1211
1212 if (link) {
1213 e_dbg("Valid link established!!!\n");
1214 hw->mac.ops.config_collision_dist(hw);
1215 ret_val = e1000e_config_fc_after_link_up(hw);
1216 } else {
1217 e_dbg("Unable to establish link!!!\n");
1218 }
1219
1220 return ret_val;
1221 }
1222
1223 /**
1224 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1225 * @hw: pointer to the HW structure
1226 *
1227 * Calls the PHY setup function to force speed and duplex. Clears the
1228 * auto-crossover to force MDI manually. Waits for link and returns
1229 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1230 **/
e1000e_phy_force_speed_duplex_igp(struct e1000_hw * hw)1231 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1232 {
1233 struct e1000_phy_info *phy = &hw->phy;
1234 s32 ret_val;
1235 u16 phy_data;
1236 bool link;
1237
1238 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1239 if (ret_val)
1240 return ret_val;
1241
1242 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1243
1244 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1245 if (ret_val)
1246 return ret_val;
1247
1248 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1249 * forced whenever speed and duplex are forced.
1250 */
1251 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1252 if (ret_val)
1253 return ret_val;
1254
1255 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1256 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1257
1258 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1259 if (ret_val)
1260 return ret_val;
1261
1262 e_dbg("IGP PSCR: %X\n", phy_data);
1263
1264 udelay(1);
1265
1266 if (phy->autoneg_wait_to_complete) {
1267 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1268
1269 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1270 100000, &link);
1271 if (ret_val)
1272 return ret_val;
1273
1274 if (!link)
1275 e_dbg("Link taking longer than expected.\n");
1276
1277 /* Try once more */
1278 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1279 100000, &link);
1280 }
1281
1282 return ret_val;
1283 }
1284
1285 /**
1286 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1287 * @hw: pointer to the HW structure
1288 *
1289 * Calls the PHY setup function to force speed and duplex. Clears the
1290 * auto-crossover to force MDI manually. Resets the PHY to commit the
1291 * changes. If time expires while waiting for link up, we reset the DSP.
1292 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1293 * successful completion, else return corresponding error code.
1294 **/
e1000e_phy_force_speed_duplex_m88(struct e1000_hw * hw)1295 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1296 {
1297 struct e1000_phy_info *phy = &hw->phy;
1298 s32 ret_val;
1299 u16 phy_data;
1300 bool link;
1301
1302 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1303 * forced whenever speed and duplex are forced.
1304 */
1305 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1306 if (ret_val)
1307 return ret_val;
1308
1309 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1310 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1311 if (ret_val)
1312 return ret_val;
1313
1314 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1315
1316 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1317 if (ret_val)
1318 return ret_val;
1319
1320 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1321
1322 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1323 if (ret_val)
1324 return ret_val;
1325
1326 /* Reset the phy to commit changes. */
1327 if (hw->phy.ops.commit) {
1328 ret_val = hw->phy.ops.commit(hw);
1329 if (ret_val)
1330 return ret_val;
1331 }
1332
1333 if (phy->autoneg_wait_to_complete) {
1334 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1335
1336 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1337 100000, &link);
1338 if (ret_val)
1339 return ret_val;
1340
1341 if (!link) {
1342 if (hw->phy.type != e1000_phy_m88) {
1343 e_dbg("Link taking longer than expected.\n");
1344 } else {
1345 /* We didn't get link.
1346 * Reset the DSP and cross our fingers.
1347 */
1348 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1349 0x001d);
1350 if (ret_val)
1351 return ret_val;
1352 ret_val = e1000e_phy_reset_dsp(hw);
1353 if (ret_val)
1354 return ret_val;
1355 }
1356 }
1357
1358 /* Try once more */
1359 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1360 100000, &link);
1361 if (ret_val)
1362 return ret_val;
1363 }
1364
1365 if (hw->phy.type != e1000_phy_m88)
1366 return 0;
1367
1368 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1369 if (ret_val)
1370 return ret_val;
1371
1372 /* Resetting the phy means we need to re-force TX_CLK in the
1373 * Extended PHY Specific Control Register to 25MHz clock from
1374 * the reset value of 2.5MHz.
1375 */
1376 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1377 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1378 if (ret_val)
1379 return ret_val;
1380
1381 /* In addition, we must re-enable CRS on Tx for both half and full
1382 * duplex.
1383 */
1384 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1385 if (ret_val)
1386 return ret_val;
1387
1388 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1389 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1390
1391 return ret_val;
1392 }
1393
1394 /**
1395 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1396 * @hw: pointer to the HW structure
1397 *
1398 * Forces the speed and duplex settings of the PHY.
1399 * This is a function pointer entry point only called by
1400 * PHY setup routines.
1401 **/
e1000_phy_force_speed_duplex_ife(struct e1000_hw * hw)1402 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1403 {
1404 struct e1000_phy_info *phy = &hw->phy;
1405 s32 ret_val;
1406 u16 data;
1407 bool link;
1408
1409 ret_val = e1e_rphy(hw, MII_BMCR, &data);
1410 if (ret_val)
1411 return ret_val;
1412
1413 e1000e_phy_force_speed_duplex_setup(hw, &data);
1414
1415 ret_val = e1e_wphy(hw, MII_BMCR, data);
1416 if (ret_val)
1417 return ret_val;
1418
1419 /* Disable MDI-X support for 10/100 */
1420 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1421 if (ret_val)
1422 return ret_val;
1423
1424 data &= ~IFE_PMC_AUTO_MDIX;
1425 data &= ~IFE_PMC_FORCE_MDIX;
1426
1427 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1428 if (ret_val)
1429 return ret_val;
1430
1431 e_dbg("IFE PMC: %X\n", data);
1432
1433 udelay(1);
1434
1435 if (phy->autoneg_wait_to_complete) {
1436 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1437
1438 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1439 100000, &link);
1440 if (ret_val)
1441 return ret_val;
1442
1443 if (!link)
1444 e_dbg("Link taking longer than expected.\n");
1445
1446 /* Try once more */
1447 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1448 100000, &link);
1449 if (ret_val)
1450 return ret_val;
1451 }
1452
1453 return 0;
1454 }
1455
1456 /**
1457 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1458 * @hw: pointer to the HW structure
1459 * @phy_ctrl: pointer to current value of MII_BMCR
1460 *
1461 * Forces speed and duplex on the PHY by doing the following: disable flow
1462 * control, force speed/duplex on the MAC, disable auto speed detection,
1463 * disable auto-negotiation, configure duplex, configure speed, configure
1464 * the collision distance, write configuration to CTRL register. The
1465 * caller must write to the MII_BMCR register for these settings to
1466 * take affect.
1467 **/
e1000e_phy_force_speed_duplex_setup(struct e1000_hw * hw,u16 * phy_ctrl)1468 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1469 {
1470 struct e1000_mac_info *mac = &hw->mac;
1471 u32 ctrl;
1472
1473 /* Turn off flow control when forcing speed/duplex */
1474 hw->fc.current_mode = e1000_fc_none;
1475
1476 /* Force speed/duplex on the mac */
1477 ctrl = er32(CTRL);
1478 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1479 ctrl &= ~E1000_CTRL_SPD_SEL;
1480
1481 /* Disable Auto Speed Detection */
1482 ctrl &= ~E1000_CTRL_ASDE;
1483
1484 /* Disable autoneg on the phy */
1485 *phy_ctrl &= ~BMCR_ANENABLE;
1486
1487 /* Forcing Full or Half Duplex? */
1488 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1489 ctrl &= ~E1000_CTRL_FD;
1490 *phy_ctrl &= ~BMCR_FULLDPLX;
1491 e_dbg("Half Duplex\n");
1492 } else {
1493 ctrl |= E1000_CTRL_FD;
1494 *phy_ctrl |= BMCR_FULLDPLX;
1495 e_dbg("Full Duplex\n");
1496 }
1497
1498 /* Forcing 10mb or 100mb? */
1499 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1500 ctrl |= E1000_CTRL_SPD_100;
1501 *phy_ctrl |= BMCR_SPEED100;
1502 *phy_ctrl &= ~BMCR_SPEED1000;
1503 e_dbg("Forcing 100mb\n");
1504 } else {
1505 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1506 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
1507 e_dbg("Forcing 10mb\n");
1508 }
1509
1510 hw->mac.ops.config_collision_dist(hw);
1511
1512 ew32(CTRL, ctrl);
1513 }
1514
1515 /**
1516 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1517 * @hw: pointer to the HW structure
1518 * @active: boolean used to enable/disable lplu
1519 *
1520 * Success returns 0, Failure returns 1
1521 *
1522 * The low power link up (lplu) state is set to the power management level D3
1523 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1524 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1525 * is used during Dx states where the power conservation is most important.
1526 * During driver activity, SmartSpeed should be enabled so performance is
1527 * maintained.
1528 **/
e1000e_set_d3_lplu_state(struct e1000_hw * hw,bool active)1529 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1530 {
1531 struct e1000_phy_info *phy = &hw->phy;
1532 s32 ret_val;
1533 u16 data;
1534
1535 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1536 if (ret_val)
1537 return ret_val;
1538
1539 if (!active) {
1540 data &= ~IGP02E1000_PM_D3_LPLU;
1541 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1542 if (ret_val)
1543 return ret_val;
1544 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1545 * during Dx states where the power conservation is most
1546 * important. During driver activity we should enable
1547 * SmartSpeed, so performance is maintained.
1548 */
1549 if (phy->smart_speed == e1000_smart_speed_on) {
1550 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1551 &data);
1552 if (ret_val)
1553 return ret_val;
1554
1555 data |= IGP01E1000_PSCFR_SMART_SPEED;
1556 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1557 data);
1558 if (ret_val)
1559 return ret_val;
1560 } else if (phy->smart_speed == e1000_smart_speed_off) {
1561 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1562 &data);
1563 if (ret_val)
1564 return ret_val;
1565
1566 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1567 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1568 data);
1569 if (ret_val)
1570 return ret_val;
1571 }
1572 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1573 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1574 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1575 data |= IGP02E1000_PM_D3_LPLU;
1576 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1577 if (ret_val)
1578 return ret_val;
1579
1580 /* When LPLU is enabled, we should disable SmartSpeed */
1581 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1582 if (ret_val)
1583 return ret_val;
1584
1585 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1586 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1587 }
1588
1589 return ret_val;
1590 }
1591
1592 /**
1593 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1594 * @hw: pointer to the HW structure
1595 *
1596 * Success returns 0, Failure returns 1
1597 *
1598 * A downshift is detected by querying the PHY link health.
1599 **/
e1000e_check_downshift(struct e1000_hw * hw)1600 s32 e1000e_check_downshift(struct e1000_hw *hw)
1601 {
1602 struct e1000_phy_info *phy = &hw->phy;
1603 s32 ret_val;
1604 u16 phy_data, offset, mask;
1605
1606 switch (phy->type) {
1607 case e1000_phy_m88:
1608 case e1000_phy_gg82563:
1609 case e1000_phy_bm:
1610 case e1000_phy_82578:
1611 offset = M88E1000_PHY_SPEC_STATUS;
1612 mask = M88E1000_PSSR_DOWNSHIFT;
1613 break;
1614 case e1000_phy_igp_2:
1615 case e1000_phy_igp_3:
1616 offset = IGP01E1000_PHY_LINK_HEALTH;
1617 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1618 break;
1619 default:
1620 /* speed downshift not supported */
1621 phy->speed_downgraded = false;
1622 return 0;
1623 }
1624
1625 ret_val = e1e_rphy(hw, offset, &phy_data);
1626
1627 if (!ret_val)
1628 phy->speed_downgraded = !!(phy_data & mask);
1629
1630 return ret_val;
1631 }
1632
1633 /**
1634 * e1000_check_polarity_m88 - Checks the polarity.
1635 * @hw: pointer to the HW structure
1636 *
1637 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1638 *
1639 * Polarity is determined based on the PHY specific status register.
1640 **/
e1000_check_polarity_m88(struct e1000_hw * hw)1641 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1642 {
1643 struct e1000_phy_info *phy = &hw->phy;
1644 s32 ret_val;
1645 u16 data;
1646
1647 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1648
1649 if (!ret_val)
1650 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
1651 ? e1000_rev_polarity_reversed
1652 : e1000_rev_polarity_normal);
1653
1654 return ret_val;
1655 }
1656
1657 /**
1658 * e1000_check_polarity_igp - Checks the polarity.
1659 * @hw: pointer to the HW structure
1660 *
1661 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1662 *
1663 * Polarity is determined based on the PHY port status register, and the
1664 * current speed (since there is no polarity at 100Mbps).
1665 **/
e1000_check_polarity_igp(struct e1000_hw * hw)1666 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1667 {
1668 struct e1000_phy_info *phy = &hw->phy;
1669 s32 ret_val;
1670 u16 data, offset, mask;
1671
1672 /* Polarity is determined based on the speed of
1673 * our connection.
1674 */
1675 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1676 if (ret_val)
1677 return ret_val;
1678
1679 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1680 IGP01E1000_PSSR_SPEED_1000MBPS) {
1681 offset = IGP01E1000_PHY_PCS_INIT_REG;
1682 mask = IGP01E1000_PHY_POLARITY_MASK;
1683 } else {
1684 /* This really only applies to 10Mbps since
1685 * there is no polarity for 100Mbps (always 0).
1686 */
1687 offset = IGP01E1000_PHY_PORT_STATUS;
1688 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1689 }
1690
1691 ret_val = e1e_rphy(hw, offset, &data);
1692
1693 if (!ret_val)
1694 phy->cable_polarity = ((data & mask)
1695 ? e1000_rev_polarity_reversed
1696 : e1000_rev_polarity_normal);
1697
1698 return ret_val;
1699 }
1700
1701 /**
1702 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1703 * @hw: pointer to the HW structure
1704 *
1705 * Polarity is determined on the polarity reversal feature being enabled.
1706 **/
e1000_check_polarity_ife(struct e1000_hw * hw)1707 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1708 {
1709 struct e1000_phy_info *phy = &hw->phy;
1710 s32 ret_val;
1711 u16 phy_data, offset, mask;
1712
1713 /* Polarity is determined based on the reversal feature being enabled.
1714 */
1715 if (phy->polarity_correction) {
1716 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1717 mask = IFE_PESC_POLARITY_REVERSED;
1718 } else {
1719 offset = IFE_PHY_SPECIAL_CONTROL;
1720 mask = IFE_PSC_FORCE_POLARITY;
1721 }
1722
1723 ret_val = e1e_rphy(hw, offset, &phy_data);
1724
1725 if (!ret_val)
1726 phy->cable_polarity = ((phy_data & mask)
1727 ? e1000_rev_polarity_reversed
1728 : e1000_rev_polarity_normal);
1729
1730 return ret_val;
1731 }
1732
1733 /**
1734 * e1000_wait_autoneg - Wait for auto-neg completion
1735 * @hw: pointer to the HW structure
1736 *
1737 * Waits for auto-negotiation to complete or for the auto-negotiation time
1738 * limit to expire, which ever happens first.
1739 **/
e1000_wait_autoneg(struct e1000_hw * hw)1740 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1741 {
1742 s32 ret_val = 0;
1743 u16 i, phy_status;
1744
1745 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1746 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1747 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1748 if (ret_val)
1749 break;
1750 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1751 if (ret_val)
1752 break;
1753 if (phy_status & BMSR_ANEGCOMPLETE)
1754 break;
1755 msleep(100);
1756 }
1757
1758 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1759 * has completed.
1760 */
1761 return ret_val;
1762 }
1763
1764 /**
1765 * e1000e_phy_has_link_generic - Polls PHY for link
1766 * @hw: pointer to the HW structure
1767 * @iterations: number of times to poll for link
1768 * @usec_interval: delay between polling attempts
1769 * @success: pointer to whether polling was successful or not
1770 *
1771 * Polls the PHY status register for link, 'iterations' number of times.
1772 **/
e1000e_phy_has_link_generic(struct e1000_hw * hw,u32 iterations,u32 usec_interval,bool * success)1773 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1774 u32 usec_interval, bool *success)
1775 {
1776 s32 ret_val = 0;
1777 u16 i, phy_status;
1778
1779 *success = false;
1780 for (i = 0; i < iterations; i++) {
1781 /* Some PHYs require the MII_BMSR register to be read
1782 * twice due to the link bit being sticky. No harm doing
1783 * it across the board.
1784 */
1785 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1786 if (ret_val) {
1787 /* If the first read fails, another entity may have
1788 * ownership of the resources, wait and try again to
1789 * see if they have relinquished the resources yet.
1790 */
1791 if (usec_interval >= 1000)
1792 msleep(usec_interval / 1000);
1793 else
1794 udelay(usec_interval);
1795 }
1796 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1797 if (ret_val)
1798 break;
1799 if (phy_status & BMSR_LSTATUS) {
1800 *success = true;
1801 break;
1802 }
1803 if (usec_interval >= 1000)
1804 msleep(usec_interval / 1000);
1805 else
1806 udelay(usec_interval);
1807 }
1808
1809 return ret_val;
1810 }
1811
1812 /**
1813 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1814 * @hw: pointer to the HW structure
1815 *
1816 * Reads the PHY specific status register to retrieve the cable length
1817 * information. The cable length is determined by averaging the minimum and
1818 * maximum values to get the "average" cable length. The m88 PHY has four
1819 * possible cable length values, which are:
1820 * Register Value Cable Length
1821 * 0 < 50 meters
1822 * 1 50 - 80 meters
1823 * 2 80 - 110 meters
1824 * 3 110 - 140 meters
1825 * 4 > 140 meters
1826 **/
e1000e_get_cable_length_m88(struct e1000_hw * hw)1827 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1828 {
1829 struct e1000_phy_info *phy = &hw->phy;
1830 s32 ret_val;
1831 u16 phy_data, index;
1832
1833 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1834 if (ret_val)
1835 return ret_val;
1836
1837 index = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data);
1838
1839 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1840 return -E1000_ERR_PHY;
1841
1842 phy->min_cable_length = e1000_m88_cable_length_table[index];
1843 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1844
1845 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1846
1847 return 0;
1848 }
1849
1850 /**
1851 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1852 * @hw: pointer to the HW structure
1853 *
1854 * The automatic gain control (agc) normalizes the amplitude of the
1855 * received signal, adjusting for the attenuation produced by the
1856 * cable. By reading the AGC registers, which represent the
1857 * combination of coarse and fine gain value, the value can be put
1858 * into a lookup table to obtain the approximate cable length
1859 * for each channel.
1860 **/
e1000e_get_cable_length_igp_2(struct e1000_hw * hw)1861 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1862 {
1863 struct e1000_phy_info *phy = &hw->phy;
1864 s32 ret_val;
1865 u16 phy_data, i, agc_value = 0;
1866 u16 cur_agc_index, max_agc_index = 0;
1867 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1868 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1869 IGP02E1000_PHY_AGC_A,
1870 IGP02E1000_PHY_AGC_B,
1871 IGP02E1000_PHY_AGC_C,
1872 IGP02E1000_PHY_AGC_D
1873 };
1874
1875 /* Read the AGC registers for all channels */
1876 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1877 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1878 if (ret_val)
1879 return ret_val;
1880
1881 /* Getting bits 15:9, which represent the combination of
1882 * coarse and fine gain values. The result is a number
1883 * that can be put into the lookup table to obtain the
1884 * approximate cable length.
1885 */
1886 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1887 IGP02E1000_AGC_LENGTH_MASK);
1888
1889 /* Array index bound check. */
1890 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1891 (cur_agc_index == 0))
1892 return -E1000_ERR_PHY;
1893
1894 /* Remove min & max AGC values from calculation. */
1895 if (e1000_igp_2_cable_length_table[min_agc_index] >
1896 e1000_igp_2_cable_length_table[cur_agc_index])
1897 min_agc_index = cur_agc_index;
1898 if (e1000_igp_2_cable_length_table[max_agc_index] <
1899 e1000_igp_2_cable_length_table[cur_agc_index])
1900 max_agc_index = cur_agc_index;
1901
1902 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1903 }
1904
1905 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1906 e1000_igp_2_cable_length_table[max_agc_index]);
1907 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1908
1909 /* Calculate cable length with the error range of +/- 10 meters. */
1910 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1911 (agc_value - IGP02E1000_AGC_RANGE) : 0);
1912 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1913
1914 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1915
1916 return 0;
1917 }
1918
1919 /**
1920 * e1000e_get_phy_info_m88 - Retrieve PHY information
1921 * @hw: pointer to the HW structure
1922 *
1923 * Valid for only copper links. Read the PHY status register (sticky read)
1924 * to verify that link is up. Read the PHY special control register to
1925 * determine the polarity and 10base-T extended distance. Read the PHY
1926 * special status register to determine MDI/MDIx and current speed. If
1927 * speed is 1000, then determine cable length, local and remote receiver.
1928 **/
e1000e_get_phy_info_m88(struct e1000_hw * hw)1929 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1930 {
1931 struct e1000_phy_info *phy = &hw->phy;
1932 s32 ret_val;
1933 u16 phy_data;
1934 bool link;
1935
1936 if (phy->media_type != e1000_media_type_copper) {
1937 e_dbg("Phy info is only valid for copper media\n");
1938 return -E1000_ERR_CONFIG;
1939 }
1940
1941 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1942 if (ret_val)
1943 return ret_val;
1944
1945 if (!link) {
1946 e_dbg("Phy info is only valid if link is up\n");
1947 return -E1000_ERR_CONFIG;
1948 }
1949
1950 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1951 if (ret_val)
1952 return ret_val;
1953
1954 phy->polarity_correction = !!(phy_data &
1955 M88E1000_PSCR_POLARITY_REVERSAL);
1956
1957 ret_val = e1000_check_polarity_m88(hw);
1958 if (ret_val)
1959 return ret_val;
1960
1961 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1962 if (ret_val)
1963 return ret_val;
1964
1965 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1966
1967 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1968 ret_val = hw->phy.ops.get_cable_length(hw);
1969 if (ret_val)
1970 return ret_val;
1971
1972 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data);
1973 if (ret_val)
1974 return ret_val;
1975
1976 phy->local_rx = (phy_data & LPA_1000LOCALRXOK)
1977 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1978
1979 phy->remote_rx = (phy_data & LPA_1000REMRXOK)
1980 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1981 } else {
1982 /* Set values to "undefined" */
1983 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1984 phy->local_rx = e1000_1000t_rx_status_undefined;
1985 phy->remote_rx = e1000_1000t_rx_status_undefined;
1986 }
1987
1988 return ret_val;
1989 }
1990
1991 /**
1992 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1993 * @hw: pointer to the HW structure
1994 *
1995 * Read PHY status to determine if link is up. If link is up, then
1996 * set/determine 10base-T extended distance and polarity correction. Read
1997 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1998 * determine on the cable length, local and remote receiver.
1999 **/
e1000e_get_phy_info_igp(struct e1000_hw * hw)2000 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
2001 {
2002 struct e1000_phy_info *phy = &hw->phy;
2003 s32 ret_val;
2004 u16 data;
2005 bool link;
2006
2007 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2008 if (ret_val)
2009 return ret_val;
2010
2011 if (!link) {
2012 e_dbg("Phy info is only valid if link is up\n");
2013 return -E1000_ERR_CONFIG;
2014 }
2015
2016 phy->polarity_correction = true;
2017
2018 ret_val = e1000_check_polarity_igp(hw);
2019 if (ret_val)
2020 return ret_val;
2021
2022 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2023 if (ret_val)
2024 return ret_val;
2025
2026 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2027
2028 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2029 IGP01E1000_PSSR_SPEED_1000MBPS) {
2030 ret_val = phy->ops.get_cable_length(hw);
2031 if (ret_val)
2032 return ret_val;
2033
2034 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
2035 if (ret_val)
2036 return ret_val;
2037
2038 phy->local_rx = (data & LPA_1000LOCALRXOK)
2039 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2040
2041 phy->remote_rx = (data & LPA_1000REMRXOK)
2042 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2043 } else {
2044 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2045 phy->local_rx = e1000_1000t_rx_status_undefined;
2046 phy->remote_rx = e1000_1000t_rx_status_undefined;
2047 }
2048
2049 return ret_val;
2050 }
2051
2052 /**
2053 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2054 * @hw: pointer to the HW structure
2055 *
2056 * Populates "phy" structure with various feature states.
2057 **/
e1000_get_phy_info_ife(struct e1000_hw * hw)2058 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2059 {
2060 struct e1000_phy_info *phy = &hw->phy;
2061 s32 ret_val;
2062 u16 data;
2063 bool link;
2064
2065 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2066 if (ret_val)
2067 return ret_val;
2068
2069 if (!link) {
2070 e_dbg("Phy info is only valid if link is up\n");
2071 return -E1000_ERR_CONFIG;
2072 }
2073
2074 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2075 if (ret_val)
2076 return ret_val;
2077 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2078
2079 if (phy->polarity_correction) {
2080 ret_val = e1000_check_polarity_ife(hw);
2081 if (ret_val)
2082 return ret_val;
2083 } else {
2084 /* Polarity is forced */
2085 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2086 ? e1000_rev_polarity_reversed
2087 : e1000_rev_polarity_normal);
2088 }
2089
2090 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2091 if (ret_val)
2092 return ret_val;
2093
2094 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2095
2096 /* The following parameters are undefined for 10/100 operation. */
2097 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2098 phy->local_rx = e1000_1000t_rx_status_undefined;
2099 phy->remote_rx = e1000_1000t_rx_status_undefined;
2100
2101 return 0;
2102 }
2103
2104 /**
2105 * e1000e_phy_sw_reset - PHY software reset
2106 * @hw: pointer to the HW structure
2107 *
2108 * Does a software reset of the PHY by reading the PHY control register and
2109 * setting/write the control register reset bit to the PHY.
2110 **/
e1000e_phy_sw_reset(struct e1000_hw * hw)2111 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2112 {
2113 s32 ret_val;
2114 u16 phy_ctrl;
2115
2116 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
2117 if (ret_val)
2118 return ret_val;
2119
2120 phy_ctrl |= BMCR_RESET;
2121 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
2122 if (ret_val)
2123 return ret_val;
2124
2125 udelay(1);
2126
2127 return ret_val;
2128 }
2129
2130 /**
2131 * e1000e_phy_hw_reset_generic - PHY hardware reset
2132 * @hw: pointer to the HW structure
2133 *
2134 * Verify the reset block is not blocking us from resetting. Acquire
2135 * semaphore (if necessary) and read/set/write the device control reset
2136 * bit in the PHY. Wait the appropriate delay time for the device to
2137 * reset and release the semaphore (if necessary).
2138 **/
e1000e_phy_hw_reset_generic(struct e1000_hw * hw)2139 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2140 {
2141 struct e1000_phy_info *phy = &hw->phy;
2142 s32 ret_val;
2143 u32 ctrl;
2144
2145 if (phy->ops.check_reset_block) {
2146 ret_val = phy->ops.check_reset_block(hw);
2147 if (ret_val)
2148 return 0;
2149 }
2150
2151 ret_val = phy->ops.acquire(hw);
2152 if (ret_val)
2153 return ret_val;
2154
2155 ctrl = er32(CTRL);
2156 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2157 e1e_flush();
2158
2159 udelay(phy->reset_delay_us);
2160
2161 ew32(CTRL, ctrl);
2162 e1e_flush();
2163
2164 usleep_range(150, 300);
2165
2166 phy->ops.release(hw);
2167
2168 return phy->ops.get_cfg_done(hw);
2169 }
2170
2171 /**
2172 * e1000e_get_cfg_done_generic - Generic configuration done
2173 * @hw: pointer to the HW structure
2174 *
2175 * Generic function to wait 10 milli-seconds for configuration to complete
2176 * and return success.
2177 **/
e1000e_get_cfg_done_generic(struct e1000_hw __always_unused * hw)2178 s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw)
2179 {
2180 mdelay(10);
2181
2182 return 0;
2183 }
2184
2185 /**
2186 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2187 * @hw: pointer to the HW structure
2188 *
2189 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2190 **/
e1000e_phy_init_script_igp3(struct e1000_hw * hw)2191 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2192 {
2193 e_dbg("Running IGP 3 PHY init script\n");
2194
2195 /* PHY init IGP 3 */
2196 /* Enable rise/fall, 10-mode work in class-A */
2197 e1e_wphy(hw, 0x2F5B, 0x9018);
2198 /* Remove all caps from Replica path filter */
2199 e1e_wphy(hw, 0x2F52, 0x0000);
2200 /* Bias trimming for ADC, AFE and Driver (Default) */
2201 e1e_wphy(hw, 0x2FB1, 0x8B24);
2202 /* Increase Hybrid poly bias */
2203 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2204 /* Add 4% to Tx amplitude in Gig mode */
2205 e1e_wphy(hw, 0x2010, 0x10B0);
2206 /* Disable trimming (TTT) */
2207 e1e_wphy(hw, 0x2011, 0x0000);
2208 /* Poly DC correction to 94.6% + 2% for all channels */
2209 e1e_wphy(hw, 0x20DD, 0x249A);
2210 /* ABS DC correction to 95.9% */
2211 e1e_wphy(hw, 0x20DE, 0x00D3);
2212 /* BG temp curve trim */
2213 e1e_wphy(hw, 0x28B4, 0x04CE);
2214 /* Increasing ADC OPAMP stage 1 currents to max */
2215 e1e_wphy(hw, 0x2F70, 0x29E4);
2216 /* Force 1000 ( required for enabling PHY regs configuration) */
2217 e1e_wphy(hw, 0x0000, 0x0140);
2218 /* Set upd_freq to 6 */
2219 e1e_wphy(hw, 0x1F30, 0x1606);
2220 /* Disable NPDFE */
2221 e1e_wphy(hw, 0x1F31, 0xB814);
2222 /* Disable adaptive fixed FFE (Default) */
2223 e1e_wphy(hw, 0x1F35, 0x002A);
2224 /* Enable FFE hysteresis */
2225 e1e_wphy(hw, 0x1F3E, 0x0067);
2226 /* Fixed FFE for short cable lengths */
2227 e1e_wphy(hw, 0x1F54, 0x0065);
2228 /* Fixed FFE for medium cable lengths */
2229 e1e_wphy(hw, 0x1F55, 0x002A);
2230 /* Fixed FFE for long cable lengths */
2231 e1e_wphy(hw, 0x1F56, 0x002A);
2232 /* Enable Adaptive Clip Threshold */
2233 e1e_wphy(hw, 0x1F72, 0x3FB0);
2234 /* AHT reset limit to 1 */
2235 e1e_wphy(hw, 0x1F76, 0xC0FF);
2236 /* Set AHT master delay to 127 msec */
2237 e1e_wphy(hw, 0x1F77, 0x1DEC);
2238 /* Set scan bits for AHT */
2239 e1e_wphy(hw, 0x1F78, 0xF9EF);
2240 /* Set AHT Preset bits */
2241 e1e_wphy(hw, 0x1F79, 0x0210);
2242 /* Change integ_factor of channel A to 3 */
2243 e1e_wphy(hw, 0x1895, 0x0003);
2244 /* Change prop_factor of channels BCD to 8 */
2245 e1e_wphy(hw, 0x1796, 0x0008);
2246 /* Change cg_icount + enable integbp for channels BCD */
2247 e1e_wphy(hw, 0x1798, 0xD008);
2248 /* Change cg_icount + enable integbp + change prop_factor_master
2249 * to 8 for channel A
2250 */
2251 e1e_wphy(hw, 0x1898, 0xD918);
2252 /* Disable AHT in Slave mode on channel A */
2253 e1e_wphy(hw, 0x187A, 0x0800);
2254 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2255 * Enable SPD+B2B
2256 */
2257 e1e_wphy(hw, 0x0019, 0x008D);
2258 /* Enable restart AN on an1000_dis change */
2259 e1e_wphy(hw, 0x001B, 0x2080);
2260 /* Enable wh_fifo read clock in 10/100 modes */
2261 e1e_wphy(hw, 0x0014, 0x0045);
2262 /* Restart AN, Speed selection is 1000 */
2263 e1e_wphy(hw, 0x0000, 0x1340);
2264
2265 return 0;
2266 }
2267
2268 /**
2269 * e1000e_get_phy_type_from_id - Get PHY type from id
2270 * @phy_id: phy_id read from the phy
2271 *
2272 * Returns the phy type from the id.
2273 **/
e1000e_get_phy_type_from_id(u32 phy_id)2274 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2275 {
2276 enum e1000_phy_type phy_type = e1000_phy_unknown;
2277
2278 switch (phy_id) {
2279 case M88E1000_I_PHY_ID:
2280 case M88E1000_E_PHY_ID:
2281 case M88E1111_I_PHY_ID:
2282 case M88E1011_I_PHY_ID:
2283 phy_type = e1000_phy_m88;
2284 break;
2285 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2286 phy_type = e1000_phy_igp_2;
2287 break;
2288 case GG82563_E_PHY_ID:
2289 phy_type = e1000_phy_gg82563;
2290 break;
2291 case IGP03E1000_E_PHY_ID:
2292 phy_type = e1000_phy_igp_3;
2293 break;
2294 case IFE_E_PHY_ID:
2295 case IFE_PLUS_E_PHY_ID:
2296 case IFE_C_E_PHY_ID:
2297 phy_type = e1000_phy_ife;
2298 break;
2299 case BME1000_E_PHY_ID:
2300 case BME1000_E_PHY_ID_R2:
2301 phy_type = e1000_phy_bm;
2302 break;
2303 case I82578_E_PHY_ID:
2304 phy_type = e1000_phy_82578;
2305 break;
2306 case I82577_E_PHY_ID:
2307 phy_type = e1000_phy_82577;
2308 break;
2309 case I82579_E_PHY_ID:
2310 phy_type = e1000_phy_82579;
2311 break;
2312 case I217_E_PHY_ID:
2313 phy_type = e1000_phy_i217;
2314 break;
2315 default:
2316 phy_type = e1000_phy_unknown;
2317 break;
2318 }
2319 return phy_type;
2320 }
2321
2322 /**
2323 * e1000e_determine_phy_address - Determines PHY address.
2324 * @hw: pointer to the HW structure
2325 *
2326 * This uses a trial and error method to loop through possible PHY
2327 * addresses. It tests each by reading the PHY ID registers and
2328 * checking for a match.
2329 **/
e1000e_determine_phy_address(struct e1000_hw * hw)2330 s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2331 {
2332 u32 phy_addr = 0;
2333 u32 i;
2334 enum e1000_phy_type phy_type = e1000_phy_unknown;
2335
2336 hw->phy.id = phy_type;
2337
2338 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2339 hw->phy.addr = phy_addr;
2340 i = 0;
2341
2342 do {
2343 e1000e_get_phy_id(hw);
2344 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2345
2346 /* If phy_type is valid, break - we found our
2347 * PHY address
2348 */
2349 if (phy_type != e1000_phy_unknown)
2350 return 0;
2351
2352 usleep_range(1000, 2000);
2353 i++;
2354 } while (i < 10);
2355 }
2356
2357 return -E1000_ERR_PHY_TYPE;
2358 }
2359
2360 /**
2361 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2362 * @page: page to access
2363 * @reg: register to check
2364 *
2365 * Returns the phy address for the page requested.
2366 **/
e1000_get_phy_addr_for_bm_page(u32 page,u32 reg)2367 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2368 {
2369 u32 phy_addr = 2;
2370
2371 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2372 phy_addr = 1;
2373
2374 return phy_addr;
2375 }
2376
2377 /**
2378 * e1000e_write_phy_reg_bm - Write BM PHY register
2379 * @hw: pointer to the HW structure
2380 * @offset: register offset to write to
2381 * @data: data to write at register offset
2382 *
2383 * Acquires semaphore, if necessary, then writes the data to PHY register
2384 * at the offset. Release any acquired semaphores before exiting.
2385 **/
e1000e_write_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 data)2386 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2387 {
2388 s32 ret_val;
2389 u32 page = offset >> IGP_PAGE_SHIFT;
2390
2391 ret_val = hw->phy.ops.acquire(hw);
2392 if (ret_val)
2393 return ret_val;
2394
2395 /* Page 800 works differently than the rest so it has its own func */
2396 if (page == BM_WUC_PAGE) {
2397 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2398 false, false);
2399 goto release;
2400 }
2401
2402 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2403
2404 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2405 u32 page_shift, page_select;
2406
2407 /* Page select is register 31 for phy address 1 and 22 for
2408 * phy address 2 and 3. Page select is shifted only for
2409 * phy address 1.
2410 */
2411 if (hw->phy.addr == 1) {
2412 page_shift = IGP_PAGE_SHIFT;
2413 page_select = IGP01E1000_PHY_PAGE_SELECT;
2414 } else {
2415 page_shift = 0;
2416 page_select = BM_PHY_PAGE_SELECT;
2417 }
2418
2419 /* Page is shifted left, PHY expects (page x 32) */
2420 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2421 (page << page_shift));
2422 if (ret_val)
2423 goto release;
2424 }
2425
2426 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2427 data);
2428
2429 release:
2430 hw->phy.ops.release(hw);
2431 return ret_val;
2432 }
2433
2434 /**
2435 * e1000e_read_phy_reg_bm - Read BM PHY register
2436 * @hw: pointer to the HW structure
2437 * @offset: register offset to be read
2438 * @data: pointer to the read data
2439 *
2440 * Acquires semaphore, if necessary, then reads the PHY register at offset
2441 * and storing the retrieved information in data. Release any acquired
2442 * semaphores before exiting.
2443 **/
e1000e_read_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data)2444 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2445 {
2446 s32 ret_val;
2447 u32 page = offset >> IGP_PAGE_SHIFT;
2448
2449 ret_val = hw->phy.ops.acquire(hw);
2450 if (ret_val)
2451 return ret_val;
2452
2453 /* Page 800 works differently than the rest so it has its own func */
2454 if (page == BM_WUC_PAGE) {
2455 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2456 true, false);
2457 goto release;
2458 }
2459
2460 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2461
2462 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2463 u32 page_shift, page_select;
2464
2465 /* Page select is register 31 for phy address 1 and 22 for
2466 * phy address 2 and 3. Page select is shifted only for
2467 * phy address 1.
2468 */
2469 if (hw->phy.addr == 1) {
2470 page_shift = IGP_PAGE_SHIFT;
2471 page_select = IGP01E1000_PHY_PAGE_SELECT;
2472 } else {
2473 page_shift = 0;
2474 page_select = BM_PHY_PAGE_SELECT;
2475 }
2476
2477 /* Page is shifted left, PHY expects (page x 32) */
2478 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2479 (page << page_shift));
2480 if (ret_val)
2481 goto release;
2482 }
2483
2484 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2485 data);
2486 release:
2487 hw->phy.ops.release(hw);
2488 return ret_val;
2489 }
2490
2491 /**
2492 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2493 * @hw: pointer to the HW structure
2494 * @offset: register offset to be read
2495 * @data: pointer to the read data
2496 *
2497 * Acquires semaphore, if necessary, then reads the PHY register at offset
2498 * and storing the retrieved information in data. Release any acquired
2499 * semaphores before exiting.
2500 **/
e1000e_read_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 * data)2501 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2502 {
2503 s32 ret_val;
2504 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2505
2506 ret_val = hw->phy.ops.acquire(hw);
2507 if (ret_val)
2508 return ret_val;
2509
2510 /* Page 800 works differently than the rest so it has its own func */
2511 if (page == BM_WUC_PAGE) {
2512 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2513 true, false);
2514 goto release;
2515 }
2516
2517 hw->phy.addr = 1;
2518
2519 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2520 /* Page is shifted left, PHY expects (page x 32) */
2521 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2522 page);
2523
2524 if (ret_val)
2525 goto release;
2526 }
2527
2528 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2529 data);
2530 release:
2531 hw->phy.ops.release(hw);
2532 return ret_val;
2533 }
2534
2535 /**
2536 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2537 * @hw: pointer to the HW structure
2538 * @offset: register offset to write to
2539 * @data: data to write at register offset
2540 *
2541 * Acquires semaphore, if necessary, then writes the data to PHY register
2542 * at the offset. Release any acquired semaphores before exiting.
2543 **/
e1000e_write_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 data)2544 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2545 {
2546 s32 ret_val;
2547 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2548
2549 ret_val = hw->phy.ops.acquire(hw);
2550 if (ret_val)
2551 return ret_val;
2552
2553 /* Page 800 works differently than the rest so it has its own func */
2554 if (page == BM_WUC_PAGE) {
2555 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2556 false, false);
2557 goto release;
2558 }
2559
2560 hw->phy.addr = 1;
2561
2562 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2563 /* Page is shifted left, PHY expects (page x 32) */
2564 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2565 page);
2566
2567 if (ret_val)
2568 goto release;
2569 }
2570
2571 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2572 data);
2573
2574 release:
2575 hw->phy.ops.release(hw);
2576 return ret_val;
2577 }
2578
2579 /**
2580 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2581 * @hw: pointer to the HW structure
2582 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2583 *
2584 * Assumes semaphore already acquired and phy_reg points to a valid memory
2585 * address to store contents of the BM_WUC_ENABLE_REG register.
2586 **/
e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)2587 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2588 {
2589 s32 ret_val;
2590 u16 temp;
2591
2592 /* All page select, port ctrl and wakeup registers use phy address 1 */
2593 hw->phy.addr = 1;
2594
2595 /* Select Port Control Registers page */
2596 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2597 if (ret_val) {
2598 e_dbg("Could not set Port Control page\n");
2599 return ret_val;
2600 }
2601
2602 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2603 if (ret_val) {
2604 e_dbg("Could not read PHY register %d.%d\n",
2605 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2606 return ret_val;
2607 }
2608
2609 /* Enable both PHY wakeup mode and Wakeup register page writes.
2610 * Prevent a power state change by disabling ME and Host PHY wakeup.
2611 */
2612 temp = *phy_reg;
2613 temp |= BM_WUC_ENABLE_BIT;
2614 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2615
2616 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2617 if (ret_val) {
2618 e_dbg("Could not write PHY register %d.%d\n",
2619 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2620 return ret_val;
2621 }
2622
2623 /* Select Host Wakeup Registers page - caller now able to write
2624 * registers on the Wakeup registers page
2625 */
2626 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2627 }
2628
2629 /**
2630 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2631 * @hw: pointer to the HW structure
2632 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2633 *
2634 * Restore BM_WUC_ENABLE_REG to its original value.
2635 *
2636 * Assumes semaphore already acquired and *phy_reg is the contents of the
2637 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2638 * caller.
2639 **/
e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)2640 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2641 {
2642 s32 ret_val;
2643
2644 /* Select Port Control Registers page */
2645 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2646 if (ret_val) {
2647 e_dbg("Could not set Port Control page\n");
2648 return ret_val;
2649 }
2650
2651 /* Restore 769.17 to its original value */
2652 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2653 if (ret_val)
2654 e_dbg("Could not restore PHY register %d.%d\n",
2655 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2656
2657 return ret_val;
2658 }
2659
2660 /**
2661 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2662 * @hw: pointer to the HW structure
2663 * @offset: register offset to be read or written
2664 * @data: pointer to the data to read or write
2665 * @read: determines if operation is read or write
2666 * @page_set: BM_WUC_PAGE already set and access enabled
2667 *
2668 * Read the PHY register at offset and store the retrieved information in
2669 * data, or write data to PHY register at offset. Note the procedure to
2670 * access the PHY wakeup registers is different than reading the other PHY
2671 * registers. It works as such:
2672 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2673 * 2) Set page to 800 for host (801 if we were manageability)
2674 * 3) Write the address using the address opcode (0x11)
2675 * 4) Read or write the data using the data opcode (0x12)
2676 * 5) Restore 769.17.2 to its original value
2677 *
2678 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2679 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2680 *
2681 * Assumes semaphore is already acquired. When page_set==true, assumes
2682 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2683 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2684 **/
e1000_access_phy_wakeup_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data,bool read,bool page_set)2685 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2686 u16 *data, bool read, bool page_set)
2687 {
2688 s32 ret_val;
2689 u16 reg = BM_PHY_REG_NUM(offset);
2690 u16 page = BM_PHY_REG_PAGE(offset);
2691 u16 phy_reg = 0;
2692
2693 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2694 if ((hw->mac.type == e1000_pchlan) &&
2695 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2696 e_dbg("Attempting to access page %d while gig enabled.\n",
2697 page);
2698
2699 if (!page_set) {
2700 /* Enable access to PHY wakeup registers */
2701 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2702 if (ret_val) {
2703 e_dbg("Could not enable PHY wakeup reg access\n");
2704 return ret_val;
2705 }
2706 }
2707
2708 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2709
2710 /* Write the Wakeup register page offset value using opcode 0x11 */
2711 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2712 if (ret_val) {
2713 e_dbg("Could not write address opcode to page %d\n", page);
2714 return ret_val;
2715 }
2716
2717 if (read) {
2718 /* Read the Wakeup register page value using opcode 0x12 */
2719 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2720 data);
2721 } else {
2722 /* Write the Wakeup register page value using opcode 0x12 */
2723 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2724 *data);
2725 }
2726
2727 if (ret_val) {
2728 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2729 return ret_val;
2730 }
2731
2732 if (!page_set)
2733 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2734
2735 return ret_val;
2736 }
2737
2738 /**
2739 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2740 * @hw: pointer to the HW structure
2741 *
2742 * In the case of a PHY power down to save power, or to turn off link during a
2743 * driver unload, or wake on lan is not enabled, restore the link to previous
2744 * settings.
2745 **/
e1000_power_up_phy_copper(struct e1000_hw * hw)2746 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2747 {
2748 u16 mii_reg = 0;
2749 int ret;
2750
2751 /* The PHY will retain its settings across a power down/up cycle */
2752 ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
2753 if (ret) {
2754 e_dbg("Error reading PHY register\n");
2755 return;
2756 }
2757 mii_reg &= ~BMCR_PDOWN;
2758 e1e_wphy(hw, MII_BMCR, mii_reg);
2759 }
2760
2761 /**
2762 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2763 * @hw: pointer to the HW structure
2764 *
2765 * In the case of a PHY power down to save power, or to turn off link during a
2766 * driver unload, or wake on lan is not enabled, restore the link to previous
2767 * settings.
2768 **/
e1000_power_down_phy_copper(struct e1000_hw * hw)2769 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2770 {
2771 u16 mii_reg = 0;
2772 int ret;
2773
2774 /* The PHY will retain its settings across a power down/up cycle */
2775 ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
2776 if (ret) {
2777 e_dbg("Error reading PHY register\n");
2778 return;
2779 }
2780 mii_reg |= BMCR_PDOWN;
2781 e1e_wphy(hw, MII_BMCR, mii_reg);
2782 usleep_range(1000, 2000);
2783 }
2784
2785 /**
2786 * __e1000_read_phy_reg_hv - Read HV PHY register
2787 * @hw: pointer to the HW structure
2788 * @offset: register offset to be read
2789 * @data: pointer to the read data
2790 * @locked: semaphore has already been acquired or not
2791 * @page_set: BM_WUC_PAGE already set and access enabled
2792 *
2793 * Acquires semaphore, if necessary, then reads the PHY register at offset
2794 * and stores the retrieved information in data. Release any acquired
2795 * semaphore before exiting.
2796 **/
__e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool locked,bool page_set)2797 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2798 bool locked, bool page_set)
2799 {
2800 s32 ret_val;
2801 u16 page = BM_PHY_REG_PAGE(offset);
2802 u16 reg = BM_PHY_REG_NUM(offset);
2803 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2804
2805 if (!locked) {
2806 ret_val = hw->phy.ops.acquire(hw);
2807 if (ret_val)
2808 return ret_val;
2809 }
2810
2811 /* Page 800 works differently than the rest so it has its own func */
2812 if (page == BM_WUC_PAGE) {
2813 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2814 true, page_set);
2815 goto out;
2816 }
2817
2818 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2819 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2820 data, true);
2821 goto out;
2822 }
2823
2824 if (!page_set) {
2825 if (page == HV_INTC_FC_PAGE_START)
2826 page = 0;
2827
2828 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2829 /* Page is shifted left, PHY expects (page x 32) */
2830 ret_val = e1000_set_page_igp(hw,
2831 (page << IGP_PAGE_SHIFT));
2832
2833 hw->phy.addr = phy_addr;
2834
2835 if (ret_val)
2836 goto out;
2837 }
2838 }
2839
2840 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2841 page << IGP_PAGE_SHIFT, reg);
2842
2843 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data);
2844 out:
2845 if (!locked)
2846 hw->phy.ops.release(hw);
2847
2848 return ret_val;
2849 }
2850
2851 /**
2852 * e1000_read_phy_reg_hv - Read HV PHY register
2853 * @hw: pointer to the HW structure
2854 * @offset: register offset to be read
2855 * @data: pointer to the read data
2856 *
2857 * Acquires semaphore then reads the PHY register at offset and stores
2858 * the retrieved information in data. Release the acquired semaphore
2859 * before exiting.
2860 **/
e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data)2861 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2862 {
2863 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2864 }
2865
2866 /**
2867 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2868 * @hw: pointer to the HW structure
2869 * @offset: register offset to be read
2870 * @data: pointer to the read data
2871 *
2872 * Reads the PHY register at offset and stores the retrieved information
2873 * in data. Assumes semaphore already acquired.
2874 **/
e1000_read_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 * data)2875 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2876 {
2877 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2878 }
2879
2880 /**
2881 * e1000_read_phy_reg_page_hv - Read HV PHY register
2882 * @hw: pointer to the HW structure
2883 * @offset: register offset to write to
2884 * @data: data to write at register offset
2885 *
2886 * Reads the PHY register at offset and stores the retrieved information
2887 * in data. Assumes semaphore already acquired and page already set.
2888 **/
e1000_read_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 * data)2889 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2890 {
2891 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2892 }
2893
2894 /**
2895 * __e1000_write_phy_reg_hv - Write HV PHY register
2896 * @hw: pointer to the HW structure
2897 * @offset: register offset to write to
2898 * @data: data to write at register offset
2899 * @locked: semaphore has already been acquired or not
2900 * @page_set: BM_WUC_PAGE already set and access enabled
2901 *
2902 * Acquires semaphore, if necessary, then writes the data to PHY register
2903 * at the offset. Release any acquired semaphores before exiting.
2904 **/
__e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data,bool locked,bool page_set)2905 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2906 bool locked, bool page_set)
2907 {
2908 s32 ret_val;
2909 u16 page = BM_PHY_REG_PAGE(offset);
2910 u16 reg = BM_PHY_REG_NUM(offset);
2911 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2912
2913 if (!locked) {
2914 ret_val = hw->phy.ops.acquire(hw);
2915 if (ret_val)
2916 return ret_val;
2917 }
2918
2919 /* Page 800 works differently than the rest so it has its own func */
2920 if (page == BM_WUC_PAGE) {
2921 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2922 false, page_set);
2923 goto out;
2924 }
2925
2926 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2927 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2928 &data, false);
2929 goto out;
2930 }
2931
2932 if (!page_set) {
2933 if (page == HV_INTC_FC_PAGE_START)
2934 page = 0;
2935
2936 /* Workaround MDIO accesses being disabled after entering IEEE
2937 * Power Down (when bit 11 of the PHY Control register is set)
2938 */
2939 if ((hw->phy.type == e1000_phy_82578) &&
2940 (hw->phy.revision >= 1) &&
2941 (hw->phy.addr == 2) &&
2942 !(MAX_PHY_REG_ADDRESS & reg) && (data & BIT(11))) {
2943 u16 data2 = 0x7EFF;
2944
2945 ret_val = e1000_access_phy_debug_regs_hv(hw,
2946 BIT(6) | 0x3,
2947 &data2, false);
2948 if (ret_val)
2949 goto out;
2950 }
2951
2952 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2953 /* Page is shifted left, PHY expects (page x 32) */
2954 ret_val = e1000_set_page_igp(hw,
2955 (page << IGP_PAGE_SHIFT));
2956
2957 hw->phy.addr = phy_addr;
2958
2959 if (ret_val)
2960 goto out;
2961 }
2962 }
2963
2964 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2965 page << IGP_PAGE_SHIFT, reg);
2966
2967 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2968 data);
2969
2970 out:
2971 if (!locked)
2972 hw->phy.ops.release(hw);
2973
2974 return ret_val;
2975 }
2976
2977 /**
2978 * e1000_write_phy_reg_hv - Write HV PHY register
2979 * @hw: pointer to the HW structure
2980 * @offset: register offset to write to
2981 * @data: data to write at register offset
2982 *
2983 * Acquires semaphore then writes the data to PHY register at the offset.
2984 * Release the acquired semaphores before exiting.
2985 **/
e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data)2986 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2987 {
2988 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
2989 }
2990
2991 /**
2992 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2993 * @hw: pointer to the HW structure
2994 * @offset: register offset to write to
2995 * @data: data to write at register offset
2996 *
2997 * Writes the data to PHY register at the offset. Assumes semaphore
2998 * already acquired.
2999 **/
e1000_write_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 data)3000 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3001 {
3002 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3003 }
3004
3005 /**
3006 * e1000_write_phy_reg_page_hv - Write HV PHY register
3007 * @hw: pointer to the HW structure
3008 * @offset: register offset to write to
3009 * @data: data to write at register offset
3010 *
3011 * Writes the data to PHY register at the offset. Assumes semaphore
3012 * already acquired and page already set.
3013 **/
e1000_write_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 data)3014 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3015 {
3016 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3017 }
3018
3019 /**
3020 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
3021 * @page: page to be accessed
3022 **/
e1000_get_phy_addr_for_hv_page(u32 page)3023 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3024 {
3025 u32 phy_addr = 2;
3026
3027 if (page >= HV_INTC_FC_PAGE_START)
3028 phy_addr = 1;
3029
3030 return phy_addr;
3031 }
3032
3033 /**
3034 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3035 * @hw: pointer to the HW structure
3036 * @offset: register offset to be read or written
3037 * @data: pointer to the data to be read or written
3038 * @read: determines if operation is read or write
3039 *
3040 * Reads the PHY register at offset and stores the retrieved information
3041 * in data. Assumes semaphore already acquired. Note that the procedure
3042 * to access these regs uses the address port and data port to read/write.
3043 * These accesses done with PHY address 2 and without using pages.
3044 **/
e1000_access_phy_debug_regs_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool read)3045 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3046 u16 *data, bool read)
3047 {
3048 s32 ret_val;
3049 u32 addr_reg;
3050 u32 data_reg;
3051
3052 /* This takes care of the difference with desktop vs mobile phy */
3053 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3054 I82578_ADDR_REG : I82577_ADDR_REG);
3055 data_reg = addr_reg + 1;
3056
3057 /* All operations in this function are phy address 2 */
3058 hw->phy.addr = 2;
3059
3060 /* masking with 0x3F to remove the page from offset */
3061 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3062 if (ret_val) {
3063 e_dbg("Could not write the Address Offset port register\n");
3064 return ret_val;
3065 }
3066
3067 /* Read or write the data value next */
3068 if (read)
3069 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3070 else
3071 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3072
3073 if (ret_val)
3074 e_dbg("Could not access the Data port register\n");
3075
3076 return ret_val;
3077 }
3078
3079 /**
3080 * e1000_link_stall_workaround_hv - Si workaround
3081 * @hw: pointer to the HW structure
3082 *
3083 * This function works around a Si bug where the link partner can get
3084 * a link up indication before the PHY does. If small packets are sent
3085 * by the link partner they can be placed in the packet buffer without
3086 * being properly accounted for by the PHY and will stall preventing
3087 * further packets from being received. The workaround is to clear the
3088 * packet buffer after the PHY detects link up.
3089 **/
e1000_link_stall_workaround_hv(struct e1000_hw * hw)3090 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3091 {
3092 s32 ret_val = 0;
3093 u16 data;
3094
3095 if (hw->phy.type != e1000_phy_82578)
3096 return 0;
3097
3098 /* Do not apply workaround if in PHY loopback bit 14 set */
3099 ret_val = e1e_rphy(hw, MII_BMCR, &data);
3100 if (ret_val) {
3101 e_dbg("Error reading PHY register\n");
3102 return ret_val;
3103 }
3104 if (data & BMCR_LOOPBACK)
3105 return 0;
3106
3107 /* check if link is up and at 1Gbps */
3108 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3109 if (ret_val)
3110 return ret_val;
3111
3112 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3113 BM_CS_STATUS_SPEED_MASK);
3114
3115 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3116 BM_CS_STATUS_SPEED_1000))
3117 return 0;
3118
3119 msleep(200);
3120
3121 /* flush the packets in the fifo buffer */
3122 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
3123 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3124 HV_MUX_DATA_CTRL_FORCE_SPEED));
3125 if (ret_val)
3126 return ret_val;
3127
3128 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3129 }
3130
3131 /**
3132 * e1000_check_polarity_82577 - Checks the polarity.
3133 * @hw: pointer to the HW structure
3134 *
3135 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3136 *
3137 * Polarity is determined based on the PHY specific status register.
3138 **/
e1000_check_polarity_82577(struct e1000_hw * hw)3139 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3140 {
3141 struct e1000_phy_info *phy = &hw->phy;
3142 s32 ret_val;
3143 u16 data;
3144
3145 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3146
3147 if (!ret_val)
3148 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3149 ? e1000_rev_polarity_reversed
3150 : e1000_rev_polarity_normal);
3151
3152 return ret_val;
3153 }
3154
3155 /**
3156 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3157 * @hw: pointer to the HW structure
3158 *
3159 * Calls the PHY setup function to force speed and duplex.
3160 **/
e1000_phy_force_speed_duplex_82577(struct e1000_hw * hw)3161 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3162 {
3163 struct e1000_phy_info *phy = &hw->phy;
3164 s32 ret_val;
3165 u16 phy_data;
3166 bool link;
3167
3168 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
3169 if (ret_val)
3170 return ret_val;
3171
3172 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3173
3174 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
3175 if (ret_val)
3176 return ret_val;
3177
3178 udelay(1);
3179
3180 if (phy->autoneg_wait_to_complete) {
3181 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3182
3183 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3184 100000, &link);
3185 if (ret_val)
3186 return ret_val;
3187
3188 if (!link)
3189 e_dbg("Link taking longer than expected.\n");
3190
3191 /* Try once more */
3192 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3193 100000, &link);
3194 }
3195
3196 return ret_val;
3197 }
3198
3199 /**
3200 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3201 * @hw: pointer to the HW structure
3202 *
3203 * Read PHY status to determine if link is up. If link is up, then
3204 * set/determine 10base-T extended distance and polarity correction. Read
3205 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3206 * determine on the cable length, local and remote receiver.
3207 **/
e1000_get_phy_info_82577(struct e1000_hw * hw)3208 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3209 {
3210 struct e1000_phy_info *phy = &hw->phy;
3211 s32 ret_val;
3212 u16 data;
3213 bool link;
3214
3215 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3216 if (ret_val)
3217 return ret_val;
3218
3219 if (!link) {
3220 e_dbg("Phy info is only valid if link is up\n");
3221 return -E1000_ERR_CONFIG;
3222 }
3223
3224 phy->polarity_correction = true;
3225
3226 ret_val = e1000_check_polarity_82577(hw);
3227 if (ret_val)
3228 return ret_val;
3229
3230 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3231 if (ret_val)
3232 return ret_val;
3233
3234 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3235
3236 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3237 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3238 ret_val = hw->phy.ops.get_cable_length(hw);
3239 if (ret_val)
3240 return ret_val;
3241
3242 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
3243 if (ret_val)
3244 return ret_val;
3245
3246 phy->local_rx = (data & LPA_1000LOCALRXOK)
3247 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3248
3249 phy->remote_rx = (data & LPA_1000REMRXOK)
3250 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3251 } else {
3252 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3253 phy->local_rx = e1000_1000t_rx_status_undefined;
3254 phy->remote_rx = e1000_1000t_rx_status_undefined;
3255 }
3256
3257 return 0;
3258 }
3259
3260 /**
3261 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3262 * @hw: pointer to the HW structure
3263 *
3264 * Reads the diagnostic status register and verifies result is valid before
3265 * placing it in the phy_cable_length field.
3266 **/
e1000_get_cable_length_82577(struct e1000_hw * hw)3267 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3268 {
3269 struct e1000_phy_info *phy = &hw->phy;
3270 s32 ret_val;
3271 u16 phy_data, length;
3272
3273 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3274 if (ret_val)
3275 return ret_val;
3276
3277 length = FIELD_GET(I82577_DSTATUS_CABLE_LENGTH, phy_data);
3278
3279 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3280 return -E1000_ERR_PHY;
3281
3282 phy->cable_length = length;
3283
3284 return 0;
3285 }
3286