1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
4 * stmmac XGMAC support.
5 */
6
7 #include <linux/bitrev.h>
8 #include <linux/crc32.h>
9 #include <linux/iopoll.h>
10 #include "stmmac.h"
11 #include "stmmac_ptp.h"
12 #include "dwxlgmac2.h"
13 #include "dwxgmac2.h"
14
dwxgmac2_core_init(struct mac_device_info * hw,struct net_device * dev)15 static void dwxgmac2_core_init(struct mac_device_info *hw,
16 struct net_device *dev)
17 {
18 void __iomem *ioaddr = hw->pcsr;
19 u32 tx, rx;
20
21 tx = readl(ioaddr + XGMAC_TX_CONFIG);
22 rx = readl(ioaddr + XGMAC_RX_CONFIG);
23
24 tx |= XGMAC_CORE_INIT_TX;
25 rx |= XGMAC_CORE_INIT_RX;
26
27 if (hw->ps) {
28 tx |= XGMAC_CONFIG_TE;
29 tx &= ~hw->link.speed_mask;
30
31 switch (hw->ps) {
32 case SPEED_10000:
33 tx |= hw->link.xgmii.speed10000;
34 break;
35 case SPEED_2500:
36 tx |= hw->link.speed2500;
37 break;
38 case SPEED_1000:
39 default:
40 tx |= hw->link.speed1000;
41 break;
42 }
43 }
44
45 writel(tx, ioaddr + XGMAC_TX_CONFIG);
46 writel(rx, ioaddr + XGMAC_RX_CONFIG);
47 writel(XGMAC_INT_DEFAULT_EN, ioaddr + XGMAC_INT_EN);
48 }
49
dwxgmac2_set_mac(void __iomem * ioaddr,bool enable)50 static void dwxgmac2_set_mac(void __iomem *ioaddr, bool enable)
51 {
52 u32 tx = readl(ioaddr + XGMAC_TX_CONFIG);
53 u32 rx = readl(ioaddr + XGMAC_RX_CONFIG);
54
55 if (enable) {
56 tx |= XGMAC_CONFIG_TE;
57 rx |= XGMAC_CONFIG_RE;
58 } else {
59 tx &= ~XGMAC_CONFIG_TE;
60 rx &= ~XGMAC_CONFIG_RE;
61 }
62
63 writel(tx, ioaddr + XGMAC_TX_CONFIG);
64 writel(rx, ioaddr + XGMAC_RX_CONFIG);
65 }
66
dwxgmac2_rx_ipc(struct mac_device_info * hw)67 static int dwxgmac2_rx_ipc(struct mac_device_info *hw)
68 {
69 void __iomem *ioaddr = hw->pcsr;
70 u32 value;
71
72 value = readl(ioaddr + XGMAC_RX_CONFIG);
73 if (hw->rx_csum)
74 value |= XGMAC_CONFIG_IPC;
75 else
76 value &= ~XGMAC_CONFIG_IPC;
77 writel(value, ioaddr + XGMAC_RX_CONFIG);
78
79 return !!(readl(ioaddr + XGMAC_RX_CONFIG) & XGMAC_CONFIG_IPC);
80 }
81
dwxgmac2_rx_queue_enable(struct mac_device_info * hw,u8 mode,u32 queue)82 static void dwxgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode,
83 u32 queue)
84 {
85 void __iomem *ioaddr = hw->pcsr;
86 u32 value;
87
88 value = readl(ioaddr + XGMAC_RXQ_CTRL0) & ~XGMAC_RXQEN(queue);
89 if (mode == MTL_QUEUE_AVB)
90 value |= 0x1 << XGMAC_RXQEN_SHIFT(queue);
91 else if (mode == MTL_QUEUE_DCB)
92 value |= 0x2 << XGMAC_RXQEN_SHIFT(queue);
93 writel(value, ioaddr + XGMAC_RXQ_CTRL0);
94 }
95
dwxgmac2_rx_queue_prio(struct mac_device_info * hw,u32 prio,u32 queue)96 static void dwxgmac2_rx_queue_prio(struct mac_device_info *hw, u32 prio,
97 u32 queue)
98 {
99 void __iomem *ioaddr = hw->pcsr;
100 u32 clear_mask = 0;
101 u32 ctrl2, ctrl3;
102 int i;
103
104 ctrl2 = readl(ioaddr + XGMAC_RXQ_CTRL2);
105 ctrl3 = readl(ioaddr + XGMAC_RXQ_CTRL3);
106
107 /* The software must ensure that the same priority
108 * is not mapped to multiple Rx queues
109 */
110 for (i = 0; i < 4; i++)
111 clear_mask |= ((prio << XGMAC_PSRQ_SHIFT(i)) &
112 XGMAC_PSRQ(i));
113
114 ctrl2 &= ~clear_mask;
115 ctrl3 &= ~clear_mask;
116
117 /* First assign new priorities to a queue, then
118 * clear them from others queues
119 */
120 if (queue < 4) {
121 ctrl2 |= (prio << XGMAC_PSRQ_SHIFT(queue)) &
122 XGMAC_PSRQ(queue);
123
124 writel(ctrl2, ioaddr + XGMAC_RXQ_CTRL2);
125 writel(ctrl3, ioaddr + XGMAC_RXQ_CTRL3);
126 } else {
127 queue -= 4;
128
129 ctrl3 |= (prio << XGMAC_PSRQ_SHIFT(queue)) &
130 XGMAC_PSRQ(queue);
131
132 writel(ctrl3, ioaddr + XGMAC_RXQ_CTRL3);
133 writel(ctrl2, ioaddr + XGMAC_RXQ_CTRL2);
134 }
135 }
136
dwxgmac2_tx_queue_prio(struct mac_device_info * hw,u32 prio,u32 queue)137 static void dwxgmac2_tx_queue_prio(struct mac_device_info *hw, u32 prio,
138 u32 queue)
139 {
140 void __iomem *ioaddr = hw->pcsr;
141 u32 value, reg;
142
143 reg = (queue < 4) ? XGMAC_TC_PRTY_MAP0 : XGMAC_TC_PRTY_MAP1;
144 if (queue >= 4)
145 queue -= 4;
146
147 value = readl(ioaddr + reg);
148 value &= ~XGMAC_PSTC(queue);
149 value |= (prio << XGMAC_PSTC_SHIFT(queue)) & XGMAC_PSTC(queue);
150
151 writel(value, ioaddr + reg);
152 }
153
dwxgmac2_rx_queue_routing(struct mac_device_info * hw,u8 packet,u32 queue)154 static void dwxgmac2_rx_queue_routing(struct mac_device_info *hw,
155 u8 packet, u32 queue)
156 {
157 void __iomem *ioaddr = hw->pcsr;
158 u32 value;
159
160 static const struct stmmac_rx_routing dwxgmac2_route_possibilities[] = {
161 { XGMAC_AVCPQ, XGMAC_AVCPQ_SHIFT },
162 { XGMAC_PTPQ, XGMAC_PTPQ_SHIFT },
163 { XGMAC_DCBCPQ, XGMAC_DCBCPQ_SHIFT },
164 { XGMAC_UPQ, XGMAC_UPQ_SHIFT },
165 { XGMAC_MCBCQ, XGMAC_MCBCQ_SHIFT },
166 };
167
168 value = readl(ioaddr + XGMAC_RXQ_CTRL1);
169
170 /* routing configuration */
171 value &= ~dwxgmac2_route_possibilities[packet - 1].reg_mask;
172 value |= (queue << dwxgmac2_route_possibilities[packet - 1].reg_shift) &
173 dwxgmac2_route_possibilities[packet - 1].reg_mask;
174
175 /* some packets require extra ops */
176 if (packet == PACKET_AVCPQ)
177 value |= FIELD_PREP(XGMAC_TACPQE, 1);
178 else if (packet == PACKET_MCBCQ)
179 value |= FIELD_PREP(XGMAC_MCBCQEN, 1);
180
181 writel(value, ioaddr + XGMAC_RXQ_CTRL1);
182 }
183
dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info * hw,u32 rx_alg)184 static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info *hw,
185 u32 rx_alg)
186 {
187 void __iomem *ioaddr = hw->pcsr;
188 u32 value;
189
190 value = readl(ioaddr + XGMAC_MTL_OPMODE);
191 value &= ~XGMAC_RAA;
192
193 switch (rx_alg) {
194 case MTL_RX_ALGORITHM_SP:
195 break;
196 case MTL_RX_ALGORITHM_WSP:
197 value |= XGMAC_RAA;
198 break;
199 default:
200 break;
201 }
202
203 writel(value, ioaddr + XGMAC_MTL_OPMODE);
204 }
205
dwxgmac2_prog_mtl_tx_algorithms(struct mac_device_info * hw,u32 tx_alg)206 static void dwxgmac2_prog_mtl_tx_algorithms(struct mac_device_info *hw,
207 u32 tx_alg)
208 {
209 void __iomem *ioaddr = hw->pcsr;
210 bool ets = true;
211 u32 value;
212 int i;
213
214 value = readl(ioaddr + XGMAC_MTL_OPMODE);
215 value &= ~XGMAC_ETSALG;
216
217 switch (tx_alg) {
218 case MTL_TX_ALGORITHM_WRR:
219 value |= XGMAC_WRR;
220 break;
221 case MTL_TX_ALGORITHM_WFQ:
222 value |= XGMAC_WFQ;
223 break;
224 case MTL_TX_ALGORITHM_DWRR:
225 value |= XGMAC_DWRR;
226 break;
227 default:
228 ets = false;
229 break;
230 }
231
232 writel(value, ioaddr + XGMAC_MTL_OPMODE);
233
234 /* Set ETS if desired */
235 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) {
236 value = readl(ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(i));
237 value &= ~XGMAC_TSA;
238 if (ets)
239 value |= XGMAC_ETS;
240 writel(value, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(i));
241 }
242 }
243
dwxgmac2_set_mtl_tx_queue_weight(struct stmmac_priv * priv,struct mac_device_info * hw,u32 weight,u32 queue)244 static void dwxgmac2_set_mtl_tx_queue_weight(struct stmmac_priv *priv,
245 struct mac_device_info *hw,
246 u32 weight, u32 queue)
247 {
248 void __iomem *ioaddr = hw->pcsr;
249
250 writel(weight, ioaddr + XGMAC_MTL_TCx_QUANTUM_WEIGHT(queue));
251 }
252
dwxgmac2_map_mtl_to_dma(struct mac_device_info * hw,u32 queue,u32 chan)253 static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue,
254 u32 chan)
255 {
256 void __iomem *ioaddr = hw->pcsr;
257 u32 value, reg;
258
259 reg = (queue < 4) ? XGMAC_MTL_RXQ_DMA_MAP0 : XGMAC_MTL_RXQ_DMA_MAP1;
260 if (queue >= 4)
261 queue -= 4;
262
263 value = readl(ioaddr + reg);
264 value &= ~XGMAC_QxMDMACH(queue);
265 value |= (chan << XGMAC_QxMDMACH_SHIFT(queue)) & XGMAC_QxMDMACH(queue);
266
267 writel(value, ioaddr + reg);
268 }
269
dwxgmac2_config_cbs(struct stmmac_priv * priv,struct mac_device_info * hw,u32 send_slope,u32 idle_slope,u32 high_credit,u32 low_credit,u32 queue)270 static void dwxgmac2_config_cbs(struct stmmac_priv *priv,
271 struct mac_device_info *hw,
272 u32 send_slope, u32 idle_slope,
273 u32 high_credit, u32 low_credit, u32 queue)
274 {
275 void __iomem *ioaddr = hw->pcsr;
276 u32 value;
277
278 writel(send_slope, ioaddr + XGMAC_MTL_TCx_SENDSLOPE(queue));
279 writel(idle_slope, ioaddr + XGMAC_MTL_TCx_QUANTUM_WEIGHT(queue));
280 writel(high_credit, ioaddr + XGMAC_MTL_TCx_HICREDIT(queue));
281 writel(low_credit, ioaddr + XGMAC_MTL_TCx_LOCREDIT(queue));
282
283 value = readl(ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(queue));
284 value &= ~XGMAC_TSA;
285 value |= XGMAC_CC | XGMAC_CBS;
286 writel(value, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(queue));
287 }
288
dwxgmac2_dump_regs(struct mac_device_info * hw,u32 * reg_space)289 static void dwxgmac2_dump_regs(struct mac_device_info *hw, u32 *reg_space)
290 {
291 void __iomem *ioaddr = hw->pcsr;
292 int i;
293
294 for (i = 0; i < XGMAC_MAC_REGSIZE; i++)
295 reg_space[i] = readl(ioaddr + i * 4);
296 }
297
dwxgmac2_host_irq_status(struct mac_device_info * hw,struct stmmac_extra_stats * x)298 static int dwxgmac2_host_irq_status(struct mac_device_info *hw,
299 struct stmmac_extra_stats *x)
300 {
301 void __iomem *ioaddr = hw->pcsr;
302 u32 stat, en;
303 int ret = 0;
304
305 en = readl(ioaddr + XGMAC_INT_EN);
306 stat = readl(ioaddr + XGMAC_INT_STATUS);
307
308 stat &= en;
309
310 if (stat & XGMAC_PMTIS) {
311 x->irq_receive_pmt_irq_n++;
312 readl(ioaddr + XGMAC_PMT);
313 }
314
315 if (stat & XGMAC_LPIIS) {
316 u32 lpi = readl(ioaddr + XGMAC_LPI_CTRL);
317
318 if (lpi & XGMAC_TLPIEN) {
319 ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
320 x->irq_tx_path_in_lpi_mode_n++;
321 }
322 if (lpi & XGMAC_TLPIEX) {
323 ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
324 x->irq_tx_path_exit_lpi_mode_n++;
325 }
326 if (lpi & XGMAC_RLPIEN)
327 x->irq_rx_path_in_lpi_mode_n++;
328 if (lpi & XGMAC_RLPIEX)
329 x->irq_rx_path_exit_lpi_mode_n++;
330 }
331
332 return ret;
333 }
334
dwxgmac2_host_mtl_irq_status(struct stmmac_priv * priv,struct mac_device_info * hw,u32 chan)335 static int dwxgmac2_host_mtl_irq_status(struct stmmac_priv *priv,
336 struct mac_device_info *hw, u32 chan)
337 {
338 void __iomem *ioaddr = hw->pcsr;
339 int ret = 0;
340 u32 status;
341
342 status = readl(ioaddr + XGMAC_MTL_INT_STATUS);
343 if (status & BIT(chan)) {
344 u32 chan_status = readl(ioaddr + XGMAC_MTL_QINT_STATUS(chan));
345
346 if (chan_status & XGMAC_RXOVFIS)
347 ret |= CORE_IRQ_MTL_RX_OVERFLOW;
348
349 writel(~0x0, ioaddr + XGMAC_MTL_QINT_STATUS(chan));
350 }
351
352 return ret;
353 }
354
dwxgmac2_flow_ctrl(struct mac_device_info * hw,unsigned int duplex,unsigned int fc,unsigned int pause_time,u32 tx_cnt)355 static void dwxgmac2_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
356 unsigned int fc, unsigned int pause_time,
357 u32 tx_cnt)
358 {
359 void __iomem *ioaddr = hw->pcsr;
360 u32 i;
361
362 if (fc & FLOW_RX)
363 writel(XGMAC_RFE, ioaddr + XGMAC_RX_FLOW_CTRL);
364 if (fc & FLOW_TX) {
365 for (i = 0; i < tx_cnt; i++) {
366 u32 value = XGMAC_TFE;
367
368 if (duplex)
369 value |= pause_time << XGMAC_PT_SHIFT;
370
371 writel(value, ioaddr + XGMAC_Qx_TX_FLOW_CTRL(i));
372 }
373 }
374 }
375
dwxgmac2_pmt(struct mac_device_info * hw,unsigned long mode)376 static void dwxgmac2_pmt(struct mac_device_info *hw, unsigned long mode)
377 {
378 void __iomem *ioaddr = hw->pcsr;
379 u32 val = 0x0;
380
381 if (mode & WAKE_MAGIC)
382 val |= XGMAC_PWRDWN | XGMAC_MGKPKTEN;
383 if (mode & WAKE_UCAST)
384 val |= XGMAC_PWRDWN | XGMAC_GLBLUCAST | XGMAC_RWKPKTEN;
385 if (val) {
386 u32 cfg = readl(ioaddr + XGMAC_RX_CONFIG);
387 cfg |= XGMAC_CONFIG_RE;
388 writel(cfg, ioaddr + XGMAC_RX_CONFIG);
389 }
390
391 writel(val, ioaddr + XGMAC_PMT);
392 }
393
dwxgmac2_set_umac_addr(struct mac_device_info * hw,const unsigned char * addr,unsigned int reg_n)394 static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,
395 const unsigned char *addr,
396 unsigned int reg_n)
397 {
398 void __iomem *ioaddr = hw->pcsr;
399 u32 value;
400
401 value = (addr[5] << 8) | addr[4];
402 writel(value | XGMAC_AE, ioaddr + XGMAC_ADDRx_HIGH(reg_n));
403
404 value = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
405 writel(value, ioaddr + XGMAC_ADDRx_LOW(reg_n));
406 }
407
dwxgmac2_get_umac_addr(struct mac_device_info * hw,unsigned char * addr,unsigned int reg_n)408 static void dwxgmac2_get_umac_addr(struct mac_device_info *hw,
409 unsigned char *addr, unsigned int reg_n)
410 {
411 void __iomem *ioaddr = hw->pcsr;
412 u32 hi_addr, lo_addr;
413
414 /* Read the MAC address from the hardware */
415 hi_addr = readl(ioaddr + XGMAC_ADDRx_HIGH(reg_n));
416 lo_addr = readl(ioaddr + XGMAC_ADDRx_LOW(reg_n));
417
418 /* Extract the MAC address from the high and low words */
419 addr[0] = lo_addr & 0xff;
420 addr[1] = (lo_addr >> 8) & 0xff;
421 addr[2] = (lo_addr >> 16) & 0xff;
422 addr[3] = (lo_addr >> 24) & 0xff;
423 addr[4] = hi_addr & 0xff;
424 addr[5] = (hi_addr >> 8) & 0xff;
425 }
426
dwxgmac2_set_eee_mode(struct mac_device_info * hw,bool en_tx_lpi_clockgating)427 static void dwxgmac2_set_eee_mode(struct mac_device_info *hw,
428 bool en_tx_lpi_clockgating)
429 {
430 void __iomem *ioaddr = hw->pcsr;
431 u32 value;
432
433 value = readl(ioaddr + XGMAC_LPI_CTRL);
434
435 value |= XGMAC_LPITXEN | XGMAC_LPITXA;
436 if (en_tx_lpi_clockgating)
437 value |= XGMAC_TXCGE;
438
439 writel(value, ioaddr + XGMAC_LPI_CTRL);
440 }
441
dwxgmac2_reset_eee_mode(struct mac_device_info * hw)442 static void dwxgmac2_reset_eee_mode(struct mac_device_info *hw)
443 {
444 void __iomem *ioaddr = hw->pcsr;
445 u32 value;
446
447 value = readl(ioaddr + XGMAC_LPI_CTRL);
448 value &= ~(XGMAC_LPITXEN | XGMAC_LPITXA | XGMAC_TXCGE);
449 writel(value, ioaddr + XGMAC_LPI_CTRL);
450 }
451
dwxgmac2_set_eee_pls(struct mac_device_info * hw,int link)452 static void dwxgmac2_set_eee_pls(struct mac_device_info *hw, int link)
453 {
454 void __iomem *ioaddr = hw->pcsr;
455 u32 value;
456
457 value = readl(ioaddr + XGMAC_LPI_CTRL);
458 if (link)
459 value |= XGMAC_PLS;
460 else
461 value &= ~XGMAC_PLS;
462 writel(value, ioaddr + XGMAC_LPI_CTRL);
463 }
464
dwxgmac2_set_eee_timer(struct mac_device_info * hw,int ls,int tw)465 static void dwxgmac2_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
466 {
467 void __iomem *ioaddr = hw->pcsr;
468 u32 value;
469
470 value = (tw & 0xffff) | ((ls & 0x3ff) << 16);
471 writel(value, ioaddr + XGMAC_LPI_TIMER_CTRL);
472 }
473
dwxgmac2_set_mchash(void __iomem * ioaddr,u32 * mcfilterbits,int mcbitslog2)474 static void dwxgmac2_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
475 int mcbitslog2)
476 {
477 int numhashregs, regs;
478
479 switch (mcbitslog2) {
480 case 6:
481 numhashregs = 2;
482 break;
483 case 7:
484 numhashregs = 4;
485 break;
486 case 8:
487 numhashregs = 8;
488 break;
489 default:
490 return;
491 }
492
493 for (regs = 0; regs < numhashregs; regs++)
494 writel(mcfilterbits[regs], ioaddr + XGMAC_HASH_TABLE(regs));
495 }
496
dwxgmac2_set_filter(struct mac_device_info * hw,struct net_device * dev)497 static void dwxgmac2_set_filter(struct mac_device_info *hw,
498 struct net_device *dev)
499 {
500 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
501 u32 value = readl(ioaddr + XGMAC_PACKET_FILTER);
502 int mcbitslog2 = hw->mcast_bits_log2;
503 u32 mc_filter[8];
504 int i;
505
506 value &= ~(XGMAC_FILTER_PR | XGMAC_FILTER_HMC | XGMAC_FILTER_PM);
507 value |= XGMAC_FILTER_HPF;
508
509 memset(mc_filter, 0, sizeof(mc_filter));
510
511 if (dev->flags & IFF_PROMISC) {
512 value |= XGMAC_FILTER_PR;
513 value |= XGMAC_FILTER_PCF;
514 } else if ((dev->flags & IFF_ALLMULTI) ||
515 (netdev_mc_count(dev) > hw->multicast_filter_bins)) {
516 value |= XGMAC_FILTER_PM;
517
518 for (i = 0; i < XGMAC_MAX_HASH_TABLE; i++)
519 writel(~0x0, ioaddr + XGMAC_HASH_TABLE(i));
520 } else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) {
521 struct netdev_hw_addr *ha;
522
523 value |= XGMAC_FILTER_HMC;
524
525 netdev_for_each_mc_addr(ha, dev) {
526 u32 nr = (bitrev32(~crc32_le(~0, ha->addr, 6)) >>
527 (32 - mcbitslog2));
528 mc_filter[nr >> 5] |= (1 << (nr & 0x1F));
529 }
530 }
531
532 dwxgmac2_set_mchash(ioaddr, mc_filter, mcbitslog2);
533
534 /* Handle multiple unicast addresses */
535 if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
536 value |= XGMAC_FILTER_PR;
537 } else {
538 struct netdev_hw_addr *ha;
539 int reg = 1;
540
541 netdev_for_each_uc_addr(ha, dev) {
542 dwxgmac2_set_umac_addr(hw, ha->addr, reg);
543 reg++;
544 }
545
546 for ( ; reg < XGMAC_ADDR_MAX; reg++) {
547 writel(0, ioaddr + XGMAC_ADDRx_HIGH(reg));
548 writel(0, ioaddr + XGMAC_ADDRx_LOW(reg));
549 }
550 }
551
552 writel(value, ioaddr + XGMAC_PACKET_FILTER);
553 }
554
dwxgmac2_set_mac_loopback(void __iomem * ioaddr,bool enable)555 static void dwxgmac2_set_mac_loopback(void __iomem *ioaddr, bool enable)
556 {
557 u32 value = readl(ioaddr + XGMAC_RX_CONFIG);
558
559 if (enable)
560 value |= XGMAC_CONFIG_LM;
561 else
562 value &= ~XGMAC_CONFIG_LM;
563
564 writel(value, ioaddr + XGMAC_RX_CONFIG);
565 }
566
dwxgmac2_rss_write_reg(void __iomem * ioaddr,bool is_key,int idx,u32 val)567 static int dwxgmac2_rss_write_reg(void __iomem *ioaddr, bool is_key, int idx,
568 u32 val)
569 {
570 u32 ctrl = 0;
571
572 writel(val, ioaddr + XGMAC_RSS_DATA);
573 ctrl |= idx << XGMAC_RSSIA_SHIFT;
574 ctrl |= is_key ? XGMAC_ADDRT : 0x0;
575 ctrl |= XGMAC_OB;
576 writel(ctrl, ioaddr + XGMAC_RSS_ADDR);
577
578 return readl_poll_timeout(ioaddr + XGMAC_RSS_ADDR, ctrl,
579 !(ctrl & XGMAC_OB), 100, 10000);
580 }
581
dwxgmac2_rss_configure(struct mac_device_info * hw,struct stmmac_rss * cfg,u32 num_rxq)582 static int dwxgmac2_rss_configure(struct mac_device_info *hw,
583 struct stmmac_rss *cfg, u32 num_rxq)
584 {
585 void __iomem *ioaddr = hw->pcsr;
586 u32 value, *key;
587 int i, ret;
588
589 value = readl(ioaddr + XGMAC_RSS_CTRL);
590 if (!cfg || !cfg->enable) {
591 value &= ~XGMAC_RSSE;
592 writel(value, ioaddr + XGMAC_RSS_CTRL);
593 return 0;
594 }
595
596 key = (u32 *)cfg->key;
597 for (i = 0; i < (ARRAY_SIZE(cfg->key) / sizeof(u32)); i++) {
598 ret = dwxgmac2_rss_write_reg(ioaddr, true, i, key[i]);
599 if (ret)
600 return ret;
601 }
602
603 for (i = 0; i < ARRAY_SIZE(cfg->table); i++) {
604 ret = dwxgmac2_rss_write_reg(ioaddr, false, i, cfg->table[i]);
605 if (ret)
606 return ret;
607 }
608
609 for (i = 0; i < num_rxq; i++)
610 dwxgmac2_map_mtl_to_dma(hw, i, XGMAC_QDDMACH);
611
612 value |= XGMAC_UDP4TE | XGMAC_TCP4TE | XGMAC_IP2TE | XGMAC_RSSE;
613 writel(value, ioaddr + XGMAC_RSS_CTRL);
614 return 0;
615 }
616
dwxgmac2_update_vlan_hash(struct mac_device_info * hw,u32 hash,__le16 perfect_match,bool is_double)617 static void dwxgmac2_update_vlan_hash(struct mac_device_info *hw, u32 hash,
618 __le16 perfect_match, bool is_double)
619 {
620 void __iomem *ioaddr = hw->pcsr;
621
622 writel(hash, ioaddr + XGMAC_VLAN_HASH_TABLE);
623
624 if (hash) {
625 u32 value = readl(ioaddr + XGMAC_PACKET_FILTER);
626
627 value |= XGMAC_FILTER_VTFE;
628
629 writel(value, ioaddr + XGMAC_PACKET_FILTER);
630
631 value = readl(ioaddr + XGMAC_VLAN_TAG);
632
633 value |= XGMAC_VLAN_VTHM | XGMAC_VLAN_ETV;
634 if (is_double) {
635 value |= XGMAC_VLAN_EDVLP;
636 value |= XGMAC_VLAN_ESVL;
637 value |= XGMAC_VLAN_DOVLTC;
638 } else {
639 value &= ~XGMAC_VLAN_EDVLP;
640 value &= ~XGMAC_VLAN_ESVL;
641 value &= ~XGMAC_VLAN_DOVLTC;
642 }
643
644 value &= ~XGMAC_VLAN_VID;
645 writel(value, ioaddr + XGMAC_VLAN_TAG);
646 } else if (perfect_match) {
647 u32 value = readl(ioaddr + XGMAC_PACKET_FILTER);
648
649 value |= XGMAC_FILTER_VTFE;
650
651 writel(value, ioaddr + XGMAC_PACKET_FILTER);
652
653 value = readl(ioaddr + XGMAC_VLAN_TAG);
654
655 value &= ~XGMAC_VLAN_VTHM;
656 value |= XGMAC_VLAN_ETV;
657 if (is_double) {
658 value |= XGMAC_VLAN_EDVLP;
659 value |= XGMAC_VLAN_ESVL;
660 value |= XGMAC_VLAN_DOVLTC;
661 } else {
662 value &= ~XGMAC_VLAN_EDVLP;
663 value &= ~XGMAC_VLAN_ESVL;
664 value &= ~XGMAC_VLAN_DOVLTC;
665 }
666
667 value &= ~XGMAC_VLAN_VID;
668 writel(value | perfect_match, ioaddr + XGMAC_VLAN_TAG);
669 } else {
670 u32 value = readl(ioaddr + XGMAC_PACKET_FILTER);
671
672 value &= ~XGMAC_FILTER_VTFE;
673
674 writel(value, ioaddr + XGMAC_PACKET_FILTER);
675
676 value = readl(ioaddr + XGMAC_VLAN_TAG);
677
678 value &= ~(XGMAC_VLAN_VTHM | XGMAC_VLAN_ETV);
679 value &= ~(XGMAC_VLAN_EDVLP | XGMAC_VLAN_ESVL);
680 value &= ~XGMAC_VLAN_DOVLTC;
681 value &= ~XGMAC_VLAN_VID;
682
683 writel(value, ioaddr + XGMAC_VLAN_TAG);
684 }
685 }
686
687 struct dwxgmac3_error_desc {
688 bool valid;
689 const char *desc;
690 const char *detailed_desc;
691 };
692
693 #define STAT_OFF(field) offsetof(struct stmmac_safety_stats, field)
694
dwxgmac3_log_error(struct net_device * ndev,u32 value,bool corr,const char * module_name,const struct dwxgmac3_error_desc * desc,unsigned long field_offset,struct stmmac_safety_stats * stats)695 static void dwxgmac3_log_error(struct net_device *ndev, u32 value, bool corr,
696 const char *module_name,
697 const struct dwxgmac3_error_desc *desc,
698 unsigned long field_offset,
699 struct stmmac_safety_stats *stats)
700 {
701 unsigned long loc, mask;
702 u8 *bptr = (u8 *)stats;
703 unsigned long *ptr;
704
705 ptr = (unsigned long *)(bptr + field_offset);
706
707 mask = value;
708 for_each_set_bit(loc, &mask, 32) {
709 netdev_err(ndev, "Found %s error in %s: '%s: %s'\n", corr ?
710 "correctable" : "uncorrectable", module_name,
711 desc[loc].desc, desc[loc].detailed_desc);
712
713 /* Update counters */
714 ptr[loc]++;
715 }
716 }
717
718 static const struct dwxgmac3_error_desc dwxgmac3_mac_errors[32]= {
719 { true, "ATPES", "Application Transmit Interface Parity Check Error" },
720 { true, "DPES", "Descriptor Cache Data Path Parity Check Error" },
721 { true, "TPES", "TSO Data Path Parity Check Error" },
722 { true, "TSOPES", "TSO Header Data Path Parity Check Error" },
723 { true, "MTPES", "MTL Data Path Parity Check Error" },
724 { true, "MTSPES", "MTL TX Status Data Path Parity Check Error" },
725 { true, "MTBUPES", "MAC TBU Data Path Parity Check Error" },
726 { true, "MTFCPES", "MAC TFC Data Path Parity Check Error" },
727 { true, "ARPES", "Application Receive Interface Data Path Parity Check Error" },
728 { true, "MRWCPES", "MTL RWC Data Path Parity Check Error" },
729 { true, "MRRCPES", "MTL RCC Data Path Parity Check Error" },
730 { true, "CWPES", "CSR Write Data Path Parity Check Error" },
731 { true, "ASRPES", "AXI Slave Read Data Path Parity Check Error" },
732 { true, "TTES", "TX FSM Timeout Error" },
733 { true, "RTES", "RX FSM Timeout Error" },
734 { true, "CTES", "CSR FSM Timeout Error" },
735 { true, "ATES", "APP FSM Timeout Error" },
736 { true, "PTES", "PTP FSM Timeout Error" },
737 { false, "UNKNOWN", "Unknown Error" }, /* 18 */
738 { false, "UNKNOWN", "Unknown Error" }, /* 19 */
739 { false, "UNKNOWN", "Unknown Error" }, /* 20 */
740 { true, "MSTTES", "Master Read/Write Timeout Error" },
741 { true, "SLVTES", "Slave Read/Write Timeout Error" },
742 { true, "ATITES", "Application Timeout on ATI Interface Error" },
743 { true, "ARITES", "Application Timeout on ARI Interface Error" },
744 { true, "FSMPES", "FSM State Parity Error" },
745 { false, "UNKNOWN", "Unknown Error" }, /* 26 */
746 { false, "UNKNOWN", "Unknown Error" }, /* 27 */
747 { false, "UNKNOWN", "Unknown Error" }, /* 28 */
748 { false, "UNKNOWN", "Unknown Error" }, /* 29 */
749 { false, "UNKNOWN", "Unknown Error" }, /* 30 */
750 { true, "CPI", "Control Register Parity Check Error" },
751 };
752
dwxgmac3_handle_mac_err(struct net_device * ndev,void __iomem * ioaddr,bool correctable,struct stmmac_safety_stats * stats)753 static void dwxgmac3_handle_mac_err(struct net_device *ndev,
754 void __iomem *ioaddr, bool correctable,
755 struct stmmac_safety_stats *stats)
756 {
757 u32 value;
758
759 value = readl(ioaddr + XGMAC_MAC_DPP_FSM_INT_STATUS);
760 writel(value, ioaddr + XGMAC_MAC_DPP_FSM_INT_STATUS);
761
762 dwxgmac3_log_error(ndev, value, correctable, "MAC",
763 dwxgmac3_mac_errors, STAT_OFF(mac_errors), stats);
764 }
765
766 static const struct dwxgmac3_error_desc dwxgmac3_mtl_errors[32]= {
767 { true, "TXCES", "MTL TX Memory Error" },
768 { true, "TXAMS", "MTL TX Memory Address Mismatch Error" },
769 { true, "TXUES", "MTL TX Memory Error" },
770 { false, "UNKNOWN", "Unknown Error" }, /* 3 */
771 { true, "RXCES", "MTL RX Memory Error" },
772 { true, "RXAMS", "MTL RX Memory Address Mismatch Error" },
773 { true, "RXUES", "MTL RX Memory Error" },
774 { false, "UNKNOWN", "Unknown Error" }, /* 7 */
775 { true, "ECES", "MTL EST Memory Error" },
776 { true, "EAMS", "MTL EST Memory Address Mismatch Error" },
777 { true, "EUES", "MTL EST Memory Error" },
778 { false, "UNKNOWN", "Unknown Error" }, /* 11 */
779 { true, "RPCES", "MTL RX Parser Memory Error" },
780 { true, "RPAMS", "MTL RX Parser Memory Address Mismatch Error" },
781 { true, "RPUES", "MTL RX Parser Memory Error" },
782 { false, "UNKNOWN", "Unknown Error" }, /* 15 */
783 { false, "UNKNOWN", "Unknown Error" }, /* 16 */
784 { false, "UNKNOWN", "Unknown Error" }, /* 17 */
785 { false, "UNKNOWN", "Unknown Error" }, /* 18 */
786 { false, "UNKNOWN", "Unknown Error" }, /* 19 */
787 { false, "UNKNOWN", "Unknown Error" }, /* 20 */
788 { false, "UNKNOWN", "Unknown Error" }, /* 21 */
789 { false, "UNKNOWN", "Unknown Error" }, /* 22 */
790 { false, "UNKNOWN", "Unknown Error" }, /* 23 */
791 { false, "UNKNOWN", "Unknown Error" }, /* 24 */
792 { false, "UNKNOWN", "Unknown Error" }, /* 25 */
793 { false, "UNKNOWN", "Unknown Error" }, /* 26 */
794 { false, "UNKNOWN", "Unknown Error" }, /* 27 */
795 { false, "UNKNOWN", "Unknown Error" }, /* 28 */
796 { false, "UNKNOWN", "Unknown Error" }, /* 29 */
797 { false, "UNKNOWN", "Unknown Error" }, /* 30 */
798 { false, "UNKNOWN", "Unknown Error" }, /* 31 */
799 };
800
dwxgmac3_handle_mtl_err(struct net_device * ndev,void __iomem * ioaddr,bool correctable,struct stmmac_safety_stats * stats)801 static void dwxgmac3_handle_mtl_err(struct net_device *ndev,
802 void __iomem *ioaddr, bool correctable,
803 struct stmmac_safety_stats *stats)
804 {
805 u32 value;
806
807 value = readl(ioaddr + XGMAC_MTL_ECC_INT_STATUS);
808 writel(value, ioaddr + XGMAC_MTL_ECC_INT_STATUS);
809
810 dwxgmac3_log_error(ndev, value, correctable, "MTL",
811 dwxgmac3_mtl_errors, STAT_OFF(mtl_errors), stats);
812 }
813
814 static const struct dwxgmac3_error_desc dwxgmac3_dma_errors[32]= {
815 { true, "TCES", "DMA TSO Memory Error" },
816 { true, "TAMS", "DMA TSO Memory Address Mismatch Error" },
817 { true, "TUES", "DMA TSO Memory Error" },
818 { false, "UNKNOWN", "Unknown Error" }, /* 3 */
819 { true, "DCES", "DMA DCACHE Memory Error" },
820 { true, "DAMS", "DMA DCACHE Address Mismatch Error" },
821 { true, "DUES", "DMA DCACHE Memory Error" },
822 { false, "UNKNOWN", "Unknown Error" }, /* 7 */
823 { false, "UNKNOWN", "Unknown Error" }, /* 8 */
824 { false, "UNKNOWN", "Unknown Error" }, /* 9 */
825 { false, "UNKNOWN", "Unknown Error" }, /* 10 */
826 { false, "UNKNOWN", "Unknown Error" }, /* 11 */
827 { false, "UNKNOWN", "Unknown Error" }, /* 12 */
828 { false, "UNKNOWN", "Unknown Error" }, /* 13 */
829 { false, "UNKNOWN", "Unknown Error" }, /* 14 */
830 { false, "UNKNOWN", "Unknown Error" }, /* 15 */
831 { false, "UNKNOWN", "Unknown Error" }, /* 16 */
832 { false, "UNKNOWN", "Unknown Error" }, /* 17 */
833 { false, "UNKNOWN", "Unknown Error" }, /* 18 */
834 { false, "UNKNOWN", "Unknown Error" }, /* 19 */
835 { false, "UNKNOWN", "Unknown Error" }, /* 20 */
836 { false, "UNKNOWN", "Unknown Error" }, /* 21 */
837 { false, "UNKNOWN", "Unknown Error" }, /* 22 */
838 { false, "UNKNOWN", "Unknown Error" }, /* 23 */
839 { false, "UNKNOWN", "Unknown Error" }, /* 24 */
840 { false, "UNKNOWN", "Unknown Error" }, /* 25 */
841 { false, "UNKNOWN", "Unknown Error" }, /* 26 */
842 { false, "UNKNOWN", "Unknown Error" }, /* 27 */
843 { false, "UNKNOWN", "Unknown Error" }, /* 28 */
844 { false, "UNKNOWN", "Unknown Error" }, /* 29 */
845 { false, "UNKNOWN", "Unknown Error" }, /* 30 */
846 { false, "UNKNOWN", "Unknown Error" }, /* 31 */
847 };
848
849 #define DPP_RX_ERR "Read Rx Descriptor Parity checker Error"
850 #define DPP_TX_ERR "Read Tx Descriptor Parity checker Error"
851
852 static const struct dwxgmac3_error_desc dwxgmac3_dma_dpp_errors[32] = {
853 { true, "TDPES0", DPP_TX_ERR },
854 { true, "TDPES1", DPP_TX_ERR },
855 { true, "TDPES2", DPP_TX_ERR },
856 { true, "TDPES3", DPP_TX_ERR },
857 { true, "TDPES4", DPP_TX_ERR },
858 { true, "TDPES5", DPP_TX_ERR },
859 { true, "TDPES6", DPP_TX_ERR },
860 { true, "TDPES7", DPP_TX_ERR },
861 { true, "TDPES8", DPP_TX_ERR },
862 { true, "TDPES9", DPP_TX_ERR },
863 { true, "TDPES10", DPP_TX_ERR },
864 { true, "TDPES11", DPP_TX_ERR },
865 { true, "TDPES12", DPP_TX_ERR },
866 { true, "TDPES13", DPP_TX_ERR },
867 { true, "TDPES14", DPP_TX_ERR },
868 { true, "TDPES15", DPP_TX_ERR },
869 { true, "RDPES0", DPP_RX_ERR },
870 { true, "RDPES1", DPP_RX_ERR },
871 { true, "RDPES2", DPP_RX_ERR },
872 { true, "RDPES3", DPP_RX_ERR },
873 { true, "RDPES4", DPP_RX_ERR },
874 { true, "RDPES5", DPP_RX_ERR },
875 { true, "RDPES6", DPP_RX_ERR },
876 { true, "RDPES7", DPP_RX_ERR },
877 { true, "RDPES8", DPP_RX_ERR },
878 { true, "RDPES9", DPP_RX_ERR },
879 { true, "RDPES10", DPP_RX_ERR },
880 { true, "RDPES11", DPP_RX_ERR },
881 { true, "RDPES12", DPP_RX_ERR },
882 { true, "RDPES13", DPP_RX_ERR },
883 { true, "RDPES14", DPP_RX_ERR },
884 { true, "RDPES15", DPP_RX_ERR },
885 };
886
dwxgmac3_handle_dma_err(struct net_device * ndev,void __iomem * ioaddr,bool correctable,struct stmmac_safety_stats * stats)887 static void dwxgmac3_handle_dma_err(struct net_device *ndev,
888 void __iomem *ioaddr, bool correctable,
889 struct stmmac_safety_stats *stats)
890 {
891 u32 value;
892
893 value = readl(ioaddr + XGMAC_DMA_ECC_INT_STATUS);
894 writel(value, ioaddr + XGMAC_DMA_ECC_INT_STATUS);
895
896 dwxgmac3_log_error(ndev, value, correctable, "DMA",
897 dwxgmac3_dma_errors, STAT_OFF(dma_errors), stats);
898
899 value = readl(ioaddr + XGMAC_DMA_DPP_INT_STATUS);
900 writel(value, ioaddr + XGMAC_DMA_DPP_INT_STATUS);
901
902 dwxgmac3_log_error(ndev, value, false, "DMA_DPP",
903 dwxgmac3_dma_dpp_errors,
904 STAT_OFF(dma_dpp_errors), stats);
905 }
906
907 static int
dwxgmac3_safety_feat_config(void __iomem * ioaddr,unsigned int asp,struct stmmac_safety_feature_cfg * safety_cfg)908 dwxgmac3_safety_feat_config(void __iomem *ioaddr, unsigned int asp,
909 struct stmmac_safety_feature_cfg *safety_cfg)
910 {
911 u32 value;
912
913 if (!asp)
914 return -EINVAL;
915
916 /* 1. Enable Safety Features */
917 writel(0x0, ioaddr + XGMAC_MTL_ECC_CONTROL);
918
919 /* 2. Enable MTL Safety Interrupts */
920 value = readl(ioaddr + XGMAC_MTL_ECC_INT_ENABLE);
921 value |= XGMAC_RPCEIE; /* RX Parser Memory Correctable Error */
922 value |= XGMAC_ECEIE; /* EST Memory Correctable Error */
923 value |= XGMAC_RXCEIE; /* RX Memory Correctable Error */
924 value |= XGMAC_TXCEIE; /* TX Memory Correctable Error */
925 writel(value, ioaddr + XGMAC_MTL_ECC_INT_ENABLE);
926
927 /* 3. Enable DMA Safety Interrupts */
928 value = readl(ioaddr + XGMAC_DMA_ECC_INT_ENABLE);
929 value |= XGMAC_DCEIE; /* Descriptor Cache Memory Correctable Error */
930 value |= XGMAC_TCEIE; /* TSO Memory Correctable Error */
931 writel(value, ioaddr + XGMAC_DMA_ECC_INT_ENABLE);
932
933 /* 0x2: Without ECC or Parity Ports on External Application Interface
934 * 0x4: Only ECC Protection for External Memory feature is selected
935 */
936 if (asp == 0x2 || asp == 0x4)
937 return 0;
938
939 /* 4. Enable Parity and Timeout for FSM */
940 value = readl(ioaddr + XGMAC_MAC_FSM_CONTROL);
941 value |= XGMAC_PRTYEN; /* FSM Parity Feature */
942 value |= XGMAC_TMOUTEN; /* FSM Timeout Feature */
943 writel(value, ioaddr + XGMAC_MAC_FSM_CONTROL);
944
945 /* 5. Enable Data Path Parity Protection */
946 value = readl(ioaddr + XGMAC_MTL_DPP_CONTROL);
947 /* already enabled by default, explicit enable it again */
948 value &= ~XGMAC_DPP_DISABLE;
949 writel(value, ioaddr + XGMAC_MTL_DPP_CONTROL);
950
951 return 0;
952 }
953
dwxgmac3_safety_feat_irq_status(struct net_device * ndev,void __iomem * ioaddr,unsigned int asp,struct stmmac_safety_stats * stats)954 static int dwxgmac3_safety_feat_irq_status(struct net_device *ndev,
955 void __iomem *ioaddr,
956 unsigned int asp,
957 struct stmmac_safety_stats *stats)
958 {
959 bool err, corr;
960 u32 mtl, dma;
961 int ret = 0;
962
963 if (!asp)
964 return -EINVAL;
965
966 mtl = readl(ioaddr + XGMAC_MTL_SAFETY_INT_STATUS);
967 dma = readl(ioaddr + XGMAC_DMA_SAFETY_INT_STATUS);
968
969 err = (mtl & XGMAC_MCSIS) || (dma & XGMAC_MCSIS);
970 corr = false;
971 if (err) {
972 dwxgmac3_handle_mac_err(ndev, ioaddr, corr, stats);
973 ret |= !corr;
974 }
975
976 err = (mtl & (XGMAC_MEUIS | XGMAC_MECIS)) ||
977 (dma & (XGMAC_MSUIS | XGMAC_MSCIS));
978 corr = (mtl & XGMAC_MECIS) || (dma & XGMAC_MSCIS);
979 if (err) {
980 dwxgmac3_handle_mtl_err(ndev, ioaddr, corr, stats);
981 ret |= !corr;
982 }
983
984 /* DMA_DPP_Interrupt_Status is indicated by MCSIS bit in
985 * DMA_Safety_Interrupt_Status, so we handle DMA Data Path
986 * Parity Errors here
987 */
988 err = dma & (XGMAC_DEUIS | XGMAC_DECIS | XGMAC_MCSIS);
989 corr = dma & XGMAC_DECIS;
990 if (err) {
991 dwxgmac3_handle_dma_err(ndev, ioaddr, corr, stats);
992 ret |= !corr;
993 }
994
995 return ret;
996 }
997
998 static const struct dwxgmac3_error {
999 const struct dwxgmac3_error_desc *desc;
1000 } dwxgmac3_all_errors[] = {
1001 { dwxgmac3_mac_errors },
1002 { dwxgmac3_mtl_errors },
1003 { dwxgmac3_dma_errors },
1004 { dwxgmac3_dma_dpp_errors },
1005 };
1006
dwxgmac3_safety_feat_dump(struct stmmac_safety_stats * stats,int index,unsigned long * count,const char ** desc)1007 static int dwxgmac3_safety_feat_dump(struct stmmac_safety_stats *stats,
1008 int index, unsigned long *count,
1009 const char **desc)
1010 {
1011 int module = index / 32, offset = index % 32;
1012 unsigned long *ptr = (unsigned long *)stats;
1013
1014 if (module >= ARRAY_SIZE(dwxgmac3_all_errors))
1015 return -EINVAL;
1016 if (!dwxgmac3_all_errors[module].desc[offset].valid)
1017 return -EINVAL;
1018 if (count)
1019 *count = *(ptr + index);
1020 if (desc)
1021 *desc = dwxgmac3_all_errors[module].desc[offset].desc;
1022 return 0;
1023 }
1024
dwxgmac3_rxp_disable(void __iomem * ioaddr)1025 static int dwxgmac3_rxp_disable(void __iomem *ioaddr)
1026 {
1027 u32 val = readl(ioaddr + XGMAC_MTL_OPMODE);
1028
1029 val &= ~XGMAC_FRPE;
1030 writel(val, ioaddr + XGMAC_MTL_OPMODE);
1031
1032 return 0;
1033 }
1034
dwxgmac3_rxp_enable(void __iomem * ioaddr)1035 static void dwxgmac3_rxp_enable(void __iomem *ioaddr)
1036 {
1037 u32 val;
1038
1039 val = readl(ioaddr + XGMAC_MTL_OPMODE);
1040 val |= XGMAC_FRPE;
1041 writel(val, ioaddr + XGMAC_MTL_OPMODE);
1042 }
1043
dwxgmac3_rxp_update_single_entry(void __iomem * ioaddr,struct stmmac_tc_entry * entry,int pos)1044 static int dwxgmac3_rxp_update_single_entry(void __iomem *ioaddr,
1045 struct stmmac_tc_entry *entry,
1046 int pos)
1047 {
1048 int ret, i;
1049
1050 for (i = 0; i < (sizeof(entry->val) / sizeof(u32)); i++) {
1051 int real_pos = pos * (sizeof(entry->val) / sizeof(u32)) + i;
1052 u32 val;
1053
1054 /* Wait for ready */
1055 ret = readl_poll_timeout(ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST,
1056 val, !(val & XGMAC_STARTBUSY), 1, 10000);
1057 if (ret)
1058 return ret;
1059
1060 /* Write data */
1061 val = *((u32 *)&entry->val + i);
1062 writel(val, ioaddr + XGMAC_MTL_RXP_IACC_DATA);
1063
1064 /* Write pos */
1065 val = real_pos & XGMAC_ADDR;
1066 writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
1067
1068 /* Write OP */
1069 val |= XGMAC_WRRDN;
1070 writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
1071
1072 /* Start Write */
1073 val |= XGMAC_STARTBUSY;
1074 writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
1075
1076 /* Wait for done */
1077 ret = readl_poll_timeout(ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST,
1078 val, !(val & XGMAC_STARTBUSY), 1, 10000);
1079 if (ret)
1080 return ret;
1081 }
1082
1083 return 0;
1084 }
1085
1086 static struct stmmac_tc_entry *
dwxgmac3_rxp_get_next_entry(struct stmmac_tc_entry * entries,unsigned int count,u32 curr_prio)1087 dwxgmac3_rxp_get_next_entry(struct stmmac_tc_entry *entries,
1088 unsigned int count, u32 curr_prio)
1089 {
1090 struct stmmac_tc_entry *entry;
1091 u32 min_prio = ~0x0;
1092 int i, min_prio_idx;
1093 bool found = false;
1094
1095 for (i = count - 1; i >= 0; i--) {
1096 entry = &entries[i];
1097
1098 /* Do not update unused entries */
1099 if (!entry->in_use)
1100 continue;
1101 /* Do not update already updated entries (i.e. fragments) */
1102 if (entry->in_hw)
1103 continue;
1104 /* Let last entry be updated last */
1105 if (entry->is_last)
1106 continue;
1107 /* Do not return fragments */
1108 if (entry->is_frag)
1109 continue;
1110 /* Check if we already checked this prio */
1111 if (entry->prio < curr_prio)
1112 continue;
1113 /* Check if this is the minimum prio */
1114 if (entry->prio < min_prio) {
1115 min_prio = entry->prio;
1116 min_prio_idx = i;
1117 found = true;
1118 }
1119 }
1120
1121 if (found)
1122 return &entries[min_prio_idx];
1123 return NULL;
1124 }
1125
dwxgmac3_rxp_config(void __iomem * ioaddr,struct stmmac_tc_entry * entries,unsigned int count)1126 static int dwxgmac3_rxp_config(void __iomem *ioaddr,
1127 struct stmmac_tc_entry *entries,
1128 unsigned int count)
1129 {
1130 struct stmmac_tc_entry *entry, *frag;
1131 int i, ret, nve = 0;
1132 u32 curr_prio = 0;
1133 u32 old_val, val;
1134
1135 /* Force disable RX */
1136 old_val = readl(ioaddr + XGMAC_RX_CONFIG);
1137 val = old_val & ~XGMAC_CONFIG_RE;
1138 writel(val, ioaddr + XGMAC_RX_CONFIG);
1139
1140 /* Disable RX Parser */
1141 ret = dwxgmac3_rxp_disable(ioaddr);
1142 if (ret)
1143 goto re_enable;
1144
1145 /* Set all entries as NOT in HW */
1146 for (i = 0; i < count; i++) {
1147 entry = &entries[i];
1148 entry->in_hw = false;
1149 }
1150
1151 /* Update entries by reverse order */
1152 while (1) {
1153 entry = dwxgmac3_rxp_get_next_entry(entries, count, curr_prio);
1154 if (!entry)
1155 break;
1156
1157 curr_prio = entry->prio;
1158 frag = entry->frag_ptr;
1159
1160 /* Set special fragment requirements */
1161 if (frag) {
1162 entry->val.af = 0;
1163 entry->val.rf = 0;
1164 entry->val.nc = 1;
1165 entry->val.ok_index = nve + 2;
1166 }
1167
1168 ret = dwxgmac3_rxp_update_single_entry(ioaddr, entry, nve);
1169 if (ret)
1170 goto re_enable;
1171
1172 entry->table_pos = nve++;
1173 entry->in_hw = true;
1174
1175 if (frag && !frag->in_hw) {
1176 ret = dwxgmac3_rxp_update_single_entry(ioaddr, frag, nve);
1177 if (ret)
1178 goto re_enable;
1179 frag->table_pos = nve++;
1180 frag->in_hw = true;
1181 }
1182 }
1183
1184 if (!nve)
1185 goto re_enable;
1186
1187 /* Update all pass entry */
1188 for (i = 0; i < count; i++) {
1189 entry = &entries[i];
1190 if (!entry->is_last)
1191 continue;
1192
1193 ret = dwxgmac3_rxp_update_single_entry(ioaddr, entry, nve);
1194 if (ret)
1195 goto re_enable;
1196
1197 entry->table_pos = nve++;
1198 }
1199
1200 /* Assume n. of parsable entries == n. of valid entries */
1201 val = (nve << 16) & XGMAC_NPE;
1202 val |= nve & XGMAC_NVE;
1203 writel(val, ioaddr + XGMAC_MTL_RXP_CONTROL_STATUS);
1204
1205 /* Enable RX Parser */
1206 dwxgmac3_rxp_enable(ioaddr);
1207
1208 re_enable:
1209 /* Re-enable RX */
1210 writel(old_val, ioaddr + XGMAC_RX_CONFIG);
1211 return ret;
1212 }
1213
dwxgmac2_get_mac_tx_timestamp(struct mac_device_info * hw,u64 * ts)1214 static int dwxgmac2_get_mac_tx_timestamp(struct mac_device_info *hw, u64 *ts)
1215 {
1216 void __iomem *ioaddr = hw->pcsr;
1217 u32 value;
1218
1219 if (readl_poll_timeout_atomic(ioaddr + XGMAC_TIMESTAMP_STATUS,
1220 value, value & XGMAC_TXTSC, 100, 10000))
1221 return -EBUSY;
1222
1223 *ts = readl(ioaddr + XGMAC_TXTIMESTAMP_NSEC) & XGMAC_TXTSSTSLO;
1224 *ts += readl(ioaddr + XGMAC_TXTIMESTAMP_SEC) * 1000000000ULL;
1225 return 0;
1226 }
1227
dwxgmac2_flex_pps_config(void __iomem * ioaddr,int index,struct stmmac_pps_cfg * cfg,bool enable,u32 sub_second_inc,u32 systime_flags)1228 static int dwxgmac2_flex_pps_config(void __iomem *ioaddr, int index,
1229 struct stmmac_pps_cfg *cfg, bool enable,
1230 u32 sub_second_inc, u32 systime_flags)
1231 {
1232 u32 tnsec = readl(ioaddr + XGMAC_PPSx_TARGET_TIME_NSEC(index));
1233 u32 val = readl(ioaddr + XGMAC_PPS_CONTROL);
1234 u64 period;
1235
1236 if (!cfg->available)
1237 return -EINVAL;
1238 if (tnsec & XGMAC_TRGTBUSY0)
1239 return -EBUSY;
1240 if (!sub_second_inc || !systime_flags)
1241 return -EINVAL;
1242
1243 val &= ~XGMAC_PPSx_MASK(index);
1244
1245 if (!enable) {
1246 val |= XGMAC_PPSCMDx(index, XGMAC_PPSCMD_STOP);
1247 writel(val, ioaddr + XGMAC_PPS_CONTROL);
1248 return 0;
1249 }
1250
1251 val |= XGMAC_PPSCMDx(index, XGMAC_PPSCMD_START);
1252 val |= XGMAC_TRGTMODSELx(index, XGMAC_PPSCMD_START);
1253
1254 /* XGMAC Core has 4 PPS outputs at most.
1255 *
1256 * Prior XGMAC Core 3.20, Fixed mode or Flexible mode are selectable for
1257 * PPS0 only via PPSEN0. PPS{1,2,3} are in Flexible mode by default,
1258 * and can not be switched to Fixed mode, since PPSEN{1,2,3} are
1259 * read-only reserved to 0.
1260 * But we always set PPSEN{1,2,3} do not make things worse ;-)
1261 *
1262 * From XGMAC Core 3.20 and later, PPSEN{0,1,2,3} are writable and must
1263 * be set, or the PPS outputs stay in Fixed PPS mode by default.
1264 */
1265 val |= XGMAC_PPSENx(index);
1266
1267 writel(cfg->start.tv_sec, ioaddr + XGMAC_PPSx_TARGET_TIME_SEC(index));
1268
1269 if (!(systime_flags & PTP_TCR_TSCTRLSSR))
1270 cfg->start.tv_nsec = (cfg->start.tv_nsec * 1000) / 465;
1271 writel(cfg->start.tv_nsec, ioaddr + XGMAC_PPSx_TARGET_TIME_NSEC(index));
1272
1273 period = cfg->period.tv_sec * 1000000000;
1274 period += cfg->period.tv_nsec;
1275
1276 do_div(period, sub_second_inc);
1277
1278 if (period <= 1)
1279 return -EINVAL;
1280
1281 writel(period - 1, ioaddr + XGMAC_PPSx_INTERVAL(index));
1282
1283 period >>= 1;
1284 if (period <= 1)
1285 return -EINVAL;
1286
1287 writel(period - 1, ioaddr + XGMAC_PPSx_WIDTH(index));
1288
1289 /* Finally, activate it */
1290 writel(val, ioaddr + XGMAC_PPS_CONTROL);
1291 return 0;
1292 }
1293
dwxgmac2_sarc_configure(void __iomem * ioaddr,int val)1294 static void dwxgmac2_sarc_configure(void __iomem *ioaddr, int val)
1295 {
1296 u32 value = readl(ioaddr + XGMAC_TX_CONFIG);
1297
1298 value &= ~XGMAC_CONFIG_SARC;
1299 value |= val << XGMAC_CONFIG_SARC_SHIFT;
1300
1301 writel(value, ioaddr + XGMAC_TX_CONFIG);
1302 }
1303
dwxgmac2_enable_vlan(struct mac_device_info * hw,u32 type)1304 static void dwxgmac2_enable_vlan(struct mac_device_info *hw, u32 type)
1305 {
1306 void __iomem *ioaddr = hw->pcsr;
1307 u32 value;
1308
1309 value = readl(ioaddr + XGMAC_VLAN_INCL);
1310 value |= XGMAC_VLAN_VLTI;
1311 value |= XGMAC_VLAN_CSVL; /* Only use SVLAN */
1312 value &= ~XGMAC_VLAN_VLC;
1313 value |= (type << XGMAC_VLAN_VLC_SHIFT) & XGMAC_VLAN_VLC;
1314 writel(value, ioaddr + XGMAC_VLAN_INCL);
1315 }
1316
dwxgmac2_filter_wait(struct mac_device_info * hw)1317 static int dwxgmac2_filter_wait(struct mac_device_info *hw)
1318 {
1319 void __iomem *ioaddr = hw->pcsr;
1320 u32 value;
1321
1322 if (readl_poll_timeout(ioaddr + XGMAC_L3L4_ADDR_CTRL, value,
1323 !(value & XGMAC_XB), 100, 10000))
1324 return -EBUSY;
1325 return 0;
1326 }
1327
dwxgmac2_filter_read(struct mac_device_info * hw,u32 filter_no,u8 reg,u32 * data)1328 static int dwxgmac2_filter_read(struct mac_device_info *hw, u32 filter_no,
1329 u8 reg, u32 *data)
1330 {
1331 void __iomem *ioaddr = hw->pcsr;
1332 u32 value;
1333 int ret;
1334
1335 ret = dwxgmac2_filter_wait(hw);
1336 if (ret)
1337 return ret;
1338
1339 value = ((filter_no << XGMAC_IDDR_FNUM) | reg) << XGMAC_IDDR_SHIFT;
1340 value |= XGMAC_TT | XGMAC_XB;
1341 writel(value, ioaddr + XGMAC_L3L4_ADDR_CTRL);
1342
1343 ret = dwxgmac2_filter_wait(hw);
1344 if (ret)
1345 return ret;
1346
1347 *data = readl(ioaddr + XGMAC_L3L4_DATA);
1348 return 0;
1349 }
1350
dwxgmac2_filter_write(struct mac_device_info * hw,u32 filter_no,u8 reg,u32 data)1351 static int dwxgmac2_filter_write(struct mac_device_info *hw, u32 filter_no,
1352 u8 reg, u32 data)
1353 {
1354 void __iomem *ioaddr = hw->pcsr;
1355 u32 value;
1356 int ret;
1357
1358 ret = dwxgmac2_filter_wait(hw);
1359 if (ret)
1360 return ret;
1361
1362 writel(data, ioaddr + XGMAC_L3L4_DATA);
1363
1364 value = ((filter_no << XGMAC_IDDR_FNUM) | reg) << XGMAC_IDDR_SHIFT;
1365 value |= XGMAC_XB;
1366 writel(value, ioaddr + XGMAC_L3L4_ADDR_CTRL);
1367
1368 return dwxgmac2_filter_wait(hw);
1369 }
1370
dwxgmac2_config_l3_filter(struct mac_device_info * hw,u32 filter_no,bool en,bool ipv6,bool sa,bool inv,u32 match)1371 static int dwxgmac2_config_l3_filter(struct mac_device_info *hw, u32 filter_no,
1372 bool en, bool ipv6, bool sa, bool inv,
1373 u32 match)
1374 {
1375 void __iomem *ioaddr = hw->pcsr;
1376 u32 value;
1377 int ret;
1378
1379 value = readl(ioaddr + XGMAC_PACKET_FILTER);
1380 value |= XGMAC_FILTER_IPFE;
1381 writel(value, ioaddr + XGMAC_PACKET_FILTER);
1382
1383 ret = dwxgmac2_filter_read(hw, filter_no, XGMAC_L3L4_CTRL, &value);
1384 if (ret)
1385 return ret;
1386
1387 /* For IPv6 not both SA/DA filters can be active */
1388 if (ipv6) {
1389 value |= XGMAC_L3PEN0;
1390 value &= ~(XGMAC_L3SAM0 | XGMAC_L3SAIM0);
1391 value &= ~(XGMAC_L3DAM0 | XGMAC_L3DAIM0);
1392 if (sa) {
1393 value |= XGMAC_L3SAM0;
1394 if (inv)
1395 value |= XGMAC_L3SAIM0;
1396 } else {
1397 value |= XGMAC_L3DAM0;
1398 if (inv)
1399 value |= XGMAC_L3DAIM0;
1400 }
1401 } else {
1402 value &= ~XGMAC_L3PEN0;
1403 if (sa) {
1404 value |= XGMAC_L3SAM0;
1405 if (inv)
1406 value |= XGMAC_L3SAIM0;
1407 } else {
1408 value |= XGMAC_L3DAM0;
1409 if (inv)
1410 value |= XGMAC_L3DAIM0;
1411 }
1412 }
1413
1414 ret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, value);
1415 if (ret)
1416 return ret;
1417
1418 if (sa) {
1419 ret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3_ADDR0, match);
1420 if (ret)
1421 return ret;
1422 } else {
1423 ret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3_ADDR1, match);
1424 if (ret)
1425 return ret;
1426 }
1427
1428 if (!en)
1429 return dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, 0);
1430
1431 return 0;
1432 }
1433
dwxgmac2_config_l4_filter(struct mac_device_info * hw,u32 filter_no,bool en,bool udp,bool sa,bool inv,u32 match)1434 static int dwxgmac2_config_l4_filter(struct mac_device_info *hw, u32 filter_no,
1435 bool en, bool udp, bool sa, bool inv,
1436 u32 match)
1437 {
1438 void __iomem *ioaddr = hw->pcsr;
1439 u32 value;
1440 int ret;
1441
1442 value = readl(ioaddr + XGMAC_PACKET_FILTER);
1443 value |= XGMAC_FILTER_IPFE;
1444 writel(value, ioaddr + XGMAC_PACKET_FILTER);
1445
1446 ret = dwxgmac2_filter_read(hw, filter_no, XGMAC_L3L4_CTRL, &value);
1447 if (ret)
1448 return ret;
1449
1450 if (udp) {
1451 value |= XGMAC_L4PEN0;
1452 } else {
1453 value &= ~XGMAC_L4PEN0;
1454 }
1455
1456 value &= ~(XGMAC_L4SPM0 | XGMAC_L4SPIM0);
1457 value &= ~(XGMAC_L4DPM0 | XGMAC_L4DPIM0);
1458 if (sa) {
1459 value |= XGMAC_L4SPM0;
1460 if (inv)
1461 value |= XGMAC_L4SPIM0;
1462 } else {
1463 value |= XGMAC_L4DPM0;
1464 if (inv)
1465 value |= XGMAC_L4DPIM0;
1466 }
1467
1468 ret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, value);
1469 if (ret)
1470 return ret;
1471
1472 if (sa) {
1473 value = match & XGMAC_L4SP0;
1474
1475 ret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L4_ADDR, value);
1476 if (ret)
1477 return ret;
1478 } else {
1479 value = (match << XGMAC_L4DP0_SHIFT) & XGMAC_L4DP0;
1480
1481 ret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L4_ADDR, value);
1482 if (ret)
1483 return ret;
1484 }
1485
1486 if (!en)
1487 return dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, 0);
1488
1489 return 0;
1490 }
1491
dwxgmac2_set_arp_offload(struct mac_device_info * hw,bool en,u32 addr)1492 static void dwxgmac2_set_arp_offload(struct mac_device_info *hw, bool en,
1493 u32 addr)
1494 {
1495 void __iomem *ioaddr = hw->pcsr;
1496 u32 value;
1497
1498 writel(addr, ioaddr + XGMAC_ARP_ADDR);
1499
1500 value = readl(ioaddr + XGMAC_RX_CONFIG);
1501 if (en)
1502 value |= XGMAC_CONFIG_ARPEN;
1503 else
1504 value &= ~XGMAC_CONFIG_ARPEN;
1505 writel(value, ioaddr + XGMAC_RX_CONFIG);
1506 }
1507
dwxgmac3_est_write(void __iomem * ioaddr,u32 reg,u32 val,bool gcl)1508 static int dwxgmac3_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl)
1509 {
1510 u32 ctrl;
1511
1512 writel(val, ioaddr + XGMAC_MTL_EST_GCL_DATA);
1513
1514 ctrl = (reg << XGMAC_ADDR_SHIFT);
1515 ctrl |= gcl ? 0 : XGMAC_GCRR;
1516
1517 writel(ctrl, ioaddr + XGMAC_MTL_EST_GCL_CONTROL);
1518
1519 ctrl |= XGMAC_SRWO;
1520 writel(ctrl, ioaddr + XGMAC_MTL_EST_GCL_CONTROL);
1521
1522 return readl_poll_timeout_atomic(ioaddr + XGMAC_MTL_EST_GCL_CONTROL,
1523 ctrl, !(ctrl & XGMAC_SRWO), 100, 5000);
1524 }
1525
dwxgmac3_est_configure(void __iomem * ioaddr,struct stmmac_est * cfg,unsigned int ptp_rate)1526 static int dwxgmac3_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
1527 unsigned int ptp_rate)
1528 {
1529 int i, ret = 0x0;
1530 u32 ctrl;
1531
1532 ret |= dwxgmac3_est_write(ioaddr, XGMAC_BTR_LOW, cfg->btr[0], false);
1533 ret |= dwxgmac3_est_write(ioaddr, XGMAC_BTR_HIGH, cfg->btr[1], false);
1534 ret |= dwxgmac3_est_write(ioaddr, XGMAC_TER, cfg->ter, false);
1535 ret |= dwxgmac3_est_write(ioaddr, XGMAC_LLR, cfg->gcl_size, false);
1536 ret |= dwxgmac3_est_write(ioaddr, XGMAC_CTR_LOW, cfg->ctr[0], false);
1537 ret |= dwxgmac3_est_write(ioaddr, XGMAC_CTR_HIGH, cfg->ctr[1], false);
1538 if (ret)
1539 return ret;
1540
1541 for (i = 0; i < cfg->gcl_size; i++) {
1542 ret = dwxgmac3_est_write(ioaddr, i, cfg->gcl[i], true);
1543 if (ret)
1544 return ret;
1545 }
1546
1547 ctrl = readl(ioaddr + XGMAC_MTL_EST_CONTROL);
1548 ctrl &= ~XGMAC_PTOV;
1549 ctrl |= ((1000000000 / ptp_rate) * 9) << XGMAC_PTOV_SHIFT;
1550 if (cfg->enable)
1551 ctrl |= XGMAC_EEST | XGMAC_SSWL;
1552 else
1553 ctrl &= ~XGMAC_EEST;
1554
1555 writel(ctrl, ioaddr + XGMAC_MTL_EST_CONTROL);
1556 return 0;
1557 }
1558
dwxgmac3_fpe_configure(void __iomem * ioaddr,struct stmmac_fpe_cfg * cfg,u32 num_txq,u32 num_rxq,bool enable)1559 static void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
1560 u32 num_txq,
1561 u32 num_rxq, bool enable)
1562 {
1563 u32 value;
1564
1565 if (!enable) {
1566 value = readl(ioaddr + XGMAC_FPE_CTRL_STS);
1567
1568 value &= ~XGMAC_EFPE;
1569
1570 writel(value, ioaddr + XGMAC_FPE_CTRL_STS);
1571 return;
1572 }
1573
1574 value = readl(ioaddr + XGMAC_RXQ_CTRL1);
1575 value &= ~XGMAC_RQ;
1576 value |= (num_rxq - 1) << XGMAC_RQ_SHIFT;
1577 writel(value, ioaddr + XGMAC_RXQ_CTRL1);
1578
1579 value = readl(ioaddr + XGMAC_FPE_CTRL_STS);
1580 value |= XGMAC_EFPE;
1581 writel(value, ioaddr + XGMAC_FPE_CTRL_STS);
1582 }
1583
1584 const struct stmmac_ops dwxgmac210_ops = {
1585 .core_init = dwxgmac2_core_init,
1586 .set_mac = dwxgmac2_set_mac,
1587 .rx_ipc = dwxgmac2_rx_ipc,
1588 .rx_queue_enable = dwxgmac2_rx_queue_enable,
1589 .rx_queue_prio = dwxgmac2_rx_queue_prio,
1590 .tx_queue_prio = dwxgmac2_tx_queue_prio,
1591 .rx_queue_routing = dwxgmac2_rx_queue_routing,
1592 .prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,
1593 .prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,
1594 .set_mtl_tx_queue_weight = dwxgmac2_set_mtl_tx_queue_weight,
1595 .map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,
1596 .config_cbs = dwxgmac2_config_cbs,
1597 .dump_regs = dwxgmac2_dump_regs,
1598 .host_irq_status = dwxgmac2_host_irq_status,
1599 .host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,
1600 .flow_ctrl = dwxgmac2_flow_ctrl,
1601 .pmt = dwxgmac2_pmt,
1602 .set_umac_addr = dwxgmac2_set_umac_addr,
1603 .get_umac_addr = dwxgmac2_get_umac_addr,
1604 .set_eee_mode = dwxgmac2_set_eee_mode,
1605 .reset_eee_mode = dwxgmac2_reset_eee_mode,
1606 .set_eee_timer = dwxgmac2_set_eee_timer,
1607 .set_eee_pls = dwxgmac2_set_eee_pls,
1608 .pcs_ctrl_ane = NULL,
1609 .pcs_rane = NULL,
1610 .pcs_get_adv_lp = NULL,
1611 .debug = NULL,
1612 .set_filter = dwxgmac2_set_filter,
1613 .safety_feat_config = dwxgmac3_safety_feat_config,
1614 .safety_feat_irq_status = dwxgmac3_safety_feat_irq_status,
1615 .safety_feat_dump = dwxgmac3_safety_feat_dump,
1616 .set_mac_loopback = dwxgmac2_set_mac_loopback,
1617 .rss_configure = dwxgmac2_rss_configure,
1618 .update_vlan_hash = dwxgmac2_update_vlan_hash,
1619 .rxp_config = dwxgmac3_rxp_config,
1620 .get_mac_tx_timestamp = dwxgmac2_get_mac_tx_timestamp,
1621 .flex_pps_config = dwxgmac2_flex_pps_config,
1622 .sarc_configure = dwxgmac2_sarc_configure,
1623 .enable_vlan = dwxgmac2_enable_vlan,
1624 .config_l3_filter = dwxgmac2_config_l3_filter,
1625 .config_l4_filter = dwxgmac2_config_l4_filter,
1626 .set_arp_offload = dwxgmac2_set_arp_offload,
1627 .est_configure = dwxgmac3_est_configure,
1628 .fpe_configure = dwxgmac3_fpe_configure,
1629 };
1630
dwxlgmac2_rx_queue_enable(struct mac_device_info * hw,u8 mode,u32 queue)1631 static void dwxlgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode,
1632 u32 queue)
1633 {
1634 void __iomem *ioaddr = hw->pcsr;
1635 u32 value;
1636
1637 value = readl(ioaddr + XLGMAC_RXQ_ENABLE_CTRL0) & ~XGMAC_RXQEN(queue);
1638 if (mode == MTL_QUEUE_AVB)
1639 value |= 0x1 << XGMAC_RXQEN_SHIFT(queue);
1640 else if (mode == MTL_QUEUE_DCB)
1641 value |= 0x2 << XGMAC_RXQEN_SHIFT(queue);
1642 writel(value, ioaddr + XLGMAC_RXQ_ENABLE_CTRL0);
1643 }
1644
1645 const struct stmmac_ops dwxlgmac2_ops = {
1646 .core_init = dwxgmac2_core_init,
1647 .set_mac = dwxgmac2_set_mac,
1648 .rx_ipc = dwxgmac2_rx_ipc,
1649 .rx_queue_enable = dwxlgmac2_rx_queue_enable,
1650 .rx_queue_prio = dwxgmac2_rx_queue_prio,
1651 .tx_queue_prio = dwxgmac2_tx_queue_prio,
1652 .rx_queue_routing = dwxgmac2_rx_queue_routing,
1653 .prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,
1654 .prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,
1655 .set_mtl_tx_queue_weight = dwxgmac2_set_mtl_tx_queue_weight,
1656 .map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,
1657 .config_cbs = dwxgmac2_config_cbs,
1658 .dump_regs = dwxgmac2_dump_regs,
1659 .host_irq_status = dwxgmac2_host_irq_status,
1660 .host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,
1661 .flow_ctrl = dwxgmac2_flow_ctrl,
1662 .pmt = dwxgmac2_pmt,
1663 .set_umac_addr = dwxgmac2_set_umac_addr,
1664 .get_umac_addr = dwxgmac2_get_umac_addr,
1665 .set_eee_mode = dwxgmac2_set_eee_mode,
1666 .reset_eee_mode = dwxgmac2_reset_eee_mode,
1667 .set_eee_timer = dwxgmac2_set_eee_timer,
1668 .set_eee_pls = dwxgmac2_set_eee_pls,
1669 .pcs_ctrl_ane = NULL,
1670 .pcs_rane = NULL,
1671 .pcs_get_adv_lp = NULL,
1672 .debug = NULL,
1673 .set_filter = dwxgmac2_set_filter,
1674 .safety_feat_config = dwxgmac3_safety_feat_config,
1675 .safety_feat_irq_status = dwxgmac3_safety_feat_irq_status,
1676 .safety_feat_dump = dwxgmac3_safety_feat_dump,
1677 .set_mac_loopback = dwxgmac2_set_mac_loopback,
1678 .rss_configure = dwxgmac2_rss_configure,
1679 .update_vlan_hash = dwxgmac2_update_vlan_hash,
1680 .rxp_config = dwxgmac3_rxp_config,
1681 .get_mac_tx_timestamp = dwxgmac2_get_mac_tx_timestamp,
1682 .flex_pps_config = dwxgmac2_flex_pps_config,
1683 .sarc_configure = dwxgmac2_sarc_configure,
1684 .enable_vlan = dwxgmac2_enable_vlan,
1685 .config_l3_filter = dwxgmac2_config_l3_filter,
1686 .config_l4_filter = dwxgmac2_config_l4_filter,
1687 .set_arp_offload = dwxgmac2_set_arp_offload,
1688 .est_configure = dwxgmac3_est_configure,
1689 .fpe_configure = dwxgmac3_fpe_configure,
1690 };
1691
dwxgmac2_setup(struct stmmac_priv * priv)1692 int dwxgmac2_setup(struct stmmac_priv *priv)
1693 {
1694 struct mac_device_info *mac = priv->hw;
1695
1696 dev_info(priv->device, "\tXGMAC2\n");
1697
1698 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1699 mac->pcsr = priv->ioaddr;
1700 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
1701 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
1702 mac->mcast_bits_log2 = 0;
1703
1704 if (mac->multicast_filter_bins)
1705 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
1706
1707 mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1708 MAC_1000FD | MAC_2500FD | MAC_5000FD |
1709 MAC_10000FD;
1710 mac->link.duplex = 0;
1711 mac->link.speed10 = XGMAC_CONFIG_SS_10_MII;
1712 mac->link.speed100 = XGMAC_CONFIG_SS_100_MII;
1713 mac->link.speed1000 = XGMAC_CONFIG_SS_1000_GMII;
1714 mac->link.speed2500 = XGMAC_CONFIG_SS_2500_GMII;
1715 mac->link.xgmii.speed2500 = XGMAC_CONFIG_SS_2500;
1716 mac->link.xgmii.speed5000 = XGMAC_CONFIG_SS_5000;
1717 mac->link.xgmii.speed10000 = XGMAC_CONFIG_SS_10000;
1718 mac->link.speed_mask = XGMAC_CONFIG_SS_MASK;
1719
1720 mac->mii.addr = XGMAC_MDIO_ADDR;
1721 mac->mii.data = XGMAC_MDIO_DATA;
1722 mac->mii.addr_shift = 16;
1723 mac->mii.addr_mask = GENMASK(20, 16);
1724 mac->mii.reg_shift = 0;
1725 mac->mii.reg_mask = GENMASK(15, 0);
1726 mac->mii.clk_csr_shift = 19;
1727 mac->mii.clk_csr_mask = GENMASK(21, 19);
1728
1729 return 0;
1730 }
1731
dwxlgmac2_setup(struct stmmac_priv * priv)1732 int dwxlgmac2_setup(struct stmmac_priv *priv)
1733 {
1734 struct mac_device_info *mac = priv->hw;
1735
1736 dev_info(priv->device, "\tXLGMAC\n");
1737
1738 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1739 mac->pcsr = priv->ioaddr;
1740 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
1741 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
1742 mac->mcast_bits_log2 = 0;
1743
1744 if (mac->multicast_filter_bins)
1745 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
1746
1747 mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1748 MAC_1000FD | MAC_2500FD | MAC_5000FD |
1749 MAC_10000FD | MAC_25000FD |
1750 MAC_40000FD | MAC_50000FD |
1751 MAC_100000FD;
1752 mac->link.duplex = 0;
1753 mac->link.speed1000 = XLGMAC_CONFIG_SS_1000;
1754 mac->link.speed2500 = XLGMAC_CONFIG_SS_2500;
1755 mac->link.xgmii.speed10000 = XLGMAC_CONFIG_SS_10G;
1756 mac->link.xlgmii.speed25000 = XLGMAC_CONFIG_SS_25G;
1757 mac->link.xlgmii.speed40000 = XLGMAC_CONFIG_SS_40G;
1758 mac->link.xlgmii.speed50000 = XLGMAC_CONFIG_SS_50G;
1759 mac->link.xlgmii.speed100000 = XLGMAC_CONFIG_SS_100G;
1760 mac->link.speed_mask = XLGMAC_CONFIG_SS;
1761
1762 mac->mii.addr = XGMAC_MDIO_ADDR;
1763 mac->mii.data = XGMAC_MDIO_DATA;
1764 mac->mii.addr_shift = 16;
1765 mac->mii.addr_mask = GENMASK(20, 16);
1766 mac->mii.reg_shift = 0;
1767 mac->mii.reg_mask = GENMASK(15, 0);
1768 mac->mii.clk_csr_shift = 19;
1769 mac->mii.clk_csr_mask = GENMASK(21, 19);
1770
1771 return 0;
1772 }
1773