1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dwc3-pci.c - PCI Specific glue layer
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/dmi.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/slab.h>
15 #include <linux/pci.h>
16 #include <linux/workqueue.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/platform_device.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/gpio/machine.h>
21 #include <linux/acpi.h>
22 #include <linux/delay.h>
23
24 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37
25 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
26 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7
27 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
28 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130
29 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
30 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
31 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa
32 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
33 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee
34 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee
35 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa
36 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
37 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
38 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0
39 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
40 #define PCI_DEVICE_ID_INTEL_EHL 0x4b7e
41 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee
42 #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee
43 #define PCI_DEVICE_ID_INTEL_JSP 0x4dee
44 #define PCI_DEVICE_ID_INTEL_ADL 0x460e
45 #define PCI_DEVICE_ID_INTEL_ADL_PCH 0x51ee
46 #define PCI_DEVICE_ID_INTEL_ADLN 0x465e
47 #define PCI_DEVICE_ID_INTEL_ADLN_PCH 0x54ee
48 #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1
49 #define PCI_DEVICE_ID_INTEL_RPL 0xa70e
50 #define PCI_DEVICE_ID_INTEL_RPLS 0x7a61
51 #define PCI_DEVICE_ID_INTEL_MTLM 0x7eb1
52 #define PCI_DEVICE_ID_INTEL_MTLP 0x7ec1
53 #define PCI_DEVICE_ID_INTEL_MTLS 0x7f6f
54 #define PCI_DEVICE_ID_INTEL_MTL 0x7e7e
55 #define PCI_DEVICE_ID_INTEL_ARLH_PCH 0x777e
56 #define PCI_DEVICE_ID_INTEL_TGL 0x9a15
57 #define PCI_DEVICE_ID_INTEL_PTLH 0xe332
58 #define PCI_DEVICE_ID_INTEL_PTLH_PCH 0xe37e
59 #define PCI_DEVICE_ID_INTEL_PTLU 0xe432
60 #define PCI_DEVICE_ID_INTEL_PTLU_PCH 0xe47e
61 #define PCI_DEVICE_ID_AMD_MR 0x163a
62
63 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
64 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4
65 #define PCI_INTEL_BXT_STATE_D0 0
66 #define PCI_INTEL_BXT_STATE_D3 3
67
68 #define GP_RWBAR 1
69 #define GP_RWREG1 0xa0
70 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
71
72 /**
73 * struct dwc3_pci - Driver private structure
74 * @dwc3: child dwc3 platform_device
75 * @pci: our link to PCI bus
76 * @guid: _DSM GUID
77 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
78 * @wakeup_work: work for asynchronous resume
79 */
80 struct dwc3_pci {
81 struct platform_device *dwc3;
82 struct pci_dev *pci;
83
84 guid_t guid;
85
86 unsigned int has_dsm_for_pm:1;
87 struct work_struct wakeup_work;
88 };
89
90 static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
91 static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
92
93 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
94 { "reset-gpios", &reset_gpios, 1 },
95 { "cs-gpios", &cs_gpios, 1 },
96 { },
97 };
98
99 static struct gpiod_lookup_table platform_bytcr_gpios = {
100 .dev_id = "0000:00:16.0",
101 .table = {
102 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH),
103 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH),
104 {}
105 },
106 };
107
dwc3_byt_enable_ulpi_refclock(struct pci_dev * pci)108 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
109 {
110 void __iomem *reg;
111 u32 value;
112
113 reg = pcim_iomap(pci, GP_RWBAR, 0);
114 if (!reg)
115 return -ENOMEM;
116
117 value = readl(reg + GP_RWREG1);
118 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
119 goto unmap; /* ULPI refclk already enabled */
120
121 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
122 writel(value, reg + GP_RWREG1);
123 /* This comes from the Intel Android x86 tree w/o any explanation */
124 msleep(100);
125 unmap:
126 pcim_iounmap(pci, reg);
127 return 0;
128 }
129
130 static const struct property_entry dwc3_pci_intel_properties[] = {
131 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
132 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
133 {}
134 };
135
136 static const struct property_entry dwc3_pci_intel_phy_charger_detect_properties[] = {
137 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
138 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
139 PROPERTY_ENTRY_BOOL("linux,phy_charger_detect"),
140 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
141 {}
142 };
143
144 static const struct property_entry dwc3_pci_intel_byt_properties[] = {
145 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
146 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
147 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
148 {}
149 };
150
151 /*
152 * Intel Merrifield SoC uses these endpoints for tracing and they cannot
153 * be re-allocated if being used because the side band flow control signals
154 * are hard wired to certain endpoints:
155 * - 1 High BW Bulk IN (IN#1) (RTIT)
156 * - 1 1KB BW Bulk IN (IN#8) + 1 1KB BW Bulk OUT (Run Control) (OUT#8)
157 */
158 static const u8 dwc3_pci_mrfld_reserved_endpoints[] = { 3, 16, 17 };
159
160 static const struct property_entry dwc3_pci_mrfld_properties[] = {
161 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
162 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
163 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
164 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
165 PROPERTY_ENTRY_U8_ARRAY("snps,reserved-endpoints", dwc3_pci_mrfld_reserved_endpoints),
166 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
167 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
168 {}
169 };
170
171 static const struct property_entry dwc3_pci_amd_properties[] = {
172 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
173 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
174 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
175 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
176 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
177 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
178 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
179 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
180 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
181 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
182 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
183 /* FIXME these quirks should be removed when AMD NL tapes out */
184 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
185 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
186 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
187 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
188 {}
189 };
190
191 static const struct property_entry dwc3_pci_mr_properties[] = {
192 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
193 PROPERTY_ENTRY_BOOL("usb-role-switch"),
194 PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"),
195 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
196 {}
197 };
198
199 static const struct software_node dwc3_pci_intel_swnode = {
200 .properties = dwc3_pci_intel_properties,
201 };
202
203 static const struct software_node dwc3_pci_intel_phy_charger_detect_swnode = {
204 .properties = dwc3_pci_intel_phy_charger_detect_properties,
205 };
206
207 static const struct software_node dwc3_pci_intel_byt_swnode = {
208 .properties = dwc3_pci_intel_byt_properties,
209 };
210
211 static const struct software_node dwc3_pci_intel_mrfld_swnode = {
212 .properties = dwc3_pci_mrfld_properties,
213 };
214
215 static const struct software_node dwc3_pci_amd_swnode = {
216 .properties = dwc3_pci_amd_properties,
217 };
218
219 static const struct software_node dwc3_pci_amd_mr_swnode = {
220 .properties = dwc3_pci_mr_properties,
221 };
222
dwc3_pci_quirks(struct dwc3_pci * dwc,const struct software_node * swnode)223 static int dwc3_pci_quirks(struct dwc3_pci *dwc,
224 const struct software_node *swnode)
225 {
226 struct pci_dev *pdev = dwc->pci;
227
228 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
229 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
230 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
231 pdev->device == PCI_DEVICE_ID_INTEL_EHL) {
232 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
233 dwc->has_dsm_for_pm = true;
234 }
235
236 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
237 struct gpio_desc *gpio;
238 const char *bios_ver;
239 int ret;
240
241 /* On BYT the FW does not always enable the refclock */
242 ret = dwc3_byt_enable_ulpi_refclock(pdev);
243 if (ret)
244 return ret;
245
246 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
247 acpi_dwc3_byt_gpios);
248 if (ret)
249 dev_dbg(&pdev->dev, "failed to add mapping table\n");
250
251 /*
252 * A lot of BYT devices lack ACPI resource entries for
253 * the GPIOs. If the ACPI entry for the GPIO controller
254 * is present add a fallback mapping to the reference
255 * design GPIOs which all boards seem to use.
256 */
257 if (acpi_dev_present("INT33FC", NULL, -1))
258 gpiod_add_lookup_table(&platform_bytcr_gpios);
259
260 /*
261 * These GPIOs will turn on the USB2 PHY. Note that we have to
262 * put the gpio descriptors again here because the phy driver
263 * might want to grab them, too.
264 */
265 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
266 if (IS_ERR(gpio))
267 return PTR_ERR(gpio);
268
269 gpiod_set_value_cansleep(gpio, 1);
270 gpiod_put(gpio);
271
272 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
273 if (IS_ERR(gpio))
274 return PTR_ERR(gpio);
275
276 if (gpio) {
277 gpiod_set_value_cansleep(gpio, 1);
278 gpiod_put(gpio);
279 usleep_range(10000, 11000);
280 }
281
282 /*
283 * Make the pdev name predictable (only 1 DWC3 on BYT)
284 * and patch the phy dev-name into the lookup table so
285 * that the phy-driver can get the GPIOs.
286 */
287 dwc->dwc3->id = PLATFORM_DEVID_NONE;
288 platform_bytcr_gpios.dev_id = "dwc3.ulpi";
289
290 /*
291 * Some Android tablets with a Crystal Cove PMIC
292 * (INT33FD), rely on the TUSB1211 phy for charger
293 * detection. These can be identified by them _not_
294 * using the standard ACPI battery and ac drivers.
295 */
296 bios_ver = dmi_get_system_info(DMI_BIOS_VERSION);
297 if (acpi_dev_present("INT33FD", "1", 2) &&
298 acpi_quirk_skip_acpi_ac_and_battery() &&
299 /* Lenovo Yoga Tablet 2 Pro 1380 uses LC824206XA instead */
300 !(bios_ver &&
301 strstarts(bios_ver, "BLADE_21.X64.0005.R00.1504101516"))) {
302 dev_info(&pdev->dev, "Using TUSB1211 phy for charger detection\n");
303 swnode = &dwc3_pci_intel_phy_charger_detect_swnode;
304 }
305 }
306 }
307
308 return device_add_software_node(&dwc->dwc3->dev, swnode);
309 }
310
311 #ifdef CONFIG_PM
dwc3_pci_resume_work(struct work_struct * work)312 static void dwc3_pci_resume_work(struct work_struct *work)
313 {
314 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
315 struct platform_device *dwc3 = dwc->dwc3;
316 int ret;
317
318 ret = pm_runtime_get_sync(&dwc3->dev);
319 if (ret < 0) {
320 pm_runtime_put_sync_autosuspend(&dwc3->dev);
321 return;
322 }
323
324 pm_runtime_mark_last_busy(&dwc3->dev);
325 pm_runtime_put_sync_autosuspend(&dwc3->dev);
326 }
327 #endif
328
dwc3_pci_probe(struct pci_dev * pci,const struct pci_device_id * id)329 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
330 {
331 struct dwc3_pci *dwc;
332 struct resource res[2];
333 int ret;
334 struct device *dev = &pci->dev;
335
336 ret = pcim_enable_device(pci);
337 if (ret) {
338 dev_err(dev, "failed to enable pci device\n");
339 return -ENODEV;
340 }
341
342 pci_set_master(pci);
343
344 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
345 if (!dwc)
346 return -ENOMEM;
347
348 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
349 if (!dwc->dwc3)
350 return -ENOMEM;
351
352 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
353
354 res[0].start = pci_resource_start(pci, 0);
355 res[0].end = pci_resource_end(pci, 0);
356 res[0].name = "dwc_usb3";
357 res[0].flags = IORESOURCE_MEM;
358
359 res[1].start = pci->irq;
360 res[1].name = "dwc_usb3";
361 res[1].flags = IORESOURCE_IRQ;
362
363 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
364 if (ret) {
365 dev_err(dev, "couldn't add resources to dwc3 device\n");
366 goto err;
367 }
368
369 dwc->pci = pci;
370 dwc->dwc3->dev.parent = dev;
371 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
372
373 ret = dwc3_pci_quirks(dwc, (void *)id->driver_data);
374 if (ret)
375 goto err;
376
377 ret = platform_device_add(dwc->dwc3);
378 if (ret) {
379 dev_err(dev, "failed to register dwc3 device\n");
380 goto err;
381 }
382
383 device_init_wakeup(dev, true);
384 pci_set_drvdata(pci, dwc);
385 pm_runtime_put(dev);
386 #ifdef CONFIG_PM
387 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
388 #endif
389
390 return 0;
391 err:
392 device_remove_software_node(&dwc->dwc3->dev);
393 platform_device_put(dwc->dwc3);
394 return ret;
395 }
396
dwc3_pci_remove(struct pci_dev * pci)397 static void dwc3_pci_remove(struct pci_dev *pci)
398 {
399 struct dwc3_pci *dwc = pci_get_drvdata(pci);
400 struct pci_dev *pdev = dwc->pci;
401
402 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
403 gpiod_remove_lookup_table(&platform_bytcr_gpios);
404 #ifdef CONFIG_PM
405 cancel_work_sync(&dwc->wakeup_work);
406 #endif
407 device_init_wakeup(&pci->dev, false);
408 pm_runtime_get(&pci->dev);
409 device_remove_software_node(&dwc->dwc3->dev);
410 platform_device_unregister(dwc->dwc3);
411 }
412
413 static const struct pci_device_id dwc3_pci_id_table[] = {
414 { PCI_DEVICE_DATA(INTEL, BSW, &dwc3_pci_intel_swnode) },
415 { PCI_DEVICE_DATA(INTEL, BYT, &dwc3_pci_intel_byt_swnode) },
416 { PCI_DEVICE_DATA(INTEL, MRFLD, &dwc3_pci_intel_mrfld_swnode) },
417 { PCI_DEVICE_DATA(INTEL, CMLLP, &dwc3_pci_intel_swnode) },
418 { PCI_DEVICE_DATA(INTEL, CMLH, &dwc3_pci_intel_swnode) },
419 { PCI_DEVICE_DATA(INTEL, SPTLP, &dwc3_pci_intel_swnode) },
420 { PCI_DEVICE_DATA(INTEL, SPTH, &dwc3_pci_intel_swnode) },
421 { PCI_DEVICE_DATA(INTEL, BXT, &dwc3_pci_intel_swnode) },
422 { PCI_DEVICE_DATA(INTEL, BXT_M, &dwc3_pci_intel_swnode) },
423 { PCI_DEVICE_DATA(INTEL, APL, &dwc3_pci_intel_swnode) },
424 { PCI_DEVICE_DATA(INTEL, KBP, &dwc3_pci_intel_swnode) },
425 { PCI_DEVICE_DATA(INTEL, GLK, &dwc3_pci_intel_swnode) },
426 { PCI_DEVICE_DATA(INTEL, CNPLP, &dwc3_pci_intel_swnode) },
427 { PCI_DEVICE_DATA(INTEL, CNPH, &dwc3_pci_intel_swnode) },
428 { PCI_DEVICE_DATA(INTEL, CNPV, &dwc3_pci_intel_swnode) },
429 { PCI_DEVICE_DATA(INTEL, ICLLP, &dwc3_pci_intel_swnode) },
430 { PCI_DEVICE_DATA(INTEL, EHL, &dwc3_pci_intel_swnode) },
431 { PCI_DEVICE_DATA(INTEL, TGPLP, &dwc3_pci_intel_swnode) },
432 { PCI_DEVICE_DATA(INTEL, TGPH, &dwc3_pci_intel_swnode) },
433 { PCI_DEVICE_DATA(INTEL, JSP, &dwc3_pci_intel_swnode) },
434 { PCI_DEVICE_DATA(INTEL, ADL, &dwc3_pci_intel_swnode) },
435 { PCI_DEVICE_DATA(INTEL, ADL_PCH, &dwc3_pci_intel_swnode) },
436 { PCI_DEVICE_DATA(INTEL, ADLN, &dwc3_pci_intel_swnode) },
437 { PCI_DEVICE_DATA(INTEL, ADLN_PCH, &dwc3_pci_intel_swnode) },
438 { PCI_DEVICE_DATA(INTEL, ADLS, &dwc3_pci_intel_swnode) },
439 { PCI_DEVICE_DATA(INTEL, RPL, &dwc3_pci_intel_swnode) },
440 { PCI_DEVICE_DATA(INTEL, RPLS, &dwc3_pci_intel_swnode) },
441 { PCI_DEVICE_DATA(INTEL, MTLM, &dwc3_pci_intel_swnode) },
442 { PCI_DEVICE_DATA(INTEL, MTLP, &dwc3_pci_intel_swnode) },
443 { PCI_DEVICE_DATA(INTEL, MTL, &dwc3_pci_intel_swnode) },
444 { PCI_DEVICE_DATA(INTEL, MTLS, &dwc3_pci_intel_swnode) },
445 { PCI_DEVICE_DATA(INTEL, ARLH_PCH, &dwc3_pci_intel_swnode) },
446 { PCI_DEVICE_DATA(INTEL, TGL, &dwc3_pci_intel_swnode) },
447 { PCI_DEVICE_DATA(INTEL, PTLH, &dwc3_pci_intel_swnode) },
448 { PCI_DEVICE_DATA(INTEL, PTLH_PCH, &dwc3_pci_intel_swnode) },
449 { PCI_DEVICE_DATA(INTEL, PTLU, &dwc3_pci_intel_swnode) },
450 { PCI_DEVICE_DATA(INTEL, PTLU_PCH, &dwc3_pci_intel_swnode) },
451
452 { PCI_DEVICE_DATA(AMD, NL_USB, &dwc3_pci_amd_swnode) },
453 { PCI_DEVICE_DATA(AMD, MR, &dwc3_pci_amd_mr_swnode) },
454
455 { } /* Terminating Entry */
456 };
457 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
458
459 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
dwc3_pci_dsm(struct dwc3_pci * dwc,int param)460 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
461 {
462 union acpi_object *obj;
463 union acpi_object tmp;
464 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
465
466 if (!dwc->has_dsm_for_pm)
467 return 0;
468
469 tmp.type = ACPI_TYPE_INTEGER;
470 tmp.integer.value = param;
471
472 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
473 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
474 if (!obj) {
475 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
476 return -EIO;
477 }
478
479 ACPI_FREE(obj);
480
481 return 0;
482 }
483 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
484
485 #ifdef CONFIG_PM
dwc3_pci_runtime_suspend(struct device * dev)486 static int dwc3_pci_runtime_suspend(struct device *dev)
487 {
488 struct dwc3_pci *dwc = dev_get_drvdata(dev);
489
490 if (device_can_wakeup(dev))
491 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
492
493 return -EBUSY;
494 }
495
dwc3_pci_runtime_resume(struct device * dev)496 static int dwc3_pci_runtime_resume(struct device *dev)
497 {
498 struct dwc3_pci *dwc = dev_get_drvdata(dev);
499 int ret;
500
501 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
502 if (ret)
503 return ret;
504
505 queue_work(pm_wq, &dwc->wakeup_work);
506
507 return 0;
508 }
509 #endif /* CONFIG_PM */
510
511 #ifdef CONFIG_PM_SLEEP
dwc3_pci_suspend(struct device * dev)512 static int dwc3_pci_suspend(struct device *dev)
513 {
514 struct dwc3_pci *dwc = dev_get_drvdata(dev);
515
516 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
517 }
518
dwc3_pci_resume(struct device * dev)519 static int dwc3_pci_resume(struct device *dev)
520 {
521 struct dwc3_pci *dwc = dev_get_drvdata(dev);
522
523 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
524 }
525 #endif /* CONFIG_PM_SLEEP */
526
527 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
528 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
529 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
530 NULL)
531 };
532
533 static struct pci_driver dwc3_pci_driver = {
534 .name = "dwc3-pci",
535 .id_table = dwc3_pci_id_table,
536 .probe = dwc3_pci_probe,
537 .remove = dwc3_pci_remove,
538 .driver = {
539 .pm = &dwc3_pci_dev_pm_ops,
540 }
541 };
542
543 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
544 MODULE_LICENSE("GPL v2");
545 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
546
547 module_pci_driver(dwc3_pci_driver);
548