1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/io.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/of.h>
26 #include <linux/of_graph.h>
27 #include <linux/acpi.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/reset.h>
30 #include <linux/bitfield.h>
31
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/of.h>
35 #include <linux/usb/otg.h>
36
37 #include "core.h"
38 #include "gadget.h"
39 #include "io.h"
40
41 #include "debug.h"
42
43 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
44
45 /**
46 * dwc3_get_dr_mode - Validates and sets dr_mode
47 * @dwc: pointer to our context structure
48 */
dwc3_get_dr_mode(struct dwc3 * dwc)49 static int dwc3_get_dr_mode(struct dwc3 *dwc)
50 {
51 enum usb_dr_mode mode;
52 struct device *dev = dwc->dev;
53 unsigned int hw_mode;
54
55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
56 dwc->dr_mode = USB_DR_MODE_OTG;
57
58 mode = dwc->dr_mode;
59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
60
61 switch (hw_mode) {
62 case DWC3_GHWPARAMS0_MODE_GADGET:
63 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
64 dev_err(dev,
65 "Controller does not support host mode.\n");
66 return -EINVAL;
67 }
68 mode = USB_DR_MODE_PERIPHERAL;
69 break;
70 case DWC3_GHWPARAMS0_MODE_HOST:
71 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
72 dev_err(dev,
73 "Controller does not support device mode.\n");
74 return -EINVAL;
75 }
76 mode = USB_DR_MODE_HOST;
77 break;
78 default:
79 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
80 mode = USB_DR_MODE_HOST;
81 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
82 mode = USB_DR_MODE_PERIPHERAL;
83
84 /*
85 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
86 * mode. If the controller supports DRD but the dr_mode is not
87 * specified or set to OTG, then set the mode to peripheral.
88 */
89 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
90 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
91 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
92 !DWC3_VER_IS_PRIOR(DWC3, 330A))
93 mode = USB_DR_MODE_PERIPHERAL;
94 }
95
96 if (mode != dwc->dr_mode) {
97 dev_warn(dev,
98 "Configuration mismatch. dr_mode forced to %s\n",
99 mode == USB_DR_MODE_HOST ? "host" : "gadget");
100
101 dwc->dr_mode = mode;
102 }
103
104 return 0;
105 }
106
dwc3_enable_susphy(struct dwc3 * dwc,bool enable)107 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable)
108 {
109 u32 reg;
110
111 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
112 if (enable && !dwc->dis_u3_susphy_quirk)
113 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
114 else
115 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
116
117 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
118
119 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
120 if (enable && !dwc->dis_u2_susphy_quirk)
121 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
122 else
123 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
124
125 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
126 }
127
dwc3_set_prtcap(struct dwc3 * dwc,u32 mode)128 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
129 {
130 u32 reg;
131
132 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
133 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
134 reg |= DWC3_GCTL_PRTCAPDIR(mode);
135 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
136
137 dwc->current_dr_role = mode;
138 }
139
__dwc3_set_mode(struct work_struct * work)140 static void __dwc3_set_mode(struct work_struct *work)
141 {
142 struct dwc3 *dwc = work_to_dwc(work);
143 unsigned long flags;
144 int ret;
145 u32 reg;
146 u32 desired_dr_role;
147
148 mutex_lock(&dwc->mutex);
149 spin_lock_irqsave(&dwc->lock, flags);
150 desired_dr_role = dwc->desired_dr_role;
151 spin_unlock_irqrestore(&dwc->lock, flags);
152
153 pm_runtime_get_sync(dwc->dev);
154
155 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
156 dwc3_otg_update(dwc, 0);
157
158 if (!desired_dr_role)
159 goto out;
160
161 if (desired_dr_role == dwc->current_dr_role)
162 goto out;
163
164 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
165 goto out;
166
167 switch (dwc->current_dr_role) {
168 case DWC3_GCTL_PRTCAP_HOST:
169 dwc3_host_exit(dwc);
170 break;
171 case DWC3_GCTL_PRTCAP_DEVICE:
172 dwc3_gadget_exit(dwc);
173 dwc3_event_buffers_cleanup(dwc);
174 break;
175 case DWC3_GCTL_PRTCAP_OTG:
176 dwc3_otg_exit(dwc);
177 spin_lock_irqsave(&dwc->lock, flags);
178 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
179 spin_unlock_irqrestore(&dwc->lock, flags);
180 dwc3_otg_update(dwc, 1);
181 break;
182 default:
183 break;
184 }
185
186 /*
187 * When current_dr_role is not set, there's no role switching.
188 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
189 */
190 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
191 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
192 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
193 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
194 reg |= DWC3_GCTL_CORESOFTRESET;
195 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
196
197 /*
198 * Wait for internal clocks to synchronized. DWC_usb31 and
199 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
200 * keep it consistent across different IPs, let's wait up to
201 * 100ms before clearing GCTL.CORESOFTRESET.
202 */
203 msleep(100);
204
205 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
206 reg &= ~DWC3_GCTL_CORESOFTRESET;
207 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
208 }
209
210 spin_lock_irqsave(&dwc->lock, flags);
211
212 dwc3_set_prtcap(dwc, desired_dr_role);
213
214 spin_unlock_irqrestore(&dwc->lock, flags);
215
216 switch (desired_dr_role) {
217 case DWC3_GCTL_PRTCAP_HOST:
218 ret = dwc3_host_init(dwc);
219 if (ret) {
220 dev_err(dwc->dev, "failed to initialize host\n");
221 } else {
222 if (dwc->usb2_phy)
223 otg_set_vbus(dwc->usb2_phy->otg, true);
224 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
225 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
226 if (dwc->dis_split_quirk) {
227 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
228 reg |= DWC3_GUCTL3_SPLITDISABLE;
229 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
230 }
231 }
232 break;
233 case DWC3_GCTL_PRTCAP_DEVICE:
234 dwc3_core_soft_reset(dwc);
235
236 dwc3_event_buffers_setup(dwc);
237
238 if (dwc->usb2_phy)
239 otg_set_vbus(dwc->usb2_phy->otg, false);
240 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
241 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
242
243 ret = dwc3_gadget_init(dwc);
244 if (ret)
245 dev_err(dwc->dev, "failed to initialize peripheral\n");
246 break;
247 case DWC3_GCTL_PRTCAP_OTG:
248 dwc3_otg_init(dwc);
249 dwc3_otg_update(dwc, 0);
250 break;
251 default:
252 break;
253 }
254
255 out:
256 pm_runtime_mark_last_busy(dwc->dev);
257 pm_runtime_put_autosuspend(dwc->dev);
258 mutex_unlock(&dwc->mutex);
259 }
260
dwc3_set_mode(struct dwc3 * dwc,u32 mode)261 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
262 {
263 unsigned long flags;
264
265 if (dwc->dr_mode != USB_DR_MODE_OTG)
266 return;
267
268 spin_lock_irqsave(&dwc->lock, flags);
269 dwc->desired_dr_role = mode;
270 spin_unlock_irqrestore(&dwc->lock, flags);
271
272 queue_work(system_freezable_wq, &dwc->drd_work);
273 }
274
dwc3_core_fifo_space(struct dwc3_ep * dep,u8 type)275 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
276 {
277 struct dwc3 *dwc = dep->dwc;
278 u32 reg;
279
280 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
281 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
282 DWC3_GDBGFIFOSPACE_TYPE(type));
283
284 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
285
286 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
287 }
288
289 /**
290 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
291 * @dwc: pointer to our context structure
292 */
dwc3_core_soft_reset(struct dwc3 * dwc)293 int dwc3_core_soft_reset(struct dwc3 *dwc)
294 {
295 u32 reg;
296 int retries = 1000;
297
298 /*
299 * We're resetting only the device side because, if we're in host mode,
300 * XHCI driver will reset the host block. If dwc3 was configured for
301 * host-only mode, then we can return early.
302 */
303 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
304 return 0;
305
306 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
307 reg |= DWC3_DCTL_CSFTRST;
308 reg &= ~DWC3_DCTL_RUN_STOP;
309 dwc3_gadget_dctl_write_safe(dwc, reg);
310
311 /*
312 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
313 * is cleared only after all the clocks are synchronized. This can
314 * take a little more than 50ms. Set the polling rate at 20ms
315 * for 10 times instead.
316 */
317 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
318 retries = 10;
319
320 do {
321 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
322 if (!(reg & DWC3_DCTL_CSFTRST))
323 goto done;
324
325 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
326 msleep(20);
327 else
328 udelay(1);
329 } while (--retries);
330
331 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
332 return -ETIMEDOUT;
333
334 done:
335 /*
336 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
337 * is cleared, we must wait at least 50ms before accessing the PHY
338 * domain (synchronization delay).
339 */
340 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
341 msleep(50);
342
343 return 0;
344 }
345
346 /*
347 * dwc3_frame_length_adjustment - Adjusts frame length if required
348 * @dwc3: Pointer to our controller context structure
349 */
dwc3_frame_length_adjustment(struct dwc3 * dwc)350 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
351 {
352 u32 reg;
353 u32 dft;
354
355 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
356 return;
357
358 if (dwc->fladj == 0)
359 return;
360
361 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
362 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
363 if (dft != dwc->fladj) {
364 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
365 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
366 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
367 }
368 }
369
370 /**
371 * dwc3_ref_clk_period - Reference clock period configuration
372 * Default reference clock period depends on hardware
373 * configuration. For systems with reference clock that differs
374 * from the default, this will set clock period in DWC3_GUCTL
375 * register.
376 * @dwc: Pointer to our controller context structure
377 */
dwc3_ref_clk_period(struct dwc3 * dwc)378 static void dwc3_ref_clk_period(struct dwc3 *dwc)
379 {
380 unsigned long period;
381 unsigned long fladj;
382 unsigned long decr;
383 unsigned long rate;
384 u32 reg;
385
386 if (dwc->ref_clk) {
387 rate = clk_get_rate(dwc->ref_clk);
388 if (!rate)
389 return;
390 period = NSEC_PER_SEC / rate;
391 } else if (dwc->ref_clk_per) {
392 period = dwc->ref_clk_per;
393 rate = NSEC_PER_SEC / period;
394 } else {
395 return;
396 }
397
398 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
399 reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
400 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
401 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
402
403 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
404 return;
405
406 /*
407 * The calculation below is
408 *
409 * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
410 *
411 * but rearranged for fixed-point arithmetic. The division must be
412 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
413 * neither does rate * period).
414 *
415 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
416 * nanoseconds of error caused by the truncation which happened during
417 * the division when calculating rate or period (whichever one was
418 * derived from the other). We first calculate the relative error, then
419 * scale it to units of 8 ppm.
420 */
421 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
422 fladj -= 125000;
423
424 /*
425 * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
426 */
427 decr = 480000000 / rate;
428
429 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
430 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
431 & ~DWC3_GFLADJ_240MHZDECR
432 & ~DWC3_GFLADJ_240MHZDECR_PLS1;
433 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
434 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
435 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
436
437 if (dwc->gfladj_refclk_lpm_sel)
438 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL;
439
440 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
441 }
442
443 /**
444 * dwc3_free_one_event_buffer - Frees one event buffer
445 * @dwc: Pointer to our controller context structure
446 * @evt: Pointer to event buffer to be freed
447 */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)448 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
449 struct dwc3_event_buffer *evt)
450 {
451 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
452 }
453
454 /**
455 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
456 * @dwc: Pointer to our controller context structure
457 * @length: size of the event buffer
458 *
459 * Returns a pointer to the allocated event buffer structure on success
460 * otherwise ERR_PTR(errno).
461 */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned int length)462 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
463 unsigned int length)
464 {
465 struct dwc3_event_buffer *evt;
466
467 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
468 if (!evt)
469 return ERR_PTR(-ENOMEM);
470
471 evt->dwc = dwc;
472 evt->length = length;
473 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
474 if (!evt->cache)
475 return ERR_PTR(-ENOMEM);
476
477 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
478 &evt->dma, GFP_KERNEL);
479 if (!evt->buf)
480 return ERR_PTR(-ENOMEM);
481
482 return evt;
483 }
484
485 /**
486 * dwc3_free_event_buffers - frees all allocated event buffers
487 * @dwc: Pointer to our controller context structure
488 */
dwc3_free_event_buffers(struct dwc3 * dwc)489 static void dwc3_free_event_buffers(struct dwc3 *dwc)
490 {
491 struct dwc3_event_buffer *evt;
492
493 evt = dwc->ev_buf;
494 if (evt)
495 dwc3_free_one_event_buffer(dwc, evt);
496 }
497
498 /**
499 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
500 * @dwc: pointer to our controller context structure
501 * @length: size of event buffer
502 *
503 * Returns 0 on success otherwise negative errno. In the error case, dwc
504 * may contain some buffers allocated but not all which were requested.
505 */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned int length)506 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
507 {
508 struct dwc3_event_buffer *evt;
509 unsigned int hw_mode;
510
511 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
512 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
513 dwc->ev_buf = NULL;
514 return 0;
515 }
516
517 evt = dwc3_alloc_one_event_buffer(dwc, length);
518 if (IS_ERR(evt)) {
519 dev_err(dwc->dev, "can't allocate event buffer\n");
520 return PTR_ERR(evt);
521 }
522 dwc->ev_buf = evt;
523
524 return 0;
525 }
526
527 /**
528 * dwc3_event_buffers_setup - setup our allocated event buffers
529 * @dwc: pointer to our controller context structure
530 *
531 * Returns 0 on success otherwise negative errno.
532 */
dwc3_event_buffers_setup(struct dwc3 * dwc)533 int dwc3_event_buffers_setup(struct dwc3 *dwc)
534 {
535 struct dwc3_event_buffer *evt;
536 u32 reg;
537
538 if (!dwc->ev_buf)
539 return 0;
540
541 evt = dwc->ev_buf;
542 evt->lpos = 0;
543 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
544 lower_32_bits(evt->dma));
545 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
546 upper_32_bits(evt->dma));
547 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
548 DWC3_GEVNTSIZ_SIZE(evt->length));
549
550 /* Clear any stale event */
551 reg = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
552 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), reg);
553 return 0;
554 }
555
dwc3_event_buffers_cleanup(struct dwc3 * dwc)556 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
557 {
558 struct dwc3_event_buffer *evt;
559 u32 reg;
560
561 if (!dwc->ev_buf)
562 return;
563 /*
564 * Exynos platforms may not be able to access event buffer if the
565 * controller failed to halt on dwc3_core_exit().
566 */
567 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
568 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
569 return;
570
571 evt = dwc->ev_buf;
572
573 evt->lpos = 0;
574
575 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
576 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
577 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
578 | DWC3_GEVNTSIZ_SIZE(0));
579
580 /* Clear any stale event */
581 reg = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
582 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), reg);
583 }
584
dwc3_core_num_eps(struct dwc3 * dwc)585 static void dwc3_core_num_eps(struct dwc3 *dwc)
586 {
587 struct dwc3_hwparams *parms = &dwc->hwparams;
588
589 dwc->num_eps = DWC3_NUM_EPS(parms);
590 }
591
dwc3_cache_hwparams(struct dwc3 * dwc)592 static void dwc3_cache_hwparams(struct dwc3 *dwc)
593 {
594 struct dwc3_hwparams *parms = &dwc->hwparams;
595
596 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
597 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
598 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
599 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
600 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
601 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
602 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
603 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
604 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
605
606 if (DWC3_IP_IS(DWC32))
607 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
608 }
609
dwc3_core_ulpi_init(struct dwc3 * dwc)610 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
611 {
612 int intf;
613 int ret = 0;
614
615 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
616
617 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
618 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
619 dwc->hsphy_interface &&
620 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
621 ret = dwc3_ulpi_init(dwc);
622
623 return ret;
624 }
625
626 /**
627 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
628 * @dwc: Pointer to our controller context structure
629 *
630 * Returns 0 on success. The USB PHY interfaces are configured but not
631 * initialized. The PHY interfaces and the PHYs get initialized together with
632 * the core in dwc3_core_init.
633 */
dwc3_phy_setup(struct dwc3 * dwc)634 static int dwc3_phy_setup(struct dwc3 *dwc)
635 {
636 u32 reg;
637
638 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
639
640 /*
641 * Make sure UX_EXIT_PX is cleared as that causes issues with some
642 * PHYs. Also, this bit is not supposed to be used in normal operation.
643 */
644 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
645
646 /*
647 * Above DWC_usb3.0 1.94a, it is recommended to set
648 * DWC3_GUSB3PIPECTL_SUSPHY to '0' during coreConsultant configuration.
649 * So default value will be '0' when the core is reset. Application
650 * needs to set it to '1' after the core initialization is completed.
651 *
652 * Similarly for DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be
653 * cleared after power-on reset, and it can be set after core
654 * initialization.
655 */
656 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
657
658 if (dwc->u2ss_inp3_quirk)
659 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
660
661 if (dwc->dis_rxdet_inp3_quirk)
662 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
663
664 if (dwc->req_p1p2p3_quirk)
665 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
666
667 if (dwc->del_p1p2p3_quirk)
668 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
669
670 if (dwc->del_phy_power_chg_quirk)
671 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
672
673 if (dwc->lfps_filter_quirk)
674 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
675
676 if (dwc->rx_detect_poll_quirk)
677 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
678
679 if (dwc->tx_de_emphasis_quirk)
680 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
681
682 if (dwc->dis_del_phy_power_chg_quirk)
683 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
684
685 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
686
687 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
688
689 /* Select the HS PHY interface */
690 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
691 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
692 if (dwc->hsphy_interface &&
693 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
694 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
695 break;
696 } else if (dwc->hsphy_interface &&
697 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
698 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
699 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
700 } else {
701 /* Relying on default value. */
702 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
703 break;
704 }
705 fallthrough;
706 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
707 default:
708 break;
709 }
710
711 switch (dwc->hsphy_mode) {
712 case USBPHY_INTERFACE_MODE_UTMI:
713 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
714 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
715 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
716 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
717 break;
718 case USBPHY_INTERFACE_MODE_UTMIW:
719 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
720 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
721 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
722 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
723 break;
724 default:
725 break;
726 }
727
728 /*
729 * Above DWC_usb3.0 1.94a, it is recommended to set
730 * DWC3_GUSB2PHYCFG_SUSPHY to '0' during coreConsultant configuration.
731 * So default value will be '0' when the core is reset. Application
732 * needs to set it to '1' after the core initialization is completed.
733 *
734 * Similarly for DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared
735 * after power-on reset, and it can be set after core initialization.
736 */
737 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
738
739 if (dwc->dis_enblslpm_quirk)
740 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
741 else
742 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
743
744 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
745 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
746
747 /*
748 * Some ULPI USB PHY does not support internal VBUS supply, to drive
749 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL
750 * bit of OTG_CTRL register. Controller configures the USB2 PHY
751 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus
752 * with an external supply.
753 */
754 if (dwc->ulpi_ext_vbus_drv)
755 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
756
757 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
758
759 return 0;
760 }
761
dwc3_phy_init(struct dwc3 * dwc)762 static int dwc3_phy_init(struct dwc3 *dwc)
763 {
764 int ret;
765
766 usb_phy_init(dwc->usb2_phy);
767 usb_phy_init(dwc->usb3_phy);
768
769 ret = phy_init(dwc->usb2_generic_phy);
770 if (ret < 0)
771 goto err_shutdown_usb3_phy;
772
773 ret = phy_init(dwc->usb3_generic_phy);
774 if (ret < 0)
775 goto err_exit_usb2_phy;
776
777 return 0;
778
779 err_exit_usb2_phy:
780 phy_exit(dwc->usb2_generic_phy);
781 err_shutdown_usb3_phy:
782 usb_phy_shutdown(dwc->usb3_phy);
783 usb_phy_shutdown(dwc->usb2_phy);
784
785 return ret;
786 }
787
dwc3_phy_exit(struct dwc3 * dwc)788 static void dwc3_phy_exit(struct dwc3 *dwc)
789 {
790 phy_exit(dwc->usb3_generic_phy);
791 phy_exit(dwc->usb2_generic_phy);
792
793 usb_phy_shutdown(dwc->usb3_phy);
794 usb_phy_shutdown(dwc->usb2_phy);
795 }
796
dwc3_phy_power_on(struct dwc3 * dwc)797 static int dwc3_phy_power_on(struct dwc3 *dwc)
798 {
799 int ret;
800
801 usb_phy_set_suspend(dwc->usb2_phy, 0);
802 usb_phy_set_suspend(dwc->usb3_phy, 0);
803
804 ret = phy_power_on(dwc->usb2_generic_phy);
805 if (ret < 0)
806 goto err_suspend_usb3_phy;
807
808 ret = phy_power_on(dwc->usb3_generic_phy);
809 if (ret < 0)
810 goto err_power_off_usb2_phy;
811
812 return 0;
813
814 err_power_off_usb2_phy:
815 phy_power_off(dwc->usb2_generic_phy);
816 err_suspend_usb3_phy:
817 usb_phy_set_suspend(dwc->usb3_phy, 1);
818 usb_phy_set_suspend(dwc->usb2_phy, 1);
819
820 return ret;
821 }
822
dwc3_phy_power_off(struct dwc3 * dwc)823 static void dwc3_phy_power_off(struct dwc3 *dwc)
824 {
825 phy_power_off(dwc->usb3_generic_phy);
826 phy_power_off(dwc->usb2_generic_phy);
827
828 usb_phy_set_suspend(dwc->usb3_phy, 1);
829 usb_phy_set_suspend(dwc->usb2_phy, 1);
830 }
831
dwc3_clk_enable(struct dwc3 * dwc)832 static int dwc3_clk_enable(struct dwc3 *dwc)
833 {
834 int ret;
835
836 ret = clk_prepare_enable(dwc->bus_clk);
837 if (ret)
838 return ret;
839
840 ret = clk_prepare_enable(dwc->ref_clk);
841 if (ret)
842 goto disable_bus_clk;
843
844 ret = clk_prepare_enable(dwc->susp_clk);
845 if (ret)
846 goto disable_ref_clk;
847
848 return 0;
849
850 disable_ref_clk:
851 clk_disable_unprepare(dwc->ref_clk);
852 disable_bus_clk:
853 clk_disable_unprepare(dwc->bus_clk);
854 return ret;
855 }
856
dwc3_clk_disable(struct dwc3 * dwc)857 static void dwc3_clk_disable(struct dwc3 *dwc)
858 {
859 clk_disable_unprepare(dwc->susp_clk);
860 clk_disable_unprepare(dwc->ref_clk);
861 clk_disable_unprepare(dwc->bus_clk);
862 }
863
dwc3_core_exit(struct dwc3 * dwc)864 static void dwc3_core_exit(struct dwc3 *dwc)
865 {
866 dwc3_event_buffers_cleanup(dwc);
867 dwc3_phy_power_off(dwc);
868 dwc3_phy_exit(dwc);
869 dwc3_clk_disable(dwc);
870 reset_control_assert(dwc->reset);
871 }
872
dwc3_core_is_valid(struct dwc3 * dwc)873 static bool dwc3_core_is_valid(struct dwc3 *dwc)
874 {
875 u32 reg;
876
877 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
878 dwc->ip = DWC3_GSNPS_ID(reg);
879
880 /* This should read as U3 followed by revision number */
881 if (DWC3_IP_IS(DWC3)) {
882 dwc->revision = reg;
883 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
884 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
885 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
886 } else {
887 return false;
888 }
889
890 return true;
891 }
892
dwc3_core_setup_global_control(struct dwc3 * dwc)893 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
894 {
895 unsigned int power_opt;
896 unsigned int hw_mode;
897 u32 reg;
898
899 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
900 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
901 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
902 power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
903
904 switch (power_opt) {
905 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
906 /**
907 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
908 * issue which would cause xHCI compliance tests to fail.
909 *
910 * Because of that we cannot enable clock gating on such
911 * configurations.
912 *
913 * Refers to:
914 *
915 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
916 * SOF/ITP Mode Used
917 */
918 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
919 dwc->dr_mode == USB_DR_MODE_OTG) &&
920 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
921 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
922 else
923 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
924 break;
925 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
926 /*
927 * REVISIT Enabling this bit so that host-mode hibernation
928 * will work. Device-mode hibernation is not yet implemented.
929 */
930 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
931 break;
932 default:
933 /* nothing */
934 break;
935 }
936
937 /*
938 * This is a workaround for STAR#4846132, which only affects
939 * DWC_usb31 version2.00a operating in host mode.
940 *
941 * There is a problem in DWC_usb31 version 2.00a operating
942 * in host mode that would cause a CSR read timeout When CSR
943 * read coincides with RAM Clock Gating Entry. By disable
944 * Clock Gating, sacrificing power consumption for normal
945 * operation.
946 */
947 if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO &&
948 hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A))
949 reg |= DWC3_GCTL_DSBLCLKGTNG;
950
951 /* check if current dwc3 is on simulation board */
952 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
953 dev_info(dwc->dev, "Running with FPGA optimizations\n");
954 dwc->is_fpga = true;
955 }
956
957 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
958 "disable_scramble cannot be used on non-FPGA builds\n");
959
960 if (dwc->disable_scramble_quirk && dwc->is_fpga)
961 reg |= DWC3_GCTL_DISSCRAMBLE;
962 else
963 reg &= ~DWC3_GCTL_DISSCRAMBLE;
964
965 if (dwc->u2exit_lfps_quirk)
966 reg |= DWC3_GCTL_U2EXIT_LFPS;
967
968 /*
969 * WORKAROUND: DWC3 revisions <1.90a have a bug
970 * where the device can fail to connect at SuperSpeed
971 * and falls back to high-speed mode which causes
972 * the device to enter a Connect/Disconnect loop
973 */
974 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
975 reg |= DWC3_GCTL_U2RSTECN;
976
977 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
978 }
979
980 static int dwc3_core_get_phy(struct dwc3 *dwc);
981 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
982
983 /* set global incr burst type configuration registers */
dwc3_set_incr_burst_type(struct dwc3 * dwc)984 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
985 {
986 struct device *dev = dwc->dev;
987 /* incrx_mode : for INCR burst type. */
988 bool incrx_mode;
989 /* incrx_size : for size of INCRX burst. */
990 u32 incrx_size;
991 u32 *vals;
992 u32 cfg;
993 int ntype;
994 int ret;
995 int i;
996
997 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
998
999 /*
1000 * Handle property "snps,incr-burst-type-adjustment".
1001 * Get the number of value from this property:
1002 * result <= 0, means this property is not supported.
1003 * result = 1, means INCRx burst mode supported.
1004 * result > 1, means undefined length burst mode supported.
1005 */
1006 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
1007 if (ntype <= 0)
1008 return;
1009
1010 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
1011 if (!vals)
1012 return;
1013
1014 /* Get INCR burst type, and parse it */
1015 ret = device_property_read_u32_array(dev,
1016 "snps,incr-burst-type-adjustment", vals, ntype);
1017 if (ret) {
1018 kfree(vals);
1019 dev_err(dev, "Error to get property\n");
1020 return;
1021 }
1022
1023 incrx_size = *vals;
1024
1025 if (ntype > 1) {
1026 /* INCRX (undefined length) burst mode */
1027 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
1028 for (i = 1; i < ntype; i++) {
1029 if (vals[i] > incrx_size)
1030 incrx_size = vals[i];
1031 }
1032 } else {
1033 /* INCRX burst mode */
1034 incrx_mode = INCRX_BURST_MODE;
1035 }
1036
1037 kfree(vals);
1038
1039 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
1040 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
1041 if (incrx_mode)
1042 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1043 switch (incrx_size) {
1044 case 256:
1045 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1046 break;
1047 case 128:
1048 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1049 break;
1050 case 64:
1051 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1052 break;
1053 case 32:
1054 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1055 break;
1056 case 16:
1057 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1058 break;
1059 case 8:
1060 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1061 break;
1062 case 4:
1063 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1064 break;
1065 case 1:
1066 break;
1067 default:
1068 dev_err(dev, "Invalid property\n");
1069 break;
1070 }
1071
1072 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1073 }
1074
dwc3_set_power_down_clk_scale(struct dwc3 * dwc)1075 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1076 {
1077 u32 scale;
1078 u32 reg;
1079
1080 if (!dwc->susp_clk)
1081 return;
1082
1083 /*
1084 * The power down scale field specifies how many suspend_clk
1085 * periods fit into a 16KHz clock period. When performing
1086 * the division, round up the remainder.
1087 *
1088 * The power down scale value is calculated using the fastest
1089 * frequency of the suspend_clk. If it isn't fixed (but within
1090 * the accuracy requirement), the driver may not know the max
1091 * rate of the suspend_clk, so only update the power down scale
1092 * if the default is less than the calculated value from
1093 * clk_get_rate() or if the default is questionably high
1094 * (3x or more) to be within the requirement.
1095 */
1096 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1097 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1098 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1099 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1100 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1101 reg |= DWC3_GCTL_PWRDNSCALE(scale);
1102 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1103 }
1104 }
1105
dwc3_config_threshold(struct dwc3 * dwc)1106 static void dwc3_config_threshold(struct dwc3 *dwc)
1107 {
1108 u32 reg;
1109 u8 rx_thr_num;
1110 u8 rx_maxburst;
1111 u8 tx_thr_num;
1112 u8 tx_maxburst;
1113
1114 /*
1115 * Must config both number of packets and max burst settings to enable
1116 * RX and/or TX threshold.
1117 */
1118 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1119 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1120 rx_maxburst = dwc->rx_max_burst_prd;
1121 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1122 tx_maxburst = dwc->tx_max_burst_prd;
1123
1124 if (rx_thr_num && rx_maxburst) {
1125 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1126 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1127
1128 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1129 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1130
1131 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1132 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1133
1134 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1135 }
1136
1137 if (tx_thr_num && tx_maxburst) {
1138 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1139 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1140
1141 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1142 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1143
1144 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1145 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1146
1147 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1148 }
1149 }
1150
1151 rx_thr_num = dwc->rx_thr_num_pkt;
1152 rx_maxburst = dwc->rx_max_burst;
1153 tx_thr_num = dwc->tx_thr_num_pkt;
1154 tx_maxburst = dwc->tx_max_burst;
1155
1156 if (DWC3_IP_IS(DWC3)) {
1157 if (rx_thr_num && rx_maxburst) {
1158 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1159 reg |= DWC3_GRXTHRCFG_PKTCNTSEL;
1160
1161 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0);
1162 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1163
1164 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1165 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1166
1167 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1168 }
1169
1170 if (tx_thr_num && tx_maxburst) {
1171 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1172 reg |= DWC3_GTXTHRCFG_PKTCNTSEL;
1173
1174 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0);
1175 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1176
1177 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1178 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1179
1180 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1181 }
1182 } else {
1183 if (rx_thr_num && rx_maxburst) {
1184 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1185 reg |= DWC31_GRXTHRCFG_PKTCNTSEL;
1186
1187 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0);
1188 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1189
1190 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1191 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1192
1193 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1194 }
1195
1196 if (tx_thr_num && tx_maxburst) {
1197 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1198 reg |= DWC31_GTXTHRCFG_PKTCNTSEL;
1199
1200 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0);
1201 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1202
1203 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1204 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1205
1206 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1207 }
1208 }
1209 }
1210
1211 /**
1212 * dwc3_core_init - Low-level initialization of DWC3 Core
1213 * @dwc: Pointer to our controller context structure
1214 *
1215 * Returns 0 on success otherwise negative errno.
1216 */
dwc3_core_init(struct dwc3 * dwc)1217 static int dwc3_core_init(struct dwc3 *dwc)
1218 {
1219 unsigned int hw_mode;
1220 u32 reg;
1221 int ret;
1222
1223 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1224
1225 /*
1226 * Write Linux Version Code to our GUID register so it's easy to figure
1227 * out which kernel version a bug was found.
1228 */
1229 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1230
1231 ret = dwc3_phy_setup(dwc);
1232 if (ret)
1233 return ret;
1234
1235 if (!dwc->ulpi_ready) {
1236 ret = dwc3_core_ulpi_init(dwc);
1237 if (ret) {
1238 if (ret == -ETIMEDOUT) {
1239 dwc3_core_soft_reset(dwc);
1240 ret = -EPROBE_DEFER;
1241 }
1242 return ret;
1243 }
1244 dwc->ulpi_ready = true;
1245 }
1246
1247 if (!dwc->phys_ready) {
1248 ret = dwc3_core_get_phy(dwc);
1249 if (ret)
1250 goto err_exit_ulpi;
1251 dwc->phys_ready = true;
1252 }
1253
1254 ret = dwc3_phy_init(dwc);
1255 if (ret)
1256 goto err_exit_ulpi;
1257
1258 ret = dwc3_core_soft_reset(dwc);
1259 if (ret)
1260 goto err_exit_phy;
1261
1262 dwc3_core_setup_global_control(dwc);
1263 dwc3_core_num_eps(dwc);
1264
1265 /* Set power down scale of suspend_clk */
1266 dwc3_set_power_down_clk_scale(dwc);
1267
1268 /* Adjust Frame Length */
1269 dwc3_frame_length_adjustment(dwc);
1270
1271 /* Adjust Reference Clock Period */
1272 dwc3_ref_clk_period(dwc);
1273
1274 dwc3_set_incr_burst_type(dwc);
1275
1276 ret = dwc3_phy_power_on(dwc);
1277 if (ret)
1278 goto err_exit_phy;
1279
1280 ret = dwc3_event_buffers_setup(dwc);
1281 if (ret) {
1282 dev_err(dwc->dev, "failed to setup event buffers\n");
1283 goto err_power_off_phy;
1284 }
1285
1286 /*
1287 * ENDXFER polling is available on version 3.10a and later of
1288 * the DWC_usb3 controller. It is NOT available in the
1289 * DWC_usb31 controller.
1290 */
1291 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1292 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1293 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1294 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1295 }
1296
1297 /*
1298 * STAR 9001285599: This issue affects DWC_usb3 version 3.20a
1299 * only. If the PM TIMER ECM is enabled through GUCTL2[19], the
1300 * link compliance test (TD7.21) may fail. If the ECN is not
1301 * enabled (GUCTL2[19] = 0), the controller will use the old timer
1302 * value (5us), which is still acceptable for the link compliance
1303 * test. Therefore, do not enable PM TIMER ECM in 3.20a by
1304 * setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0.
1305 */
1306 if (DWC3_VER_IS(DWC3, 320A)) {
1307 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1308 reg &= ~DWC3_GUCTL2_LC_TIMER;
1309 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1310 }
1311
1312 /*
1313 * When configured in HOST mode, after issuing U3/L2 exit controller
1314 * fails to send proper CRC checksum in CRC5 feild. Because of this
1315 * behaviour Transaction Error is generated, resulting in reset and
1316 * re-enumeration of usb device attached. All the termsel, xcvrsel,
1317 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
1318 * will correct this problem. This option is to support certain
1319 * legacy ULPI PHYs.
1320 */
1321 if (dwc->resume_hs_terminations) {
1322 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1323 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
1324 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1325 }
1326
1327 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1328 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1329
1330 /*
1331 * Enable hardware control of sending remote wakeup
1332 * in HS when the device is in the L1 state.
1333 */
1334 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1335 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1336
1337 /*
1338 * Decouple USB 2.0 L1 & L2 events which will allow for
1339 * gadget driver to only receive U3/L2 suspend & wakeup
1340 * events and prevent the more frequent L1 LPM transitions
1341 * from interrupting the driver.
1342 */
1343 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1344 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1345
1346 if (dwc->dis_tx_ipgap_linecheck_quirk)
1347 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1348
1349 if (dwc->parkmode_disable_ss_quirk)
1350 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1351
1352 if (dwc->parkmode_disable_hs_quirk)
1353 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
1354
1355 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1356 (dwc->maximum_speed == USB_SPEED_HIGH ||
1357 dwc->maximum_speed == USB_SPEED_FULL))
1358 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1359
1360 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1361 }
1362
1363 dwc3_config_threshold(dwc);
1364
1365 return 0;
1366
1367 err_power_off_phy:
1368 dwc3_phy_power_off(dwc);
1369 err_exit_phy:
1370 dwc3_phy_exit(dwc);
1371 err_exit_ulpi:
1372 dwc3_ulpi_exit(dwc);
1373
1374 return ret;
1375 }
1376
dwc3_core_get_phy(struct dwc3 * dwc)1377 static int dwc3_core_get_phy(struct dwc3 *dwc)
1378 {
1379 struct device *dev = dwc->dev;
1380 struct device_node *node = dev->of_node;
1381 int ret;
1382
1383 if (node) {
1384 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1385 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1386 } else {
1387 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1388 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1389 }
1390
1391 if (IS_ERR(dwc->usb2_phy)) {
1392 ret = PTR_ERR(dwc->usb2_phy);
1393 if (ret == -ENXIO || ret == -ENODEV)
1394 dwc->usb2_phy = NULL;
1395 else
1396 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1397 }
1398
1399 if (IS_ERR(dwc->usb3_phy)) {
1400 ret = PTR_ERR(dwc->usb3_phy);
1401 if (ret == -ENXIO || ret == -ENODEV)
1402 dwc->usb3_phy = NULL;
1403 else
1404 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1405 }
1406
1407 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1408 if (IS_ERR(dwc->usb2_generic_phy)) {
1409 ret = PTR_ERR(dwc->usb2_generic_phy);
1410 if (ret == -ENOSYS || ret == -ENODEV)
1411 dwc->usb2_generic_phy = NULL;
1412 else
1413 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1414 }
1415
1416 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1417 if (IS_ERR(dwc->usb3_generic_phy)) {
1418 ret = PTR_ERR(dwc->usb3_generic_phy);
1419 if (ret == -ENOSYS || ret == -ENODEV)
1420 dwc->usb3_generic_phy = NULL;
1421 else
1422 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1423 }
1424
1425 return 0;
1426 }
1427
dwc3_core_init_mode(struct dwc3 * dwc)1428 static int dwc3_core_init_mode(struct dwc3 *dwc)
1429 {
1430 struct device *dev = dwc->dev;
1431 int ret;
1432
1433 switch (dwc->dr_mode) {
1434 case USB_DR_MODE_PERIPHERAL:
1435 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1436
1437 if (dwc->usb2_phy)
1438 otg_set_vbus(dwc->usb2_phy->otg, false);
1439 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1440 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1441
1442 ret = dwc3_gadget_init(dwc);
1443 if (ret)
1444 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1445 break;
1446 case USB_DR_MODE_HOST:
1447 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1448
1449 if (dwc->usb2_phy)
1450 otg_set_vbus(dwc->usb2_phy->otg, true);
1451 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1452 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1453
1454 ret = dwc3_host_init(dwc);
1455 if (ret)
1456 return dev_err_probe(dev, ret, "failed to initialize host\n");
1457 break;
1458 case USB_DR_MODE_OTG:
1459 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1460 ret = dwc3_drd_init(dwc);
1461 if (ret)
1462 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1463 break;
1464 default:
1465 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1466 return -EINVAL;
1467 }
1468
1469 return 0;
1470 }
1471
dwc3_core_exit_mode(struct dwc3 * dwc)1472 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1473 {
1474 switch (dwc->dr_mode) {
1475 case USB_DR_MODE_PERIPHERAL:
1476 dwc3_gadget_exit(dwc);
1477 break;
1478 case USB_DR_MODE_HOST:
1479 dwc3_host_exit(dwc);
1480 break;
1481 case USB_DR_MODE_OTG:
1482 dwc3_drd_exit(dwc);
1483 break;
1484 default:
1485 /* do nothing */
1486 break;
1487 }
1488
1489 /* de-assert DRVVBUS for HOST and OTG mode */
1490 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1491 }
1492
dwc3_get_properties(struct dwc3 * dwc)1493 static void dwc3_get_properties(struct dwc3 *dwc)
1494 {
1495 struct device *dev = dwc->dev;
1496 u8 lpm_nyet_threshold;
1497 u8 tx_de_emphasis;
1498 u8 hird_threshold;
1499 u8 rx_thr_num_pkt = 0;
1500 u8 rx_max_burst = 0;
1501 u8 tx_thr_num_pkt = 0;
1502 u8 tx_max_burst = 0;
1503 u8 rx_thr_num_pkt_prd = 0;
1504 u8 rx_max_burst_prd = 0;
1505 u8 tx_thr_num_pkt_prd = 0;
1506 u8 tx_max_burst_prd = 0;
1507 u8 tx_fifo_resize_max_num;
1508
1509 /* default to highest possible threshold */
1510 lpm_nyet_threshold = 0xf;
1511
1512 /* default to -3.5dB de-emphasis */
1513 tx_de_emphasis = 1;
1514
1515 /*
1516 * default to assert utmi_sleep_n and use maximum allowed HIRD
1517 * threshold value of 0b1100
1518 */
1519 hird_threshold = 12;
1520
1521 /*
1522 * default to a TXFIFO size large enough to fit 6 max packets. This
1523 * allows for systems with larger bus latencies to have some headroom
1524 * for endpoints that have a large bMaxBurst value.
1525 */
1526 tx_fifo_resize_max_num = 6;
1527
1528 dwc->maximum_speed = usb_get_maximum_speed(dev);
1529 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1530 dwc->dr_mode = usb_get_dr_mode(dev);
1531 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1532
1533 dwc->sysdev_is_parent = device_property_read_bool(dev,
1534 "linux,sysdev_is_parent");
1535 if (dwc->sysdev_is_parent)
1536 dwc->sysdev = dwc->dev->parent;
1537 else
1538 dwc->sysdev = dwc->dev;
1539
1540 dwc->sys_wakeup = device_may_wakeup(dwc->sysdev);
1541
1542 dwc->has_lpm_erratum = device_property_read_bool(dev,
1543 "snps,has-lpm-erratum");
1544 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1545 &lpm_nyet_threshold);
1546 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1547 "snps,is-utmi-l1-suspend");
1548 device_property_read_u8(dev, "snps,hird-threshold",
1549 &hird_threshold);
1550 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1551 "snps,dis-start-transfer-quirk");
1552 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1553 "snps,usb3_lpm_capable");
1554 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1555 "snps,usb2-lpm-disable");
1556 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1557 "snps,usb2-gadget-lpm-disable");
1558 device_property_read_u8(dev, "snps,rx-thr-num-pkt",
1559 &rx_thr_num_pkt);
1560 device_property_read_u8(dev, "snps,rx-max-burst",
1561 &rx_max_burst);
1562 device_property_read_u8(dev, "snps,tx-thr-num-pkt",
1563 &tx_thr_num_pkt);
1564 device_property_read_u8(dev, "snps,tx-max-burst",
1565 &tx_max_burst);
1566 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1567 &rx_thr_num_pkt_prd);
1568 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1569 &rx_max_burst_prd);
1570 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1571 &tx_thr_num_pkt_prd);
1572 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1573 &tx_max_burst_prd);
1574 dwc->do_fifo_resize = device_property_read_bool(dev,
1575 "tx-fifo-resize");
1576 if (dwc->do_fifo_resize)
1577 device_property_read_u8(dev, "tx-fifo-max-num",
1578 &tx_fifo_resize_max_num);
1579
1580 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1581 "snps,disable_scramble_quirk");
1582 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1583 "snps,u2exit_lfps_quirk");
1584 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1585 "snps,u2ss_inp3_quirk");
1586 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1587 "snps,req_p1p2p3_quirk");
1588 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1589 "snps,del_p1p2p3_quirk");
1590 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1591 "snps,del_phy_power_chg_quirk");
1592 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1593 "snps,lfps_filter_quirk");
1594 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1595 "snps,rx_detect_poll_quirk");
1596 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1597 "snps,dis_u3_susphy_quirk");
1598 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1599 "snps,dis_u2_susphy_quirk");
1600 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1601 "snps,dis_enblslpm_quirk");
1602 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1603 "snps,dis-u1-entry-quirk");
1604 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1605 "snps,dis-u2-entry-quirk");
1606 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1607 "snps,dis_rxdet_inp3_quirk");
1608 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1609 "snps,dis-u2-freeclk-exists-quirk");
1610 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1611 "snps,dis-del-phy-power-chg-quirk");
1612 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1613 "snps,dis-tx-ipgap-linecheck-quirk");
1614 dwc->resume_hs_terminations = device_property_read_bool(dev,
1615 "snps,resume-hs-terminations");
1616 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
1617 "snps,ulpi-ext-vbus-drv");
1618 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1619 "snps,parkmode-disable-ss-quirk");
1620 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,
1621 "snps,parkmode-disable-hs-quirk");
1622 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
1623 "snps,gfladj-refclk-lpm-sel-quirk");
1624
1625 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1626 "snps,tx_de_emphasis_quirk");
1627 device_property_read_u8(dev, "snps,tx_de_emphasis",
1628 &tx_de_emphasis);
1629 device_property_read_string(dev, "snps,hsphy_interface",
1630 &dwc->hsphy_interface);
1631 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1632 &dwc->fladj);
1633 device_property_read_u32(dev, "snps,ref-clock-period-ns",
1634 &dwc->ref_clk_per);
1635
1636 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1637 "snps,dis_metastability_quirk");
1638
1639 dwc->dis_split_quirk = device_property_read_bool(dev,
1640 "snps,dis-split-quirk");
1641
1642 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1643 dwc->tx_de_emphasis = tx_de_emphasis;
1644
1645 dwc->hird_threshold = hird_threshold;
1646
1647 dwc->rx_thr_num_pkt = rx_thr_num_pkt;
1648 dwc->rx_max_burst = rx_max_burst;
1649
1650 dwc->tx_thr_num_pkt = tx_thr_num_pkt;
1651 dwc->tx_max_burst = tx_max_burst;
1652
1653 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1654 dwc->rx_max_burst_prd = rx_max_burst_prd;
1655
1656 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1657 dwc->tx_max_burst_prd = tx_max_burst_prd;
1658
1659 dwc->imod_interval = 0;
1660
1661 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1662 }
1663
1664 /* check whether the core supports IMOD */
dwc3_has_imod(struct dwc3 * dwc)1665 bool dwc3_has_imod(struct dwc3 *dwc)
1666 {
1667 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1668 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1669 DWC3_IP_IS(DWC32);
1670 }
1671
dwc3_check_params(struct dwc3 * dwc)1672 static void dwc3_check_params(struct dwc3 *dwc)
1673 {
1674 struct device *dev = dwc->dev;
1675 unsigned int hwparam_gen =
1676 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1677
1678 /* Check for proper value of imod_interval */
1679 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1680 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1681 dwc->imod_interval = 0;
1682 }
1683
1684 /*
1685 * Workaround for STAR 9000961433 which affects only version
1686 * 3.00a of the DWC_usb3 core. This prevents the controller
1687 * interrupt from being masked while handling events. IMOD
1688 * allows us to work around this issue. Enable it for the
1689 * affected version.
1690 */
1691 if (!dwc->imod_interval &&
1692 DWC3_VER_IS(DWC3, 300A))
1693 dwc->imod_interval = 1;
1694
1695 /* Check the maximum_speed parameter */
1696 switch (dwc->maximum_speed) {
1697 case USB_SPEED_FULL:
1698 case USB_SPEED_HIGH:
1699 break;
1700 case USB_SPEED_SUPER:
1701 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1702 dev_warn(dev, "UDC doesn't support Gen 1\n");
1703 break;
1704 case USB_SPEED_SUPER_PLUS:
1705 if ((DWC3_IP_IS(DWC32) &&
1706 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1707 (!DWC3_IP_IS(DWC32) &&
1708 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1709 dev_warn(dev, "UDC doesn't support SSP\n");
1710 break;
1711 default:
1712 dev_err(dev, "invalid maximum_speed parameter %d\n",
1713 dwc->maximum_speed);
1714 fallthrough;
1715 case USB_SPEED_UNKNOWN:
1716 switch (hwparam_gen) {
1717 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1718 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1719 break;
1720 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1721 if (DWC3_IP_IS(DWC32))
1722 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1723 else
1724 dwc->maximum_speed = USB_SPEED_SUPER;
1725 break;
1726 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1727 dwc->maximum_speed = USB_SPEED_HIGH;
1728 break;
1729 default:
1730 dwc->maximum_speed = USB_SPEED_SUPER;
1731 break;
1732 }
1733 break;
1734 }
1735
1736 /*
1737 * Currently the controller does not have visibility into the HW
1738 * parameter to determine the maximum number of lanes the HW supports.
1739 * If the number of lanes is not specified in the device property, then
1740 * set the default to support dual-lane for DWC_usb32 and single-lane
1741 * for DWC_usb31 for super-speed-plus.
1742 */
1743 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1744 switch (dwc->max_ssp_rate) {
1745 case USB_SSP_GEN_2x1:
1746 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1747 dev_warn(dev, "UDC only supports Gen 1\n");
1748 break;
1749 case USB_SSP_GEN_1x2:
1750 case USB_SSP_GEN_2x2:
1751 if (DWC3_IP_IS(DWC31))
1752 dev_warn(dev, "UDC only supports single lane\n");
1753 break;
1754 case USB_SSP_GEN_UNKNOWN:
1755 default:
1756 switch (hwparam_gen) {
1757 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1758 if (DWC3_IP_IS(DWC32))
1759 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1760 else
1761 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1762 break;
1763 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1764 if (DWC3_IP_IS(DWC32))
1765 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1766 break;
1767 }
1768 break;
1769 }
1770 }
1771 }
1772
dwc3_get_extcon(struct dwc3 * dwc)1773 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1774 {
1775 struct device *dev = dwc->dev;
1776 struct device_node *np_phy;
1777 struct extcon_dev *edev = NULL;
1778 const char *name;
1779
1780 if (device_property_read_bool(dev, "extcon"))
1781 return extcon_get_edev_by_phandle(dev, 0);
1782
1783 /*
1784 * Device tree platforms should get extcon via phandle.
1785 * On ACPI platforms, we get the name from a device property.
1786 * This device property is for kernel internal use only and
1787 * is expected to be set by the glue code.
1788 */
1789 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1790 return extcon_get_extcon_dev(name);
1791
1792 /*
1793 * Check explicitly if "usb-role-switch" is used since
1794 * extcon_find_edev_by_node() can not be used to check the absence of
1795 * an extcon device. In the absence of an device it will always return
1796 * EPROBE_DEFER.
1797 */
1798 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) &&
1799 device_property_read_bool(dev, "usb-role-switch"))
1800 return NULL;
1801
1802 /*
1803 * Try to get an extcon device from the USB PHY controller's "port"
1804 * node. Check if it has the "port" node first, to avoid printing the
1805 * error message from underlying code, as it's a valid case: extcon
1806 * device (and "port" node) may be missing in case of "usb-role-switch"
1807 * or OTG mode.
1808 */
1809 np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1810 if (of_graph_is_present(np_phy)) {
1811 struct device_node *np_conn;
1812
1813 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1814 if (np_conn)
1815 edev = extcon_find_edev_by_node(np_conn);
1816 of_node_put(np_conn);
1817 }
1818 of_node_put(np_phy);
1819
1820 return edev;
1821 }
1822
dwc3_get_clocks(struct dwc3 * dwc)1823 static int dwc3_get_clocks(struct dwc3 *dwc)
1824 {
1825 struct device *dev = dwc->dev;
1826
1827 if (!dev->of_node)
1828 return 0;
1829
1830 /*
1831 * Clocks are optional, but new DT platforms should support all clocks
1832 * as required by the DT-binding.
1833 * Some devices have different clock names in legacy device trees,
1834 * check for them to retain backwards compatibility.
1835 */
1836 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1837 if (IS_ERR(dwc->bus_clk)) {
1838 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1839 "could not get bus clock\n");
1840 }
1841
1842 if (dwc->bus_clk == NULL) {
1843 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1844 if (IS_ERR(dwc->bus_clk)) {
1845 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1846 "could not get bus clock\n");
1847 }
1848 }
1849
1850 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1851 if (IS_ERR(dwc->ref_clk)) {
1852 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1853 "could not get ref clock\n");
1854 }
1855
1856 if (dwc->ref_clk == NULL) {
1857 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1858 if (IS_ERR(dwc->ref_clk)) {
1859 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1860 "could not get ref clock\n");
1861 }
1862 }
1863
1864 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1865 if (IS_ERR(dwc->susp_clk)) {
1866 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1867 "could not get suspend clock\n");
1868 }
1869
1870 if (dwc->susp_clk == NULL) {
1871 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1872 if (IS_ERR(dwc->susp_clk)) {
1873 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1874 "could not get suspend clock\n");
1875 }
1876 }
1877
1878 return 0;
1879 }
1880
dwc3_get_usb_power_supply(struct dwc3 * dwc)1881 static struct power_supply *dwc3_get_usb_power_supply(struct dwc3 *dwc)
1882 {
1883 struct power_supply *usb_psy;
1884 const char *usb_psy_name;
1885 int ret;
1886
1887 ret = device_property_read_string(dwc->dev, "usb-psy-name", &usb_psy_name);
1888 if (ret < 0)
1889 return NULL;
1890
1891 usb_psy = power_supply_get_by_name(usb_psy_name);
1892 if (!usb_psy)
1893 return ERR_PTR(-EPROBE_DEFER);
1894
1895 return usb_psy;
1896 }
1897
dwc3_probe(struct platform_device * pdev)1898 static int dwc3_probe(struct platform_device *pdev)
1899 {
1900 struct device *dev = &pdev->dev;
1901 struct resource *res, dwc_res;
1902 void __iomem *regs;
1903 struct dwc3 *dwc;
1904 int ret;
1905
1906 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1907 if (!dwc)
1908 return -ENOMEM;
1909
1910 dwc->dev = dev;
1911
1912 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1913 if (!res) {
1914 dev_err(dev, "missing memory resource\n");
1915 return -ENODEV;
1916 }
1917
1918 dwc->xhci_resources[0].start = res->start;
1919 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1920 DWC3_XHCI_REGS_END;
1921 dwc->xhci_resources[0].flags = res->flags;
1922 dwc->xhci_resources[0].name = res->name;
1923
1924 /*
1925 * Request memory region but exclude xHCI regs,
1926 * since it will be requested by the xhci-plat driver.
1927 */
1928 dwc_res = *res;
1929 dwc_res.start += DWC3_GLOBALS_REGS_START;
1930
1931 if (dev->of_node) {
1932 struct device_node *parent = of_get_parent(dev->of_node);
1933
1934 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) {
1935 dwc_res.start -= DWC3_GLOBALS_REGS_START;
1936 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
1937 }
1938
1939 of_node_put(parent);
1940 }
1941
1942 regs = devm_ioremap_resource(dev, &dwc_res);
1943 if (IS_ERR(regs))
1944 return PTR_ERR(regs);
1945
1946 dwc->regs = regs;
1947 dwc->regs_size = resource_size(&dwc_res);
1948
1949 dwc3_get_properties(dwc);
1950
1951 dwc->usb_psy = dwc3_get_usb_power_supply(dwc);
1952 if (IS_ERR(dwc->usb_psy))
1953 return dev_err_probe(dev, PTR_ERR(dwc->usb_psy), "couldn't get usb power supply\n");
1954
1955 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1956 if (IS_ERR(dwc->reset)) {
1957 ret = PTR_ERR(dwc->reset);
1958 goto err_put_psy;
1959 }
1960
1961 ret = dwc3_get_clocks(dwc);
1962 if (ret)
1963 goto err_put_psy;
1964
1965 ret = reset_control_deassert(dwc->reset);
1966 if (ret)
1967 goto err_put_psy;
1968
1969 ret = dwc3_clk_enable(dwc);
1970 if (ret)
1971 goto err_assert_reset;
1972
1973 if (!dwc3_core_is_valid(dwc)) {
1974 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1975 ret = -ENODEV;
1976 goto err_disable_clks;
1977 }
1978
1979 platform_set_drvdata(pdev, dwc);
1980 dwc3_cache_hwparams(dwc);
1981
1982 if (!dwc->sysdev_is_parent &&
1983 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
1984 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1985 if (ret)
1986 goto err_disable_clks;
1987 }
1988
1989 spin_lock_init(&dwc->lock);
1990 mutex_init(&dwc->mutex);
1991
1992 pm_runtime_get_noresume(dev);
1993 pm_runtime_set_active(dev);
1994 pm_runtime_use_autosuspend(dev);
1995 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1996 pm_runtime_enable(dev);
1997
1998 pm_runtime_forbid(dev);
1999
2000 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
2001 if (ret) {
2002 dev_err(dwc->dev, "failed to allocate event buffers\n");
2003 ret = -ENOMEM;
2004 goto err_allow_rpm;
2005 }
2006
2007 dwc->edev = dwc3_get_extcon(dwc);
2008 if (IS_ERR(dwc->edev)) {
2009 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n");
2010 goto err_free_event_buffers;
2011 }
2012
2013 ret = dwc3_get_dr_mode(dwc);
2014 if (ret)
2015 goto err_free_event_buffers;
2016
2017 ret = dwc3_core_init(dwc);
2018 if (ret) {
2019 dev_err_probe(dev, ret, "failed to initialize core\n");
2020 goto err_free_event_buffers;
2021 }
2022
2023 dwc3_check_params(dwc);
2024 dwc3_debugfs_init(dwc);
2025
2026 ret = dwc3_core_init_mode(dwc);
2027 if (ret)
2028 goto err_exit_debugfs;
2029
2030 pm_runtime_put(dev);
2031
2032 dma_set_max_seg_size(dev, UINT_MAX);
2033
2034 return 0;
2035
2036 err_exit_debugfs:
2037 dwc3_debugfs_exit(dwc);
2038 dwc3_event_buffers_cleanup(dwc);
2039 dwc3_phy_power_off(dwc);
2040 dwc3_phy_exit(dwc);
2041 dwc3_ulpi_exit(dwc);
2042 err_free_event_buffers:
2043 dwc3_free_event_buffers(dwc);
2044 err_allow_rpm:
2045 pm_runtime_allow(dev);
2046 pm_runtime_disable(dev);
2047 pm_runtime_dont_use_autosuspend(dev);
2048 pm_runtime_set_suspended(dev);
2049 pm_runtime_put_noidle(dev);
2050 err_disable_clks:
2051 dwc3_clk_disable(dwc);
2052 err_assert_reset:
2053 reset_control_assert(dwc->reset);
2054 err_put_psy:
2055 if (dwc->usb_psy)
2056 power_supply_put(dwc->usb_psy);
2057
2058 return ret;
2059 }
2060
dwc3_remove(struct platform_device * pdev)2061 static void dwc3_remove(struct platform_device *pdev)
2062 {
2063 struct dwc3 *dwc = platform_get_drvdata(pdev);
2064
2065 pm_runtime_get_sync(&pdev->dev);
2066
2067 dwc3_core_exit_mode(dwc);
2068 dwc3_debugfs_exit(dwc);
2069
2070 dwc3_core_exit(dwc);
2071 dwc3_ulpi_exit(dwc);
2072
2073 pm_runtime_allow(&pdev->dev);
2074 pm_runtime_disable(&pdev->dev);
2075 pm_runtime_dont_use_autosuspend(&pdev->dev);
2076 pm_runtime_put_noidle(&pdev->dev);
2077 /*
2078 * HACK: Clear the driver data, which is currently accessed by parent
2079 * glue drivers, before allowing the parent to suspend.
2080 */
2081 platform_set_drvdata(pdev, NULL);
2082 pm_runtime_set_suspended(&pdev->dev);
2083
2084 dwc3_free_event_buffers(dwc);
2085
2086 if (dwc->usb_psy)
2087 power_supply_put(dwc->usb_psy);
2088 }
2089
2090 #ifdef CONFIG_PM
dwc3_core_init_for_resume(struct dwc3 * dwc)2091 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
2092 {
2093 int ret;
2094
2095 ret = reset_control_deassert(dwc->reset);
2096 if (ret)
2097 return ret;
2098
2099 ret = dwc3_clk_enable(dwc);
2100 if (ret)
2101 goto assert_reset;
2102
2103 ret = dwc3_core_init(dwc);
2104 if (ret)
2105 goto disable_clks;
2106
2107 return 0;
2108
2109 disable_clks:
2110 dwc3_clk_disable(dwc);
2111 assert_reset:
2112 reset_control_assert(dwc->reset);
2113
2114 return ret;
2115 }
2116
dwc3_suspend_common(struct dwc3 * dwc,pm_message_t msg)2117 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
2118 {
2119 u32 reg;
2120
2121 if (!pm_runtime_suspended(dwc->dev) && !PMSG_IS_AUTO(msg)) {
2122 dwc->susphy_state = (dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)) &
2123 DWC3_GUSB2PHYCFG_SUSPHY) ||
2124 (dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)) &
2125 DWC3_GUSB3PIPECTL_SUSPHY);
2126 /*
2127 * TI AM62 platform requires SUSPHY to be
2128 * enabled for system suspend to work.
2129 */
2130 if (!dwc->susphy_state)
2131 dwc3_enable_susphy(dwc, true);
2132 }
2133
2134 switch (dwc->current_dr_role) {
2135 case DWC3_GCTL_PRTCAP_DEVICE:
2136 if (pm_runtime_suspended(dwc->dev))
2137 break;
2138 dwc3_gadget_suspend(dwc);
2139 synchronize_irq(dwc->irq_gadget);
2140 dwc3_core_exit(dwc);
2141 break;
2142 case DWC3_GCTL_PRTCAP_HOST:
2143 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2144 dwc3_core_exit(dwc);
2145 break;
2146 }
2147
2148 /* Let controller to suspend HSPHY before PHY driver suspends */
2149 if (dwc->dis_u2_susphy_quirk ||
2150 dwc->dis_enblslpm_quirk) {
2151 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2152 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
2153 DWC3_GUSB2PHYCFG_SUSPHY;
2154 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2155
2156 /* Give some time for USB2 PHY to suspend */
2157 usleep_range(5000, 6000);
2158 }
2159
2160 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
2161 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
2162 break;
2163 case DWC3_GCTL_PRTCAP_OTG:
2164 /* do nothing during runtime_suspend */
2165 if (PMSG_IS_AUTO(msg))
2166 break;
2167
2168 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2169 dwc3_gadget_suspend(dwc);
2170 synchronize_irq(dwc->irq_gadget);
2171 }
2172
2173 dwc3_otg_exit(dwc);
2174 dwc3_core_exit(dwc);
2175 break;
2176 default:
2177 /* do nothing */
2178 break;
2179 }
2180
2181 return 0;
2182 }
2183
dwc3_resume_common(struct dwc3 * dwc,pm_message_t msg)2184 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
2185 {
2186 int ret;
2187 u32 reg;
2188
2189 switch (dwc->current_dr_role) {
2190 case DWC3_GCTL_PRTCAP_DEVICE:
2191 ret = dwc3_core_init_for_resume(dwc);
2192 if (ret)
2193 return ret;
2194
2195 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2196 dwc3_gadget_resume(dwc);
2197 break;
2198 case DWC3_GCTL_PRTCAP_HOST:
2199 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2200 ret = dwc3_core_init_for_resume(dwc);
2201 if (ret)
2202 return ret;
2203 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2204 break;
2205 }
2206 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2207 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2208 if (dwc->dis_u2_susphy_quirk)
2209 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2210
2211 if (dwc->dis_enblslpm_quirk)
2212 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2213
2214 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2215
2216 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2217 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
2218 break;
2219 case DWC3_GCTL_PRTCAP_OTG:
2220 /* nothing to do on runtime_resume */
2221 if (PMSG_IS_AUTO(msg))
2222 break;
2223
2224 ret = dwc3_core_init_for_resume(dwc);
2225 if (ret)
2226 return ret;
2227
2228 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2229
2230 dwc3_otg_init(dwc);
2231 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2232 dwc3_otg_host_init(dwc);
2233 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2234 dwc3_gadget_resume(dwc);
2235 }
2236
2237 break;
2238 default:
2239 /* do nothing */
2240 break;
2241 }
2242
2243 if (!PMSG_IS_AUTO(msg)) {
2244 /* restore SUSPHY state to that before system suspend. */
2245 dwc3_enable_susphy(dwc, dwc->susphy_state);
2246 }
2247
2248 return 0;
2249 }
2250
dwc3_runtime_checks(struct dwc3 * dwc)2251 static int dwc3_runtime_checks(struct dwc3 *dwc)
2252 {
2253 switch (dwc->current_dr_role) {
2254 case DWC3_GCTL_PRTCAP_DEVICE:
2255 if (dwc->connected)
2256 return -EBUSY;
2257 break;
2258 case DWC3_GCTL_PRTCAP_HOST:
2259 default:
2260 /* do nothing */
2261 break;
2262 }
2263
2264 return 0;
2265 }
2266
dwc3_runtime_suspend(struct device * dev)2267 static int dwc3_runtime_suspend(struct device *dev)
2268 {
2269 struct dwc3 *dwc = dev_get_drvdata(dev);
2270 int ret;
2271
2272 if (dwc3_runtime_checks(dwc))
2273 return -EBUSY;
2274
2275 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2276 if (ret)
2277 return ret;
2278
2279 return 0;
2280 }
2281
dwc3_runtime_resume(struct device * dev)2282 static int dwc3_runtime_resume(struct device *dev)
2283 {
2284 struct dwc3 *dwc = dev_get_drvdata(dev);
2285 int ret;
2286
2287 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2288 if (ret)
2289 return ret;
2290
2291 switch (dwc->current_dr_role) {
2292 case DWC3_GCTL_PRTCAP_DEVICE:
2293 if (dwc->pending_events) {
2294 pm_runtime_put(dwc->dev);
2295 dwc->pending_events = false;
2296 enable_irq(dwc->irq_gadget);
2297 }
2298 break;
2299 case DWC3_GCTL_PRTCAP_HOST:
2300 default:
2301 /* do nothing */
2302 break;
2303 }
2304
2305 pm_runtime_mark_last_busy(dev);
2306
2307 return 0;
2308 }
2309
dwc3_runtime_idle(struct device * dev)2310 static int dwc3_runtime_idle(struct device *dev)
2311 {
2312 struct dwc3 *dwc = dev_get_drvdata(dev);
2313
2314 switch (dwc->current_dr_role) {
2315 case DWC3_GCTL_PRTCAP_DEVICE:
2316 if (dwc3_runtime_checks(dwc))
2317 return -EBUSY;
2318 break;
2319 case DWC3_GCTL_PRTCAP_HOST:
2320 default:
2321 /* do nothing */
2322 break;
2323 }
2324
2325 pm_runtime_mark_last_busy(dev);
2326 pm_runtime_autosuspend(dev);
2327
2328 return 0;
2329 }
2330 #endif /* CONFIG_PM */
2331
2332 #ifdef CONFIG_PM_SLEEP
dwc3_suspend(struct device * dev)2333 static int dwc3_suspend(struct device *dev)
2334 {
2335 struct dwc3 *dwc = dev_get_drvdata(dev);
2336 int ret;
2337
2338 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2339 if (ret)
2340 return ret;
2341
2342 pinctrl_pm_select_sleep_state(dev);
2343
2344 return 0;
2345 }
2346
dwc3_resume(struct device * dev)2347 static int dwc3_resume(struct device *dev)
2348 {
2349 struct dwc3 *dwc = dev_get_drvdata(dev);
2350 int ret;
2351
2352 pinctrl_pm_select_default_state(dev);
2353
2354 ret = dwc3_resume_common(dwc, PMSG_RESUME);
2355 if (ret)
2356 return ret;
2357
2358 pm_runtime_disable(dev);
2359 pm_runtime_set_active(dev);
2360 pm_runtime_enable(dev);
2361
2362 return 0;
2363 }
2364
dwc3_complete(struct device * dev)2365 static void dwc3_complete(struct device *dev)
2366 {
2367 struct dwc3 *dwc = dev_get_drvdata(dev);
2368 u32 reg;
2369
2370 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2371 dwc->dis_split_quirk) {
2372 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2373 reg |= DWC3_GUCTL3_SPLITDISABLE;
2374 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2375 }
2376 }
2377 #else
2378 #define dwc3_complete NULL
2379 #endif /* CONFIG_PM_SLEEP */
2380
2381 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2382 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2383 .complete = dwc3_complete,
2384
2385 /*
2386 * Runtime suspend halts the controller on disconnection. It relies on
2387 * platforms with custom connection notification to start the controller
2388 * again.
2389 */
2390 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2391 dwc3_runtime_idle)
2392 };
2393
2394 #ifdef CONFIG_OF
2395 static const struct of_device_id of_dwc3_match[] = {
2396 {
2397 .compatible = "snps,dwc3"
2398 },
2399 {
2400 .compatible = "synopsys,dwc3"
2401 },
2402 { },
2403 };
2404 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2405 #endif
2406
2407 #ifdef CONFIG_ACPI
2408
2409 #define ACPI_ID_INTEL_BSW "808622B7"
2410
2411 static const struct acpi_device_id dwc3_acpi_match[] = {
2412 { ACPI_ID_INTEL_BSW, 0 },
2413 { },
2414 };
2415 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2416 #endif
2417
2418 static struct platform_driver dwc3_driver = {
2419 .probe = dwc3_probe,
2420 .remove_new = dwc3_remove,
2421 .driver = {
2422 .name = "dwc3",
2423 .of_match_table = of_match_ptr(of_dwc3_match),
2424 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2425 .pm = &dwc3_dev_pm_ops,
2426 },
2427 };
2428
2429 module_platform_driver(dwc3_driver);
2430
2431 MODULE_ALIAS("platform:dwc3");
2432 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2433 MODULE_LICENSE("GPL v2");
2434 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
2435