1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/iopoll.h>
11 #include <linux/math64.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/of_platform.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20
21 #include <video/mipi_display.h>
22
23 #include <drm/bridge/dw_mipi_dsi.h>
24 #include <drm/drm_mipi_dsi.h>
25 #include <drm/drm_of.h>
26 #include <drm/drm_simple_kms_helper.h>
27
28 #include "rockchip_drm_drv.h"
29
30 #define DSI_PHY_RSTZ 0xa0
31 #define PHY_DISFORCEPLL 0
32 #define PHY_ENFORCEPLL BIT(3)
33 #define PHY_DISABLECLK 0
34 #define PHY_ENABLECLK BIT(2)
35 #define PHY_RSTZ 0
36 #define PHY_UNRSTZ BIT(1)
37 #define PHY_SHUTDOWNZ 0
38 #define PHY_UNSHUTDOWNZ BIT(0)
39
40 #define DSI_PHY_IF_CFG 0xa4
41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
42 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
43
44 #define DSI_PHY_STATUS 0xb0
45 #define LOCK BIT(0)
46 #define STOP_STATE_CLK_LANE BIT(2)
47
48 #define DSI_PHY_TST_CTRL0 0xb4
49 #define PHY_TESTCLK BIT(1)
50 #define PHY_UNTESTCLK 0
51 #define PHY_TESTCLR BIT(0)
52 #define PHY_UNTESTCLR 0
53
54 #define DSI_PHY_TST_CTRL1 0xb8
55 #define PHY_TESTEN BIT(16)
56 #define PHY_UNTESTEN 0
57 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
58 #define PHY_TESTDIN(n) (((n) & 0xff) << 0)
59
60 #define DSI_INT_ST0 0xbc
61 #define DSI_INT_ST1 0xc0
62 #define DSI_INT_MSK0 0xc4
63 #define DSI_INT_MSK1 0xc8
64
65 #define PHY_STATUS_TIMEOUT_US 10000
66 #define CMD_PKT_STATUS_TIMEOUT_US 20000
67
68 #define BYPASS_VCO_RANGE BIT(7)
69 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
70 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
71 #define VCO_IN_CAP_CON_LOW (0x1 << 1)
72 #define VCO_IN_CAP_CON_HIGH (0x2 << 1)
73 #define REF_BIAS_CUR_SEL BIT(0)
74
75 #define CP_CURRENT_3UA 0x1
76 #define CP_CURRENT_4_5UA 0x2
77 #define CP_CURRENT_7_5UA 0x6
78 #define CP_CURRENT_6UA 0x9
79 #define CP_CURRENT_12UA 0xb
80 #define CP_CURRENT_SEL(val) ((val) & 0xf)
81 #define CP_PROGRAM_EN BIT(7)
82
83 #define LPF_RESISTORS_15_5KOHM 0x1
84 #define LPF_RESISTORS_13KOHM 0x2
85 #define LPF_RESISTORS_11_5KOHM 0x4
86 #define LPF_RESISTORS_10_5KOHM 0x8
87 #define LPF_RESISTORS_8KOHM 0x10
88 #define LPF_PROGRAM_EN BIT(6)
89 #define LPF_RESISTORS_SEL(val) ((val) & 0x3f)
90
91 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
92
93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
94 #define LOW_PROGRAM_EN 0
95 #define HIGH_PROGRAM_EN BIT(7)
96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
98 #define PLL_LOOP_DIV_EN BIT(5)
99 #define PLL_INPUT_DIV_EN BIT(4)
100
101 #define POWER_CONTROL BIT(6)
102 #define INTERNAL_REG_CURRENT BIT(3)
103 #define BIAS_BLOCK_ON BIT(2)
104 #define BANDGAP_ON BIT(0)
105
106 #define TER_RESISTOR_HIGH BIT(7)
107 #define TER_RESISTOR_LOW 0
108 #define LEVEL_SHIFTERS_ON BIT(6)
109 #define TER_CAL_DONE BIT(5)
110 #define SETRD_MAX (0x7 << 2)
111 #define POWER_MANAGE BIT(1)
112 #define TER_RESISTORS_ON BIT(0)
113
114 #define BIASEXTR_SEL(val) ((val) & 0x7)
115 #define BANDGAP_SEL(val) ((val) & 0x7)
116 #define TLP_PROGRAM_EN BIT(7)
117 #define THS_PRE_PROGRAM_EN BIT(7)
118 #define THS_ZERO_PROGRAM_EN BIT(6)
119
120 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10
121 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11
122 #define PLL_LPF_AND_CP_CONTROL 0x12
123 #define PLL_INPUT_DIVIDER_RATIO 0x17
124 #define PLL_LOOP_DIVIDER_RATIO 0x18
125 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19
126 #define BANDGAP_AND_BIAS_CONTROL 0x20
127 #define TERMINATION_RESISTER_CONTROL 0x21
128 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22
129 #define HS_RX_CONTROL_OF_LANE_CLK 0x34
130 #define HS_RX_CONTROL_OF_LANE_0 0x44
131 #define HS_RX_CONTROL_OF_LANE_1 0x54
132 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60
133 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61
134 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62
135 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63
136 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64
137 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65
138 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70
139 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71
140 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72
141 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73
142 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74
143 #define HS_RX_DATA_LANE_THS_SETTLE_CONTROL 0x75
144 #define HS_RX_CONTROL_OF_LANE_2 0x84
145 #define HS_RX_CONTROL_OF_LANE_3 0x94
146
147 #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0)
148 #define DW_MIPI_NEEDS_GRF_CLK BIT(1)
149
150 #define PX30_GRF_PD_VO_CON1 0x0438
151 #define PX30_DSI_FORCETXSTOPMODE (0xf << 7)
152 #define PX30_DSI_FORCERXMODE BIT(6)
153 #define PX30_DSI_TURNDISABLE BIT(5)
154 #define PX30_DSI_LCDC_SEL BIT(0)
155
156 #define RK3288_GRF_SOC_CON6 0x025c
157 #define RK3288_DSI0_LCDC_SEL BIT(6)
158 #define RK3288_DSI1_LCDC_SEL BIT(9)
159
160 #define RK3399_GRF_SOC_CON20 0x6250
161 #define RK3399_DSI0_LCDC_SEL BIT(0)
162 #define RK3399_DSI1_LCDC_SEL BIT(4)
163
164 #define RK3399_GRF_SOC_CON22 0x6258
165 #define RK3399_DSI0_TURNREQUEST (0xf << 12)
166 #define RK3399_DSI0_TURNDISABLE (0xf << 8)
167 #define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4)
168 #define RK3399_DSI0_FORCERXMODE (0xf << 0)
169
170 #define RK3399_GRF_SOC_CON23 0x625c
171 #define RK3399_DSI1_TURNDISABLE (0xf << 12)
172 #define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8)
173 #define RK3399_DSI1_FORCERXMODE (0xf << 4)
174 #define RK3399_DSI1_ENABLE (0xf << 0)
175
176 #define RK3399_GRF_SOC_CON24 0x6260
177 #define RK3399_TXRX_MASTERSLAVEZ BIT(7)
178 #define RK3399_TXRX_ENABLECLK BIT(6)
179 #define RK3399_TXRX_BASEDIR BIT(5)
180 #define RK3399_TXRX_SRC_SEL_ISP0 BIT(4)
181 #define RK3399_TXRX_TURNREQUEST GENMASK(3, 0)
182
183 #define RK3568_GRF_VO_CON2 0x0368
184 #define RK3568_DSI0_SKEWCALHS (0x1f << 11)
185 #define RK3568_DSI0_FORCETXSTOPMODE (0xf << 4)
186 #define RK3568_DSI0_TURNDISABLE BIT(2)
187 #define RK3568_DSI0_FORCERXMODE BIT(0)
188
189 /*
190 * Note these registers do not appear in the datasheet, they are
191 * however present in the BSP driver which is where these values
192 * come from. Name GRF_VO_CON3 is assumed.
193 */
194 #define RK3568_GRF_VO_CON3 0x36c
195 #define RK3568_DSI1_SKEWCALHS (0x1f << 11)
196 #define RK3568_DSI1_FORCETXSTOPMODE (0xf << 4)
197 #define RK3568_DSI1_TURNDISABLE BIT(2)
198 #define RK3568_DSI1_FORCERXMODE BIT(0)
199
200 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
201
202 enum {
203 DW_DSI_USAGE_IDLE,
204 DW_DSI_USAGE_DSI,
205 DW_DSI_USAGE_PHY,
206 };
207
208 enum {
209 BANDGAP_97_07,
210 BANDGAP_98_05,
211 BANDGAP_99_02,
212 BANDGAP_100_00,
213 BANDGAP_93_17,
214 BANDGAP_94_15,
215 BANDGAP_95_12,
216 BANDGAP_96_10,
217 };
218
219 enum {
220 BIASEXTR_87_1,
221 BIASEXTR_91_5,
222 BIASEXTR_95_9,
223 BIASEXTR_100,
224 BIASEXTR_105_94,
225 BIASEXTR_111_88,
226 BIASEXTR_118_8,
227 BIASEXTR_127_7,
228 };
229
230 struct rockchip_dw_dsi_chip_data {
231 u32 reg;
232
233 u32 lcdsel_grf_reg;
234 u32 lcdsel_big;
235 u32 lcdsel_lit;
236
237 u32 enable_grf_reg;
238 u32 enable;
239
240 u32 lanecfg1_grf_reg;
241 u32 lanecfg1;
242 u32 lanecfg2_grf_reg;
243 u32 lanecfg2;
244
245 int (*dphy_rx_init)(struct phy *phy);
246 int (*dphy_rx_power_on)(struct phy *phy);
247 int (*dphy_rx_power_off)(struct phy *phy);
248
249 unsigned int flags;
250 unsigned int max_data_lanes;
251 };
252
253 struct dw_mipi_dsi_rockchip {
254 struct device *dev;
255 struct rockchip_encoder encoder;
256 void __iomem *base;
257
258 struct regmap *grf_regmap;
259 struct clk *pclk;
260 struct clk *pllref_clk;
261 struct clk *grf_clk;
262 struct clk *phy_cfg_clk;
263
264 /* dual-channel */
265 bool is_slave;
266 struct dw_mipi_dsi_rockchip *slave;
267
268 /* optional external dphy */
269 struct phy *phy;
270 union phy_configure_opts phy_opts;
271
272 /* being a phy for other mipi hosts */
273 unsigned int usage_mode;
274 struct mutex usage_mutex;
275 struct phy *dphy;
276 struct phy_configure_opts_mipi_dphy dphy_config;
277
278 unsigned int lane_mbps; /* per lane */
279 u16 input_div;
280 u16 feedback_div;
281 u32 format;
282
283 struct dw_mipi_dsi *dmd;
284 const struct rockchip_dw_dsi_chip_data *cdata;
285 struct dw_mipi_dsi_plat_data pdata;
286
287 bool dsi_bound;
288 };
289
to_dsi(struct drm_encoder * encoder)290 static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder)
291 {
292 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
293
294 return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder);
295 }
296
297 struct dphy_pll_parameter_map {
298 unsigned int max_mbps;
299 u8 hsfreqrange;
300 u8 icpctrl;
301 u8 lpfctrl;
302 };
303
304 /* The table is based on 27MHz DPHY pll reference clock. */
305 static const struct dphy_pll_parameter_map dppa_map[] = {
306 { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
307 { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
308 { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
309 { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
310 { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
311 { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
312 { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
313 { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
314 { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
315 { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
316 { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
317 { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
318 { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
319 { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
320 { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
321 { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
322 { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
323 { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
324 { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
325 { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
326 { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
327 { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
328 { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
329 { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
330 { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
331 { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
332 { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
333 { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
334 { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
335 {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
336 {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
337 {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
338 {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
339 {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
340 {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
341 {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
342 {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
343 {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
344 {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }
345 };
346
max_mbps_to_parameter(unsigned int max_mbps)347 static int max_mbps_to_parameter(unsigned int max_mbps)
348 {
349 int i;
350
351 for (i = 0; i < ARRAY_SIZE(dppa_map); i++)
352 if (dppa_map[i].max_mbps >= max_mbps)
353 return i;
354
355 return -EINVAL;
356 }
357
dsi_write(struct dw_mipi_dsi_rockchip * dsi,u32 reg,u32 val)358 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val)
359 {
360 writel(val, dsi->base + reg);
361 }
362
dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip * dsi,u8 test_code,u8 test_data)363 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi,
364 u8 test_code,
365 u8 test_data)
366 {
367 /*
368 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
369 * is latched internally as the current test code. Test data is
370 * programmed internally by rising edge on TESTCLK.
371 */
372 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
373
374 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
375 PHY_TESTDIN(test_code));
376
377 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
378
379 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
380 PHY_TESTDIN(test_data));
381
382 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
383 }
384
385 /*
386 * ns2bc - Nanoseconds to byte clock cycles
387 */
ns2bc(struct dw_mipi_dsi_rockchip * dsi,int ns)388 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns)
389 {
390 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
391 }
392
393 /*
394 * ns2ui - Nanoseconds to UI time periods
395 */
ns2ui(struct dw_mipi_dsi_rockchip * dsi,int ns)396 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns)
397 {
398 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
399 }
400
dw_mipi_dsi_phy_init(void * priv_data)401 static int dw_mipi_dsi_phy_init(void *priv_data)
402 {
403 struct dw_mipi_dsi_rockchip *dsi = priv_data;
404 int ret, i, vco;
405
406 if (dsi->phy)
407 return 0;
408
409 /*
410 * Get vco from frequency(lane_mbps)
411 * vco frequency table
412 * 000 - between 80 and 200 MHz
413 * 001 - between 200 and 300 MHz
414 * 010 - between 300 and 500 MHz
415 * 011 - between 500 and 700 MHz
416 * 100 - between 700 and 900 MHz
417 * 101 - between 900 and 1100 MHz
418 * 110 - between 1100 and 1300 MHz
419 * 111 - between 1300 and 1500 MHz
420 */
421 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
422
423 i = max_mbps_to_parameter(dsi->lane_mbps);
424 if (i < 0) {
425 DRM_DEV_ERROR(dsi->dev,
426 "failed to get parameter for %dmbps clock\n",
427 dsi->lane_mbps);
428 return i;
429 }
430
431 ret = clk_prepare_enable(dsi->phy_cfg_clk);
432 if (ret) {
433 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
434 return ret;
435 }
436
437 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
438 BYPASS_VCO_RANGE |
439 VCO_RANGE_CON_SEL(vco) |
440 VCO_IN_CAP_CON_LOW |
441 REF_BIAS_CUR_SEL);
442
443 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
444 CP_CURRENT_SEL(dppa_map[i].icpctrl));
445 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
446 CP_PROGRAM_EN | LPF_PROGRAM_EN |
447 LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));
448
449 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
450 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
451
452 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
453 INPUT_DIVIDER(dsi->input_div));
454 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
455 LOOP_DIV_LOW_SEL(dsi->feedback_div) |
456 LOW_PROGRAM_EN);
457 /*
458 * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately
459 * to make the configured LSB effective according to IP simulation
460 * and lab test results.
461 * Only in this way can we get correct mipi phy pll frequency.
462 */
463 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
464 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
465 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
466 LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
467 HIGH_PROGRAM_EN);
468 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
469 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
470
471 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
472 LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7));
473 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
474 HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10));
475
476 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
477 POWER_CONTROL | INTERNAL_REG_CURRENT |
478 BIAS_BLOCK_ON | BANDGAP_ON);
479
480 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
481 TER_RESISTOR_LOW | TER_CAL_DONE |
482 SETRD_MAX | TER_RESISTORS_ON);
483 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
484 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
485 SETRD_MAX | POWER_MANAGE |
486 TER_RESISTORS_ON);
487
488 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
489 TLP_PROGRAM_EN | ns2bc(dsi, 500));
490 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
491 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
492 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
493 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
494 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
495 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
496 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
497 BIT(5) | ns2bc(dsi, 100));
498 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
499 BIT(5) | (ns2bc(dsi, 60) + 7));
500
501 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
502 TLP_PROGRAM_EN | ns2bc(dsi, 500));
503 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
504 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
505 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
506 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
507 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
508 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
509 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
510 BIT(5) | ns2bc(dsi, 100));
511
512 clk_disable_unprepare(dsi->phy_cfg_clk);
513
514 return ret;
515 }
516
dw_mipi_dsi_phy_power_on(void * priv_data)517 static void dw_mipi_dsi_phy_power_on(void *priv_data)
518 {
519 struct dw_mipi_dsi_rockchip *dsi = priv_data;
520 int ret;
521
522 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
523 if (ret) {
524 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
525 return;
526 }
527
528 phy_configure(dsi->phy, &dsi->phy_opts);
529 phy_power_on(dsi->phy);
530 }
531
dw_mipi_dsi_phy_power_off(void * priv_data)532 static void dw_mipi_dsi_phy_power_off(void *priv_data)
533 {
534 struct dw_mipi_dsi_rockchip *dsi = priv_data;
535
536 phy_power_off(dsi->phy);
537 }
538
539 static int
dw_mipi_dsi_get_lane_mbps(void * priv_data,const struct drm_display_mode * mode,unsigned long mode_flags,u32 lanes,u32 format,unsigned int * lane_mbps)540 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
541 unsigned long mode_flags, u32 lanes, u32 format,
542 unsigned int *lane_mbps)
543 {
544 struct dw_mipi_dsi_rockchip *dsi = priv_data;
545 int bpp;
546 unsigned long mpclk, tmp;
547 unsigned int target_mbps = 1000;
548 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
549 unsigned long best_freq = 0;
550 unsigned long fvco_min, fvco_max, fin, fout;
551 unsigned int min_prediv, max_prediv;
552 unsigned int _prediv, best_prediv;
553 unsigned long _fbdiv, best_fbdiv;
554 unsigned long min_delta = ULONG_MAX;
555
556 dsi->format = format;
557 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
558 if (bpp < 0) {
559 DRM_DEV_ERROR(dsi->dev,
560 "failed to get bpp for pixel format %d\n",
561 dsi->format);
562 return bpp;
563 }
564
565 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
566 if (mpclk) {
567 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
568 tmp = mpclk * (bpp / lanes) * 10 / 8;
569 if (tmp < max_mbps)
570 target_mbps = tmp;
571 else
572 DRM_DEV_ERROR(dsi->dev,
573 "DPHY clock frequency is out of range\n");
574 }
575
576 /* for external phy only a the mipi_dphy_config is necessary */
577 if (dsi->phy) {
578 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8,
579 bpp, lanes,
580 &dsi->phy_opts.mipi_dphy);
581 dsi->lane_mbps = target_mbps;
582 *lane_mbps = dsi->lane_mbps;
583
584 return 0;
585 }
586
587 fin = clk_get_rate(dsi->pllref_clk);
588 fout = target_mbps * USEC_PER_SEC;
589
590 /* constraint: 5Mhz <= Fref / N <= 40MHz */
591 min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
592 max_prediv = fin / (5 * USEC_PER_SEC);
593
594 /* constraint: 80MHz <= Fvco <= 1500Mhz */
595 fvco_min = 80 * USEC_PER_SEC;
596 fvco_max = 1500 * USEC_PER_SEC;
597
598 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
599 u64 tmp;
600 u32 delta;
601 /* Fvco = Fref * M / N */
602 tmp = (u64)fout * _prediv;
603 do_div(tmp, fin);
604 _fbdiv = tmp;
605 /*
606 * Due to the use of a "by 2 pre-scaler," the range of the
607 * feedback multiplication value M is limited to even division
608 * numbers, and m must be greater than 6, not bigger than 512.
609 */
610 if (_fbdiv < 6 || _fbdiv > 512)
611 continue;
612
613 _fbdiv += _fbdiv % 2;
614
615 tmp = (u64)_fbdiv * fin;
616 do_div(tmp, _prediv);
617 if (tmp < fvco_min || tmp > fvco_max)
618 continue;
619
620 delta = abs(fout - tmp);
621 if (delta < min_delta) {
622 best_prediv = _prediv;
623 best_fbdiv = _fbdiv;
624 min_delta = delta;
625 best_freq = tmp;
626 }
627 }
628
629 if (best_freq) {
630 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
631 *lane_mbps = dsi->lane_mbps;
632 dsi->input_div = best_prediv;
633 dsi->feedback_div = best_fbdiv;
634 } else {
635 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");
636 return -EINVAL;
637 }
638
639 return 0;
640 }
641
642 struct hstt {
643 unsigned int maxfreq;
644 struct dw_mipi_dsi_dphy_timing timing;
645 };
646
647 #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \
648 { \
649 .maxfreq = _maxfreq, \
650 .timing = { \
651 .clk_lp2hs = _c_lp2hs, \
652 .clk_hs2lp = _c_hs2lp, \
653 .data_lp2hs = _d_lp2hs, \
654 .data_hs2lp = _d_hs2lp, \
655 } \
656 }
657
658 /* Table A-3 High-Speed Transition Times */
659 static struct hstt hstt_table[] = {
660 HSTT( 90, 32, 20, 26, 13),
661 HSTT( 100, 35, 23, 28, 14),
662 HSTT( 110, 32, 22, 26, 13),
663 HSTT( 130, 31, 20, 27, 13),
664 HSTT( 140, 33, 22, 26, 14),
665 HSTT( 150, 33, 21, 26, 14),
666 HSTT( 170, 32, 20, 27, 13),
667 HSTT( 180, 36, 23, 30, 15),
668 HSTT( 200, 40, 22, 33, 15),
669 HSTT( 220, 40, 22, 33, 15),
670 HSTT( 240, 44, 24, 36, 16),
671 HSTT( 250, 48, 24, 38, 17),
672 HSTT( 270, 48, 24, 38, 17),
673 HSTT( 300, 50, 27, 41, 18),
674 HSTT( 330, 56, 28, 45, 18),
675 HSTT( 360, 59, 28, 48, 19),
676 HSTT( 400, 61, 30, 50, 20),
677 HSTT( 450, 67, 31, 55, 21),
678 HSTT( 500, 73, 31, 59, 22),
679 HSTT( 550, 79, 36, 63, 24),
680 HSTT( 600, 83, 37, 68, 25),
681 HSTT( 650, 90, 38, 73, 27),
682 HSTT( 700, 95, 40, 77, 28),
683 HSTT( 750, 102, 40, 84, 28),
684 HSTT( 800, 106, 42, 87, 30),
685 HSTT( 850, 113, 44, 93, 31),
686 HSTT( 900, 118, 47, 98, 32),
687 HSTT( 950, 124, 47, 102, 34),
688 HSTT(1000, 130, 49, 107, 35),
689 HSTT(1050, 135, 51, 111, 37),
690 HSTT(1100, 139, 51, 114, 38),
691 HSTT(1150, 146, 54, 120, 40),
692 HSTT(1200, 153, 57, 125, 41),
693 HSTT(1250, 158, 58, 130, 42),
694 HSTT(1300, 163, 58, 135, 44),
695 HSTT(1350, 168, 60, 140, 45),
696 HSTT(1400, 172, 64, 144, 47),
697 HSTT(1450, 176, 65, 148, 48),
698 HSTT(1500, 181, 66, 153, 50)
699 };
700
701 static int
dw_mipi_dsi_phy_get_timing(void * priv_data,unsigned int lane_mbps,struct dw_mipi_dsi_dphy_timing * timing)702 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
703 struct dw_mipi_dsi_dphy_timing *timing)
704 {
705 int i;
706
707 for (i = 0; i < ARRAY_SIZE(hstt_table); i++)
708 if (lane_mbps < hstt_table[i].maxfreq)
709 break;
710
711 if (i == ARRAY_SIZE(hstt_table))
712 i--;
713
714 *timing = hstt_table[i].timing;
715
716 return 0;
717 }
718
719 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
720 .init = dw_mipi_dsi_phy_init,
721 .power_on = dw_mipi_dsi_phy_power_on,
722 .power_off = dw_mipi_dsi_phy_power_off,
723 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
724 .get_timing = dw_mipi_dsi_phy_get_timing,
725 };
726
dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip * dsi)727 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi)
728 {
729 if (dsi->cdata->lanecfg1_grf_reg)
730 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,
731 dsi->cdata->lanecfg1);
732
733 if (dsi->cdata->lanecfg2_grf_reg)
734 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg,
735 dsi->cdata->lanecfg2);
736
737 if (dsi->cdata->enable_grf_reg)
738 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg,
739 dsi->cdata->enable);
740 }
741
dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip * dsi,int mux)742 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi,
743 int mux)
744 {
745 if (dsi->cdata->lcdsel_grf_reg)
746 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
747 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
748 }
749
750 static int
dw_mipi_dsi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)751 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
752 struct drm_crtc_state *crtc_state,
753 struct drm_connector_state *conn_state)
754 {
755 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
756 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
757
758 switch (dsi->format) {
759 case MIPI_DSI_FMT_RGB888:
760 s->output_mode = ROCKCHIP_OUT_MODE_P888;
761 break;
762 case MIPI_DSI_FMT_RGB666:
763 s->output_mode = ROCKCHIP_OUT_MODE_P666;
764 break;
765 case MIPI_DSI_FMT_RGB565:
766 s->output_mode = ROCKCHIP_OUT_MODE_P565;
767 break;
768 default:
769 WARN_ON(1);
770 return -EINVAL;
771 }
772
773 s->output_type = DRM_MODE_CONNECTOR_DSI;
774 if (dsi->slave)
775 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL;
776
777 return 0;
778 }
779
dw_mipi_dsi_encoder_enable(struct drm_encoder * encoder)780 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
781 {
782 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
783 int ret, mux;
784
785 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
786 &dsi->encoder.encoder);
787 if (mux < 0)
788 return;
789
790 /*
791 * For the RK3399, the clk of grf must be enabled before writing grf
792 * register. And for RK3288 or other soc, this grf_clk must be NULL,
793 * the clk_prepare_enable return true directly.
794 */
795 ret = clk_prepare_enable(dsi->grf_clk);
796 if (ret) {
797 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
798 return;
799 }
800
801 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux);
802 if (dsi->slave)
803 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux);
804
805 clk_disable_unprepare(dsi->grf_clk);
806 }
807
808 static const struct drm_encoder_helper_funcs
809 dw_mipi_dsi_encoder_helper_funcs = {
810 .atomic_check = dw_mipi_dsi_encoder_atomic_check,
811 .enable = dw_mipi_dsi_encoder_enable,
812 };
813
rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip * dsi,struct drm_device * drm_dev)814 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
815 struct drm_device *drm_dev)
816 {
817 struct drm_encoder *encoder = &dsi->encoder.encoder;
818 int ret;
819
820 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
821 dsi->dev->of_node);
822
823 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI);
824 if (ret) {
825 DRM_ERROR("Failed to initialize encoder with drm\n");
826 return ret;
827 }
828
829 drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs);
830
831 return 0;
832 }
833
834 static struct device
dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip * dsi)835 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi)
836 {
837 const struct of_device_id *match;
838 struct device_node *node = NULL, *local;
839
840 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev);
841
842 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0);
843 if (!local)
844 return NULL;
845
846 while ((node = of_find_compatible_node(node, NULL,
847 match->compatible))) {
848 struct device_node *remote;
849
850 /* found ourself */
851 if (node == dsi->dev->of_node)
852 continue;
853
854 remote = of_graph_get_remote_node(node, 1, 0);
855 if (!remote)
856 continue;
857
858 /* same display device in port1-ep0 for both */
859 if (remote == local) {
860 struct dw_mipi_dsi_rockchip *dsi2;
861 struct platform_device *pdev;
862
863 pdev = of_find_device_by_node(node);
864
865 /*
866 * we have found the second, so will either return it
867 * or return with an error. In any case won't need the
868 * nodes anymore nor continue the loop.
869 */
870 of_node_put(remote);
871 of_node_put(node);
872 of_node_put(local);
873
874 if (!pdev)
875 return ERR_PTR(-EPROBE_DEFER);
876
877 dsi2 = platform_get_drvdata(pdev);
878 if (!dsi2) {
879 platform_device_put(pdev);
880 return ERR_PTR(-EPROBE_DEFER);
881 }
882
883 return &pdev->dev;
884 }
885
886 of_node_put(remote);
887 }
888
889 of_node_put(local);
890
891 return NULL;
892 }
893
dw_mipi_dsi_rockchip_bind(struct device * dev,struct device * master,void * data)894 static int dw_mipi_dsi_rockchip_bind(struct device *dev,
895 struct device *master,
896 void *data)
897 {
898 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
899 struct drm_device *drm_dev = data;
900 struct device *second;
901 bool master1, master2;
902 int ret;
903
904 second = dw_mipi_dsi_rockchip_find_second(dsi);
905 if (IS_ERR(second))
906 return PTR_ERR(second);
907
908 if (second) {
909 master1 = of_property_read_bool(dsi->dev->of_node,
910 "clock-master");
911 master2 = of_property_read_bool(second->of_node,
912 "clock-master");
913
914 if (master1 && master2) {
915 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n");
916 return -EINVAL;
917 }
918
919 if (!master1 && !master2) {
920 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n");
921 return -EINVAL;
922 }
923
924 /* we are the slave in dual-DSI */
925 if (!master1) {
926 dsi->is_slave = true;
927 return 0;
928 }
929
930 dsi->slave = dev_get_drvdata(second);
931 if (!dsi->slave) {
932 DRM_DEV_ERROR(dev, "could not get slaves data\n");
933 return -ENODEV;
934 }
935
936 dsi->slave->is_slave = true;
937 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd);
938 put_device(second);
939 }
940
941 pm_runtime_get_sync(dsi->dev);
942 if (dsi->slave)
943 pm_runtime_get_sync(dsi->slave->dev);
944
945 ret = clk_prepare_enable(dsi->pllref_clk);
946 if (ret) {
947 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
948 goto out_pm_runtime;
949 }
950
951 /*
952 * With the GRF clock running, write lane and dual-mode configurations
953 * that won't change immediately. If we waited until enable() to do
954 * this, things like panel preparation would not be able to send
955 * commands over DSI.
956 */
957 ret = clk_prepare_enable(dsi->grf_clk);
958 if (ret) {
959 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
960 goto out_pll_clk;
961 }
962
963 dw_mipi_dsi_rockchip_config(dsi);
964 if (dsi->slave)
965 dw_mipi_dsi_rockchip_config(dsi->slave);
966
967 clk_disable_unprepare(dsi->grf_clk);
968
969 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);
970 if (ret) {
971 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");
972 goto out_pll_clk;
973 }
974 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder,
975 dev->of_node, 0, 0);
976
977 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder);
978 if (ret) {
979 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
980 goto out_pll_clk;
981 }
982
983 dsi->dsi_bound = true;
984
985 return 0;
986
987 out_pll_clk:
988 clk_disable_unprepare(dsi->pllref_clk);
989 out_pm_runtime:
990 pm_runtime_put(dsi->dev);
991 if (dsi->slave)
992 pm_runtime_put(dsi->slave->dev);
993
994 return ret;
995 }
996
dw_mipi_dsi_rockchip_unbind(struct device * dev,struct device * master,void * data)997 static void dw_mipi_dsi_rockchip_unbind(struct device *dev,
998 struct device *master,
999 void *data)
1000 {
1001 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
1002
1003 if (dsi->is_slave)
1004 return;
1005
1006 dsi->dsi_bound = false;
1007
1008 dw_mipi_dsi_unbind(dsi->dmd);
1009
1010 clk_disable_unprepare(dsi->pllref_clk);
1011
1012 pm_runtime_put(dsi->dev);
1013 if (dsi->slave)
1014 pm_runtime_put(dsi->slave->dev);
1015 }
1016
1017 static const struct component_ops dw_mipi_dsi_rockchip_ops = {
1018 .bind = dw_mipi_dsi_rockchip_bind,
1019 .unbind = dw_mipi_dsi_rockchip_unbind,
1020 };
1021
dw_mipi_dsi_rockchip_host_attach(void * priv_data,struct mipi_dsi_device * device)1022 static int dw_mipi_dsi_rockchip_host_attach(void *priv_data,
1023 struct mipi_dsi_device *device)
1024 {
1025 struct dw_mipi_dsi_rockchip *dsi = priv_data;
1026 struct device *second;
1027 int ret;
1028
1029 mutex_lock(&dsi->usage_mutex);
1030
1031 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) {
1032 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n");
1033 mutex_unlock(&dsi->usage_mutex);
1034 return -EBUSY;
1035 }
1036
1037 dsi->usage_mode = DW_DSI_USAGE_DSI;
1038 mutex_unlock(&dsi->usage_mutex);
1039
1040 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops);
1041 if (ret) {
1042 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",
1043 ret);
1044 goto out;
1045 }
1046
1047 second = dw_mipi_dsi_rockchip_find_second(dsi);
1048 if (IS_ERR(second)) {
1049 ret = PTR_ERR(second);
1050 goto out;
1051 }
1052 if (second) {
1053 ret = component_add(second, &dw_mipi_dsi_rockchip_ops);
1054 if (ret) {
1055 DRM_DEV_ERROR(second,
1056 "Failed to register component: %d\n",
1057 ret);
1058 goto out;
1059 }
1060 }
1061
1062 return 0;
1063
1064 out:
1065 mutex_lock(&dsi->usage_mutex);
1066 dsi->usage_mode = DW_DSI_USAGE_IDLE;
1067 mutex_unlock(&dsi->usage_mutex);
1068 return ret;
1069 }
1070
dw_mipi_dsi_rockchip_host_detach(void * priv_data,struct mipi_dsi_device * device)1071 static int dw_mipi_dsi_rockchip_host_detach(void *priv_data,
1072 struct mipi_dsi_device *device)
1073 {
1074 struct dw_mipi_dsi_rockchip *dsi = priv_data;
1075 struct device *second;
1076
1077 second = dw_mipi_dsi_rockchip_find_second(dsi);
1078 if (second && !IS_ERR(second))
1079 component_del(second, &dw_mipi_dsi_rockchip_ops);
1080
1081 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
1082
1083 mutex_lock(&dsi->usage_mutex);
1084 dsi->usage_mode = DW_DSI_USAGE_IDLE;
1085 mutex_unlock(&dsi->usage_mutex);
1086
1087 return 0;
1088 }
1089
1090 static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = {
1091 .attach = dw_mipi_dsi_rockchip_host_attach,
1092 .detach = dw_mipi_dsi_rockchip_host_detach,
1093 };
1094
dw_mipi_dsi_rockchip_dphy_bind(struct device * dev,struct device * master,void * data)1095 static int dw_mipi_dsi_rockchip_dphy_bind(struct device *dev,
1096 struct device *master,
1097 void *data)
1098 {
1099 /*
1100 * Nothing to do when used as a dphy.
1101 * Just make the rest of Rockchip-DRM happy
1102 * by being here.
1103 */
1104
1105 return 0;
1106 }
1107
dw_mipi_dsi_rockchip_dphy_unbind(struct device * dev,struct device * master,void * data)1108 static void dw_mipi_dsi_rockchip_dphy_unbind(struct device *dev,
1109 struct device *master,
1110 void *data)
1111 {
1112 /* Nothing to do when used as a dphy. */
1113 }
1114
1115 static const struct component_ops dw_mipi_dsi_rockchip_dphy_ops = {
1116 .bind = dw_mipi_dsi_rockchip_dphy_bind,
1117 .unbind = dw_mipi_dsi_rockchip_dphy_unbind,
1118 };
1119
dw_mipi_dsi_dphy_init(struct phy * phy)1120 static int dw_mipi_dsi_dphy_init(struct phy *phy)
1121 {
1122 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1123 int ret;
1124
1125 mutex_lock(&dsi->usage_mutex);
1126
1127 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) {
1128 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n");
1129 mutex_unlock(&dsi->usage_mutex);
1130 return -EBUSY;
1131 }
1132
1133 dsi->usage_mode = DW_DSI_USAGE_PHY;
1134 mutex_unlock(&dsi->usage_mutex);
1135
1136 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops);
1137 if (ret < 0)
1138 goto err_graph;
1139
1140 if (dsi->cdata->dphy_rx_init) {
1141 ret = clk_prepare_enable(dsi->pclk);
1142 if (ret < 0)
1143 goto err_init;
1144
1145 ret = clk_prepare_enable(dsi->grf_clk);
1146 if (ret) {
1147 clk_disable_unprepare(dsi->pclk);
1148 goto err_init;
1149 }
1150
1151 ret = dsi->cdata->dphy_rx_init(phy);
1152 clk_disable_unprepare(dsi->grf_clk);
1153 clk_disable_unprepare(dsi->pclk);
1154 if (ret < 0)
1155 goto err_init;
1156 }
1157
1158 return 0;
1159
1160 err_init:
1161 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops);
1162 err_graph:
1163 mutex_lock(&dsi->usage_mutex);
1164 dsi->usage_mode = DW_DSI_USAGE_IDLE;
1165 mutex_unlock(&dsi->usage_mutex);
1166
1167 return ret;
1168 }
1169
dw_mipi_dsi_dphy_exit(struct phy * phy)1170 static int dw_mipi_dsi_dphy_exit(struct phy *phy)
1171 {
1172 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1173
1174 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops);
1175
1176 mutex_lock(&dsi->usage_mutex);
1177 dsi->usage_mode = DW_DSI_USAGE_IDLE;
1178 mutex_unlock(&dsi->usage_mutex);
1179
1180 return 0;
1181 }
1182
dw_mipi_dsi_dphy_configure(struct phy * phy,union phy_configure_opts * opts)1183 static int dw_mipi_dsi_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
1184 {
1185 struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy;
1186 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1187 int ret;
1188
1189 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
1190 if (ret)
1191 return ret;
1192
1193 dsi->dphy_config = *config;
1194 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1);
1195
1196 return 0;
1197 }
1198
dw_mipi_dsi_dphy_power_on(struct phy * phy)1199 static int dw_mipi_dsi_dphy_power_on(struct phy *phy)
1200 {
1201 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1202 int i, ret;
1203
1204 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n",
1205 dsi->dphy_config.lanes, dsi->lane_mbps);
1206
1207 i = max_mbps_to_parameter(dsi->lane_mbps);
1208 if (i < 0) {
1209 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n",
1210 dsi->lane_mbps);
1211 return i;
1212 }
1213
1214 ret = pm_runtime_resume_and_get(dsi->dev);
1215 if (ret < 0) {
1216 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret);
1217 return ret;
1218 }
1219
1220 ret = clk_prepare_enable(dsi->pclk);
1221 if (ret) {
1222 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret);
1223 goto err_pclk;
1224 }
1225
1226 ret = clk_prepare_enable(dsi->grf_clk);
1227 if (ret) {
1228 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
1229 goto err_grf_clk;
1230 }
1231
1232 ret = clk_prepare_enable(dsi->phy_cfg_clk);
1233 if (ret) {
1234 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret);
1235 goto err_phy_cfg_clk;
1236 }
1237
1238 /* do soc-variant specific init */
1239 if (dsi->cdata->dphy_rx_power_on) {
1240 ret = dsi->cdata->dphy_rx_power_on(phy);
1241 if (ret < 0) {
1242 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret);
1243 goto err_pwr_on;
1244 }
1245 }
1246
1247 /*
1248 * Configure hsfreqrange according to frequency values
1249 * Set clock lane and hsfreqrange by lane0(test code 0x44)
1250 */
1251 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0);
1252 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
1253 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
1254 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0);
1255 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0);
1256 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0);
1257
1258 /* Normal operation */
1259 dw_mipi_dsi_phy_write(dsi, 0x0, 0);
1260
1261 clk_disable_unprepare(dsi->phy_cfg_clk);
1262 clk_disable_unprepare(dsi->grf_clk);
1263
1264 return ret;
1265
1266 err_pwr_on:
1267 clk_disable_unprepare(dsi->phy_cfg_clk);
1268 err_phy_cfg_clk:
1269 clk_disable_unprepare(dsi->grf_clk);
1270 err_grf_clk:
1271 clk_disable_unprepare(dsi->pclk);
1272 err_pclk:
1273 pm_runtime_put(dsi->dev);
1274 return ret;
1275 }
1276
dw_mipi_dsi_dphy_power_off(struct phy * phy)1277 static int dw_mipi_dsi_dphy_power_off(struct phy *phy)
1278 {
1279 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1280 int ret;
1281
1282 ret = clk_prepare_enable(dsi->grf_clk);
1283 if (ret) {
1284 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
1285 return ret;
1286 }
1287
1288 if (dsi->cdata->dphy_rx_power_off) {
1289 ret = dsi->cdata->dphy_rx_power_off(phy);
1290 if (ret < 0)
1291 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret);
1292 }
1293
1294 clk_disable_unprepare(dsi->grf_clk);
1295 clk_disable_unprepare(dsi->pclk);
1296
1297 pm_runtime_put(dsi->dev);
1298
1299 return ret;
1300 }
1301
1302 static const struct phy_ops dw_mipi_dsi_dphy_ops = {
1303 .configure = dw_mipi_dsi_dphy_configure,
1304 .power_on = dw_mipi_dsi_dphy_power_on,
1305 .power_off = dw_mipi_dsi_dphy_power_off,
1306 .init = dw_mipi_dsi_dphy_init,
1307 .exit = dw_mipi_dsi_dphy_exit,
1308 };
1309
dw_mipi_dsi_rockchip_resume(struct device * dev)1310 static int __maybe_unused dw_mipi_dsi_rockchip_resume(struct device *dev)
1311 {
1312 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
1313 int ret;
1314
1315 /*
1316 * Re-configure DSI state, if we were previously initialized. We need
1317 * to do this before rockchip_drm_drv tries to re-enable() any panels.
1318 */
1319 if (dsi->dsi_bound) {
1320 ret = clk_prepare_enable(dsi->grf_clk);
1321 if (ret) {
1322 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
1323 return ret;
1324 }
1325
1326 dw_mipi_dsi_rockchip_config(dsi);
1327 if (dsi->slave)
1328 dw_mipi_dsi_rockchip_config(dsi->slave);
1329
1330 clk_disable_unprepare(dsi->grf_clk);
1331 }
1332
1333 return 0;
1334 }
1335
1336 static const struct dev_pm_ops dw_mipi_dsi_rockchip_pm_ops = {
1337 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, dw_mipi_dsi_rockchip_resume)
1338 };
1339
dw_mipi_dsi_rockchip_probe(struct platform_device * pdev)1340 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
1341 {
1342 struct device *dev = &pdev->dev;
1343 struct device_node *np = dev->of_node;
1344 struct dw_mipi_dsi_rockchip *dsi;
1345 struct phy_provider *phy_provider;
1346 struct resource *res;
1347 const struct rockchip_dw_dsi_chip_data *cdata =
1348 of_device_get_match_data(dev);
1349 int ret, i;
1350
1351 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1352 if (!dsi)
1353 return -ENOMEM;
1354
1355 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1356 dsi->base = devm_ioremap_resource(dev, res);
1357 if (IS_ERR(dsi->base)) {
1358 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");
1359 return PTR_ERR(dsi->base);
1360 }
1361
1362 i = 0;
1363 while (cdata[i].reg) {
1364 if (cdata[i].reg == res->start) {
1365 dsi->cdata = &cdata[i];
1366 break;
1367 }
1368
1369 i++;
1370 }
1371
1372 if (!dsi->cdata) {
1373 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name);
1374 return -EINVAL;
1375 }
1376
1377 /* try to get a possible external dphy */
1378 dsi->phy = devm_phy_optional_get(dev, "dphy");
1379 if (IS_ERR(dsi->phy)) {
1380 ret = PTR_ERR(dsi->phy);
1381 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
1382 return ret;
1383 }
1384
1385 dsi->pclk = devm_clk_get(dev, "pclk");
1386 if (IS_ERR(dsi->pclk)) {
1387 ret = PTR_ERR(dsi->pclk);
1388 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret);
1389 return ret;
1390 }
1391
1392 dsi->pllref_clk = devm_clk_get(dev, "ref");
1393 if (IS_ERR(dsi->pllref_clk)) {
1394 if (dsi->phy) {
1395 /*
1396 * if external phy is present, pll will be
1397 * generated there.
1398 */
1399 dsi->pllref_clk = NULL;
1400 } else {
1401 ret = PTR_ERR(dsi->pllref_clk);
1402 DRM_DEV_ERROR(dev,
1403 "Unable to get pll reference clock: %d\n",
1404 ret);
1405 return ret;
1406 }
1407 }
1408
1409 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
1410 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1411 if (IS_ERR(dsi->phy_cfg_clk)) {
1412 ret = PTR_ERR(dsi->phy_cfg_clk);
1413 DRM_DEV_ERROR(dev,
1414 "Unable to get phy_cfg_clk: %d\n", ret);
1415 return ret;
1416 }
1417 }
1418
1419 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
1420 dsi->grf_clk = devm_clk_get(dev, "grf");
1421 if (IS_ERR(dsi->grf_clk)) {
1422 ret = PTR_ERR(dsi->grf_clk);
1423 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
1424 return ret;
1425 }
1426 }
1427
1428 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1429 if (IS_ERR(dsi->grf_regmap)) {
1430 DRM_DEV_ERROR(dev, "Unable to get rockchip,grf\n");
1431 return PTR_ERR(dsi->grf_regmap);
1432 }
1433
1434 dsi->dev = dev;
1435 dsi->pdata.base = dsi->base;
1436 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
1437 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
1438 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;
1439 dsi->pdata.priv_data = dsi;
1440 platform_set_drvdata(pdev, dsi);
1441
1442 mutex_init(&dsi->usage_mutex);
1443
1444 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops);
1445 if (IS_ERR(dsi->dphy)) {
1446 DRM_DEV_ERROR(&pdev->dev, "failed to create PHY\n");
1447 return PTR_ERR(dsi->dphy);
1448 }
1449
1450 phy_set_drvdata(dsi->dphy, dsi);
1451 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1452 if (IS_ERR(phy_provider))
1453 return PTR_ERR(phy_provider);
1454
1455 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata);
1456 if (IS_ERR(dsi->dmd)) {
1457 ret = PTR_ERR(dsi->dmd);
1458 if (ret != -EPROBE_DEFER)
1459 DRM_DEV_ERROR(dev,
1460 "Failed to probe dw_mipi_dsi: %d\n", ret);
1461 return ret;
1462 }
1463
1464 return 0;
1465 }
1466
dw_mipi_dsi_rockchip_remove(struct platform_device * pdev)1467 static void dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
1468 {
1469 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);
1470
1471 dw_mipi_dsi_remove(dsi->dmd);
1472 }
1473
1474 static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
1475 {
1476 .reg = 0xff450000,
1477 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,
1478 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1479 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
1480 PX30_DSI_LCDC_SEL),
1481
1482 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,
1483 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1484 PX30_DSI_FORCERXMODE |
1485 PX30_DSI_FORCETXSTOPMODE),
1486
1487 .max_data_lanes = 4,
1488 },
1489 { /* sentinel */ }
1490 };
1491
1492 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
1493 {
1494 .reg = 0xff960000,
1495 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1496 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1497 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1498
1499 .max_data_lanes = 4,
1500 },
1501 {
1502 .reg = 0xff964000,
1503 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
1504 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1505 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1506
1507 .max_data_lanes = 4,
1508 },
1509 { /* sentinel */ }
1510 };
1511
rk3399_dphy_tx1rx1_init(struct phy * phy)1512 static int rk3399_dphy_tx1rx1_init(struct phy *phy)
1513 {
1514 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1515
1516 /*
1517 * Set TX1RX1 source to isp1.
1518 * Assume ISP0 is supplied by the RX0 dphy.
1519 */
1520 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1521 HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0));
1522 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1523 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));
1524 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1525 HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR));
1526 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1527 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));
1528
1529 return 0;
1530 }
1531
rk3399_dphy_tx1rx1_power_on(struct phy * phy)1532 static int rk3399_dphy_tx1rx1_power_on(struct phy *phy)
1533 {
1534 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1535
1536 /* tester reset pulse */
1537 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR);
1538 usleep_range(100, 150);
1539
1540 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1541 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));
1542 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1543 HIWORD_UPDATE(RK3399_TXRX_BASEDIR, RK3399_TXRX_BASEDIR));
1544
1545 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1546 HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE));
1547 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1548 HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE));
1549
1550 /* Disable lane turn around, which is ignored in receive mode */
1551 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1552 HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST));
1553 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1554 HIWORD_UPDATE(RK3399_DSI1_TURNDISABLE,
1555 RK3399_DSI1_TURNDISABLE));
1556 usleep_range(100, 150);
1557
1558 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
1559 usleep_range(100, 150);
1560
1561 /* Enable dphy lanes */
1562 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1563 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0),
1564 RK3399_DSI1_ENABLE));
1565
1566 usleep_range(100, 150);
1567
1568 return 0;
1569 }
1570
rk3399_dphy_tx1rx1_power_off(struct phy * phy)1571 static int rk3399_dphy_tx1rx1_power_off(struct phy *phy)
1572 {
1573 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1574
1575 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1576 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));
1577
1578 return 0;
1579 }
1580
1581 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
1582 {
1583 .reg = 0xff960000,
1584 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1585 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1586 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
1587 RK3399_DSI0_LCDC_SEL),
1588
1589 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
1590 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
1591 RK3399_DSI0_TURNDISABLE |
1592 RK3399_DSI0_FORCETXSTOPMODE |
1593 RK3399_DSI0_FORCERXMODE),
1594
1595 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1596 .max_data_lanes = 4,
1597 },
1598 {
1599 .reg = 0xff968000,
1600 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
1601 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
1602 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
1603 RK3399_DSI1_LCDC_SEL),
1604
1605 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
1606 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
1607 RK3399_DSI1_FORCETXSTOPMODE |
1608 RK3399_DSI1_FORCERXMODE |
1609 RK3399_DSI1_ENABLE),
1610
1611 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,
1612 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
1613 RK3399_TXRX_ENABLECLK,
1614 RK3399_TXRX_MASTERSLAVEZ |
1615 RK3399_TXRX_ENABLECLK |
1616 RK3399_TXRX_BASEDIR),
1617
1618 .enable_grf_reg = RK3399_GRF_SOC_CON23,
1619 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
1620
1621 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
1622 .max_data_lanes = 4,
1623
1624 .dphy_rx_init = rk3399_dphy_tx1rx1_init,
1625 .dphy_rx_power_on = rk3399_dphy_tx1rx1_power_on,
1626 .dphy_rx_power_off = rk3399_dphy_tx1rx1_power_off,
1627 },
1628 { /* sentinel */ }
1629 };
1630
1631 static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = {
1632 {
1633 .reg = 0xfe060000,
1634 .lanecfg1_grf_reg = RK3568_GRF_VO_CON2,
1635 .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS |
1636 RK3568_DSI0_FORCETXSTOPMODE |
1637 RK3568_DSI0_TURNDISABLE |
1638 RK3568_DSI0_FORCERXMODE),
1639 .max_data_lanes = 4,
1640 },
1641 {
1642 .reg = 0xfe070000,
1643 .lanecfg1_grf_reg = RK3568_GRF_VO_CON3,
1644 .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS |
1645 RK3568_DSI1_FORCETXSTOPMODE |
1646 RK3568_DSI1_TURNDISABLE |
1647 RK3568_DSI1_FORCERXMODE),
1648 .max_data_lanes = 4,
1649 },
1650 { /* sentinel */ }
1651 };
1652
1653 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
1654 {
1655 .compatible = "rockchip,px30-mipi-dsi",
1656 .data = &px30_chip_data,
1657 }, {
1658 .compatible = "rockchip,rk3288-mipi-dsi",
1659 .data = &rk3288_chip_data,
1660 }, {
1661 .compatible = "rockchip,rk3399-mipi-dsi",
1662 .data = &rk3399_chip_data,
1663 }, {
1664 .compatible = "rockchip,rk3568-mipi-dsi",
1665 .data = &rk3568_chip_data,
1666 },
1667 { /* sentinel */ }
1668 };
1669 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids);
1670
1671 struct platform_driver dw_mipi_dsi_rockchip_driver = {
1672 .probe = dw_mipi_dsi_rockchip_probe,
1673 .remove_new = dw_mipi_dsi_rockchip_remove,
1674 .driver = {
1675 .of_match_table = dw_mipi_dsi_rockchip_dt_ids,
1676 .pm = &dw_mipi_dsi_rockchip_pm_ops,
1677 .name = "dw-mipi-dsi-rockchip",
1678 /*
1679 * For dual-DSI display, one DSI pokes at the other DSI's
1680 * drvdata in dw_mipi_dsi_rockchip_find_second(). This is not
1681 * safe for asynchronous probe.
1682 */
1683 .probe_type = PROBE_FORCE_SYNCHRONOUS,
1684 },
1685 };
1686