1 /*
2  * Copyright 2013 Advanced Micro Devices, Inc.
3  * Copyright 2014 Rafał Miłecki
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  */
23 #include <linux/hdmi.h>
24 
25 #include "radeon.h"
26 #include "radeon_asic.h"
27 #include "radeon_audio.h"
28 #include "r600d.h"
29 
dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder * encoder,u8 * sadb,int sad_count)30 void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
31 	u8 *sadb, int sad_count)
32 {
33 	struct radeon_device *rdev = encoder->dev->dev_private;
34 	u32 tmp;
35 
36 	/* program the speaker allocation */
37 	tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
38 	tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
39 	/* set HDMI mode */
40 	tmp |= HDMI_CONNECTION;
41 	if (sad_count)
42 		tmp |= SPEAKER_ALLOCATION(sadb[0]);
43 	else
44 		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
45 	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
46 }
47 
dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder * encoder,u8 * sadb,int sad_count)48 void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
49 	u8 *sadb, int sad_count)
50 {
51 	struct radeon_device *rdev = encoder->dev->dev_private;
52 	u32 tmp;
53 
54 	/* program the speaker allocation */
55 	tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
56 	tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
57 	/* set DP mode */
58 	tmp |= DP_CONNECTION;
59 	if (sad_count)
60 		tmp |= SPEAKER_ALLOCATION(sadb[0]);
61 	else
62 		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
63 	WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
64 }
65 
dce3_2_afmt_write_sad_regs(struct drm_encoder * encoder,struct cea_sad * sads,int sad_count)66 void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder,
67 	struct cea_sad *sads, int sad_count)
68 {
69 	int i;
70 	struct radeon_device *rdev = encoder->dev->dev_private;
71 	static const u16 eld_reg_to_type[][2] = {
72 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
73 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
74 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
75 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
76 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
77 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
78 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
79 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
80 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
81 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
82 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
83 		{ AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
84 	};
85 
86 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
87 		u32 value = 0;
88 		u8 stereo_freqs = 0;
89 		int max_channels = -1;
90 		int j;
91 
92 		for (j = 0; j < sad_count; j++) {
93 			struct cea_sad *sad = &sads[j];
94 
95 			if (sad->format == eld_reg_to_type[i][1]) {
96 				if (sad->channels > max_channels) {
97 					value = MAX_CHANNELS(sad->channels) |
98 						DESCRIPTOR_BYTE_2(sad->byte2) |
99 						SUPPORTED_FREQUENCIES(sad->freq);
100 					max_channels = sad->channels;
101 				}
102 
103 				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
104 					stereo_freqs |= sad->freq;
105 				else
106 					break;
107 			}
108 		}
109 
110 		value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
111 
112 		WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
113 	}
114 }
115 
dce3_2_audio_set_dto(struct radeon_device * rdev,struct radeon_crtc * crtc,unsigned int clock)116 void dce3_2_audio_set_dto(struct radeon_device *rdev,
117 	struct radeon_crtc *crtc, unsigned int clock)
118 {
119 	struct radeon_encoder *radeon_encoder;
120 	struct radeon_encoder_atom_dig *dig;
121 	unsigned int max_ratio = clock / 24000;
122 	u32 dto_phase;
123 	u32 wallclock_ratio;
124 	u32 dto_cntl;
125 
126 	if (!crtc)
127 		return;
128 
129 	radeon_encoder = to_radeon_encoder(crtc->encoder);
130 	dig = radeon_encoder->enc_priv;
131 
132 	if (!dig)
133 		return;
134 
135 	if (max_ratio >= 8) {
136 		dto_phase = 192 * 1000;
137 		wallclock_ratio = 3;
138 	} else if (max_ratio >= 4) {
139 		dto_phase = 96 * 1000;
140 		wallclock_ratio = 2;
141 	} else if (max_ratio >= 2) {
142 		dto_phase = 48 * 1000;
143 		wallclock_ratio = 1;
144 	} else {
145 		dto_phase = 24 * 1000;
146 		wallclock_ratio = 0;
147 	}
148 
149 	/* Express [24MHz / target pixel clock] as an exact rational
150 	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
151 	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
152 	 */
153 	if (dig->dig_encoder == 0) {
154 		dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
155 		dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
156 		WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
157 		WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
158 		WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
159 		WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
160 	} else {
161 		dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
162 		dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
163 		WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
164 		WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
165 		WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
166 		WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
167 	}
168 }
169 
dce3_2_hdmi_update_acr(struct drm_encoder * encoder,long offset,const struct radeon_hdmi_acr * acr)170 void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset,
171 	const struct radeon_hdmi_acr *acr)
172 {
173 	struct drm_device *dev = encoder->dev;
174 	struct radeon_device *rdev = dev->dev_private;
175 
176 	WREG32(DCE3_HDMI0_ACR_PACKET_CONTROL + offset,
177 		HDMI0_ACR_SOURCE |		/* select SW CTS value */
178 		HDMI0_ACR_AUTO_SEND);	/* allow hw to sent ACR packets when required */
179 
180 	WREG32_P(HDMI0_ACR_32_0 + offset,
181 		HDMI0_ACR_CTS_32(acr->cts_32khz),
182 		~HDMI0_ACR_CTS_32_MASK);
183 	WREG32_P(HDMI0_ACR_32_1 + offset,
184 		HDMI0_ACR_N_32(acr->n_32khz),
185 		~HDMI0_ACR_N_32_MASK);
186 
187 	WREG32_P(HDMI0_ACR_44_0 + offset,
188 		HDMI0_ACR_CTS_44(acr->cts_44_1khz),
189 		~HDMI0_ACR_CTS_44_MASK);
190 	WREG32_P(HDMI0_ACR_44_1 + offset,
191 		HDMI0_ACR_N_44(acr->n_44_1khz),
192 		~HDMI0_ACR_N_44_MASK);
193 
194 	WREG32_P(HDMI0_ACR_48_0 + offset,
195 		HDMI0_ACR_CTS_48(acr->cts_48khz),
196 		~HDMI0_ACR_CTS_48_MASK);
197 	WREG32_P(HDMI0_ACR_48_1 + offset,
198 		HDMI0_ACR_N_48(acr->n_48khz),
199 		~HDMI0_ACR_N_48_MASK);
200 }
201 
dce3_2_set_audio_packet(struct drm_encoder * encoder,u32 offset)202 void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset)
203 {
204 	struct drm_device *dev = encoder->dev;
205 	struct radeon_device *rdev = dev->dev_private;
206 
207 	WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
208 		HDMI0_AUDIO_DELAY_EN(1) |			/* default audio delay */
209 		HDMI0_AUDIO_PACKETS_PER_LINE(3));	/* should be suffient for all audio modes and small enough for all hblanks */
210 
211 	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
212 		AFMT_AUDIO_SAMPLE_SEND |			/* send audio packets */
213 		AFMT_60958_CS_UPDATE);				/* allow 60958 channel status fields to be updated */
214 
215 	WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
216 		HDMI0_AUDIO_INFO_SEND |				/* enable audio info frames (frames won't be set until audio is enabled) */
217 		HDMI0_AUDIO_INFO_CONT);				/* send audio info frames every frame/field */
218 
219 	WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
220 		HDMI0_AUDIO_INFO_LINE(2));			/* anything other than 0 */
221 }
222 
dce3_2_set_mute(struct drm_encoder * encoder,u32 offset,bool mute)223 void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
224 {
225 	struct drm_device *dev = encoder->dev;
226 	struct radeon_device *rdev = dev->dev_private;
227 
228 	if (mute)
229 		WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE);
230 	else
231 		WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE);
232 }
233