xref: /openbmc/u-boot/board/Synology/ds414/ds414.c (revision e8f80a5a)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *
4  * Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
5  */
6 
7 #include <common.h>
8 #include <miiphy.h>
9 #include <asm/io.h>
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/soc.h>
12 #include <linux/mbus.h>
13 
14 #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
15 #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
16 #include "../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h"
17 
18 DECLARE_GLOBAL_DATA_PTR;
19 
20 /* GPP and MPP settings as found in mvBoardEnvSpec.c of Synology's U-Boot */
21 
22 #define DS414_GPP_OUT_VAL_LOW		(BIT(25) | BIT(30))
23 #define DS414_GPP_OUT_VAL_MID		(BIT(10) | BIT(15))
24 #define DS414_GPP_OUT_VAL_HIGH		(0)
25 
26 #define DS414_GPP_OUT_POL_LOW		(0)
27 #define DS414_GPP_OUT_POL_MID		(0)
28 #define DS414_GPP_OUT_POL_HIGH		(0)
29 
30 #define DS414_GPP_OUT_ENA_LOW		(~(BIT(25) | BIT(30)))
31 #define DS414_GPP_OUT_ENA_MID		(~(BIT(10) | BIT(12) | \
32 					   BIT(13) | BIT(14) | BIT(15)))
33 #define DS414_GPP_OUT_ENA_HIGH		(~0)
34 
35 static const u32 ds414_mpp_control[] = {
36 	0x11111111,
37 	0x22221111,
38 	0x22222222,
39 	0x00000000,
40 	0x11110000,
41 	0x00004000,
42 	0x00000000,
43 	0x00000000,
44 	0x00000000
45 };
46 
47 /* DDR3 static MC configuration */
48 
49 /* 1G_v1 (4x2Gbits) adapted by DS414 */
50 MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = {
51 	{0x00001400, 0x73014A28},	/*DDR SDRAM Configuration Register */
52 	{0x00001404, 0x30000800},	/*Dunit Control Low Register */
53 	{0x00001408, 0x44148887},	/*DDR SDRAM Timing (Low) Register */
54 	{0x0000140C, 0x3AD83FEA},	/*DDR SDRAM Timing (High) Register */
55 
56 	{0x00001410, 0x14000000},	/*DDR SDRAM Address Control Register */
57 
58 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
59 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
60 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
61 	{0x00001424, 0x0000F3FF},	/*Dunit Control High Register */
62 	{0x00001428, 0x000F8830},	/*Dunit Control High Register */
63 	{0x0000142C, 0x054C36F4},	/*Dunit Control High Register */
64 	{0x0000147C, 0x0000C671},
65 
66 	{0x000014a0, 0x00000001},
67 	{0x000014a8, 0x00000100},	/*2:1 */
68 	{0x00020220, 0x00000006},
69 
70 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
71 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
72 	{0x0000149C, 0x00000001},	/*DDR Dunit ODT Control Register */
73 
74 	{0x000014C0, 0x192424C9},	/* DRAM address and Control Driving Strenght  */
75 	{0x000014C4, 0x0AAA24C9},	/* DRAM Data and DQS Driving Strenght  */
76 
77 	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence*/
78 	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
79 
80 	{0x0001504, 0x3FFFFFE1},	/* CS0 Size */
81 	{0x000150C, 0x00000000},	/* CS1 Size */
82 	{0x0001514, 0x00000000},	/* CS2 Size */
83 	{0x000151C, 0x00000000},	/* CS3 Size */
84 
85 	{0x00001538, 0x00000009},	/*Read Data Sample Delays Register */
86 	{0x0000153C, 0x00000009},	/*Read Data Ready Delay Register */
87 
88 	{0x000015D0, 0x00000650},	/*MR0 */
89 	{0x000015D4, 0x00000044},	/*MR1 */
90 	{0x000015D8, 0x00000010},	/*MR2 */
91 	{0x000015DC, 0x00000000},	/*MR3 */
92 
93 	{0x000015E4, 0x00203c18},	/*ZQC Configuration Register */
94 	{0x000015EC, 0xF800A225},	/*DDR PHY */
95 
96 	{0x0, 0x0}
97 };
98 
99 MV_DRAM_MODES ds414_ddr_modes[MV_DDR3_MODES_NUMBER] = {
100 	{"ds414_1333-667",   0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1,  NULL},
101 };
102 
103 extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
104 
105 MV_BIN_SERDES_CFG ds414_serdes_cfg[] = {
106 	{ MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000,
107 	  { PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
108 	    PEX_BUS_DISABLED },
109 	  0x0040, serdes_change_m_phy
110 	}
111 };
112 
ddr3_get_static_ddr_mode(void)113 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
114 {
115 	return &ds414_ddr_modes[0];
116 }
117 
board_serdes_cfg_get(u8 pex_mode)118 MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
119 {
120 	return &ds414_serdes_cfg[0];
121 }
122 
board_sat_r_get(u8 dev_num,u8 reg)123 u8 board_sat_r_get(u8 dev_num, u8 reg)
124 {
125 	return (0x1 << 1 | 1);
126 }
127 
board_early_init_f(void)128 int board_early_init_f(void)
129 {
130 	int i;
131 
132 	/* Set GPP Out value */
133 	reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW);
134 	reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID);
135 	reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH);
136 
137 	/* set GPP polarity */
138 	reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW);
139 	reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID);
140 	reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH);
141 
142 	/* Set GPP Out Enable */
143 	reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW);
144 	reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID);
145 	reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH);
146 
147 	for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++)
148 		reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]);
149 
150 	return 0;
151 }
152 
board_init(void)153 int board_init(void)
154 {
155 	u32 pwr_mng_ctrl_reg;
156 
157 	/* Adress of boot parameters */
158 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
159 
160 	/* Gate unused clocks
161 	 *
162 	 * Note: Disabling unused PCIe lanes will hang PCI bus scan.
163 	 *       Once this is resolved, bits 10-12, 26 and 27 can be
164 	 *       unset here as well.
165 	 */
166 	pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG);
167 	pwr_mng_ctrl_reg &= ~(BIT(0));				/* Audio */
168 	pwr_mng_ctrl_reg &= ~(BIT(1) | BIT(2));			/* GE3, GE2 */
169 	pwr_mng_ctrl_reg &= ~(BIT(14) | BIT(15));		/* SATA0 link and core */
170 	pwr_mng_ctrl_reg &= ~(BIT(16));				/* LCD */
171 	pwr_mng_ctrl_reg &= ~(BIT(17));				/* SDIO */
172 	pwr_mng_ctrl_reg &= ~(BIT(19) | BIT(20));		/* USB1 and USB2 */
173 	pwr_mng_ctrl_reg &= ~(BIT(29) | BIT(30));		/* SATA1 link and core */
174 	reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg);
175 
176 	return 0;
177 }
178 
checkboard(void)179 int checkboard(void)
180 {
181 	puts("Board: DS414\n");
182 
183 	return 0;
184 }
185