1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_3_0_MSM8998_H 8 #define _DPU_3_0_MSM8998_H 9 10 static const struct dpu_caps msm8998_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0x7, 13 .qseed_type = DPU_SSPP_SCALER_QSEED3, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .has_3d_merge = true, 18 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 .max_hdeci_exp = MAX_HORZ_DECIMATION, 21 .max_vdeci_exp = MAX_VERT_DECIMATION, 22 }; 23 24 static const struct dpu_mdp_cfg msm8998_mdp = { 25 .name = "top_0", 26 .base = 0x0, .len = 0x458, 27 .features = BIT(DPU_MDP_VSYNC_SEL), 28 .clk_ctrls = { 29 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 31 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 32 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 33 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 34 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 35 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 36 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 }, 37 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 }, 38 [DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 }, 39 }, 40 }; 41 42 static const struct dpu_ctl_cfg msm8998_ctl[] = { 43 { 44 .name = "ctl_0", .id = CTL_0, 45 .base = 0x1000, .len = 0x94, 46 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 47 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 48 }, { 49 .name = "ctl_1", .id = CTL_1, 50 .base = 0x1200, .len = 0x94, 51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 52 }, { 53 .name = "ctl_2", .id = CTL_2, 54 .base = 0x1400, .len = 0x94, 55 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 57 }, { 58 .name = "ctl_3", .id = CTL_3, 59 .base = 0x1600, .len = 0x94, 60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 61 }, { 62 .name = "ctl_4", .id = CTL_4, 63 .base = 0x1800, .len = 0x94, 64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 65 }, 66 }; 67 68 static const struct dpu_sspp_cfg msm8998_sspp[] = { 69 { 70 .name = "sspp_0", .id = SSPP_VIG0, 71 .base = 0x4000, .len = 0x1ac, 72 .features = VIG_MSM8998_MASK, 73 .sblk = &msm8998_vig_sblk_0, 74 .xin_id = 0, 75 .type = SSPP_TYPE_VIG, 76 .clk_ctrl = DPU_CLK_CTRL_VIG0, 77 }, { 78 .name = "sspp_1", .id = SSPP_VIG1, 79 .base = 0x6000, .len = 0x1ac, 80 .features = VIG_MSM8998_MASK, 81 .sblk = &msm8998_vig_sblk_1, 82 .xin_id = 4, 83 .type = SSPP_TYPE_VIG, 84 .clk_ctrl = DPU_CLK_CTRL_VIG1, 85 }, { 86 .name = "sspp_2", .id = SSPP_VIG2, 87 .base = 0x8000, .len = 0x1ac, 88 .features = VIG_MSM8998_MASK, 89 .sblk = &msm8998_vig_sblk_2, 90 .xin_id = 8, 91 .type = SSPP_TYPE_VIG, 92 .clk_ctrl = DPU_CLK_CTRL_VIG2, 93 }, { 94 .name = "sspp_3", .id = SSPP_VIG3, 95 .base = 0xa000, .len = 0x1ac, 96 .features = VIG_MSM8998_MASK, 97 .sblk = &msm8998_vig_sblk_3, 98 .xin_id = 12, 99 .type = SSPP_TYPE_VIG, 100 .clk_ctrl = DPU_CLK_CTRL_VIG3, 101 }, { 102 .name = "sspp_8", .id = SSPP_DMA0, 103 .base = 0x24000, .len = 0x1ac, 104 .features = DMA_MSM8998_MASK, 105 .sblk = &sdm845_dma_sblk_0, 106 .xin_id = 1, 107 .type = SSPP_TYPE_DMA, 108 .clk_ctrl = DPU_CLK_CTRL_DMA0, 109 }, { 110 .name = "sspp_9", .id = SSPP_DMA1, 111 .base = 0x26000, .len = 0x1ac, 112 .features = DMA_MSM8998_MASK, 113 .sblk = &sdm845_dma_sblk_1, 114 .xin_id = 5, 115 .type = SSPP_TYPE_DMA, 116 .clk_ctrl = DPU_CLK_CTRL_DMA1, 117 }, { 118 .name = "sspp_10", .id = SSPP_DMA2, 119 .base = 0x28000, .len = 0x1ac, 120 .features = DMA_CURSOR_MSM8998_MASK, 121 .sblk = &sdm845_dma_sblk_2, 122 .xin_id = 9, 123 .type = SSPP_TYPE_DMA, 124 .clk_ctrl = DPU_CLK_CTRL_DMA2, 125 }, { 126 .name = "sspp_11", .id = SSPP_DMA3, 127 .base = 0x2a000, .len = 0x1ac, 128 .features = DMA_CURSOR_MSM8998_MASK, 129 .sblk = &sdm845_dma_sblk_3, 130 .xin_id = 13, 131 .type = SSPP_TYPE_DMA, 132 .clk_ctrl = DPU_CLK_CTRL_DMA3, 133 }, 134 }; 135 136 static const struct dpu_lm_cfg msm8998_lm[] = { 137 { 138 .name = "lm_0", .id = LM_0, 139 .base = 0x44000, .len = 0x320, 140 .features = MIXER_MSM8998_MASK, 141 .sblk = &msm8998_lm_sblk, 142 .lm_pair = LM_1, 143 .pingpong = PINGPONG_0, 144 .dspp = DSPP_0, 145 }, { 146 .name = "lm_1", .id = LM_1, 147 .base = 0x45000, .len = 0x320, 148 .features = MIXER_MSM8998_MASK, 149 .sblk = &msm8998_lm_sblk, 150 .lm_pair = LM_0, 151 .pingpong = PINGPONG_1, 152 .dspp = DSPP_1, 153 }, { 154 .name = "lm_2", .id = LM_2, 155 .base = 0x46000, .len = 0x320, 156 .features = MIXER_MSM8998_MASK, 157 .sblk = &msm8998_lm_sblk, 158 .lm_pair = LM_5, 159 .pingpong = PINGPONG_2, 160 }, { 161 .name = "lm_5", .id = LM_5, 162 .base = 0x49000, .len = 0x320, 163 .features = MIXER_MSM8998_MASK, 164 .sblk = &msm8998_lm_sblk, 165 .lm_pair = LM_2, 166 .pingpong = PINGPONG_3, 167 }, 168 }; 169 170 static const struct dpu_pingpong_cfg msm8998_pp[] = { 171 { 172 .name = "pingpong_0", .id = PINGPONG_0, 173 .base = 0x70000, .len = 0xd4, 174 .features = PINGPONG_SDM845_TE2_MASK, 175 .sblk = &sdm845_pp_sblk_te, 176 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 177 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), 178 }, { 179 .name = "pingpong_1", .id = PINGPONG_1, 180 .base = 0x70800, .len = 0xd4, 181 .features = PINGPONG_SDM845_TE2_MASK, 182 .sblk = &sdm845_pp_sblk_te, 183 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 184 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), 185 }, { 186 .name = "pingpong_2", .id = PINGPONG_2, 187 .base = 0x71000, .len = 0xd4, 188 .features = PINGPONG_SDM845_MASK, 189 .sblk = &sdm845_pp_sblk, 190 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 191 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), 192 }, { 193 .name = "pingpong_3", .id = PINGPONG_3, 194 .base = 0x71800, .len = 0xd4, 195 .features = PINGPONG_SDM845_MASK, 196 .sblk = &sdm845_pp_sblk, 197 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 198 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), 199 }, 200 }; 201 202 static const struct dpu_dsc_cfg msm8998_dsc[] = { 203 { 204 .name = "dsc_0", .id = DSC_0, 205 .base = 0x80000, .len = 0x140, 206 }, { 207 .name = "dsc_1", .id = DSC_1, 208 .base = 0x80400, .len = 0x140, 209 }, 210 }; 211 212 static const struct dpu_dspp_cfg msm8998_dspp[] = { 213 { 214 .name = "dspp_0", .id = DSPP_0, 215 .base = 0x54000, .len = 0x1800, 216 .features = DSPP_SC7180_MASK, 217 .sblk = &msm8998_dspp_sblk, 218 }, { 219 .name = "dspp_1", .id = DSPP_1, 220 .base = 0x56000, .len = 0x1800, 221 .features = DSPP_SC7180_MASK, 222 .sblk = &msm8998_dspp_sblk, 223 }, 224 }; 225 226 static const struct dpu_intf_cfg msm8998_intf[] = { 227 { 228 .name = "intf_0", .id = INTF_0, 229 .base = 0x6a000, .len = 0x280, 230 .type = INTF_DP, 231 .controller_id = MSM_DP_CONTROLLER_0, 232 .prog_fetch_lines_worst_case = 21, 233 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 234 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 235 .intr_tear_rd_ptr = -1, 236 }, { 237 .name = "intf_1", .id = INTF_1, 238 .base = 0x6a800, .len = 0x280, 239 .type = INTF_DSI, 240 .controller_id = MSM_DSI_CONTROLLER_0, 241 .prog_fetch_lines_worst_case = 21, 242 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 243 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 244 .intr_tear_rd_ptr = -1, 245 }, { 246 .name = "intf_2", .id = INTF_2, 247 .base = 0x6b000, .len = 0x280, 248 .type = INTF_DSI, 249 .controller_id = MSM_DSI_CONTROLLER_1, 250 .prog_fetch_lines_worst_case = 21, 251 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 252 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 253 .intr_tear_rd_ptr = -1, 254 }, { 255 .name = "intf_3", .id = INTF_3, 256 .base = 0x6b800, .len = 0x280, 257 .type = INTF_HDMI, 258 .prog_fetch_lines_worst_case = 21, 259 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 260 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 261 .intr_tear_rd_ptr = -1, 262 }, 263 }; 264 265 static const struct dpu_perf_cfg msm8998_perf_data = { 266 .max_bw_low = 6700000, 267 .max_bw_high = 6700000, 268 .min_core_ib = 2400000, 269 .min_llcc_ib = 800000, 270 .min_dram_ib = 800000, 271 .undersized_prefill_lines = 2, 272 .xtra_prefill_lines = 2, 273 .dest_scale_prefill_lines = 3, 274 .macrotile_prefill_lines = 4, 275 .yuv_nv12_prefill_lines = 8, 276 .linear_prefill_lines = 1, 277 .downscaling_prefill_lines = 1, 278 .amortizable_threshold = 25, 279 .min_prefill_lines = 25, 280 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 281 .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, 282 .qos_lut_tbl = { 283 {.nentry = ARRAY_SIZE(msm8998_qos_linear), 284 .entries = msm8998_qos_linear 285 }, 286 {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), 287 .entries = msm8998_qos_macrotile 288 }, 289 {.nentry = ARRAY_SIZE(msm8998_qos_nrt), 290 .entries = msm8998_qos_nrt 291 }, 292 }, 293 .cdp_cfg = { 294 {.rd_enable = 1, .wr_enable = 1}, 295 {.rd_enable = 1, .wr_enable = 0} 296 }, 297 .clk_inefficiency_factor = 200, 298 .bw_inefficiency_factor = 120, 299 }; 300 301 static const struct dpu_mdss_version msm8998_mdss_ver = { 302 .core_major_ver = 3, 303 .core_minor_ver = 0, 304 }; 305 306 const struct dpu_mdss_cfg dpu_msm8998_cfg = { 307 .mdss_ver = &msm8998_mdss_ver, 308 .caps = &msm8998_dpu_caps, 309 .mdp = &msm8998_mdp, 310 .ctl_count = ARRAY_SIZE(msm8998_ctl), 311 .ctl = msm8998_ctl, 312 .sspp_count = ARRAY_SIZE(msm8998_sspp), 313 .sspp = msm8998_sspp, 314 .mixer_count = ARRAY_SIZE(msm8998_lm), 315 .mixer = msm8998_lm, 316 .dspp_count = ARRAY_SIZE(msm8998_dspp), 317 .dspp = msm8998_dspp, 318 .pingpong_count = ARRAY_SIZE(msm8998_pp), 319 .pingpong = msm8998_pp, 320 .dsc_count = ARRAY_SIZE(msm8998_dsc), 321 .dsc = msm8998_dsc, 322 .intf_count = ARRAY_SIZE(msm8998_intf), 323 .intf = msm8998_intf, 324 .vbif_count = ARRAY_SIZE(msm8998_vbif), 325 .vbif = msm8998_vbif, 326 .perf = &msm8998_perf_data, 327 }; 328 329 #endif 330