1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dc.h"
27 #include "dc_dmub_srv.h"
28 #include "dmub/dmub_srv.h"
29 #include "core_types.h"
30 #include "dmub_replay.h"
31
32 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
33
34 #define MAX_PIPES 6
35
36 /*
37 * Get Replay state from firmware.
38 */
dmub_replay_get_state(struct dmub_replay * dmub,enum replay_state * state,uint8_t panel_inst)39 static void dmub_replay_get_state(struct dmub_replay *dmub, enum replay_state *state, uint8_t panel_inst)
40 {
41 struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
42 /* uint32_t raw_state = 0; */
43 uint32_t retry_count = 0;
44 enum dmub_status status;
45
46 do {
47 // Send gpint command and wait for ack
48 status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_REPLAY_STATE, panel_inst, 30);
49
50 if (status == DMUB_STATUS_OK) {
51 // GPINT was executed, get response
52 dmub_srv_get_gpint_response(srv, (uint32_t *)state);
53 } else
54 // Return invalid state when GPINT times out
55 *state = REPLAY_STATE_INVALID;
56 } while (++retry_count <= 1000 && *state == REPLAY_STATE_INVALID);
57
58 // Assert if max retry hit
59 if (retry_count >= 1000 && *state == REPLAY_STATE_INVALID) {
60 ASSERT(0);
61 /* To-do: Add retry fail log */
62 }
63 }
64
65 /*
66 * Enable/Disable Replay.
67 */
dmub_replay_enable(struct dmub_replay * dmub,bool enable,bool wait,uint8_t panel_inst)68 static void dmub_replay_enable(struct dmub_replay *dmub, bool enable, bool wait, uint8_t panel_inst)
69 {
70 union dmub_rb_cmd cmd;
71 struct dc_context *dc = dmub->ctx;
72 uint32_t retry_count;
73 enum replay_state state = REPLAY_STATE_0;
74
75 memset(&cmd, 0, sizeof(cmd));
76 cmd.replay_enable.header.type = DMUB_CMD__REPLAY;
77 cmd.replay_enable.data.panel_inst = panel_inst;
78
79 cmd.replay_enable.header.sub_type = DMUB_CMD__REPLAY_ENABLE;
80 if (enable)
81 cmd.replay_enable.data.enable = REPLAY_ENABLE;
82 else
83 cmd.replay_enable.data.enable = REPLAY_DISABLE;
84
85 cmd.replay_enable.header.payload_bytes = sizeof(struct dmub_rb_cmd_replay_enable_data);
86
87 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
88
89 /* Below loops 1000 x 500us = 500 ms.
90 * Exit REPLAY may need to wait 1-2 frames to power up. Timeout after at
91 * least a few frames. Should never hit the max retry assert below.
92 */
93 if (wait) {
94 for (retry_count = 0; retry_count <= 1000; retry_count++) {
95 dmub_replay_get_state(dmub, &state, panel_inst);
96
97 if (enable) {
98 if (state != REPLAY_STATE_0)
99 break;
100 } else {
101 if (state == REPLAY_STATE_0)
102 break;
103 }
104
105 /* must *not* be fsleep - this can be called from high irq levels */
106 udelay(500);
107 }
108
109 /* assert if max retry hit */
110 if (retry_count >= 1000)
111 ASSERT(0);
112 }
113
114 }
115
116 /*
117 * Set REPLAY power optimization flags.
118 */
dmub_replay_set_power_opt(struct dmub_replay * dmub,unsigned int power_opt,uint8_t panel_inst)119 static void dmub_replay_set_power_opt(struct dmub_replay *dmub, unsigned int power_opt, uint8_t panel_inst)
120 {
121 union dmub_rb_cmd cmd;
122 struct dc_context *dc = dmub->ctx;
123
124 memset(&cmd, 0, sizeof(cmd));
125 cmd.replay_set_power_opt.header.type = DMUB_CMD__REPLAY;
126 cmd.replay_set_power_opt.header.sub_type = DMUB_CMD__SET_REPLAY_POWER_OPT;
127 cmd.replay_set_power_opt.header.payload_bytes = sizeof(struct dmub_cmd_replay_set_power_opt_data);
128 cmd.replay_set_power_opt.replay_set_power_opt_data.power_opt = power_opt;
129 cmd.replay_set_power_opt.replay_set_power_opt_data.panel_inst = panel_inst;
130
131 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
132 }
133
134 /*
135 * Setup Replay by programming phy registers and sending replay hw context values to firmware.
136 */
dmub_replay_copy_settings(struct dmub_replay * dmub,struct dc_link * link,struct replay_context * replay_context,uint8_t panel_inst)137 static bool dmub_replay_copy_settings(struct dmub_replay *dmub,
138 struct dc_link *link,
139 struct replay_context *replay_context,
140 uint8_t panel_inst)
141 {
142 union dmub_rb_cmd cmd;
143 struct dc_context *dc = dmub->ctx;
144 struct dmub_cmd_replay_copy_settings_data *copy_settings_data
145 = &cmd.replay_copy_settings.replay_copy_settings_data;
146 struct pipe_ctx *pipe_ctx = NULL;
147 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;
148 int i = 0;
149
150 for (i = 0; i < MAX_PIPES; i++) {
151 if (res_ctx &&
152 res_ctx->pipe_ctx[i].stream &&
153 res_ctx->pipe_ctx[i].stream->link &&
154 res_ctx->pipe_ctx[i].stream->link == link &&
155 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {
156 pipe_ctx = &res_ctx->pipe_ctx[i];
157 //TODO: refactor for multi edp support
158 break;
159 }
160 }
161
162 if (!pipe_ctx)
163 return false;
164
165 memset(&cmd, 0, sizeof(cmd));
166 cmd.replay_copy_settings.header.type = DMUB_CMD__REPLAY;
167 cmd.replay_copy_settings.header.sub_type = DMUB_CMD__REPLAY_COPY_SETTINGS;
168 cmd.replay_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_replay_copy_settings_data);
169
170 // HW insts
171 copy_settings_data->aux_inst = replay_context->aux_inst;
172 copy_settings_data->digbe_inst = replay_context->digbe_inst;
173 copy_settings_data->digfe_inst = replay_context->digfe_inst;
174
175 if (pipe_ctx->plane_res.dpp)
176 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
177 else
178 copy_settings_data->dpp_inst = 0;
179 if (pipe_ctx->stream_res.tg)
180 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst;
181 else
182 copy_settings_data->otg_inst = 0;
183
184 copy_settings_data->dpphy_inst = link->link_enc->transmitter;
185
186 // Misc
187 copy_settings_data->line_time_in_ns = replay_context->line_time_in_ns;
188 copy_settings_data->panel_inst = panel_inst;
189 copy_settings_data->debug.u32All = link->replay_settings.config.debug_flags;
190 copy_settings_data->pixel_deviation_per_line = link->dpcd_caps.pr_info.pixel_deviation_per_line;
191 copy_settings_data->max_deviation_line = link->dpcd_caps.pr_info.max_deviation_line;
192 copy_settings_data->smu_optimizations_en = link->replay_settings.replay_smu_opt_enable;
193 copy_settings_data->replay_timing_sync_supported = link->replay_settings.config.replay_timing_sync_supported;
194
195 copy_settings_data->flags.u32All = 0;
196 copy_settings_data->flags.bitfields.fec_enable_status = (link->fec_state == dc_link_fec_enabled);
197 copy_settings_data->flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);
198 // WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update)
199 if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
200 !link->dc->debug.disable_fec) &&
201 (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
202 !link->panel_config.dsc.disable_dsc_edp &&
203 link->dc->caps.edp_dsc_support)) &&
204 link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 /*&&
205 (!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
206 sizeof(DP_SINK_DEVICE_STR_ID_1)) ||
207 !memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_2,
208 sizeof(DP_SINK_DEVICE_STR_ID_2)))*/)
209 copy_settings_data->flags.bitfields.force_wakeup_by_tps3 = 1;
210 else
211 copy_settings_data->flags.bitfields.force_wakeup_by_tps3 = 0;
212
213
214 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
215
216 return true;
217 }
218
219 /*
220 * Set coasting vtotal.
221 */
dmub_replay_set_coasting_vtotal(struct dmub_replay * dmub,uint16_t coasting_vtotal,uint8_t panel_inst)222 static void dmub_replay_set_coasting_vtotal(struct dmub_replay *dmub,
223 uint16_t coasting_vtotal,
224 uint8_t panel_inst)
225 {
226 union dmub_rb_cmd cmd;
227 struct dc_context *dc = dmub->ctx;
228
229 memset(&cmd, 0, sizeof(cmd));
230 cmd.replay_set_coasting_vtotal.header.type = DMUB_CMD__REPLAY;
231 cmd.replay_set_coasting_vtotal.header.sub_type = DMUB_CMD__REPLAY_SET_COASTING_VTOTAL;
232 cmd.replay_set_coasting_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_replay_set_coasting_vtotal_data);
233 cmd.replay_set_coasting_vtotal.replay_set_coasting_vtotal_data.coasting_vtotal = coasting_vtotal;
234
235 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
236 }
237
238 /*
239 * Get Replay residency from firmware.
240 */
dmub_replay_residency(struct dmub_replay * dmub,uint8_t panel_inst,uint32_t * residency,const bool is_start,const bool is_alpm)241 static void dmub_replay_residency(struct dmub_replay *dmub, uint8_t panel_inst,
242 uint32_t *residency, const bool is_start, const bool is_alpm)
243 {
244 struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
245 uint16_t param = (uint16_t)(panel_inst << 8);
246
247 if (is_alpm)
248 param |= REPLAY_RESIDENCY_MODE_ALPM;
249
250 if (is_start)
251 param |= REPLAY_RESIDENCY_ENABLE;
252
253 // Send gpint command and wait for ack
254 dmub_srv_send_gpint_command(srv, DMUB_GPINT__REPLAY_RESIDENCY, param, 30);
255
256 if (!is_start)
257 dmub_srv_get_gpint_response(srv, residency);
258 else
259 *residency = 0;
260 }
261
262 static const struct dmub_replay_funcs replay_funcs = {
263 .replay_copy_settings = dmub_replay_copy_settings,
264 .replay_enable = dmub_replay_enable,
265 .replay_get_state = dmub_replay_get_state,
266 .replay_set_power_opt = dmub_replay_set_power_opt,
267 .replay_set_coasting_vtotal = dmub_replay_set_coasting_vtotal,
268 .replay_residency = dmub_replay_residency,
269 };
270
271 /*
272 * Construct Replay object.
273 */
dmub_replay_construct(struct dmub_replay * replay,struct dc_context * ctx)274 static void dmub_replay_construct(struct dmub_replay *replay, struct dc_context *ctx)
275 {
276 replay->ctx = ctx;
277 replay->funcs = &replay_funcs;
278 }
279
280 /*
281 * Allocate and initialize Replay object.
282 */
dmub_replay_create(struct dc_context * ctx)283 struct dmub_replay *dmub_replay_create(struct dc_context *ctx)
284 {
285 struct dmub_replay *replay = kzalloc(sizeof(struct dmub_replay), GFP_KERNEL);
286
287 if (replay == NULL) {
288 BREAK_TO_DEBUGGER();
289 return NULL;
290 }
291
292 dmub_replay_construct(replay, ctx);
293
294 return replay;
295 }
296
297 /*
298 * Deallocate Replay object.
299 */
dmub_replay_destroy(struct dmub_replay ** dmub)300 void dmub_replay_destroy(struct dmub_replay **dmub)
301 {
302 kfree(*dmub);
303 *dmub = NULL;
304 }
305