1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #undef DEBUG 19 20 #include <linux/clk.h> 21 #include <linux/console.h> 22 #include <linux/ctype.h> 23 #include <linux/cpufreq.h> 24 #include <linux/delay.h> 25 #include <linux/dmaengine.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/err.h> 28 #include <linux/errno.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/ioport.h> 32 #include <linux/ktime.h> 33 #include <linux/major.h> 34 #include <linux/minmax.h> 35 #include <linux/module.h> 36 #include <linux/mm.h> 37 #include <linux/of.h> 38 #include <linux/platform_device.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/reset.h> 41 #include <linux/scatterlist.h> 42 #include <linux/serial.h> 43 #include <linux/serial_sci.h> 44 #include <linux/sh_dma.h> 45 #include <linux/slab.h> 46 #include <linux/string.h> 47 #include <linux/sysrq.h> 48 #include <linux/timer.h> 49 #include <linux/tty.h> 50 #include <linux/tty_flip.h> 51 52 #ifdef CONFIG_SUPERH 53 #include <asm/sh_bios.h> 54 #include <asm/platform_early.h> 55 #endif 56 57 #include "serial_mctrl_gpio.h" 58 #include "sh-sci.h" 59 60 /* Offsets into the sci_port->irqs array */ 61 enum { 62 SCIx_ERI_IRQ, 63 SCIx_RXI_IRQ, 64 SCIx_TXI_IRQ, 65 SCIx_BRI_IRQ, 66 SCIx_DRI_IRQ, 67 SCIx_TEI_IRQ, 68 SCIx_NR_IRQS, 69 70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 71 }; 72 73 #define SCIx_IRQ_IS_MUXED(port) \ 74 ((port)->irqs[SCIx_ERI_IRQ] == \ 75 (port)->irqs[SCIx_RXI_IRQ]) || \ 76 ((port)->irqs[SCIx_ERI_IRQ] && \ 77 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 78 79 enum SCI_CLKS { 80 SCI_FCK, /* Functional Clock */ 81 SCI_SCK, /* Optional External Clock */ 82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 84 SCI_NUM_CLKS 85 }; 86 87 /* Bit x set means sampling rate x + 1 is supported */ 88 #define SCI_SR(x) BIT((x) - 1) 89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 90 91 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 93 SCI_SR(19) | SCI_SR(27) 94 95 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 96 #define max_sr(_port) fls((_port)->sampling_rate_mask) 97 98 /* Iterate over all supported sampling rates, from high to low */ 99 #define for_each_sr(_sr, _port) \ 100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 101 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 102 103 struct plat_sci_reg { 104 u8 offset, size; 105 }; 106 107 struct sci_port_params { 108 const struct plat_sci_reg regs[SCIx_NR_REGS]; 109 unsigned int fifosize; 110 unsigned int overrun_reg; 111 unsigned int overrun_mask; 112 unsigned int sampling_rate_mask; 113 unsigned int error_mask; 114 unsigned int error_clear; 115 }; 116 117 struct sci_port { 118 struct uart_port port; 119 120 /* Platform configuration */ 121 const struct sci_port_params *params; 122 const struct plat_sci_port *cfg; 123 unsigned int sampling_rate_mask; 124 resource_size_t reg_size; 125 struct mctrl_gpios *gpios; 126 127 /* Clocks */ 128 struct clk *clks[SCI_NUM_CLKS]; 129 unsigned long clk_rates[SCI_NUM_CLKS]; 130 131 int irqs[SCIx_NR_IRQS]; 132 char *irqstr[SCIx_NR_IRQS]; 133 134 struct dma_chan *chan_tx; 135 struct dma_chan *chan_rx; 136 137 #ifdef CONFIG_SERIAL_SH_SCI_DMA 138 struct dma_chan *chan_tx_saved; 139 struct dma_chan *chan_rx_saved; 140 dma_cookie_t cookie_tx; 141 dma_cookie_t cookie_rx[2]; 142 dma_cookie_t active_rx; 143 dma_addr_t tx_dma_addr; 144 unsigned int tx_dma_len; 145 struct scatterlist sg_rx[2]; 146 void *rx_buf[2]; 147 size_t buf_len_rx; 148 struct work_struct work_tx; 149 struct hrtimer rx_timer; 150 unsigned int rx_timeout; /* microseconds */ 151 #endif 152 unsigned int rx_frame; 153 int rx_trigger; 154 struct timer_list rx_fifo_timer; 155 int rx_fifo_timeout; 156 u16 hscif_tot; 157 158 bool has_rtscts; 159 bool autorts; 160 }; 161 162 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 163 164 static struct sci_port sci_ports[SCI_NPORTS]; 165 static unsigned long sci_ports_in_use; 166 static struct uart_driver sci_uart_driver; 167 static bool sci_uart_earlycon; 168 169 static inline struct sci_port * to_sci_port(struct uart_port * uart)170 to_sci_port(struct uart_port *uart) 171 { 172 return container_of(uart, struct sci_port, port); 173 } 174 175 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 176 /* 177 * Common SCI definitions, dependent on the port's regshift 178 * value. 179 */ 180 [SCIx_SCI_REGTYPE] = { 181 .regs = { 182 [SCSMR] = { 0x00, 8 }, 183 [SCBRR] = { 0x01, 8 }, 184 [SCSCR] = { 0x02, 8 }, 185 [SCxTDR] = { 0x03, 8 }, 186 [SCxSR] = { 0x04, 8 }, 187 [SCxRDR] = { 0x05, 8 }, 188 }, 189 .fifosize = 1, 190 .overrun_reg = SCxSR, 191 .overrun_mask = SCI_ORER, 192 .sampling_rate_mask = SCI_SR(32), 193 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 194 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 195 }, 196 197 /* 198 * Common definitions for legacy IrDA ports. 199 */ 200 [SCIx_IRDA_REGTYPE] = { 201 .regs = { 202 [SCSMR] = { 0x00, 8 }, 203 [SCBRR] = { 0x02, 8 }, 204 [SCSCR] = { 0x04, 8 }, 205 [SCxTDR] = { 0x06, 8 }, 206 [SCxSR] = { 0x08, 16 }, 207 [SCxRDR] = { 0x0a, 8 }, 208 [SCFCR] = { 0x0c, 8 }, 209 [SCFDR] = { 0x0e, 16 }, 210 }, 211 .fifosize = 1, 212 .overrun_reg = SCxSR, 213 .overrun_mask = SCI_ORER, 214 .sampling_rate_mask = SCI_SR(32), 215 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 216 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 217 }, 218 219 /* 220 * Common SCIFA definitions. 221 */ 222 [SCIx_SCIFA_REGTYPE] = { 223 .regs = { 224 [SCSMR] = { 0x00, 16 }, 225 [SCBRR] = { 0x04, 8 }, 226 [SCSCR] = { 0x08, 16 }, 227 [SCxTDR] = { 0x20, 8 }, 228 [SCxSR] = { 0x14, 16 }, 229 [SCxRDR] = { 0x24, 8 }, 230 [SCFCR] = { 0x18, 16 }, 231 [SCFDR] = { 0x1c, 16 }, 232 [SCPCR] = { 0x30, 16 }, 233 [SCPDR] = { 0x34, 16 }, 234 }, 235 .fifosize = 64, 236 .overrun_reg = SCxSR, 237 .overrun_mask = SCIFA_ORER, 238 .sampling_rate_mask = SCI_SR_SCIFAB, 239 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 240 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 241 }, 242 243 /* 244 * Common SCIFB definitions. 245 */ 246 [SCIx_SCIFB_REGTYPE] = { 247 .regs = { 248 [SCSMR] = { 0x00, 16 }, 249 [SCBRR] = { 0x04, 8 }, 250 [SCSCR] = { 0x08, 16 }, 251 [SCxTDR] = { 0x40, 8 }, 252 [SCxSR] = { 0x14, 16 }, 253 [SCxRDR] = { 0x60, 8 }, 254 [SCFCR] = { 0x18, 16 }, 255 [SCTFDR] = { 0x38, 16 }, 256 [SCRFDR] = { 0x3c, 16 }, 257 [SCPCR] = { 0x30, 16 }, 258 [SCPDR] = { 0x34, 16 }, 259 }, 260 .fifosize = 256, 261 .overrun_reg = SCxSR, 262 .overrun_mask = SCIFA_ORER, 263 .sampling_rate_mask = SCI_SR_SCIFAB, 264 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 265 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 266 }, 267 268 /* 269 * Common SH-2(A) SCIF definitions for ports with FIFO data 270 * count registers. 271 */ 272 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 273 .regs = { 274 [SCSMR] = { 0x00, 16 }, 275 [SCBRR] = { 0x04, 8 }, 276 [SCSCR] = { 0x08, 16 }, 277 [SCxTDR] = { 0x0c, 8 }, 278 [SCxSR] = { 0x10, 16 }, 279 [SCxRDR] = { 0x14, 8 }, 280 [SCFCR] = { 0x18, 16 }, 281 [SCFDR] = { 0x1c, 16 }, 282 [SCSPTR] = { 0x20, 16 }, 283 [SCLSR] = { 0x24, 16 }, 284 }, 285 .fifosize = 16, 286 .overrun_reg = SCLSR, 287 .overrun_mask = SCLSR_ORER, 288 .sampling_rate_mask = SCI_SR(32), 289 .error_mask = SCIF_DEFAULT_ERROR_MASK, 290 .error_clear = SCIF_ERROR_CLEAR, 291 }, 292 293 /* 294 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. 295 * It looks like a normal SCIF with FIFO data, but with a 296 * compressed address space. Also, the break out of interrupts 297 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 298 */ 299 [SCIx_RZ_SCIFA_REGTYPE] = { 300 .regs = { 301 [SCSMR] = { 0x00, 16 }, 302 [SCBRR] = { 0x02, 8 }, 303 [SCSCR] = { 0x04, 16 }, 304 [SCxTDR] = { 0x06, 8 }, 305 [SCxSR] = { 0x08, 16 }, 306 [SCxRDR] = { 0x0A, 8 }, 307 [SCFCR] = { 0x0C, 16 }, 308 [SCFDR] = { 0x0E, 16 }, 309 [SCSPTR] = { 0x10, 16 }, 310 [SCLSR] = { 0x12, 16 }, 311 [SEMR] = { 0x14, 8 }, 312 }, 313 .fifosize = 16, 314 .overrun_reg = SCLSR, 315 .overrun_mask = SCLSR_ORER, 316 .sampling_rate_mask = SCI_SR(32), 317 .error_mask = SCIF_DEFAULT_ERROR_MASK, 318 .error_clear = SCIF_ERROR_CLEAR, 319 }, 320 321 /* 322 * Common SH-3 SCIF definitions. 323 */ 324 [SCIx_SH3_SCIF_REGTYPE] = { 325 .regs = { 326 [SCSMR] = { 0x00, 8 }, 327 [SCBRR] = { 0x02, 8 }, 328 [SCSCR] = { 0x04, 8 }, 329 [SCxTDR] = { 0x06, 8 }, 330 [SCxSR] = { 0x08, 16 }, 331 [SCxRDR] = { 0x0a, 8 }, 332 [SCFCR] = { 0x0c, 8 }, 333 [SCFDR] = { 0x0e, 16 }, 334 }, 335 .fifosize = 16, 336 .overrun_reg = SCLSR, 337 .overrun_mask = SCLSR_ORER, 338 .sampling_rate_mask = SCI_SR(32), 339 .error_mask = SCIF_DEFAULT_ERROR_MASK, 340 .error_clear = SCIF_ERROR_CLEAR, 341 }, 342 343 /* 344 * Common SH-4(A) SCIF(B) definitions. 345 */ 346 [SCIx_SH4_SCIF_REGTYPE] = { 347 .regs = { 348 [SCSMR] = { 0x00, 16 }, 349 [SCBRR] = { 0x04, 8 }, 350 [SCSCR] = { 0x08, 16 }, 351 [SCxTDR] = { 0x0c, 8 }, 352 [SCxSR] = { 0x10, 16 }, 353 [SCxRDR] = { 0x14, 8 }, 354 [SCFCR] = { 0x18, 16 }, 355 [SCFDR] = { 0x1c, 16 }, 356 [SCSPTR] = { 0x20, 16 }, 357 [SCLSR] = { 0x24, 16 }, 358 }, 359 .fifosize = 16, 360 .overrun_reg = SCLSR, 361 .overrun_mask = SCLSR_ORER, 362 .sampling_rate_mask = SCI_SR(32), 363 .error_mask = SCIF_DEFAULT_ERROR_MASK, 364 .error_clear = SCIF_ERROR_CLEAR, 365 }, 366 367 /* 368 * Common SCIF definitions for ports with a Baud Rate Generator for 369 * External Clock (BRG). 370 */ 371 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 372 .regs = { 373 [SCSMR] = { 0x00, 16 }, 374 [SCBRR] = { 0x04, 8 }, 375 [SCSCR] = { 0x08, 16 }, 376 [SCxTDR] = { 0x0c, 8 }, 377 [SCxSR] = { 0x10, 16 }, 378 [SCxRDR] = { 0x14, 8 }, 379 [SCFCR] = { 0x18, 16 }, 380 [SCFDR] = { 0x1c, 16 }, 381 [SCSPTR] = { 0x20, 16 }, 382 [SCLSR] = { 0x24, 16 }, 383 [SCDL] = { 0x30, 16 }, 384 [SCCKS] = { 0x34, 16 }, 385 }, 386 .fifosize = 16, 387 .overrun_reg = SCLSR, 388 .overrun_mask = SCLSR_ORER, 389 .sampling_rate_mask = SCI_SR(32), 390 .error_mask = SCIF_DEFAULT_ERROR_MASK, 391 .error_clear = SCIF_ERROR_CLEAR, 392 }, 393 394 /* 395 * Common HSCIF definitions. 396 */ 397 [SCIx_HSCIF_REGTYPE] = { 398 .regs = { 399 [SCSMR] = { 0x00, 16 }, 400 [SCBRR] = { 0x04, 8 }, 401 [SCSCR] = { 0x08, 16 }, 402 [SCxTDR] = { 0x0c, 8 }, 403 [SCxSR] = { 0x10, 16 }, 404 [SCxRDR] = { 0x14, 8 }, 405 [SCFCR] = { 0x18, 16 }, 406 [SCFDR] = { 0x1c, 16 }, 407 [SCSPTR] = { 0x20, 16 }, 408 [SCLSR] = { 0x24, 16 }, 409 [HSSRR] = { 0x40, 16 }, 410 [SCDL] = { 0x30, 16 }, 411 [SCCKS] = { 0x34, 16 }, 412 [HSRTRGR] = { 0x54, 16 }, 413 [HSTTRGR] = { 0x58, 16 }, 414 }, 415 .fifosize = 128, 416 .overrun_reg = SCLSR, 417 .overrun_mask = SCLSR_ORER, 418 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 419 .error_mask = SCIF_DEFAULT_ERROR_MASK, 420 .error_clear = SCIF_ERROR_CLEAR, 421 }, 422 423 /* 424 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 425 * register. 426 */ 427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 428 .regs = { 429 [SCSMR] = { 0x00, 16 }, 430 [SCBRR] = { 0x04, 8 }, 431 [SCSCR] = { 0x08, 16 }, 432 [SCxTDR] = { 0x0c, 8 }, 433 [SCxSR] = { 0x10, 16 }, 434 [SCxRDR] = { 0x14, 8 }, 435 [SCFCR] = { 0x18, 16 }, 436 [SCFDR] = { 0x1c, 16 }, 437 [SCLSR] = { 0x24, 16 }, 438 }, 439 .fifosize = 16, 440 .overrun_reg = SCLSR, 441 .overrun_mask = SCLSR_ORER, 442 .sampling_rate_mask = SCI_SR(32), 443 .error_mask = SCIF_DEFAULT_ERROR_MASK, 444 .error_clear = SCIF_ERROR_CLEAR, 445 }, 446 447 /* 448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 449 * count registers. 450 */ 451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 452 .regs = { 453 [SCSMR] = { 0x00, 16 }, 454 [SCBRR] = { 0x04, 8 }, 455 [SCSCR] = { 0x08, 16 }, 456 [SCxTDR] = { 0x0c, 8 }, 457 [SCxSR] = { 0x10, 16 }, 458 [SCxRDR] = { 0x14, 8 }, 459 [SCFCR] = { 0x18, 16 }, 460 [SCFDR] = { 0x1c, 16 }, 461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 462 [SCRFDR] = { 0x20, 16 }, 463 [SCSPTR] = { 0x24, 16 }, 464 [SCLSR] = { 0x28, 16 }, 465 }, 466 .fifosize = 16, 467 .overrun_reg = SCLSR, 468 .overrun_mask = SCLSR_ORER, 469 .sampling_rate_mask = SCI_SR(32), 470 .error_mask = SCIF_DEFAULT_ERROR_MASK, 471 .error_clear = SCIF_ERROR_CLEAR, 472 }, 473 474 /* 475 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 476 * registers. 477 */ 478 [SCIx_SH7705_SCIF_REGTYPE] = { 479 .regs = { 480 [SCSMR] = { 0x00, 16 }, 481 [SCBRR] = { 0x04, 8 }, 482 [SCSCR] = { 0x08, 16 }, 483 [SCxTDR] = { 0x20, 8 }, 484 [SCxSR] = { 0x14, 16 }, 485 [SCxRDR] = { 0x24, 8 }, 486 [SCFCR] = { 0x18, 16 }, 487 [SCFDR] = { 0x1c, 16 }, 488 }, 489 .fifosize = 64, 490 .overrun_reg = SCxSR, 491 .overrun_mask = SCIFA_ORER, 492 .sampling_rate_mask = SCI_SR(16), 493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 495 }, 496 }; 497 498 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 499 500 /* 501 * The "offset" here is rather misleading, in that it refers to an enum 502 * value relative to the port mapping rather than the fixed offset 503 * itself, which needs to be manually retrieved from the platform's 504 * register map for the given port. 505 */ sci_serial_in(struct uart_port * p,int offset)506 static unsigned int sci_serial_in(struct uart_port *p, int offset) 507 { 508 const struct plat_sci_reg *reg = sci_getreg(p, offset); 509 510 if (reg->size == 8) 511 return ioread8(p->membase + (reg->offset << p->regshift)); 512 else if (reg->size == 16) 513 return ioread16(p->membase + (reg->offset << p->regshift)); 514 else 515 WARN(1, "Invalid register access\n"); 516 517 return 0; 518 } 519 sci_serial_out(struct uart_port * p,int offset,int value)520 static void sci_serial_out(struct uart_port *p, int offset, int value) 521 { 522 const struct plat_sci_reg *reg = sci_getreg(p, offset); 523 524 if (reg->size == 8) 525 iowrite8(value, p->membase + (reg->offset << p->regshift)); 526 else if (reg->size == 16) 527 iowrite16(value, p->membase + (reg->offset << p->regshift)); 528 else 529 WARN(1, "Invalid register access\n"); 530 } 531 sci_port_enable(struct sci_port * sci_port)532 static void sci_port_enable(struct sci_port *sci_port) 533 { 534 unsigned int i; 535 536 if (!sci_port->port.dev) 537 return; 538 539 pm_runtime_get_sync(sci_port->port.dev); 540 541 for (i = 0; i < SCI_NUM_CLKS; i++) { 542 clk_prepare_enable(sci_port->clks[i]); 543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 544 } 545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 546 } 547 sci_port_disable(struct sci_port * sci_port)548 static void sci_port_disable(struct sci_port *sci_port) 549 { 550 unsigned int i; 551 552 if (!sci_port->port.dev) 553 return; 554 555 for (i = SCI_NUM_CLKS; i-- > 0; ) 556 clk_disable_unprepare(sci_port->clks[i]); 557 558 pm_runtime_put_sync(sci_port->port.dev); 559 } 560 port_rx_irq_mask(struct uart_port * port)561 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 562 { 563 /* 564 * Not all ports (such as SCIFA) will support REIE. Rather than 565 * special-casing the port type, we check the port initialization 566 * IRQ enable mask to see whether the IRQ is desired at all. If 567 * it's unset, it's logically inferred that there's no point in 568 * testing for it. 569 */ 570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 571 } 572 sci_start_tx(struct uart_port * port)573 static void sci_start_tx(struct uart_port *port) 574 { 575 struct sci_port *s = to_sci_port(port); 576 unsigned short ctrl; 577 578 #ifdef CONFIG_SERIAL_SH_SCI_DMA 579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 580 u16 new, scr = serial_port_in(port, SCSCR); 581 if (s->chan_tx) 582 new = scr | SCSCR_TDRQE; 583 else 584 new = scr & ~SCSCR_TDRQE; 585 if (new != scr) 586 serial_port_out(port, SCSCR, new); 587 } 588 589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 590 dma_submit_error(s->cookie_tx)) { 591 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 592 /* Switch irq from SCIF to DMA */ 593 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]); 594 595 s->cookie_tx = 0; 596 schedule_work(&s->work_tx); 597 } 598 #endif 599 600 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE || 601 port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 602 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 603 ctrl = serial_port_in(port, SCSCR); 604 605 /* 606 * For SCI, TE (transmit enable) must be set after setting TIE 607 * (transmit interrupt enable) or in the same instruction to start 608 * the transmit process. 609 */ 610 if (port->type == PORT_SCI) 611 ctrl |= SCSCR_TE; 612 613 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 614 } 615 } 616 sci_stop_tx(struct uart_port * port)617 static void sci_stop_tx(struct uart_port *port) 618 { 619 unsigned short ctrl; 620 621 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 622 ctrl = serial_port_in(port, SCSCR); 623 624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 625 ctrl &= ~SCSCR_TDRQE; 626 627 ctrl &= ~SCSCR_TIE; 628 629 serial_port_out(port, SCSCR, ctrl); 630 631 #ifdef CONFIG_SERIAL_SH_SCI_DMA 632 if (to_sci_port(port)->chan_tx && 633 !dma_submit_error(to_sci_port(port)->cookie_tx)) { 634 dmaengine_terminate_async(to_sci_port(port)->chan_tx); 635 to_sci_port(port)->cookie_tx = -EINVAL; 636 } 637 #endif 638 } 639 sci_start_rx(struct uart_port * port)640 static void sci_start_rx(struct uart_port *port) 641 { 642 unsigned short ctrl; 643 644 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 645 646 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 647 ctrl &= ~SCSCR_RDRQE; 648 649 serial_port_out(port, SCSCR, ctrl); 650 } 651 sci_stop_rx(struct uart_port * port)652 static void sci_stop_rx(struct uart_port *port) 653 { 654 unsigned short ctrl; 655 656 ctrl = serial_port_in(port, SCSCR); 657 658 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 659 ctrl &= ~SCSCR_RDRQE; 660 661 ctrl &= ~port_rx_irq_mask(port); 662 663 serial_port_out(port, SCSCR, ctrl); 664 } 665 sci_clear_SCxSR(struct uart_port * port,unsigned int mask)666 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 667 { 668 if (port->type == PORT_SCI) { 669 /* Just store the mask */ 670 serial_port_out(port, SCxSR, mask); 671 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 672 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 673 /* Only clear the status bits we want to clear */ 674 serial_port_out(port, SCxSR, 675 serial_port_in(port, SCxSR) & mask); 676 } else { 677 /* Store the mask, clear parity/framing errors */ 678 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 679 } 680 } 681 682 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 683 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 684 685 #ifdef CONFIG_CONSOLE_POLL sci_poll_get_char(struct uart_port * port)686 static int sci_poll_get_char(struct uart_port *port) 687 { 688 unsigned short status; 689 int c; 690 691 do { 692 status = serial_port_in(port, SCxSR); 693 if (status & SCxSR_ERRORS(port)) { 694 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 695 continue; 696 } 697 break; 698 } while (1); 699 700 if (!(status & SCxSR_RDxF(port))) 701 return NO_POLL_CHAR; 702 703 c = serial_port_in(port, SCxRDR); 704 705 /* Dummy read */ 706 serial_port_in(port, SCxSR); 707 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 708 709 return c; 710 } 711 #endif 712 sci_poll_put_char(struct uart_port * port,unsigned char c)713 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 714 { 715 unsigned short status; 716 717 do { 718 status = serial_port_in(port, SCxSR); 719 } while (!(status & SCxSR_TDxE(port))); 720 721 serial_port_out(port, SCxTDR, c); 722 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 723 } 724 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 725 CONFIG_SERIAL_SH_SCI_EARLYCON */ 726 sci_init_pins(struct uart_port * port,unsigned int cflag)727 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 728 { 729 struct sci_port *s = to_sci_port(port); 730 731 /* 732 * Use port-specific handler if provided. 733 */ 734 if (s->cfg->ops && s->cfg->ops->init_pins) { 735 s->cfg->ops->init_pins(port, cflag); 736 return; 737 } 738 739 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 740 u16 data = serial_port_in(port, SCPDR); 741 u16 ctrl = serial_port_in(port, SCPCR); 742 743 /* Enable RXD and TXD pin functions */ 744 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 745 if (to_sci_port(port)->has_rtscts) { 746 /* RTS# is output, active low, unless autorts */ 747 if (!(port->mctrl & TIOCM_RTS)) { 748 ctrl |= SCPCR_RTSC; 749 data |= SCPDR_RTSD; 750 } else if (!s->autorts) { 751 ctrl |= SCPCR_RTSC; 752 data &= ~SCPDR_RTSD; 753 } else { 754 /* Enable RTS# pin function */ 755 ctrl &= ~SCPCR_RTSC; 756 } 757 /* Enable CTS# pin function */ 758 ctrl &= ~SCPCR_CTSC; 759 } 760 serial_port_out(port, SCPDR, data); 761 serial_port_out(port, SCPCR, ctrl); 762 } else if (sci_getreg(port, SCSPTR)->size) { 763 u16 status = serial_port_in(port, SCSPTR); 764 765 /* RTS# is always output; and active low, unless autorts */ 766 status |= SCSPTR_RTSIO; 767 if (!(port->mctrl & TIOCM_RTS)) 768 status |= SCSPTR_RTSDT; 769 else if (!s->autorts) 770 status &= ~SCSPTR_RTSDT; 771 /* CTS# and SCK are inputs */ 772 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 773 serial_port_out(port, SCSPTR, status); 774 } 775 } 776 sci_txfill(struct uart_port * port)777 static int sci_txfill(struct uart_port *port) 778 { 779 struct sci_port *s = to_sci_port(port); 780 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 781 const struct plat_sci_reg *reg; 782 783 reg = sci_getreg(port, SCTFDR); 784 if (reg->size) 785 return serial_port_in(port, SCTFDR) & fifo_mask; 786 787 reg = sci_getreg(port, SCFDR); 788 if (reg->size) 789 return serial_port_in(port, SCFDR) >> 8; 790 791 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 792 } 793 sci_txroom(struct uart_port * port)794 static int sci_txroom(struct uart_port *port) 795 { 796 return port->fifosize - sci_txfill(port); 797 } 798 sci_rxfill(struct uart_port * port)799 static int sci_rxfill(struct uart_port *port) 800 { 801 struct sci_port *s = to_sci_port(port); 802 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 803 const struct plat_sci_reg *reg; 804 805 reg = sci_getreg(port, SCRFDR); 806 if (reg->size) 807 return serial_port_in(port, SCRFDR) & fifo_mask; 808 809 reg = sci_getreg(port, SCFDR); 810 if (reg->size) 811 return serial_port_in(port, SCFDR) & fifo_mask; 812 813 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 814 } 815 816 /* ********************************************************************** * 817 * the interrupt related routines * 818 * ********************************************************************** */ 819 sci_transmit_chars(struct uart_port * port)820 static void sci_transmit_chars(struct uart_port *port) 821 { 822 struct circ_buf *xmit = &port->state->xmit; 823 unsigned int stopped = uart_tx_stopped(port); 824 unsigned short status; 825 unsigned short ctrl; 826 int count; 827 828 status = serial_port_in(port, SCxSR); 829 if (!(status & SCxSR_TDxE(port))) { 830 ctrl = serial_port_in(port, SCSCR); 831 if (uart_circ_empty(xmit)) 832 ctrl &= ~SCSCR_TIE; 833 else 834 ctrl |= SCSCR_TIE; 835 serial_port_out(port, SCSCR, ctrl); 836 return; 837 } 838 839 count = sci_txroom(port); 840 841 do { 842 unsigned char c; 843 844 if (port->x_char) { 845 c = port->x_char; 846 port->x_char = 0; 847 } else if (!uart_circ_empty(xmit) && !stopped) { 848 c = xmit->buf[xmit->tail]; 849 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 850 } else if (port->type == PORT_SCI && uart_circ_empty(xmit)) { 851 ctrl = serial_port_in(port, SCSCR); 852 ctrl &= ~SCSCR_TE; 853 serial_port_out(port, SCSCR, ctrl); 854 return; 855 } else { 856 break; 857 } 858 859 serial_port_out(port, SCxTDR, c); 860 861 port->icount.tx++; 862 } while (--count > 0); 863 864 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 865 866 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 867 uart_write_wakeup(port); 868 if (uart_circ_empty(xmit)) { 869 if (port->type == PORT_SCI) { 870 ctrl = serial_port_in(port, SCSCR); 871 ctrl &= ~SCSCR_TIE; 872 ctrl |= SCSCR_TEIE; 873 serial_port_out(port, SCSCR, ctrl); 874 } 875 876 sci_stop_tx(port); 877 } 878 } 879 sci_receive_chars(struct uart_port * port)880 static void sci_receive_chars(struct uart_port *port) 881 { 882 struct tty_port *tport = &port->state->port; 883 int i, count, copied = 0; 884 unsigned short status; 885 unsigned char flag; 886 887 status = serial_port_in(port, SCxSR); 888 if (!(status & SCxSR_RDxF(port))) 889 return; 890 891 while (1) { 892 /* Don't copy more bytes than there is room for in the buffer */ 893 count = tty_buffer_request_room(tport, sci_rxfill(port)); 894 895 /* If for any reason we can't copy more data, we're done! */ 896 if (count == 0) 897 break; 898 899 if (port->type == PORT_SCI) { 900 char c = serial_port_in(port, SCxRDR); 901 if (uart_handle_sysrq_char(port, c)) 902 count = 0; 903 else 904 tty_insert_flip_char(tport, c, TTY_NORMAL); 905 } else { 906 for (i = 0; i < count; i++) { 907 char c; 908 909 if (port->type == PORT_SCIF || 910 port->type == PORT_HSCIF) { 911 status = serial_port_in(port, SCxSR); 912 c = serial_port_in(port, SCxRDR); 913 } else { 914 c = serial_port_in(port, SCxRDR); 915 status = serial_port_in(port, SCxSR); 916 } 917 if (uart_handle_sysrq_char(port, c)) { 918 count--; i--; 919 continue; 920 } 921 922 /* Store data and status */ 923 if (status & SCxSR_FER(port)) { 924 flag = TTY_FRAME; 925 port->icount.frame++; 926 } else if (status & SCxSR_PER(port)) { 927 flag = TTY_PARITY; 928 port->icount.parity++; 929 } else 930 flag = TTY_NORMAL; 931 932 tty_insert_flip_char(tport, c, flag); 933 } 934 } 935 936 serial_port_in(port, SCxSR); /* dummy read */ 937 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 938 939 copied += count; 940 port->icount.rx += count; 941 } 942 943 if (copied) { 944 /* Tell the rest of the system the news. New characters! */ 945 tty_flip_buffer_push(tport); 946 } else { 947 /* TTY buffers full; read from RX reg to prevent lockup */ 948 serial_port_in(port, SCxRDR); 949 serial_port_in(port, SCxSR); /* dummy read */ 950 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 951 } 952 } 953 sci_handle_errors(struct uart_port * port)954 static int sci_handle_errors(struct uart_port *port) 955 { 956 int copied = 0; 957 unsigned short status = serial_port_in(port, SCxSR); 958 struct tty_port *tport = &port->state->port; 959 struct sci_port *s = to_sci_port(port); 960 961 /* Handle overruns */ 962 if (status & s->params->overrun_mask) { 963 port->icount.overrun++; 964 965 /* overrun error */ 966 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 967 copied++; 968 } 969 970 if (status & SCxSR_FER(port)) { 971 /* frame error */ 972 port->icount.frame++; 973 974 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 975 copied++; 976 } 977 978 if (status & SCxSR_PER(port)) { 979 /* parity error */ 980 port->icount.parity++; 981 982 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 983 copied++; 984 } 985 986 if (copied) 987 tty_flip_buffer_push(tport); 988 989 return copied; 990 } 991 sci_handle_fifo_overrun(struct uart_port * port)992 static int sci_handle_fifo_overrun(struct uart_port *port) 993 { 994 struct tty_port *tport = &port->state->port; 995 struct sci_port *s = to_sci_port(port); 996 const struct plat_sci_reg *reg; 997 int copied = 0; 998 u16 status; 999 1000 reg = sci_getreg(port, s->params->overrun_reg); 1001 if (!reg->size) 1002 return 0; 1003 1004 status = serial_port_in(port, s->params->overrun_reg); 1005 if (status & s->params->overrun_mask) { 1006 status &= ~s->params->overrun_mask; 1007 serial_port_out(port, s->params->overrun_reg, status); 1008 1009 port->icount.overrun++; 1010 1011 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1012 tty_flip_buffer_push(tport); 1013 copied++; 1014 } 1015 1016 return copied; 1017 } 1018 sci_handle_breaks(struct uart_port * port)1019 static int sci_handle_breaks(struct uart_port *port) 1020 { 1021 int copied = 0; 1022 unsigned short status = serial_port_in(port, SCxSR); 1023 struct tty_port *tport = &port->state->port; 1024 1025 if (uart_handle_break(port)) 1026 return 0; 1027 1028 if (status & SCxSR_BRK(port)) { 1029 port->icount.brk++; 1030 1031 /* Notify of BREAK */ 1032 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1033 copied++; 1034 } 1035 1036 if (copied) 1037 tty_flip_buffer_push(tport); 1038 1039 copied += sci_handle_fifo_overrun(port); 1040 1041 return copied; 1042 } 1043 scif_set_rtrg(struct uart_port * port,int rx_trig)1044 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1045 { 1046 unsigned int bits; 1047 1048 if (rx_trig >= port->fifosize) 1049 rx_trig = port->fifosize - 1; 1050 if (rx_trig < 1) 1051 rx_trig = 1; 1052 1053 /* HSCIF can be set to an arbitrary level. */ 1054 if (sci_getreg(port, HSRTRGR)->size) { 1055 serial_port_out(port, HSRTRGR, rx_trig); 1056 return rx_trig; 1057 } 1058 1059 switch (port->type) { 1060 case PORT_SCIF: 1061 if (rx_trig < 4) { 1062 bits = 0; 1063 rx_trig = 1; 1064 } else if (rx_trig < 8) { 1065 bits = SCFCR_RTRG0; 1066 rx_trig = 4; 1067 } else if (rx_trig < 14) { 1068 bits = SCFCR_RTRG1; 1069 rx_trig = 8; 1070 } else { 1071 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1072 rx_trig = 14; 1073 } 1074 break; 1075 case PORT_SCIFA: 1076 case PORT_SCIFB: 1077 if (rx_trig < 16) { 1078 bits = 0; 1079 rx_trig = 1; 1080 } else if (rx_trig < 32) { 1081 bits = SCFCR_RTRG0; 1082 rx_trig = 16; 1083 } else if (rx_trig < 48) { 1084 bits = SCFCR_RTRG1; 1085 rx_trig = 32; 1086 } else { 1087 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1088 rx_trig = 48; 1089 } 1090 break; 1091 default: 1092 WARN(1, "unknown FIFO configuration"); 1093 return 1; 1094 } 1095 1096 serial_port_out(port, SCFCR, 1097 (serial_port_in(port, SCFCR) & 1098 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1099 1100 return rx_trig; 1101 } 1102 scif_rtrg_enabled(struct uart_port * port)1103 static int scif_rtrg_enabled(struct uart_port *port) 1104 { 1105 if (sci_getreg(port, HSRTRGR)->size) 1106 return serial_port_in(port, HSRTRGR) != 0; 1107 else 1108 return (serial_port_in(port, SCFCR) & 1109 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1110 } 1111 rx_fifo_timer_fn(struct timer_list * t)1112 static void rx_fifo_timer_fn(struct timer_list *t) 1113 { 1114 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1115 struct uart_port *port = &s->port; 1116 1117 dev_dbg(port->dev, "Rx timed out\n"); 1118 scif_set_rtrg(port, 1); 1119 } 1120 rx_fifo_trigger_show(struct device * dev,struct device_attribute * attr,char * buf)1121 static ssize_t rx_fifo_trigger_show(struct device *dev, 1122 struct device_attribute *attr, char *buf) 1123 { 1124 struct uart_port *port = dev_get_drvdata(dev); 1125 struct sci_port *sci = to_sci_port(port); 1126 1127 return sprintf(buf, "%d\n", sci->rx_trigger); 1128 } 1129 rx_fifo_trigger_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1130 static ssize_t rx_fifo_trigger_store(struct device *dev, 1131 struct device_attribute *attr, 1132 const char *buf, size_t count) 1133 { 1134 struct uart_port *port = dev_get_drvdata(dev); 1135 struct sci_port *sci = to_sci_port(port); 1136 int ret; 1137 long r; 1138 1139 ret = kstrtol(buf, 0, &r); 1140 if (ret) 1141 return ret; 1142 1143 sci->rx_trigger = scif_set_rtrg(port, r); 1144 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1145 scif_set_rtrg(port, 1); 1146 1147 return count; 1148 } 1149 1150 static DEVICE_ATTR_RW(rx_fifo_trigger); 1151 rx_fifo_timeout_show(struct device * dev,struct device_attribute * attr,char * buf)1152 static ssize_t rx_fifo_timeout_show(struct device *dev, 1153 struct device_attribute *attr, 1154 char *buf) 1155 { 1156 struct uart_port *port = dev_get_drvdata(dev); 1157 struct sci_port *sci = to_sci_port(port); 1158 int v; 1159 1160 if (port->type == PORT_HSCIF) 1161 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1162 else 1163 v = sci->rx_fifo_timeout; 1164 1165 return sprintf(buf, "%d\n", v); 1166 } 1167 rx_fifo_timeout_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1168 static ssize_t rx_fifo_timeout_store(struct device *dev, 1169 struct device_attribute *attr, 1170 const char *buf, 1171 size_t count) 1172 { 1173 struct uart_port *port = dev_get_drvdata(dev); 1174 struct sci_port *sci = to_sci_port(port); 1175 int ret; 1176 long r; 1177 1178 ret = kstrtol(buf, 0, &r); 1179 if (ret) 1180 return ret; 1181 1182 if (port->type == PORT_HSCIF) { 1183 if (r < 0 || r > 3) 1184 return -EINVAL; 1185 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1186 } else { 1187 sci->rx_fifo_timeout = r; 1188 scif_set_rtrg(port, 1); 1189 if (r > 0) 1190 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1191 } 1192 1193 return count; 1194 } 1195 1196 static DEVICE_ATTR_RW(rx_fifo_timeout); 1197 1198 1199 #ifdef CONFIG_SERIAL_SH_SCI_DMA sci_dma_tx_complete(void * arg)1200 static void sci_dma_tx_complete(void *arg) 1201 { 1202 struct sci_port *s = arg; 1203 struct uart_port *port = &s->port; 1204 struct circ_buf *xmit = &port->state->xmit; 1205 unsigned long flags; 1206 1207 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1208 1209 spin_lock_irqsave(&port->lock, flags); 1210 1211 uart_xmit_advance(port, s->tx_dma_len); 1212 1213 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1214 uart_write_wakeup(port); 1215 1216 if (!uart_circ_empty(xmit)) { 1217 s->cookie_tx = 0; 1218 schedule_work(&s->work_tx); 1219 } else { 1220 s->cookie_tx = -EINVAL; 1221 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1222 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1223 u16 ctrl = serial_port_in(port, SCSCR); 1224 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1225 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1226 /* Switch irq from DMA to SCIF */ 1227 dmaengine_pause(s->chan_tx_saved); 1228 enable_irq(s->irqs[SCIx_TXI_IRQ]); 1229 } 1230 } 1231 } 1232 1233 spin_unlock_irqrestore(&port->lock, flags); 1234 } 1235 1236 /* Locking: called with port lock held */ sci_dma_rx_push(struct sci_port * s,void * buf,size_t count)1237 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1238 { 1239 struct uart_port *port = &s->port; 1240 struct tty_port *tport = &port->state->port; 1241 int copied; 1242 1243 copied = tty_insert_flip_string(tport, buf, count); 1244 if (copied < count) 1245 port->icount.buf_overrun++; 1246 1247 port->icount.rx += copied; 1248 1249 return copied; 1250 } 1251 sci_dma_rx_find_active(struct sci_port * s)1252 static int sci_dma_rx_find_active(struct sci_port *s) 1253 { 1254 unsigned int i; 1255 1256 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1257 if (s->active_rx == s->cookie_rx[i]) 1258 return i; 1259 1260 return -1; 1261 } 1262 sci_dma_rx_chan_invalidate(struct sci_port * s)1263 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1264 { 1265 unsigned int i; 1266 1267 s->chan_rx = NULL; 1268 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1269 s->cookie_rx[i] = -EINVAL; 1270 s->active_rx = 0; 1271 } 1272 sci_dma_rx_release(struct sci_port * s)1273 static void sci_dma_rx_release(struct sci_port *s) 1274 { 1275 struct dma_chan *chan = s->chan_rx_saved; 1276 struct uart_port *port = &s->port; 1277 unsigned long flags; 1278 1279 uart_port_lock_irqsave(port, &flags); 1280 s->chan_rx_saved = NULL; 1281 sci_dma_rx_chan_invalidate(s); 1282 uart_port_unlock_irqrestore(port, flags); 1283 1284 dmaengine_terminate_sync(chan); 1285 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1286 sg_dma_address(&s->sg_rx[0])); 1287 dma_release_channel(chan); 1288 } 1289 start_hrtimer_us(struct hrtimer * hrt,unsigned long usec)1290 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1291 { 1292 long sec = usec / 1000000; 1293 long nsec = (usec % 1000000) * 1000; 1294 ktime_t t = ktime_set(sec, nsec); 1295 1296 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1297 } 1298 sci_dma_rx_reenable_irq(struct sci_port * s)1299 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1300 { 1301 struct uart_port *port = &s->port; 1302 u16 scr; 1303 1304 /* Direct new serial port interrupts back to CPU */ 1305 scr = serial_port_in(port, SCSCR); 1306 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1307 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1308 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1309 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1310 scif_set_rtrg(port, s->rx_trigger); 1311 else 1312 scr &= ~SCSCR_RDRQE; 1313 } 1314 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1315 } 1316 sci_dma_rx_complete(void * arg)1317 static void sci_dma_rx_complete(void *arg) 1318 { 1319 struct sci_port *s = arg; 1320 struct dma_chan *chan = s->chan_rx; 1321 struct uart_port *port = &s->port; 1322 struct dma_async_tx_descriptor *desc; 1323 unsigned long flags; 1324 int active, count = 0; 1325 1326 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1327 s->active_rx); 1328 1329 spin_lock_irqsave(&port->lock, flags); 1330 1331 active = sci_dma_rx_find_active(s); 1332 if (active >= 0) 1333 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1334 1335 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1336 1337 if (count) 1338 tty_flip_buffer_push(&port->state->port); 1339 1340 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1341 DMA_DEV_TO_MEM, 1342 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1343 if (!desc) 1344 goto fail; 1345 1346 desc->callback = sci_dma_rx_complete; 1347 desc->callback_param = s; 1348 s->cookie_rx[active] = dmaengine_submit(desc); 1349 if (dma_submit_error(s->cookie_rx[active])) 1350 goto fail; 1351 1352 s->active_rx = s->cookie_rx[!active]; 1353 1354 dma_async_issue_pending(chan); 1355 1356 spin_unlock_irqrestore(&port->lock, flags); 1357 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1358 __func__, s->cookie_rx[active], active, s->active_rx); 1359 return; 1360 1361 fail: 1362 spin_unlock_irqrestore(&port->lock, flags); 1363 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1364 /* Switch to PIO */ 1365 spin_lock_irqsave(&port->lock, flags); 1366 dmaengine_terminate_async(chan); 1367 sci_dma_rx_chan_invalidate(s); 1368 sci_dma_rx_reenable_irq(s); 1369 spin_unlock_irqrestore(&port->lock, flags); 1370 } 1371 sci_dma_tx_release(struct sci_port * s)1372 static void sci_dma_tx_release(struct sci_port *s) 1373 { 1374 struct dma_chan *chan = s->chan_tx_saved; 1375 1376 cancel_work_sync(&s->work_tx); 1377 s->chan_tx_saved = s->chan_tx = NULL; 1378 s->cookie_tx = -EINVAL; 1379 dmaengine_terminate_sync(chan); 1380 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1381 DMA_TO_DEVICE); 1382 dma_release_channel(chan); 1383 } 1384 sci_dma_rx_submit(struct sci_port * s,bool port_lock_held)1385 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1386 { 1387 struct dma_chan *chan = s->chan_rx; 1388 struct uart_port *port = &s->port; 1389 unsigned long flags; 1390 int i; 1391 1392 for (i = 0; i < 2; i++) { 1393 struct scatterlist *sg = &s->sg_rx[i]; 1394 struct dma_async_tx_descriptor *desc; 1395 1396 desc = dmaengine_prep_slave_sg(chan, 1397 sg, 1, DMA_DEV_TO_MEM, 1398 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1399 if (!desc) 1400 goto fail; 1401 1402 desc->callback = sci_dma_rx_complete; 1403 desc->callback_param = s; 1404 s->cookie_rx[i] = dmaengine_submit(desc); 1405 if (dma_submit_error(s->cookie_rx[i])) 1406 goto fail; 1407 1408 } 1409 1410 s->active_rx = s->cookie_rx[0]; 1411 1412 dma_async_issue_pending(chan); 1413 return 0; 1414 1415 fail: 1416 /* Switch to PIO */ 1417 if (!port_lock_held) 1418 spin_lock_irqsave(&port->lock, flags); 1419 if (i) 1420 dmaengine_terminate_async(chan); 1421 sci_dma_rx_chan_invalidate(s); 1422 sci_start_rx(port); 1423 if (!port_lock_held) 1424 spin_unlock_irqrestore(&port->lock, flags); 1425 return -EAGAIN; 1426 } 1427 sci_dma_tx_work_fn(struct work_struct * work)1428 static void sci_dma_tx_work_fn(struct work_struct *work) 1429 { 1430 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1431 struct dma_async_tx_descriptor *desc; 1432 struct dma_chan *chan = s->chan_tx; 1433 struct uart_port *port = &s->port; 1434 struct circ_buf *xmit = &port->state->xmit; 1435 unsigned long flags; 1436 dma_addr_t buf; 1437 int head, tail; 1438 1439 /* 1440 * DMA is idle now. 1441 * Port xmit buffer is already mapped, and it is one page... Just adjust 1442 * offsets and lengths. Since it is a circular buffer, we have to 1443 * transmit till the end, and then the rest. Take the port lock to get a 1444 * consistent xmit buffer state. 1445 */ 1446 spin_lock_irq(&port->lock); 1447 head = xmit->head; 1448 tail = xmit->tail; 1449 buf = s->tx_dma_addr + tail; 1450 s->tx_dma_len = CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE); 1451 if (!s->tx_dma_len) { 1452 /* Transmit buffer has been flushed */ 1453 spin_unlock_irq(&port->lock); 1454 return; 1455 } 1456 1457 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1458 DMA_MEM_TO_DEV, 1459 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1460 if (!desc) { 1461 spin_unlock_irq(&port->lock); 1462 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1463 goto switch_to_pio; 1464 } 1465 1466 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1467 DMA_TO_DEVICE); 1468 1469 desc->callback = sci_dma_tx_complete; 1470 desc->callback_param = s; 1471 s->cookie_tx = dmaengine_submit(desc); 1472 if (dma_submit_error(s->cookie_tx)) { 1473 spin_unlock_irq(&port->lock); 1474 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1475 goto switch_to_pio; 1476 } 1477 1478 spin_unlock_irq(&port->lock); 1479 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1480 __func__, xmit->buf, tail, head, s->cookie_tx); 1481 1482 dma_async_issue_pending(chan); 1483 return; 1484 1485 switch_to_pio: 1486 spin_lock_irqsave(&port->lock, flags); 1487 s->chan_tx = NULL; 1488 sci_start_tx(port); 1489 spin_unlock_irqrestore(&port->lock, flags); 1490 return; 1491 } 1492 sci_dma_rx_timer_fn(struct hrtimer * t)1493 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1494 { 1495 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1496 struct dma_chan *chan = s->chan_rx; 1497 struct uart_port *port = &s->port; 1498 struct dma_tx_state state; 1499 enum dma_status status; 1500 unsigned long flags; 1501 unsigned int read; 1502 int active, count; 1503 1504 dev_dbg(port->dev, "DMA Rx timed out\n"); 1505 1506 spin_lock_irqsave(&port->lock, flags); 1507 1508 active = sci_dma_rx_find_active(s); 1509 if (active < 0) { 1510 spin_unlock_irqrestore(&port->lock, flags); 1511 return HRTIMER_NORESTART; 1512 } 1513 1514 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1515 if (status == DMA_COMPLETE) { 1516 spin_unlock_irqrestore(&port->lock, flags); 1517 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1518 s->active_rx, active); 1519 1520 /* Let packet complete handler take care of the packet */ 1521 return HRTIMER_NORESTART; 1522 } 1523 1524 dmaengine_pause(chan); 1525 1526 /* 1527 * sometimes DMA transfer doesn't stop even if it is stopped and 1528 * data keeps on coming until transaction is complete so check 1529 * for DMA_COMPLETE again 1530 * Let packet complete handler take care of the packet 1531 */ 1532 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1533 if (status == DMA_COMPLETE) { 1534 spin_unlock_irqrestore(&port->lock, flags); 1535 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1536 return HRTIMER_NORESTART; 1537 } 1538 1539 /* Handle incomplete DMA receive */ 1540 dmaengine_terminate_async(s->chan_rx); 1541 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1542 1543 if (read) { 1544 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1545 if (count) 1546 tty_flip_buffer_push(&port->state->port); 1547 } 1548 1549 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1550 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1551 sci_dma_rx_submit(s, true); 1552 1553 sci_dma_rx_reenable_irq(s); 1554 1555 spin_unlock_irqrestore(&port->lock, flags); 1556 1557 return HRTIMER_NORESTART; 1558 } 1559 sci_request_dma_chan(struct uart_port * port,enum dma_transfer_direction dir)1560 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1561 enum dma_transfer_direction dir) 1562 { 1563 struct dma_chan *chan; 1564 struct dma_slave_config cfg; 1565 int ret; 1566 1567 chan = dma_request_slave_channel(port->dev, 1568 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1569 if (!chan) { 1570 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); 1571 return NULL; 1572 } 1573 1574 memset(&cfg, 0, sizeof(cfg)); 1575 cfg.direction = dir; 1576 cfg.dst_addr = port->mapbase + 1577 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1578 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1579 cfg.src_addr = port->mapbase + 1580 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1581 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1582 1583 ret = dmaengine_slave_config(chan, &cfg); 1584 if (ret) { 1585 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1586 dma_release_channel(chan); 1587 return NULL; 1588 } 1589 1590 return chan; 1591 } 1592 sci_request_dma(struct uart_port * port)1593 static void sci_request_dma(struct uart_port *port) 1594 { 1595 struct sci_port *s = to_sci_port(port); 1596 struct dma_chan *chan; 1597 1598 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1599 1600 /* 1601 * DMA on console may interfere with Kernel log messages which use 1602 * plain putchar(). So, simply don't use it with a console. 1603 */ 1604 if (uart_console(port)) 1605 return; 1606 1607 if (!port->dev->of_node) 1608 return; 1609 1610 s->cookie_tx = -EINVAL; 1611 1612 /* 1613 * Don't request a dma channel if no channel was specified 1614 * in the device tree. 1615 */ 1616 if (!of_property_present(port->dev->of_node, "dmas")) 1617 return; 1618 1619 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1620 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1621 if (chan) { 1622 /* UART circular tx buffer is an aligned page. */ 1623 s->tx_dma_addr = dma_map_single(chan->device->dev, 1624 port->state->xmit.buf, 1625 UART_XMIT_SIZE, 1626 DMA_TO_DEVICE); 1627 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1628 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1629 dma_release_channel(chan); 1630 } else { 1631 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1632 __func__, UART_XMIT_SIZE, 1633 port->state->xmit.buf, &s->tx_dma_addr); 1634 1635 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1636 s->chan_tx_saved = s->chan_tx = chan; 1637 } 1638 } 1639 1640 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1641 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1642 if (chan) { 1643 unsigned int i; 1644 dma_addr_t dma; 1645 void *buf; 1646 1647 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1648 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1649 &dma, GFP_KERNEL); 1650 if (!buf) { 1651 dev_warn(port->dev, 1652 "Failed to allocate Rx dma buffer, using PIO\n"); 1653 dma_release_channel(chan); 1654 return; 1655 } 1656 1657 for (i = 0; i < 2; i++) { 1658 struct scatterlist *sg = &s->sg_rx[i]; 1659 1660 sg_init_table(sg, 1); 1661 s->rx_buf[i] = buf; 1662 sg_dma_address(sg) = dma; 1663 sg_dma_len(sg) = s->buf_len_rx; 1664 1665 buf += s->buf_len_rx; 1666 dma += s->buf_len_rx; 1667 } 1668 1669 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1670 s->rx_timer.function = sci_dma_rx_timer_fn; 1671 1672 s->chan_rx_saved = s->chan_rx = chan; 1673 1674 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1675 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1676 sci_dma_rx_submit(s, false); 1677 } 1678 } 1679 sci_free_dma(struct uart_port * port)1680 static void sci_free_dma(struct uart_port *port) 1681 { 1682 struct sci_port *s = to_sci_port(port); 1683 1684 if (s->chan_tx_saved) 1685 sci_dma_tx_release(s); 1686 if (s->chan_rx_saved) 1687 sci_dma_rx_release(s); 1688 } 1689 sci_flush_buffer(struct uart_port * port)1690 static void sci_flush_buffer(struct uart_port *port) 1691 { 1692 struct sci_port *s = to_sci_port(port); 1693 1694 /* 1695 * In uart_flush_buffer(), the xmit circular buffer has just been 1696 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1697 * pending transfers 1698 */ 1699 s->tx_dma_len = 0; 1700 if (s->chan_tx) { 1701 dmaengine_terminate_async(s->chan_tx); 1702 s->cookie_tx = -EINVAL; 1703 } 1704 } 1705 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ sci_request_dma(struct uart_port * port)1706 static inline void sci_request_dma(struct uart_port *port) 1707 { 1708 } 1709 sci_free_dma(struct uart_port * port)1710 static inline void sci_free_dma(struct uart_port *port) 1711 { 1712 } 1713 1714 #define sci_flush_buffer NULL 1715 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1716 sci_rx_interrupt(int irq,void * ptr)1717 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1718 { 1719 struct uart_port *port = ptr; 1720 struct sci_port *s = to_sci_port(port); 1721 1722 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1723 if (s->chan_rx) { 1724 u16 scr = serial_port_in(port, SCSCR); 1725 u16 ssr = serial_port_in(port, SCxSR); 1726 1727 /* Disable future Rx interrupts */ 1728 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1729 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1730 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); 1731 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1732 scif_set_rtrg(port, 1); 1733 scr |= SCSCR_RIE; 1734 } else { 1735 scr |= SCSCR_RDRQE; 1736 } 1737 } else { 1738 if (sci_dma_rx_submit(s, false) < 0) 1739 goto handle_pio; 1740 1741 scr &= ~SCSCR_RIE; 1742 } 1743 serial_port_out(port, SCSCR, scr); 1744 /* Clear current interrupt */ 1745 serial_port_out(port, SCxSR, 1746 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1747 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1748 jiffies, s->rx_timeout); 1749 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1750 1751 return IRQ_HANDLED; 1752 } 1753 1754 handle_pio: 1755 #endif 1756 1757 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1758 if (!scif_rtrg_enabled(port)) 1759 scif_set_rtrg(port, s->rx_trigger); 1760 1761 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1762 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1763 } 1764 1765 /* I think sci_receive_chars has to be called irrespective 1766 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1767 * to be disabled? 1768 */ 1769 sci_receive_chars(port); 1770 1771 return IRQ_HANDLED; 1772 } 1773 sci_tx_interrupt(int irq,void * ptr)1774 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1775 { 1776 struct uart_port *port = ptr; 1777 unsigned long flags; 1778 1779 spin_lock_irqsave(&port->lock, flags); 1780 sci_transmit_chars(port); 1781 spin_unlock_irqrestore(&port->lock, flags); 1782 1783 return IRQ_HANDLED; 1784 } 1785 sci_tx_end_interrupt(int irq,void * ptr)1786 static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr) 1787 { 1788 struct uart_port *port = ptr; 1789 unsigned long flags; 1790 unsigned short ctrl; 1791 1792 if (port->type != PORT_SCI) 1793 return sci_tx_interrupt(irq, ptr); 1794 1795 spin_lock_irqsave(&port->lock, flags); 1796 ctrl = serial_port_in(port, SCSCR); 1797 ctrl &= ~(SCSCR_TE | SCSCR_TEIE); 1798 serial_port_out(port, SCSCR, ctrl); 1799 spin_unlock_irqrestore(&port->lock, flags); 1800 1801 return IRQ_HANDLED; 1802 } 1803 sci_br_interrupt(int irq,void * ptr)1804 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1805 { 1806 struct uart_port *port = ptr; 1807 1808 /* Handle BREAKs */ 1809 sci_handle_breaks(port); 1810 1811 /* drop invalid character received before break was detected */ 1812 serial_port_in(port, SCxRDR); 1813 1814 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1815 1816 return IRQ_HANDLED; 1817 } 1818 sci_er_interrupt(int irq,void * ptr)1819 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1820 { 1821 struct uart_port *port = ptr; 1822 struct sci_port *s = to_sci_port(port); 1823 1824 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1825 /* Break and Error interrupts are muxed */ 1826 unsigned short ssr_status = serial_port_in(port, SCxSR); 1827 1828 /* Break Interrupt */ 1829 if (ssr_status & SCxSR_BRK(port)) 1830 sci_br_interrupt(irq, ptr); 1831 1832 /* Break only? */ 1833 if (!(ssr_status & SCxSR_ERRORS(port))) 1834 return IRQ_HANDLED; 1835 } 1836 1837 /* Handle errors */ 1838 if (port->type == PORT_SCI) { 1839 if (sci_handle_errors(port)) { 1840 /* discard character in rx buffer */ 1841 serial_port_in(port, SCxSR); 1842 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1843 } 1844 } else { 1845 sci_handle_fifo_overrun(port); 1846 if (!s->chan_rx) 1847 sci_receive_chars(port); 1848 } 1849 1850 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1851 1852 /* Kick the transmission */ 1853 if (!s->chan_tx) 1854 sci_tx_interrupt(irq, ptr); 1855 1856 return IRQ_HANDLED; 1857 } 1858 sci_mpxed_interrupt(int irq,void * ptr)1859 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1860 { 1861 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1862 struct uart_port *port = ptr; 1863 struct sci_port *s = to_sci_port(port); 1864 irqreturn_t ret = IRQ_NONE; 1865 1866 ssr_status = serial_port_in(port, SCxSR); 1867 scr_status = serial_port_in(port, SCSCR); 1868 if (s->params->overrun_reg == SCxSR) 1869 orer_status = ssr_status; 1870 else if (sci_getreg(port, s->params->overrun_reg)->size) 1871 orer_status = serial_port_in(port, s->params->overrun_reg); 1872 1873 err_enabled = scr_status & port_rx_irq_mask(port); 1874 1875 /* Tx Interrupt */ 1876 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1877 !s->chan_tx) 1878 ret = sci_tx_interrupt(irq, ptr); 1879 1880 /* 1881 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1882 * DR flags 1883 */ 1884 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1885 (scr_status & SCSCR_RIE)) 1886 ret = sci_rx_interrupt(irq, ptr); 1887 1888 /* Error Interrupt */ 1889 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1890 ret = sci_er_interrupt(irq, ptr); 1891 1892 /* Break Interrupt */ 1893 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && 1894 (ssr_status & SCxSR_BRK(port)) && err_enabled) 1895 ret = sci_br_interrupt(irq, ptr); 1896 1897 /* Overrun Interrupt */ 1898 if (orer_status & s->params->overrun_mask) { 1899 sci_handle_fifo_overrun(port); 1900 ret = IRQ_HANDLED; 1901 } 1902 1903 return ret; 1904 } 1905 1906 static const struct sci_irq_desc { 1907 const char *desc; 1908 irq_handler_t handler; 1909 } sci_irq_desc[] = { 1910 /* 1911 * Split out handlers, the default case. 1912 */ 1913 [SCIx_ERI_IRQ] = { 1914 .desc = "rx err", 1915 .handler = sci_er_interrupt, 1916 }, 1917 1918 [SCIx_RXI_IRQ] = { 1919 .desc = "rx full", 1920 .handler = sci_rx_interrupt, 1921 }, 1922 1923 [SCIx_TXI_IRQ] = { 1924 .desc = "tx empty", 1925 .handler = sci_tx_interrupt, 1926 }, 1927 1928 [SCIx_BRI_IRQ] = { 1929 .desc = "break", 1930 .handler = sci_br_interrupt, 1931 }, 1932 1933 [SCIx_DRI_IRQ] = { 1934 .desc = "rx ready", 1935 .handler = sci_rx_interrupt, 1936 }, 1937 1938 [SCIx_TEI_IRQ] = { 1939 .desc = "tx end", 1940 .handler = sci_tx_end_interrupt, 1941 }, 1942 1943 /* 1944 * Special muxed handler. 1945 */ 1946 [SCIx_MUX_IRQ] = { 1947 .desc = "mux", 1948 .handler = sci_mpxed_interrupt, 1949 }, 1950 }; 1951 sci_request_irq(struct sci_port * port)1952 static int sci_request_irq(struct sci_port *port) 1953 { 1954 struct uart_port *up = &port->port; 1955 int i, j, w, ret = 0; 1956 1957 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1958 const struct sci_irq_desc *desc; 1959 int irq; 1960 1961 /* Check if already registered (muxed) */ 1962 for (w = 0; w < i; w++) 1963 if (port->irqs[w] == port->irqs[i]) 1964 w = i + 1; 1965 if (w > i) 1966 continue; 1967 1968 if (SCIx_IRQ_IS_MUXED(port)) { 1969 i = SCIx_MUX_IRQ; 1970 irq = up->irq; 1971 } else { 1972 irq = port->irqs[i]; 1973 1974 /* 1975 * Certain port types won't support all of the 1976 * available interrupt sources. 1977 */ 1978 if (unlikely(irq < 0)) 1979 continue; 1980 } 1981 1982 desc = sci_irq_desc + i; 1983 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1984 dev_name(up->dev), desc->desc); 1985 if (!port->irqstr[j]) { 1986 ret = -ENOMEM; 1987 goto out_nomem; 1988 } 1989 1990 ret = request_irq(irq, desc->handler, up->irqflags, 1991 port->irqstr[j], port); 1992 if (unlikely(ret)) { 1993 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1994 goto out_noirq; 1995 } 1996 } 1997 1998 return 0; 1999 2000 out_noirq: 2001 while (--i >= 0) 2002 free_irq(port->irqs[i], port); 2003 2004 out_nomem: 2005 while (--j >= 0) 2006 kfree(port->irqstr[j]); 2007 2008 return ret; 2009 } 2010 sci_free_irq(struct sci_port * port)2011 static void sci_free_irq(struct sci_port *port) 2012 { 2013 int i, j; 2014 2015 /* 2016 * Intentionally in reverse order so we iterate over the muxed 2017 * IRQ first. 2018 */ 2019 for (i = 0; i < SCIx_NR_IRQS; i++) { 2020 int irq = port->irqs[i]; 2021 2022 /* 2023 * Certain port types won't support all of the available 2024 * interrupt sources. 2025 */ 2026 if (unlikely(irq < 0)) 2027 continue; 2028 2029 /* Check if already freed (irq was muxed) */ 2030 for (j = 0; j < i; j++) 2031 if (port->irqs[j] == irq) 2032 j = i + 1; 2033 if (j > i) 2034 continue; 2035 2036 free_irq(port->irqs[i], port); 2037 kfree(port->irqstr[i]); 2038 2039 if (SCIx_IRQ_IS_MUXED(port)) { 2040 /* If there's only one IRQ, we're done. */ 2041 return; 2042 } 2043 } 2044 } 2045 sci_tx_empty(struct uart_port * port)2046 static unsigned int sci_tx_empty(struct uart_port *port) 2047 { 2048 unsigned short status = serial_port_in(port, SCxSR); 2049 unsigned short in_tx_fifo = sci_txfill(port); 2050 2051 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 2052 } 2053 sci_set_rts(struct uart_port * port,bool state)2054 static void sci_set_rts(struct uart_port *port, bool state) 2055 { 2056 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2057 u16 data = serial_port_in(port, SCPDR); 2058 2059 /* Active low */ 2060 if (state) 2061 data &= ~SCPDR_RTSD; 2062 else 2063 data |= SCPDR_RTSD; 2064 serial_port_out(port, SCPDR, data); 2065 2066 /* RTS# is output */ 2067 serial_port_out(port, SCPCR, 2068 serial_port_in(port, SCPCR) | SCPCR_RTSC); 2069 } else if (sci_getreg(port, SCSPTR)->size) { 2070 u16 ctrl = serial_port_in(port, SCSPTR); 2071 2072 /* Active low */ 2073 if (state) 2074 ctrl &= ~SCSPTR_RTSDT; 2075 else 2076 ctrl |= SCSPTR_RTSDT; 2077 serial_port_out(port, SCSPTR, ctrl); 2078 } 2079 } 2080 sci_get_cts(struct uart_port * port)2081 static bool sci_get_cts(struct uart_port *port) 2082 { 2083 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2084 /* Active low */ 2085 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 2086 } else if (sci_getreg(port, SCSPTR)->size) { 2087 /* Active low */ 2088 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 2089 } 2090 2091 return true; 2092 } 2093 2094 /* 2095 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2096 * CTS/RTS is supported in hardware by at least one port and controlled 2097 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2098 * handled via the ->init_pins() op, which is a bit of a one-way street, 2099 * lacking any ability to defer pin control -- this will later be 2100 * converted over to the GPIO framework). 2101 * 2102 * Other modes (such as loopback) are supported generically on certain 2103 * port types, but not others. For these it's sufficient to test for the 2104 * existence of the support register and simply ignore the port type. 2105 */ sci_set_mctrl(struct uart_port * port,unsigned int mctrl)2106 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2107 { 2108 struct sci_port *s = to_sci_port(port); 2109 2110 if (mctrl & TIOCM_LOOP) { 2111 const struct plat_sci_reg *reg; 2112 2113 /* 2114 * Standard loopback mode for SCFCR ports. 2115 */ 2116 reg = sci_getreg(port, SCFCR); 2117 if (reg->size) 2118 serial_port_out(port, SCFCR, 2119 serial_port_in(port, SCFCR) | 2120 SCFCR_LOOP); 2121 } 2122 2123 mctrl_gpio_set(s->gpios, mctrl); 2124 2125 if (!s->has_rtscts) 2126 return; 2127 2128 if (!(mctrl & TIOCM_RTS)) { 2129 /* Disable Auto RTS */ 2130 serial_port_out(port, SCFCR, 2131 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 2132 2133 /* Clear RTS */ 2134 sci_set_rts(port, 0); 2135 } else if (s->autorts) { 2136 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2137 /* Enable RTS# pin function */ 2138 serial_port_out(port, SCPCR, 2139 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 2140 } 2141 2142 /* Enable Auto RTS */ 2143 serial_port_out(port, SCFCR, 2144 serial_port_in(port, SCFCR) | SCFCR_MCE); 2145 } else { 2146 /* Set RTS */ 2147 sci_set_rts(port, 1); 2148 } 2149 } 2150 sci_get_mctrl(struct uart_port * port)2151 static unsigned int sci_get_mctrl(struct uart_port *port) 2152 { 2153 struct sci_port *s = to_sci_port(port); 2154 struct mctrl_gpios *gpios = s->gpios; 2155 unsigned int mctrl = 0; 2156 2157 mctrl_gpio_get(gpios, &mctrl); 2158 2159 /* 2160 * CTS/RTS is handled in hardware when supported, while nothing 2161 * else is wired up. 2162 */ 2163 if (s->autorts) { 2164 if (sci_get_cts(port)) 2165 mctrl |= TIOCM_CTS; 2166 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2167 mctrl |= TIOCM_CTS; 2168 } 2169 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2170 mctrl |= TIOCM_DSR; 2171 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2172 mctrl |= TIOCM_CAR; 2173 2174 return mctrl; 2175 } 2176 sci_enable_ms(struct uart_port * port)2177 static void sci_enable_ms(struct uart_port *port) 2178 { 2179 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2180 } 2181 sci_break_ctl(struct uart_port * port,int break_state)2182 static void sci_break_ctl(struct uart_port *port, int break_state) 2183 { 2184 unsigned short scscr, scsptr; 2185 unsigned long flags; 2186 2187 /* check whether the port has SCSPTR */ 2188 if (!sci_getreg(port, SCSPTR)->size) { 2189 /* 2190 * Not supported by hardware. Most parts couple break and rx 2191 * interrupts together, with break detection always enabled. 2192 */ 2193 return; 2194 } 2195 2196 spin_lock_irqsave(&port->lock, flags); 2197 scsptr = serial_port_in(port, SCSPTR); 2198 scscr = serial_port_in(port, SCSCR); 2199 2200 if (break_state == -1) { 2201 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2202 scscr &= ~SCSCR_TE; 2203 } else { 2204 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2205 scscr |= SCSCR_TE; 2206 } 2207 2208 serial_port_out(port, SCSPTR, scsptr); 2209 serial_port_out(port, SCSCR, scscr); 2210 spin_unlock_irqrestore(&port->lock, flags); 2211 } 2212 sci_startup(struct uart_port * port)2213 static int sci_startup(struct uart_port *port) 2214 { 2215 struct sci_port *s = to_sci_port(port); 2216 int ret; 2217 2218 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2219 2220 sci_request_dma(port); 2221 2222 ret = sci_request_irq(s); 2223 if (unlikely(ret < 0)) { 2224 sci_free_dma(port); 2225 return ret; 2226 } 2227 2228 return 0; 2229 } 2230 sci_shutdown(struct uart_port * port)2231 static void sci_shutdown(struct uart_port *port) 2232 { 2233 struct sci_port *s = to_sci_port(port); 2234 unsigned long flags; 2235 u16 scr; 2236 2237 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2238 2239 s->autorts = false; 2240 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2241 2242 spin_lock_irqsave(&port->lock, flags); 2243 sci_stop_rx(port); 2244 sci_stop_tx(port); 2245 /* 2246 * Stop RX and TX, disable related interrupts, keep clock source 2247 * and HSCIF TOT bits 2248 */ 2249 scr = serial_port_in(port, SCSCR); 2250 serial_port_out(port, SCSCR, scr & 2251 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2252 spin_unlock_irqrestore(&port->lock, flags); 2253 2254 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2255 if (s->chan_rx_saved) { 2256 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2257 port->line); 2258 hrtimer_cancel(&s->rx_timer); 2259 } 2260 #endif 2261 2262 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2263 del_timer_sync(&s->rx_fifo_timer); 2264 sci_free_irq(s); 2265 sci_free_dma(port); 2266 } 2267 sci_sck_calc(struct sci_port * s,unsigned int bps,unsigned int * srr)2268 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2269 unsigned int *srr) 2270 { 2271 unsigned long freq = s->clk_rates[SCI_SCK]; 2272 int err, min_err = INT_MAX; 2273 unsigned int sr; 2274 2275 if (s->port.type != PORT_HSCIF) 2276 freq *= 2; 2277 2278 for_each_sr(sr, s) { 2279 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2280 if (abs(err) >= abs(min_err)) 2281 continue; 2282 2283 min_err = err; 2284 *srr = sr - 1; 2285 2286 if (!err) 2287 break; 2288 } 2289 2290 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2291 *srr + 1); 2292 return min_err; 2293 } 2294 sci_brg_calc(struct sci_port * s,unsigned int bps,unsigned long freq,unsigned int * dlr,unsigned int * srr)2295 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2296 unsigned long freq, unsigned int *dlr, 2297 unsigned int *srr) 2298 { 2299 int err, min_err = INT_MAX; 2300 unsigned int sr, dl; 2301 2302 if (s->port.type != PORT_HSCIF) 2303 freq *= 2; 2304 2305 for_each_sr(sr, s) { 2306 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2307 dl = clamp(dl, 1U, 65535U); 2308 2309 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2310 if (abs(err) >= abs(min_err)) 2311 continue; 2312 2313 min_err = err; 2314 *dlr = dl; 2315 *srr = sr - 1; 2316 2317 if (!err) 2318 break; 2319 } 2320 2321 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2322 min_err, *dlr, *srr + 1); 2323 return min_err; 2324 } 2325 2326 /* calculate sample rate, BRR, and clock select */ sci_scbrr_calc(struct sci_port * s,unsigned int bps,unsigned int * brr,unsigned int * srr,unsigned int * cks)2327 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2328 unsigned int *brr, unsigned int *srr, 2329 unsigned int *cks) 2330 { 2331 unsigned long freq = s->clk_rates[SCI_FCK]; 2332 unsigned int sr, br, prediv, scrate, c; 2333 int err, min_err = INT_MAX; 2334 2335 if (s->port.type != PORT_HSCIF) 2336 freq *= 2; 2337 2338 /* 2339 * Find the combination of sample rate and clock select with the 2340 * smallest deviation from the desired baud rate. 2341 * Prefer high sample rates to maximise the receive margin. 2342 * 2343 * M: Receive margin (%) 2344 * N: Ratio of bit rate to clock (N = sampling rate) 2345 * D: Clock duty (D = 0 to 1.0) 2346 * L: Frame length (L = 9 to 12) 2347 * F: Absolute value of clock frequency deviation 2348 * 2349 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2350 * (|D - 0.5| / N * (1 + F))| 2351 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2352 */ 2353 for_each_sr(sr, s) { 2354 for (c = 0; c <= 3; c++) { 2355 /* integerized formulas from HSCIF documentation */ 2356 prediv = sr << (2 * c + 1); 2357 2358 /* 2359 * We need to calculate: 2360 * 2361 * br = freq / (prediv * bps) clamped to [1..256] 2362 * err = freq / (br * prediv) - bps 2363 * 2364 * Watch out for overflow when calculating the desired 2365 * sampling clock rate! 2366 */ 2367 if (bps > UINT_MAX / prediv) 2368 break; 2369 2370 scrate = prediv * bps; 2371 br = DIV_ROUND_CLOSEST(freq, scrate); 2372 br = clamp(br, 1U, 256U); 2373 2374 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2375 if (abs(err) >= abs(min_err)) 2376 continue; 2377 2378 min_err = err; 2379 *brr = br - 1; 2380 *srr = sr - 1; 2381 *cks = c; 2382 2383 if (!err) 2384 goto found; 2385 } 2386 } 2387 2388 found: 2389 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2390 min_err, *brr, *srr + 1, *cks); 2391 return min_err; 2392 } 2393 sci_reset(struct uart_port * port)2394 static void sci_reset(struct uart_port *port) 2395 { 2396 const struct plat_sci_reg *reg; 2397 unsigned int status; 2398 struct sci_port *s = to_sci_port(port); 2399 2400 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2401 2402 reg = sci_getreg(port, SCFCR); 2403 if (reg->size) 2404 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2405 2406 sci_clear_SCxSR(port, 2407 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2408 SCxSR_BREAK_CLEAR(port)); 2409 if (sci_getreg(port, SCLSR)->size) { 2410 status = serial_port_in(port, SCLSR); 2411 status &= ~(SCLSR_TO | SCLSR_ORER); 2412 serial_port_out(port, SCLSR, status); 2413 } 2414 2415 if (s->rx_trigger > 1) { 2416 if (s->rx_fifo_timeout) { 2417 scif_set_rtrg(port, 1); 2418 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2419 } else { 2420 if (port->type == PORT_SCIFA || 2421 port->type == PORT_SCIFB) 2422 scif_set_rtrg(port, 1); 2423 else 2424 scif_set_rtrg(port, s->rx_trigger); 2425 } 2426 } 2427 } 2428 sci_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)2429 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2430 const struct ktermios *old) 2431 { 2432 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2433 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2434 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2435 struct sci_port *s = to_sci_port(port); 2436 const struct plat_sci_reg *reg; 2437 int min_err = INT_MAX, err; 2438 unsigned long max_freq = 0; 2439 int best_clk = -1; 2440 unsigned long flags; 2441 2442 if ((termios->c_cflag & CSIZE) == CS7) { 2443 smr_val |= SCSMR_CHR; 2444 } else { 2445 termios->c_cflag &= ~CSIZE; 2446 termios->c_cflag |= CS8; 2447 } 2448 if (termios->c_cflag & PARENB) 2449 smr_val |= SCSMR_PE; 2450 if (termios->c_cflag & PARODD) 2451 smr_val |= SCSMR_PE | SCSMR_ODD; 2452 if (termios->c_cflag & CSTOPB) 2453 smr_val |= SCSMR_STOP; 2454 2455 /* 2456 * earlyprintk comes here early on with port->uartclk set to zero. 2457 * the clock framework is not up and running at this point so here 2458 * we assume that 115200 is the maximum baud rate. please note that 2459 * the baud rate is not programmed during earlyprintk - it is assumed 2460 * that the previous boot loader has enabled required clocks and 2461 * setup the baud rate generator hardware for us already. 2462 */ 2463 if (!port->uartclk) { 2464 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2465 goto done; 2466 } 2467 2468 for (i = 0; i < SCI_NUM_CLKS; i++) 2469 max_freq = max(max_freq, s->clk_rates[i]); 2470 2471 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2472 if (!baud) 2473 goto done; 2474 2475 /* 2476 * There can be multiple sources for the sampling clock. Find the one 2477 * that gives us the smallest deviation from the desired baud rate. 2478 */ 2479 2480 /* Optional Undivided External Clock */ 2481 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2482 port->type != PORT_SCIFB) { 2483 err = sci_sck_calc(s, baud, &srr1); 2484 if (abs(err) < abs(min_err)) { 2485 best_clk = SCI_SCK; 2486 scr_val = SCSCR_CKE1; 2487 sccks = SCCKS_CKS; 2488 min_err = err; 2489 srr = srr1; 2490 if (!err) 2491 goto done; 2492 } 2493 } 2494 2495 /* Optional BRG Frequency Divided External Clock */ 2496 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2497 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2498 &srr1); 2499 if (abs(err) < abs(min_err)) { 2500 best_clk = SCI_SCIF_CLK; 2501 scr_val = SCSCR_CKE1; 2502 sccks = 0; 2503 min_err = err; 2504 dl = dl1; 2505 srr = srr1; 2506 if (!err) 2507 goto done; 2508 } 2509 } 2510 2511 /* Optional BRG Frequency Divided Internal Clock */ 2512 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2513 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2514 &srr1); 2515 if (abs(err) < abs(min_err)) { 2516 best_clk = SCI_BRG_INT; 2517 scr_val = SCSCR_CKE1; 2518 sccks = SCCKS_XIN; 2519 min_err = err; 2520 dl = dl1; 2521 srr = srr1; 2522 if (!min_err) 2523 goto done; 2524 } 2525 } 2526 2527 /* Divided Functional Clock using standard Bit Rate Register */ 2528 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2529 if (abs(err) < abs(min_err)) { 2530 best_clk = SCI_FCK; 2531 scr_val = 0; 2532 min_err = err; 2533 brr = brr1; 2534 srr = srr1; 2535 cks = cks1; 2536 } 2537 2538 done: 2539 if (best_clk >= 0) 2540 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2541 s->clks[best_clk], baud, min_err); 2542 2543 sci_port_enable(s); 2544 2545 /* 2546 * Program the optional External Baud Rate Generator (BRG) first. 2547 * It controls the mux to select (H)SCK or frequency divided clock. 2548 */ 2549 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2550 serial_port_out(port, SCDL, dl); 2551 serial_port_out(port, SCCKS, sccks); 2552 } 2553 2554 spin_lock_irqsave(&port->lock, flags); 2555 2556 sci_reset(port); 2557 2558 uart_update_timeout(port, termios->c_cflag, baud); 2559 2560 /* byte size and parity */ 2561 bits = tty_get_frame_size(termios->c_cflag); 2562 2563 if (sci_getreg(port, SEMR)->size) 2564 serial_port_out(port, SEMR, 0); 2565 2566 if (best_clk >= 0) { 2567 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2568 switch (srr + 1) { 2569 case 5: smr_val |= SCSMR_SRC_5; break; 2570 case 7: smr_val |= SCSMR_SRC_7; break; 2571 case 11: smr_val |= SCSMR_SRC_11; break; 2572 case 13: smr_val |= SCSMR_SRC_13; break; 2573 case 16: smr_val |= SCSMR_SRC_16; break; 2574 case 17: smr_val |= SCSMR_SRC_17; break; 2575 case 19: smr_val |= SCSMR_SRC_19; break; 2576 case 27: smr_val |= SCSMR_SRC_27; break; 2577 } 2578 smr_val |= cks; 2579 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2580 serial_port_out(port, SCSMR, smr_val); 2581 serial_port_out(port, SCBRR, brr); 2582 if (sci_getreg(port, HSSRR)->size) { 2583 unsigned int hssrr = srr | HSCIF_SRE; 2584 /* Calculate deviation from intended rate at the 2585 * center of the last stop bit in sampling clocks. 2586 */ 2587 int last_stop = bits * 2 - 1; 2588 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2589 (int)(srr + 1), 2590 2 * (int)baud); 2591 2592 if (abs(deviation) >= 2) { 2593 /* At least two sampling clocks off at the 2594 * last stop bit; we can increase the error 2595 * margin by shifting the sampling point. 2596 */ 2597 int shift = clamp(deviation / 2, -8, 7); 2598 2599 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2600 HSCIF_SRHP_MASK; 2601 hssrr |= HSCIF_SRDE; 2602 } 2603 serial_port_out(port, HSSRR, hssrr); 2604 } 2605 2606 /* Wait one bit interval */ 2607 udelay((1000000 + (baud - 1)) / baud); 2608 } else { 2609 /* Don't touch the bit rate configuration */ 2610 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2611 smr_val |= serial_port_in(port, SCSMR) & 2612 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2613 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2614 serial_port_out(port, SCSMR, smr_val); 2615 } 2616 2617 sci_init_pins(port, termios->c_cflag); 2618 2619 port->status &= ~UPSTAT_AUTOCTS; 2620 s->autorts = false; 2621 reg = sci_getreg(port, SCFCR); 2622 if (reg->size) { 2623 unsigned short ctrl = serial_port_in(port, SCFCR); 2624 2625 if ((port->flags & UPF_HARD_FLOW) && 2626 (termios->c_cflag & CRTSCTS)) { 2627 /* There is no CTS interrupt to restart the hardware */ 2628 port->status |= UPSTAT_AUTOCTS; 2629 /* MCE is enabled when RTS is raised */ 2630 s->autorts = true; 2631 } 2632 2633 /* 2634 * As we've done a sci_reset() above, ensure we don't 2635 * interfere with the FIFOs while toggling MCE. As the 2636 * reset values could still be set, simply mask them out. 2637 */ 2638 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2639 2640 serial_port_out(port, SCFCR, ctrl); 2641 } 2642 if (port->flags & UPF_HARD_FLOW) { 2643 /* Refresh (Auto) RTS */ 2644 sci_set_mctrl(port, port->mctrl); 2645 } 2646 2647 /* 2648 * For SCI, TE (transmit enable) must be set after setting TIE 2649 * (transmit interrupt enable) or in the same instruction to 2650 * start the transmitting process. So skip setting TE here for SCI. 2651 */ 2652 if (port->type != PORT_SCI) 2653 scr_val |= SCSCR_TE; 2654 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2655 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2656 if ((srr + 1 == 5) && 2657 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2658 /* 2659 * In asynchronous mode, when the sampling rate is 1/5, first 2660 * received data may become invalid on some SCIFA and SCIFB. 2661 * To avoid this problem wait more than 1 serial data time (1 2662 * bit time x serial data number) after setting SCSCR.RE = 1. 2663 */ 2664 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2665 } 2666 2667 /* Calculate delay for 2 DMA buffers (4 FIFO). */ 2668 s->rx_frame = (10000 * bits) / (baud / 100); 2669 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2670 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2671 #endif 2672 2673 if ((termios->c_cflag & CREAD) != 0) 2674 sci_start_rx(port); 2675 2676 spin_unlock_irqrestore(&port->lock, flags); 2677 2678 sci_port_disable(s); 2679 2680 if (UART_ENABLE_MS(port, termios->c_cflag)) 2681 sci_enable_ms(port); 2682 } 2683 sci_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2684 static void sci_pm(struct uart_port *port, unsigned int state, 2685 unsigned int oldstate) 2686 { 2687 struct sci_port *sci_port = to_sci_port(port); 2688 2689 switch (state) { 2690 case UART_PM_STATE_OFF: 2691 sci_port_disable(sci_port); 2692 break; 2693 default: 2694 sci_port_enable(sci_port); 2695 break; 2696 } 2697 } 2698 sci_type(struct uart_port * port)2699 static const char *sci_type(struct uart_port *port) 2700 { 2701 switch (port->type) { 2702 case PORT_IRDA: 2703 return "irda"; 2704 case PORT_SCI: 2705 return "sci"; 2706 case PORT_SCIF: 2707 return "scif"; 2708 case PORT_SCIFA: 2709 return "scifa"; 2710 case PORT_SCIFB: 2711 return "scifb"; 2712 case PORT_HSCIF: 2713 return "hscif"; 2714 } 2715 2716 return NULL; 2717 } 2718 sci_remap_port(struct uart_port * port)2719 static int sci_remap_port(struct uart_port *port) 2720 { 2721 struct sci_port *sport = to_sci_port(port); 2722 2723 /* 2724 * Nothing to do if there's already an established membase. 2725 */ 2726 if (port->membase) 2727 return 0; 2728 2729 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2730 port->membase = ioremap(port->mapbase, sport->reg_size); 2731 if (unlikely(!port->membase)) { 2732 dev_err(port->dev, "can't remap port#%d\n", port->line); 2733 return -ENXIO; 2734 } 2735 } else { 2736 /* 2737 * For the simple (and majority of) cases where we don't 2738 * need to do any remapping, just cast the cookie 2739 * directly. 2740 */ 2741 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2742 } 2743 2744 return 0; 2745 } 2746 sci_release_port(struct uart_port * port)2747 static void sci_release_port(struct uart_port *port) 2748 { 2749 struct sci_port *sport = to_sci_port(port); 2750 2751 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2752 iounmap(port->membase); 2753 port->membase = NULL; 2754 } 2755 2756 release_mem_region(port->mapbase, sport->reg_size); 2757 } 2758 sci_request_port(struct uart_port * port)2759 static int sci_request_port(struct uart_port *port) 2760 { 2761 struct resource *res; 2762 struct sci_port *sport = to_sci_port(port); 2763 int ret; 2764 2765 res = request_mem_region(port->mapbase, sport->reg_size, 2766 dev_name(port->dev)); 2767 if (unlikely(res == NULL)) { 2768 dev_err(port->dev, "request_mem_region failed."); 2769 return -EBUSY; 2770 } 2771 2772 ret = sci_remap_port(port); 2773 if (unlikely(ret != 0)) { 2774 release_resource(res); 2775 return ret; 2776 } 2777 2778 return 0; 2779 } 2780 sci_config_port(struct uart_port * port,int flags)2781 static void sci_config_port(struct uart_port *port, int flags) 2782 { 2783 if (flags & UART_CONFIG_TYPE) { 2784 struct sci_port *sport = to_sci_port(port); 2785 2786 port->type = sport->cfg->type; 2787 sci_request_port(port); 2788 } 2789 } 2790 sci_verify_port(struct uart_port * port,struct serial_struct * ser)2791 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2792 { 2793 if (ser->baud_base < 2400) 2794 /* No paper tape reader for Mitch.. */ 2795 return -EINVAL; 2796 2797 return 0; 2798 } 2799 2800 static const struct uart_ops sci_uart_ops = { 2801 .tx_empty = sci_tx_empty, 2802 .set_mctrl = sci_set_mctrl, 2803 .get_mctrl = sci_get_mctrl, 2804 .start_tx = sci_start_tx, 2805 .stop_tx = sci_stop_tx, 2806 .stop_rx = sci_stop_rx, 2807 .enable_ms = sci_enable_ms, 2808 .break_ctl = sci_break_ctl, 2809 .startup = sci_startup, 2810 .shutdown = sci_shutdown, 2811 .flush_buffer = sci_flush_buffer, 2812 .set_termios = sci_set_termios, 2813 .pm = sci_pm, 2814 .type = sci_type, 2815 .release_port = sci_release_port, 2816 .request_port = sci_request_port, 2817 .config_port = sci_config_port, 2818 .verify_port = sci_verify_port, 2819 #ifdef CONFIG_CONSOLE_POLL 2820 .poll_get_char = sci_poll_get_char, 2821 .poll_put_char = sci_poll_put_char, 2822 #endif 2823 }; 2824 sci_init_clocks(struct sci_port * sci_port,struct device * dev)2825 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2826 { 2827 const char *clk_names[] = { 2828 [SCI_FCK] = "fck", 2829 [SCI_SCK] = "sck", 2830 [SCI_BRG_INT] = "brg_int", 2831 [SCI_SCIF_CLK] = "scif_clk", 2832 }; 2833 struct clk *clk; 2834 unsigned int i; 2835 2836 if (sci_port->cfg->type == PORT_HSCIF) 2837 clk_names[SCI_SCK] = "hsck"; 2838 2839 for (i = 0; i < SCI_NUM_CLKS; i++) { 2840 clk = devm_clk_get_optional(dev, clk_names[i]); 2841 if (IS_ERR(clk)) 2842 return PTR_ERR(clk); 2843 2844 if (!clk && i == SCI_FCK) { 2845 /* 2846 * Not all SH platforms declare a clock lookup entry 2847 * for SCI devices, in which case we need to get the 2848 * global "peripheral_clk" clock. 2849 */ 2850 clk = devm_clk_get(dev, "peripheral_clk"); 2851 if (IS_ERR(clk)) 2852 return dev_err_probe(dev, PTR_ERR(clk), 2853 "failed to get %s\n", 2854 clk_names[i]); 2855 } 2856 2857 if (!clk) 2858 dev_dbg(dev, "failed to get %s\n", clk_names[i]); 2859 else 2860 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2861 clk, clk_get_rate(clk)); 2862 sci_port->clks[i] = clk; 2863 } 2864 return 0; 2865 } 2866 2867 static const struct sci_port_params * sci_probe_regmap(const struct plat_sci_port * cfg)2868 sci_probe_regmap(const struct plat_sci_port *cfg) 2869 { 2870 unsigned int regtype; 2871 2872 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2873 return &sci_port_params[cfg->regtype]; 2874 2875 switch (cfg->type) { 2876 case PORT_SCI: 2877 regtype = SCIx_SCI_REGTYPE; 2878 break; 2879 case PORT_IRDA: 2880 regtype = SCIx_IRDA_REGTYPE; 2881 break; 2882 case PORT_SCIFA: 2883 regtype = SCIx_SCIFA_REGTYPE; 2884 break; 2885 case PORT_SCIFB: 2886 regtype = SCIx_SCIFB_REGTYPE; 2887 break; 2888 case PORT_SCIF: 2889 /* 2890 * The SH-4 is a bit of a misnomer here, although that's 2891 * where this particular port layout originated. This 2892 * configuration (or some slight variation thereof) 2893 * remains the dominant model for all SCIFs. 2894 */ 2895 regtype = SCIx_SH4_SCIF_REGTYPE; 2896 break; 2897 case PORT_HSCIF: 2898 regtype = SCIx_HSCIF_REGTYPE; 2899 break; 2900 default: 2901 pr_err("Can't probe register map for given port\n"); 2902 return NULL; 2903 } 2904 2905 return &sci_port_params[regtype]; 2906 } 2907 sci_init_single(struct platform_device * dev,struct sci_port * sci_port,unsigned int index,const struct plat_sci_port * p,bool early)2908 static int sci_init_single(struct platform_device *dev, 2909 struct sci_port *sci_port, unsigned int index, 2910 const struct plat_sci_port *p, bool early) 2911 { 2912 struct uart_port *port = &sci_port->port; 2913 const struct resource *res; 2914 unsigned int i; 2915 int ret; 2916 2917 sci_port->cfg = p; 2918 2919 port->ops = &sci_uart_ops; 2920 port->iotype = UPIO_MEM; 2921 port->line = index; 2922 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); 2923 2924 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2925 if (res == NULL) 2926 return -ENOMEM; 2927 2928 port->mapbase = res->start; 2929 sci_port->reg_size = resource_size(res); 2930 2931 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 2932 if (i) 2933 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 2934 else 2935 sci_port->irqs[i] = platform_get_irq(dev, i); 2936 } 2937 2938 /* 2939 * The fourth interrupt on SCI port is transmit end interrupt, so 2940 * shuffle the interrupts. 2941 */ 2942 if (p->type == PORT_SCI) 2943 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); 2944 2945 /* The SCI generates several interrupts. They can be muxed together or 2946 * connected to different interrupt lines. In the muxed case only one 2947 * interrupt resource is specified as there is only one interrupt ID. 2948 * In the non-muxed case, up to 6 interrupt signals might be generated 2949 * from the SCI, however those signals might have their own individual 2950 * interrupt ID numbers, or muxed together with another interrupt. 2951 */ 2952 if (sci_port->irqs[0] < 0) 2953 return -ENXIO; 2954 2955 if (sci_port->irqs[1] < 0) 2956 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2957 sci_port->irqs[i] = sci_port->irqs[0]; 2958 2959 sci_port->params = sci_probe_regmap(p); 2960 if (unlikely(sci_port->params == NULL)) 2961 return -EINVAL; 2962 2963 switch (p->type) { 2964 case PORT_SCIFB: 2965 sci_port->rx_trigger = 48; 2966 break; 2967 case PORT_HSCIF: 2968 sci_port->rx_trigger = 64; 2969 break; 2970 case PORT_SCIFA: 2971 sci_port->rx_trigger = 32; 2972 break; 2973 case PORT_SCIF: 2974 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2975 /* RX triggering not implemented for this IP */ 2976 sci_port->rx_trigger = 1; 2977 else 2978 sci_port->rx_trigger = 8; 2979 break; 2980 default: 2981 sci_port->rx_trigger = 1; 2982 break; 2983 } 2984 2985 sci_port->rx_fifo_timeout = 0; 2986 sci_port->hscif_tot = 0; 2987 2988 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2989 * match the SoC datasheet, this should be investigated. Let platform 2990 * data override the sampling rate for now. 2991 */ 2992 sci_port->sampling_rate_mask = p->sampling_rate 2993 ? SCI_SR(p->sampling_rate) 2994 : sci_port->params->sampling_rate_mask; 2995 2996 if (!early) { 2997 ret = sci_init_clocks(sci_port, &dev->dev); 2998 if (ret < 0) 2999 return ret; 3000 3001 port->dev = &dev->dev; 3002 3003 pm_runtime_enable(&dev->dev); 3004 } 3005 3006 port->type = p->type; 3007 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 3008 port->fifosize = sci_port->params->fifosize; 3009 3010 if (port->type == PORT_SCI && !dev->dev.of_node) { 3011 if (sci_port->reg_size >= 0x20) 3012 port->regshift = 2; 3013 else 3014 port->regshift = 1; 3015 } 3016 3017 /* 3018 * The UART port needs an IRQ value, so we peg this to the RX IRQ 3019 * for the multi-IRQ ports, which is where we are primarily 3020 * concerned with the shutdown path synchronization. 3021 * 3022 * For the muxed case there's nothing more to do. 3023 */ 3024 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 3025 port->irqflags = 0; 3026 3027 port->serial_in = sci_serial_in; 3028 port->serial_out = sci_serial_out; 3029 3030 return 0; 3031 } 3032 sci_cleanup_single(struct sci_port * port)3033 static void sci_cleanup_single(struct sci_port *port) 3034 { 3035 pm_runtime_disable(port->port.dev); 3036 } 3037 3038 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 3039 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) serial_console_putchar(struct uart_port * port,unsigned char ch)3040 static void serial_console_putchar(struct uart_port *port, unsigned char ch) 3041 { 3042 sci_poll_put_char(port, ch); 3043 } 3044 3045 /* 3046 * Print a string to the serial port trying not to disturb 3047 * any possible real use of the port... 3048 */ serial_console_write(struct console * co,const char * s,unsigned count)3049 static void serial_console_write(struct console *co, const char *s, 3050 unsigned count) 3051 { 3052 struct sci_port *sci_port = &sci_ports[co->index]; 3053 struct uart_port *port = &sci_port->port; 3054 unsigned short bits, ctrl, ctrl_temp; 3055 unsigned long flags; 3056 int locked = 1; 3057 3058 if (port->sysrq) 3059 locked = 0; 3060 else if (oops_in_progress) 3061 locked = spin_trylock_irqsave(&port->lock, flags); 3062 else 3063 spin_lock_irqsave(&port->lock, flags); 3064 3065 /* first save SCSCR then disable interrupts, keep clock source */ 3066 ctrl = serial_port_in(port, SCSCR); 3067 ctrl_temp = SCSCR_RE | SCSCR_TE | 3068 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3069 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3070 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3071 3072 uart_console_write(port, s, count, serial_console_putchar); 3073 3074 /* wait until fifo is empty and last bit has been transmitted */ 3075 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3076 while ((serial_port_in(port, SCxSR) & bits) != bits) 3077 cpu_relax(); 3078 3079 /* restore the SCSCR */ 3080 serial_port_out(port, SCSCR, ctrl); 3081 3082 if (locked) 3083 spin_unlock_irqrestore(&port->lock, flags); 3084 } 3085 serial_console_setup(struct console * co,char * options)3086 static int serial_console_setup(struct console *co, char *options) 3087 { 3088 struct sci_port *sci_port; 3089 struct uart_port *port; 3090 int baud = 115200; 3091 int bits = 8; 3092 int parity = 'n'; 3093 int flow = 'n'; 3094 int ret; 3095 3096 /* 3097 * Refuse to handle any bogus ports. 3098 */ 3099 if (co->index < 0 || co->index >= SCI_NPORTS) 3100 return -ENODEV; 3101 3102 sci_port = &sci_ports[co->index]; 3103 port = &sci_port->port; 3104 3105 /* 3106 * Refuse to handle uninitialized ports. 3107 */ 3108 if (!port->ops) 3109 return -ENODEV; 3110 3111 ret = sci_remap_port(port); 3112 if (unlikely(ret != 0)) 3113 return ret; 3114 3115 if (options) 3116 uart_parse_options(options, &baud, &parity, &bits, &flow); 3117 3118 return uart_set_options(port, co, baud, parity, bits, flow); 3119 } 3120 3121 static struct console serial_console = { 3122 .name = "ttySC", 3123 .device = uart_console_device, 3124 .write = serial_console_write, 3125 .setup = serial_console_setup, 3126 .flags = CON_PRINTBUFFER, 3127 .index = -1, 3128 .data = &sci_uart_driver, 3129 }; 3130 3131 #ifdef CONFIG_SUPERH 3132 static char early_serial_buf[32]; 3133 early_serial_console_setup(struct console * co,char * options)3134 static int early_serial_console_setup(struct console *co, char *options) 3135 { 3136 /* 3137 * This early console is always registered using the earlyprintk= 3138 * parameter, which does not call add_preferred_console(). Thus 3139 * @options is always NULL and the options for this early console 3140 * are passed using a custom buffer. 3141 */ 3142 WARN_ON(options); 3143 3144 return serial_console_setup(co, early_serial_buf); 3145 } 3146 3147 static struct console early_serial_console = { 3148 .name = "early_ttySC", 3149 .write = serial_console_write, 3150 .setup = early_serial_console_setup, 3151 .flags = CON_PRINTBUFFER, 3152 .index = -1, 3153 }; 3154 sci_probe_earlyprintk(struct platform_device * pdev)3155 static int sci_probe_earlyprintk(struct platform_device *pdev) 3156 { 3157 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3158 3159 if (early_serial_console.data) 3160 return -EEXIST; 3161 3162 early_serial_console.index = pdev->id; 3163 3164 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3165 3166 if (!strstr(early_serial_buf, "keep")) 3167 early_serial_console.flags |= CON_BOOT; 3168 3169 register_console(&early_serial_console); 3170 return 0; 3171 } 3172 #endif 3173 3174 #define SCI_CONSOLE (&serial_console) 3175 3176 #else sci_probe_earlyprintk(struct platform_device * pdev)3177 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3178 { 3179 return -EINVAL; 3180 } 3181 3182 #define SCI_CONSOLE NULL 3183 3184 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3185 3186 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3187 3188 static DEFINE_MUTEX(sci_uart_registration_lock); 3189 static struct uart_driver sci_uart_driver = { 3190 .owner = THIS_MODULE, 3191 .driver_name = "sci", 3192 .dev_name = "ttySC", 3193 .major = SCI_MAJOR, 3194 .minor = SCI_MINOR_START, 3195 .nr = SCI_NPORTS, 3196 .cons = SCI_CONSOLE, 3197 }; 3198 sci_remove(struct platform_device * dev)3199 static int sci_remove(struct platform_device *dev) 3200 { 3201 struct sci_port *port = platform_get_drvdata(dev); 3202 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3203 3204 sci_ports_in_use &= ~BIT(port->port.line); 3205 uart_remove_one_port(&sci_uart_driver, &port->port); 3206 3207 sci_cleanup_single(port); 3208 3209 if (port->port.fifosize > 1) 3210 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3211 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) 3212 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3213 3214 return 0; 3215 } 3216 3217 3218 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3219 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3220 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3221 3222 static const struct of_device_id of_sci_match[] __maybe_unused = { 3223 /* SoC-specific types */ 3224 { 3225 .compatible = "renesas,scif-r7s72100", 3226 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3227 }, 3228 { 3229 .compatible = "renesas,scif-r7s9210", 3230 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3231 }, 3232 { 3233 .compatible = "renesas,scif-r9a07g044", 3234 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3235 }, 3236 /* Family-specific types */ 3237 { 3238 .compatible = "renesas,rcar-gen1-scif", 3239 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3240 }, { 3241 .compatible = "renesas,rcar-gen2-scif", 3242 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3243 }, { 3244 .compatible = "renesas,rcar-gen3-scif", 3245 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3246 }, { 3247 .compatible = "renesas,rcar-gen4-scif", 3248 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3249 }, 3250 /* Generic types */ 3251 { 3252 .compatible = "renesas,scif", 3253 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3254 }, { 3255 .compatible = "renesas,scifa", 3256 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3257 }, { 3258 .compatible = "renesas,scifb", 3259 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3260 }, { 3261 .compatible = "renesas,hscif", 3262 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3263 }, { 3264 .compatible = "renesas,sci", 3265 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3266 }, { 3267 /* Terminator */ 3268 }, 3269 }; 3270 MODULE_DEVICE_TABLE(of, of_sci_match); 3271 sci_reset_control_assert(void * data)3272 static void sci_reset_control_assert(void *data) 3273 { 3274 reset_control_assert(data); 3275 } 3276 sci_parse_dt(struct platform_device * pdev,unsigned int * dev_id)3277 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3278 unsigned int *dev_id) 3279 { 3280 struct device_node *np = pdev->dev.of_node; 3281 struct reset_control *rstc; 3282 struct plat_sci_port *p; 3283 struct sci_port *sp; 3284 const void *data; 3285 int id, ret; 3286 3287 if (!IS_ENABLED(CONFIG_OF) || !np) 3288 return ERR_PTR(-EINVAL); 3289 3290 data = of_device_get_match_data(&pdev->dev); 3291 3292 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 3293 if (IS_ERR(rstc)) 3294 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), 3295 "failed to get reset ctrl\n")); 3296 3297 ret = reset_control_deassert(rstc); 3298 if (ret) { 3299 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); 3300 return ERR_PTR(ret); 3301 } 3302 3303 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); 3304 if (ret) { 3305 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", 3306 ret); 3307 return ERR_PTR(ret); 3308 } 3309 3310 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3311 if (!p) 3312 return ERR_PTR(-ENOMEM); 3313 3314 /* Get the line number from the aliases node. */ 3315 id = of_alias_get_id(np, "serial"); 3316 if (id < 0 && ~sci_ports_in_use) 3317 id = ffz(sci_ports_in_use); 3318 if (id < 0) { 3319 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3320 return ERR_PTR(-EINVAL); 3321 } 3322 if (id >= ARRAY_SIZE(sci_ports)) { 3323 dev_err(&pdev->dev, "serial%d out of range\n", id); 3324 return ERR_PTR(-EINVAL); 3325 } 3326 3327 sp = &sci_ports[id]; 3328 *dev_id = id; 3329 3330 p->type = SCI_OF_TYPE(data); 3331 p->regtype = SCI_OF_REGTYPE(data); 3332 3333 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3334 3335 return p; 3336 } 3337 sci_probe_single(struct platform_device * dev,unsigned int index,struct plat_sci_port * p,struct sci_port * sciport)3338 static int sci_probe_single(struct platform_device *dev, 3339 unsigned int index, 3340 struct plat_sci_port *p, 3341 struct sci_port *sciport) 3342 { 3343 int ret; 3344 3345 /* Sanity check */ 3346 if (unlikely(index >= SCI_NPORTS)) { 3347 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3348 index+1, SCI_NPORTS); 3349 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3350 return -EINVAL; 3351 } 3352 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3353 if (sci_ports_in_use & BIT(index)) 3354 return -EBUSY; 3355 3356 mutex_lock(&sci_uart_registration_lock); 3357 if (!sci_uart_driver.state) { 3358 ret = uart_register_driver(&sci_uart_driver); 3359 if (ret) { 3360 mutex_unlock(&sci_uart_registration_lock); 3361 return ret; 3362 } 3363 } 3364 mutex_unlock(&sci_uart_registration_lock); 3365 3366 ret = sci_init_single(dev, sciport, index, p, false); 3367 if (ret) 3368 return ret; 3369 3370 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3371 if (IS_ERR(sciport->gpios)) 3372 return PTR_ERR(sciport->gpios); 3373 3374 if (sciport->has_rtscts) { 3375 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3376 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3377 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3378 return -EINVAL; 3379 } 3380 sciport->port.flags |= UPF_HARD_FLOW; 3381 } 3382 3383 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3384 if (ret) { 3385 sci_cleanup_single(sciport); 3386 return ret; 3387 } 3388 3389 return 0; 3390 } 3391 sci_probe(struct platform_device * dev)3392 static int sci_probe(struct platform_device *dev) 3393 { 3394 struct plat_sci_port *p; 3395 struct resource *res; 3396 struct sci_port *sp; 3397 unsigned int dev_id; 3398 int ret; 3399 3400 /* 3401 * If we've come here via earlyprintk initialization, head off to 3402 * the special early probe. We don't have sufficient device state 3403 * to make it beyond this yet. 3404 */ 3405 #ifdef CONFIG_SUPERH 3406 if (is_sh_early_platform_device(dev)) 3407 return sci_probe_earlyprintk(dev); 3408 #endif 3409 3410 if (dev->dev.of_node) { 3411 p = sci_parse_dt(dev, &dev_id); 3412 if (IS_ERR(p)) 3413 return PTR_ERR(p); 3414 } else { 3415 p = dev->dev.platform_data; 3416 if (p == NULL) { 3417 dev_err(&dev->dev, "no platform data supplied\n"); 3418 return -EINVAL; 3419 } 3420 3421 dev_id = dev->id; 3422 } 3423 3424 sp = &sci_ports[dev_id]; 3425 3426 /* 3427 * In case: 3428 * - the probed port alias is zero (as the one used by earlycon), and 3429 * - the earlycon is still active (e.g., "earlycon keep_bootcon" in 3430 * bootargs) 3431 * 3432 * defer the probe of this serial. This is a debug scenario and the user 3433 * must be aware of it. 3434 * 3435 * Except when the probed port is the same as the earlycon port. 3436 */ 3437 3438 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 3439 if (!res) 3440 return -ENODEV; 3441 3442 if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start) 3443 return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n"); 3444 3445 platform_set_drvdata(dev, sp); 3446 3447 ret = sci_probe_single(dev, dev_id, p, sp); 3448 if (ret) 3449 return ret; 3450 3451 if (sp->port.fifosize > 1) { 3452 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3453 if (ret) 3454 return ret; 3455 } 3456 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3457 sp->port.type == PORT_HSCIF) { 3458 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3459 if (ret) { 3460 if (sp->port.fifosize > 1) { 3461 device_remove_file(&dev->dev, 3462 &dev_attr_rx_fifo_trigger); 3463 } 3464 return ret; 3465 } 3466 } 3467 3468 #ifdef CONFIG_SH_STANDARD_BIOS 3469 sh_bios_gdb_detach(); 3470 #endif 3471 3472 sci_ports_in_use |= BIT(dev_id); 3473 return 0; 3474 } 3475 sci_suspend(struct device * dev)3476 static __maybe_unused int sci_suspend(struct device *dev) 3477 { 3478 struct sci_port *sport = dev_get_drvdata(dev); 3479 3480 if (sport) 3481 uart_suspend_port(&sci_uart_driver, &sport->port); 3482 3483 return 0; 3484 } 3485 sci_resume(struct device * dev)3486 static __maybe_unused int sci_resume(struct device *dev) 3487 { 3488 struct sci_port *sport = dev_get_drvdata(dev); 3489 3490 if (sport) 3491 uart_resume_port(&sci_uart_driver, &sport->port); 3492 3493 return 0; 3494 } 3495 3496 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3497 3498 static struct platform_driver sci_driver = { 3499 .probe = sci_probe, 3500 .remove = sci_remove, 3501 .driver = { 3502 .name = "sh-sci", 3503 .pm = &sci_dev_pm_ops, 3504 .of_match_table = of_match_ptr(of_sci_match), 3505 }, 3506 }; 3507 sci_init(void)3508 static int __init sci_init(void) 3509 { 3510 pr_info("%s\n", banner); 3511 3512 return platform_driver_register(&sci_driver); 3513 } 3514 sci_exit(void)3515 static void __exit sci_exit(void) 3516 { 3517 platform_driver_unregister(&sci_driver); 3518 3519 if (sci_uart_driver.state) 3520 uart_unregister_driver(&sci_uart_driver); 3521 } 3522 3523 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 3524 sh_early_platform_init_buffer("earlyprintk", &sci_driver, 3525 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3526 #endif 3527 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3528 static struct plat_sci_port port_cfg; 3529 early_console_setup(struct earlycon_device * device,int type)3530 static int __init early_console_setup(struct earlycon_device *device, 3531 int type) 3532 { 3533 if (!device->port.membase) 3534 return -ENODEV; 3535 3536 device->port.serial_in = sci_serial_in; 3537 device->port.serial_out = sci_serial_out; 3538 device->port.type = type; 3539 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3540 port_cfg.type = type; 3541 sci_ports[0].cfg = &port_cfg; 3542 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3543 sci_uart_earlycon = true; 3544 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3545 sci_serial_out(&sci_ports[0].port, SCSCR, 3546 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3547 3548 device->con->write = serial_console_write; 3549 return 0; 3550 } sci_early_console_setup(struct earlycon_device * device,const char * opt)3551 static int __init sci_early_console_setup(struct earlycon_device *device, 3552 const char *opt) 3553 { 3554 return early_console_setup(device, PORT_SCI); 3555 } scif_early_console_setup(struct earlycon_device * device,const char * opt)3556 static int __init scif_early_console_setup(struct earlycon_device *device, 3557 const char *opt) 3558 { 3559 return early_console_setup(device, PORT_SCIF); 3560 } rzscifa_early_console_setup(struct earlycon_device * device,const char * opt)3561 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3562 const char *opt) 3563 { 3564 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3565 return early_console_setup(device, PORT_SCIF); 3566 } 3567 scifa_early_console_setup(struct earlycon_device * device,const char * opt)3568 static int __init scifa_early_console_setup(struct earlycon_device *device, 3569 const char *opt) 3570 { 3571 return early_console_setup(device, PORT_SCIFA); 3572 } scifb_early_console_setup(struct earlycon_device * device,const char * opt)3573 static int __init scifb_early_console_setup(struct earlycon_device *device, 3574 const char *opt) 3575 { 3576 return early_console_setup(device, PORT_SCIFB); 3577 } hscif_early_console_setup(struct earlycon_device * device,const char * opt)3578 static int __init hscif_early_console_setup(struct earlycon_device *device, 3579 const char *opt) 3580 { 3581 return early_console_setup(device, PORT_HSCIF); 3582 } 3583 3584 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3585 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3586 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3587 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); 3588 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3589 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3590 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3591 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3592 3593 module_init(sci_init); 3594 module_exit(sci_exit); 3595 3596 MODULE_LICENSE("GPL"); 3597 MODULE_ALIAS("platform:sh-sci"); 3598 MODULE_AUTHOR("Paul Mundt"); 3599 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3600