1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/delay.h>
4 #include <linux/clk-provider.h>
5 #include <linux/io.h>
6 #include <linux/of.h>
7 #include <linux/platform_device.h>
8 #include <dt-bindings/clock/en7523-clk.h>
9
10 #define REG_PCI_CONTROL 0x88
11 #define REG_PCI_CONTROL_PERSTOUT BIT(29)
12 #define REG_PCI_CONTROL_PERSTOUT1 BIT(26)
13 #define REG_PCI_CONTROL_REFCLK_EN1 BIT(22)
14 #define REG_GSW_CLK_DIV_SEL 0x1b4
15 #define REG_EMI_CLK_DIV_SEL 0x1b8
16 #define REG_BUS_CLK_DIV_SEL 0x1bc
17 #define REG_SPI_CLK_DIV_SEL 0x1c4
18 #define REG_SPI_CLK_FREQ_SEL 0x1c8
19 #define REG_NPU_CLK_DIV_SEL 0x1fc
20 #define REG_CRYPTO_CLKSRC 0x200
21 #define REG_RESET_CONTROL 0x834
22 #define REG_RESET_CONTROL_PCIEHB BIT(29)
23 #define REG_RESET_CONTROL_PCIE1 BIT(27)
24 #define REG_RESET_CONTROL_PCIE2 BIT(26)
25
26 struct en_clk_desc {
27 int id;
28 const char *name;
29 u32 base_reg;
30 u8 base_bits;
31 u8 base_shift;
32 union {
33 const unsigned int *base_values;
34 unsigned int base_value;
35 };
36 size_t n_base_values;
37
38 u16 div_reg;
39 u8 div_bits;
40 u8 div_shift;
41 u16 div_val0;
42 u8 div_step;
43 u8 div_offset;
44 };
45
46 struct en_clk_gate {
47 void __iomem *base;
48 struct clk_hw hw;
49 };
50
51 static const u32 gsw_base[] = { 400000000, 500000000 };
52 static const u32 emi_base[] = { 333000000, 400000000 };
53 static const u32 bus_base[] = { 500000000, 540000000 };
54 static const u32 slic_base[] = { 100000000, 3125000 };
55 static const u32 npu_base[] = { 333000000, 400000000, 500000000 };
56
57 static const struct en_clk_desc en7523_base_clks[] = {
58 {
59 .id = EN7523_CLK_GSW,
60 .name = "gsw",
61
62 .base_reg = REG_GSW_CLK_DIV_SEL,
63 .base_bits = 1,
64 .base_shift = 8,
65 .base_values = gsw_base,
66 .n_base_values = ARRAY_SIZE(gsw_base),
67
68 .div_bits = 3,
69 .div_shift = 0,
70 .div_step = 1,
71 .div_offset = 1,
72 }, {
73 .id = EN7523_CLK_EMI,
74 .name = "emi",
75
76 .base_reg = REG_EMI_CLK_DIV_SEL,
77 .base_bits = 1,
78 .base_shift = 8,
79 .base_values = emi_base,
80 .n_base_values = ARRAY_SIZE(emi_base),
81
82 .div_bits = 3,
83 .div_shift = 0,
84 .div_step = 1,
85 .div_offset = 1,
86 }, {
87 .id = EN7523_CLK_BUS,
88 .name = "bus",
89
90 .base_reg = REG_BUS_CLK_DIV_SEL,
91 .base_bits = 1,
92 .base_shift = 8,
93 .base_values = bus_base,
94 .n_base_values = ARRAY_SIZE(bus_base),
95
96 .div_bits = 3,
97 .div_shift = 0,
98 .div_step = 1,
99 .div_offset = 1,
100 }, {
101 .id = EN7523_CLK_SLIC,
102 .name = "slic",
103
104 .base_reg = REG_SPI_CLK_FREQ_SEL,
105 .base_bits = 1,
106 .base_shift = 0,
107 .base_values = slic_base,
108 .n_base_values = ARRAY_SIZE(slic_base),
109
110 .div_reg = REG_SPI_CLK_DIV_SEL,
111 .div_bits = 5,
112 .div_shift = 24,
113 .div_val0 = 20,
114 .div_step = 2,
115 }, {
116 .id = EN7523_CLK_SPI,
117 .name = "spi",
118
119 .base_reg = REG_SPI_CLK_DIV_SEL,
120
121 .base_value = 400000000,
122
123 .div_bits = 5,
124 .div_shift = 8,
125 .div_val0 = 40,
126 .div_step = 2,
127 }, {
128 .id = EN7523_CLK_NPU,
129 .name = "npu",
130
131 .base_reg = REG_NPU_CLK_DIV_SEL,
132 .base_bits = 2,
133 .base_shift = 8,
134 .base_values = npu_base,
135 .n_base_values = ARRAY_SIZE(npu_base),
136
137 .div_bits = 3,
138 .div_shift = 0,
139 .div_step = 1,
140 .div_offset = 1,
141 }, {
142 .id = EN7523_CLK_CRYPTO,
143 .name = "crypto",
144
145 .base_reg = REG_CRYPTO_CLKSRC,
146 .base_bits = 1,
147 .base_shift = 0,
148 .base_values = emi_base,
149 .n_base_values = ARRAY_SIZE(emi_base),
150 }
151 };
152
153 static const struct of_device_id of_match_clk_en7523[] = {
154 { .compatible = "airoha,en7523-scu", },
155 { /* sentinel */ }
156 };
157
en7523_get_base_rate(void __iomem * base,unsigned int i)158 static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i)
159 {
160 const struct en_clk_desc *desc = &en7523_base_clks[i];
161 u32 val;
162
163 if (!desc->base_bits)
164 return desc->base_value;
165
166 val = readl(base + desc->base_reg);
167 val >>= desc->base_shift;
168 val &= (1 << desc->base_bits) - 1;
169
170 if (val >= desc->n_base_values)
171 return 0;
172
173 return desc->base_values[val];
174 }
175
en7523_get_div(void __iomem * base,int i)176 static u32 en7523_get_div(void __iomem *base, int i)
177 {
178 const struct en_clk_desc *desc = &en7523_base_clks[i];
179 u32 reg, val;
180
181 if (!desc->div_bits)
182 return 1;
183
184 reg = desc->div_reg ? desc->div_reg : desc->base_reg;
185 val = readl(base + reg);
186 val >>= desc->div_shift;
187 val &= (1 << desc->div_bits) - 1;
188
189 if (!val && desc->div_val0)
190 return desc->div_val0;
191
192 return (val + desc->div_offset) * desc->div_step;
193 }
194
en7523_pci_is_enabled(struct clk_hw * hw)195 static int en7523_pci_is_enabled(struct clk_hw *hw)
196 {
197 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
198
199 return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1);
200 }
201
en7523_pci_prepare(struct clk_hw * hw)202 static int en7523_pci_prepare(struct clk_hw *hw)
203 {
204 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
205 void __iomem *np_base = cg->base;
206 u32 val, mask;
207
208 /* Need to pull device low before reset */
209 val = readl(np_base + REG_PCI_CONTROL);
210 val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT);
211 writel(val, np_base + REG_PCI_CONTROL);
212 usleep_range(1000, 2000);
213
214 /* Enable PCIe port 1 */
215 val |= REG_PCI_CONTROL_REFCLK_EN1;
216 writel(val, np_base + REG_PCI_CONTROL);
217 usleep_range(1000, 2000);
218
219 /* Reset to default */
220 val = readl(np_base + REG_RESET_CONTROL);
221 mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
222 REG_RESET_CONTROL_PCIEHB;
223 writel(val & ~mask, np_base + REG_RESET_CONTROL);
224 usleep_range(1000, 2000);
225 writel(val | mask, np_base + REG_RESET_CONTROL);
226 msleep(100);
227 writel(val & ~mask, np_base + REG_RESET_CONTROL);
228 usleep_range(5000, 10000);
229
230 /* Release device */
231 mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT;
232 val = readl(np_base + REG_PCI_CONTROL);
233 writel(val & ~mask, np_base + REG_PCI_CONTROL);
234 usleep_range(1000, 2000);
235 writel(val | mask, np_base + REG_PCI_CONTROL);
236 msleep(250);
237
238 return 0;
239 }
240
en7523_pci_unprepare(struct clk_hw * hw)241 static void en7523_pci_unprepare(struct clk_hw *hw)
242 {
243 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
244 void __iomem *np_base = cg->base;
245 u32 val;
246
247 val = readl(np_base + REG_PCI_CONTROL);
248 val &= ~REG_PCI_CONTROL_REFCLK_EN1;
249 writel(val, np_base + REG_PCI_CONTROL);
250 }
251
en7523_register_pcie_clk(struct device * dev,void __iomem * np_base)252 static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
253 void __iomem *np_base)
254 {
255 static const struct clk_ops pcie_gate_ops = {
256 .is_enabled = en7523_pci_is_enabled,
257 .prepare = en7523_pci_prepare,
258 .unprepare = en7523_pci_unprepare,
259 };
260 struct clk_init_data init = {
261 .name = "pcie",
262 .ops = &pcie_gate_ops,
263 };
264 struct en_clk_gate *cg;
265
266 cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL);
267 if (!cg)
268 return NULL;
269
270 cg->base = np_base;
271 cg->hw.init = &init;
272 en7523_pci_unprepare(&cg->hw);
273
274 if (clk_hw_register(dev, &cg->hw))
275 return NULL;
276
277 return &cg->hw;
278 }
279
en7523_register_clocks(struct device * dev,struct clk_hw_onecell_data * clk_data,void __iomem * base,void __iomem * np_base)280 static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
281 void __iomem *base, void __iomem *np_base)
282 {
283 struct clk_hw *hw;
284 u32 rate;
285 int i;
286
287 for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) {
288 const struct en_clk_desc *desc = &en7523_base_clks[i];
289
290 rate = en7523_get_base_rate(base, i);
291 rate /= en7523_get_div(base, i);
292
293 hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate);
294 if (IS_ERR(hw)) {
295 pr_err("Failed to register clk %s: %ld\n",
296 desc->name, PTR_ERR(hw));
297 continue;
298 }
299
300 clk_data->hws[desc->id] = hw;
301 }
302
303 hw = en7523_register_pcie_clk(dev, np_base);
304 clk_data->hws[EN7523_CLK_PCIE] = hw;
305
306 clk_data->num = EN7523_NUM_CLOCKS;
307 }
308
en7523_clk_probe(struct platform_device * pdev)309 static int en7523_clk_probe(struct platform_device *pdev)
310 {
311 struct device_node *node = pdev->dev.of_node;
312 struct clk_hw_onecell_data *clk_data;
313 void __iomem *base, *np_base;
314 int r;
315
316 base = devm_platform_ioremap_resource(pdev, 0);
317 if (IS_ERR(base))
318 return PTR_ERR(base);
319
320 np_base = devm_platform_ioremap_resource(pdev, 1);
321 if (IS_ERR(np_base))
322 return PTR_ERR(np_base);
323
324 clk_data = devm_kzalloc(&pdev->dev,
325 struct_size(clk_data, hws, EN7523_NUM_CLOCKS),
326 GFP_KERNEL);
327 if (!clk_data)
328 return -ENOMEM;
329
330 en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
331
332 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
333 if (r)
334 dev_err(&pdev->dev,
335 "could not register clock provider: %s: %d\n",
336 pdev->name, r);
337
338 return r;
339 }
340
341 static struct platform_driver clk_en7523_drv = {
342 .probe = en7523_clk_probe,
343 .driver = {
344 .name = "clk-en7523",
345 .of_match_table = of_match_clk_en7523,
346 .suppress_bind_attrs = true,
347 },
348 };
349
clk_en7523_init(void)350 static int __init clk_en7523_init(void)
351 {
352 return platform_driver_register(&clk_en7523_drv);
353 }
354
355 arch_initcall(clk_en7523_init);
356