Searched defs:div0 (Results 1 – 4 of 4) sorted by relevance
| /openbmc/u-boot/drivers/clk/ |
| H A D | clk_zynq.c | 227 u32 clk_ctrl, div0, div1; in zynq_clk_get_dci_rate() local
243 u32 clk_ctrl, div0; in zynq_clk_get_peripheral_rate() local
289 u32 *div0, u32 *div1) in zynq_clk_calc_peripheral_two_divs()
318 u32 clk_ctrl, div0 = 0, div1 = 0; in zynq_clk_set_peripheral_rate() local
|
| H A D | clk_zynqmp.c | 419 u32 clk_ctrl, div0; in zynqmp_clk_get_peripheral_rate() local
454 u32 clk_ctrl, div0; in zynqmp_clk_get_wdt_rate() local
495 u32 *div0, u32 *div1) in zynqmp_clk_calc_peripheral_two_divs()
524 u32 clk_ctrl, div0 = 0, div1 = 0; in zynqmp_clk_set_peripheral_rate() local
|
| /openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
| H A D | clock.h | 28 unsigned int div0; member
64 unsigned int div0; member
|
| /openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | clock_sun50i_h6.h | 239 #define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) argument
|