1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * drivers/mb862xx/mb862xxfb.c
4 *
5 * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver
6 *
7 * (C) 2008 Anatolij Gustschin <agust@denx.de>
8 * DENX Software Engineering
9 */
10
11 #undef DEBUG
12
13 #include <linux/aperture.h>
14 #include <linux/fb.h>
15 #include <linux/delay.h>
16 #include <linux/uaccess.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/of.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
24 #include <linux/platform_device.h>
25
26 #include "mb862xxfb.h"
27 #include "mb862xx_reg.h"
28
29 #define NR_PALETTE 256
30 #define MB862XX_MEM_SIZE 0x1000000
31 #define CORALP_MEM_SIZE 0x2000000
32 #define CARMINE_MEM_SIZE 0x8000000
33 #define DRV_NAME "mb862xxfb"
34
35 #if defined(CONFIG_SOCRATES)
36 static struct mb862xx_gc_mode socrates_gc_mode = {
37 /* Mode for Prime View PM070WL4 TFT LCD Panel */
38 { "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 },
39 /* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */
40 16, 0x1000000, GC_CCF_COT_133, 0x4157ba63
41 };
42 #endif
43
44 /* Helpers */
h_total(struct fb_var_screeninfo * var)45 static inline int h_total(struct fb_var_screeninfo *var)
46 {
47 return var->xres + var->left_margin +
48 var->right_margin + var->hsync_len;
49 }
50
v_total(struct fb_var_screeninfo * var)51 static inline int v_total(struct fb_var_screeninfo *var)
52 {
53 return var->yres + var->upper_margin +
54 var->lower_margin + var->vsync_len;
55 }
56
hsp(struct fb_var_screeninfo * var)57 static inline int hsp(struct fb_var_screeninfo *var)
58 {
59 return var->xres + var->right_margin - 1;
60 }
61
vsp(struct fb_var_screeninfo * var)62 static inline int vsp(struct fb_var_screeninfo *var)
63 {
64 return var->yres + var->lower_margin - 1;
65 }
66
d_pitch(struct fb_var_screeninfo * var)67 static inline int d_pitch(struct fb_var_screeninfo *var)
68 {
69 return var->xres * var->bits_per_pixel / 8;
70 }
71
chan_to_field(unsigned int chan,struct fb_bitfield * bf)72 static inline unsigned int chan_to_field(unsigned int chan,
73 struct fb_bitfield *bf)
74 {
75 chan &= 0xffff;
76 chan >>= 16 - bf->length;
77 return chan << bf->offset;
78 }
79
mb862xxfb_setcolreg(unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp,struct fb_info * info)80 static int mb862xxfb_setcolreg(unsigned regno,
81 unsigned red, unsigned green, unsigned blue,
82 unsigned transp, struct fb_info *info)
83 {
84 struct mb862xxfb_par *par = info->par;
85 unsigned int val;
86
87 switch (info->fix.visual) {
88 case FB_VISUAL_TRUECOLOR:
89 if (regno < 16) {
90 val = chan_to_field(red, &info->var.red);
91 val |= chan_to_field(green, &info->var.green);
92 val |= chan_to_field(blue, &info->var.blue);
93 par->pseudo_palette[regno] = val;
94 }
95 break;
96 case FB_VISUAL_PSEUDOCOLOR:
97 if (regno < 256) {
98 val = (red >> 8) << 16;
99 val |= (green >> 8) << 8;
100 val |= blue >> 8;
101 outreg(disp, GC_L0PAL0 + (regno * 4), val);
102 }
103 break;
104 default:
105 return 1; /* unsupported type */
106 }
107 return 0;
108 }
109
mb862xxfb_check_var(struct fb_var_screeninfo * var,struct fb_info * fbi)110 static int mb862xxfb_check_var(struct fb_var_screeninfo *var,
111 struct fb_info *fbi)
112 {
113 unsigned long tmp;
114
115 fb_dbg(fbi, "%s\n", __func__);
116
117 /* check if these values fit into the registers */
118 if (var->hsync_len > 255 || var->vsync_len > 255)
119 return -EINVAL;
120
121 if ((var->xres + var->right_margin) >= 4096)
122 return -EINVAL;
123
124 if ((var->yres + var->lower_margin) > 4096)
125 return -EINVAL;
126
127 if (h_total(var) > 4096 || v_total(var) > 4096)
128 return -EINVAL;
129
130 if (var->xres_virtual > 4096 || var->yres_virtual > 4096)
131 return -EINVAL;
132
133 if (var->bits_per_pixel <= 8)
134 var->bits_per_pixel = 8;
135 else if (var->bits_per_pixel <= 16)
136 var->bits_per_pixel = 16;
137 else if (var->bits_per_pixel <= 32)
138 var->bits_per_pixel = 32;
139
140 /*
141 * can cope with 8,16 or 24/32bpp if resulting
142 * pitch is divisible by 64 without remainder
143 */
144 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) {
145 int r;
146
147 var->bits_per_pixel = 0;
148 do {
149 var->bits_per_pixel += 8;
150 r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT;
151 } while (r && var->bits_per_pixel <= 32);
152
153 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT)
154 return -EINVAL;
155 }
156
157 /* line length is going to be 128 bit aligned */
158 tmp = (var->xres * var->bits_per_pixel) / 8;
159 if ((tmp & 15) != 0)
160 return -EINVAL;
161
162 /* set r/g/b positions and validate bpp */
163 switch (var->bits_per_pixel) {
164 case 8:
165 var->red.length = var->bits_per_pixel;
166 var->green.length = var->bits_per_pixel;
167 var->blue.length = var->bits_per_pixel;
168 var->red.offset = 0;
169 var->green.offset = 0;
170 var->blue.offset = 0;
171 var->transp.length = 0;
172 break;
173 case 16:
174 var->red.length = 5;
175 var->green.length = 5;
176 var->blue.length = 5;
177 var->red.offset = 10;
178 var->green.offset = 5;
179 var->blue.offset = 0;
180 var->transp.length = 0;
181 break;
182 case 24:
183 case 32:
184 var->transp.length = 8;
185 var->red.length = 8;
186 var->green.length = 8;
187 var->blue.length = 8;
188 var->transp.offset = 24;
189 var->red.offset = 16;
190 var->green.offset = 8;
191 var->blue.offset = 0;
192 break;
193 default:
194 return -EINVAL;
195 }
196 return 0;
197 }
198
199 static struct fb_ops mb862xxfb_ops;
200
201 /*
202 * set display parameters
203 */
mb862xxfb_set_par(struct fb_info * fbi)204 static int mb862xxfb_set_par(struct fb_info *fbi)
205 {
206 struct mb862xxfb_par *par = fbi->par;
207 unsigned long reg, sc;
208
209 dev_dbg(par->dev, "%s\n", __func__);
210 if (par->type == BT_CORALP)
211 mb862xxfb_init_accel(fbi, &mb862xxfb_ops, fbi->var.xres);
212
213 if (par->pre_init)
214 return 0;
215
216 /* disp off */
217 reg = inreg(disp, GC_DCM1);
218 reg &= ~GC_DCM01_DEN;
219 outreg(disp, GC_DCM1, reg);
220
221 /* set display reference clock div. */
222 sc = par->refclk / (1000000 / fbi->var.pixclock) - 1;
223 reg = inreg(disp, GC_DCM1);
224 reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC);
225 reg |= sc << 8;
226 outreg(disp, GC_DCM1, reg);
227 dev_dbg(par->dev, "SC 0x%lx\n", sc);
228
229 /* disp dimension, format */
230 reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT,
231 (fbi->var.yres - 1));
232 if (fbi->var.bits_per_pixel == 16)
233 reg |= GC_L0M_L0C_16;
234 outreg(disp, GC_L0M, reg);
235
236 if (fbi->var.bits_per_pixel == 32) {
237 reg = inreg(disp, GC_L0EM);
238 outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24);
239 }
240 outreg(disp, GC_WY_WX, 0);
241 reg = pack(fbi->var.yres - 1, fbi->var.xres);
242 outreg(disp, GC_WH_WW, reg);
243 outreg(disp, GC_L0OA0, 0);
244 outreg(disp, GC_L0DA0, 0);
245 outreg(disp, GC_L0DY_L0DX, 0);
246 outreg(disp, GC_L0WY_L0WX, 0);
247 outreg(disp, GC_L0WH_L0WW, reg);
248
249 /* both HW-cursors off */
250 reg = inreg(disp, GC_CPM_CUTC);
251 reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1);
252 outreg(disp, GC_CPM_CUTC, reg);
253
254 /* timings */
255 reg = pack(fbi->var.xres - 1, fbi->var.xres - 1);
256 outreg(disp, GC_HDB_HDP, reg);
257 reg = pack((fbi->var.yres - 1), vsp(&fbi->var));
258 outreg(disp, GC_VDP_VSP, reg);
259 reg = ((fbi->var.vsync_len - 1) << 24) |
260 pack((fbi->var.hsync_len - 1), hsp(&fbi->var));
261 outreg(disp, GC_VSW_HSW_HSP, reg);
262 outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0));
263 outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0));
264
265 /* display on */
266 reg = inreg(disp, GC_DCM1);
267 reg |= GC_DCM01_DEN | GC_DCM01_L0E;
268 reg &= ~GC_DCM01_ESY;
269 outreg(disp, GC_DCM1, reg);
270 return 0;
271 }
272
mb862xxfb_pan(struct fb_var_screeninfo * var,struct fb_info * info)273 static int mb862xxfb_pan(struct fb_var_screeninfo *var,
274 struct fb_info *info)
275 {
276 struct mb862xxfb_par *par = info->par;
277 unsigned long reg;
278
279 reg = pack(var->yoffset, var->xoffset);
280 outreg(disp, GC_L0WY_L0WX, reg);
281
282 reg = pack(info->var.yres_virtual, info->var.xres_virtual);
283 outreg(disp, GC_L0WH_L0WW, reg);
284 return 0;
285 }
286
mb862xxfb_blank(int mode,struct fb_info * fbi)287 static int mb862xxfb_blank(int mode, struct fb_info *fbi)
288 {
289 struct mb862xxfb_par *par = fbi->par;
290 unsigned long reg;
291
292 fb_dbg(fbi, "blank mode=%d\n", mode);
293
294 switch (mode) {
295 case FB_BLANK_POWERDOWN:
296 reg = inreg(disp, GC_DCM1);
297 reg &= ~GC_DCM01_DEN;
298 outreg(disp, GC_DCM1, reg);
299 break;
300 case FB_BLANK_UNBLANK:
301 reg = inreg(disp, GC_DCM1);
302 reg |= GC_DCM01_DEN;
303 outreg(disp, GC_DCM1, reg);
304 break;
305 case FB_BLANK_NORMAL:
306 case FB_BLANK_VSYNC_SUSPEND:
307 case FB_BLANK_HSYNC_SUSPEND:
308 default:
309 return 1;
310 }
311 return 0;
312 }
313
mb862xxfb_ioctl(struct fb_info * fbi,unsigned int cmd,unsigned long arg)314 static int mb862xxfb_ioctl(struct fb_info *fbi, unsigned int cmd,
315 unsigned long arg)
316 {
317 struct mb862xxfb_par *par = fbi->par;
318 struct mb862xx_l1_cfg *l1_cfg = &par->l1_cfg;
319 void __user *argp = (void __user *)arg;
320 int *enable;
321 u32 l1em = 0;
322
323 switch (cmd) {
324 case MB862XX_L1_GET_CFG:
325 if (copy_to_user(argp, l1_cfg, sizeof(*l1_cfg)))
326 return -EFAULT;
327 break;
328 case MB862XX_L1_SET_CFG:
329 if (copy_from_user(l1_cfg, argp, sizeof(*l1_cfg)))
330 return -EFAULT;
331 if (l1_cfg->dh == 0 || l1_cfg->dw == 0)
332 return -EINVAL;
333 if ((l1_cfg->sw >= l1_cfg->dw) && (l1_cfg->sh >= l1_cfg->dh)) {
334 /* downscaling */
335 outreg(cap, GC_CAP_CSC,
336 pack((l1_cfg->sh << 11) / l1_cfg->dh,
337 (l1_cfg->sw << 11) / l1_cfg->dw));
338 l1em = inreg(disp, GC_L1EM);
339 l1em &= ~GC_L1EM_DM;
340 } else if ((l1_cfg->sw <= l1_cfg->dw) &&
341 (l1_cfg->sh <= l1_cfg->dh)) {
342 /* upscaling */
343 outreg(cap, GC_CAP_CSC,
344 pack((l1_cfg->sh << 11) / l1_cfg->dh,
345 (l1_cfg->sw << 11) / l1_cfg->dw));
346 outreg(cap, GC_CAP_CMSS,
347 pack(l1_cfg->sw >> 1, l1_cfg->sh));
348 outreg(cap, GC_CAP_CMDS,
349 pack(l1_cfg->dw >> 1, l1_cfg->dh));
350 l1em = inreg(disp, GC_L1EM);
351 l1em |= GC_L1EM_DM;
352 }
353
354 if (l1_cfg->mirror) {
355 outreg(cap, GC_CAP_CBM,
356 inreg(cap, GC_CAP_CBM) | GC_CBM_HRV);
357 l1em |= l1_cfg->dw * 2 - 8;
358 } else {
359 outreg(cap, GC_CAP_CBM,
360 inreg(cap, GC_CAP_CBM) & ~GC_CBM_HRV);
361 l1em &= 0xffff0000;
362 }
363 outreg(disp, GC_L1EM, l1em);
364 break;
365 case MB862XX_L1_ENABLE:
366 enable = (int *)arg;
367 if (*enable) {
368 outreg(disp, GC_L1DA, par->cap_buf);
369 outreg(cap, GC_CAP_IMG_START,
370 pack(l1_cfg->sy >> 1, l1_cfg->sx));
371 outreg(cap, GC_CAP_IMG_END,
372 pack(l1_cfg->sh, l1_cfg->sw));
373 outreg(disp, GC_L1M, GC_L1M_16 | GC_L1M_YC | GC_L1M_CS |
374 (par->l1_stride << 16));
375 outreg(disp, GC_L1WY_L1WX,
376 pack(l1_cfg->dy, l1_cfg->dx));
377 outreg(disp, GC_L1WH_L1WW,
378 pack(l1_cfg->dh - 1, l1_cfg->dw));
379 outreg(disp, GC_DLS, 1);
380 outreg(cap, GC_CAP_VCM,
381 GC_VCM_VIE | GC_VCM_CM | GC_VCM_VS_PAL);
382 outreg(disp, GC_DCM1, inreg(disp, GC_DCM1) |
383 GC_DCM1_DEN | GC_DCM1_L1E);
384 } else {
385 outreg(cap, GC_CAP_VCM,
386 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
387 outreg(disp, GC_DCM1,
388 inreg(disp, GC_DCM1) & ~GC_DCM1_L1E);
389 }
390 break;
391 case MB862XX_L1_CAP_CTL:
392 enable = (int *)arg;
393 if (*enable) {
394 outreg(cap, GC_CAP_VCM,
395 inreg(cap, GC_CAP_VCM) | GC_VCM_VIE);
396 } else {
397 outreg(cap, GC_CAP_VCM,
398 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
399 }
400 break;
401 default:
402 return -EINVAL;
403 }
404 return 0;
405 }
406
407 /* framebuffer ops */
408 static struct fb_ops mb862xxfb_ops = {
409 .owner = THIS_MODULE,
410 FB_DEFAULT_IOMEM_OPS,
411 .fb_check_var = mb862xxfb_check_var,
412 .fb_set_par = mb862xxfb_set_par,
413 .fb_setcolreg = mb862xxfb_setcolreg,
414 .fb_blank = mb862xxfb_blank,
415 .fb_pan_display = mb862xxfb_pan,
416 .fb_ioctl = mb862xxfb_ioctl,
417 };
418
419 /* initialize fb_info data */
mb862xxfb_init_fbinfo(struct fb_info * fbi)420 static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
421 {
422 struct mb862xxfb_par *par = fbi->par;
423 struct mb862xx_gc_mode *mode = par->gc_mode;
424 unsigned long reg;
425 int stride;
426
427 fbi->fbops = &mb862xxfb_ops;
428 fbi->pseudo_palette = par->pseudo_palette;
429 fbi->screen_base = par->fb_base;
430 fbi->screen_size = par->mapped_vram;
431
432 strcpy(fbi->fix.id, DRV_NAME);
433 fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
434 fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
435 fbi->fix.mmio_len = par->mmio_len;
436 fbi->fix.accel = FB_ACCEL_NONE;
437 fbi->fix.type = FB_TYPE_PACKED_PIXELS;
438 fbi->fix.type_aux = 0;
439 fbi->fix.xpanstep = 1;
440 fbi->fix.ypanstep = 1;
441 fbi->fix.ywrapstep = 0;
442
443 reg = inreg(disp, GC_DCM1);
444 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) {
445 /* get the disp mode from active display cfg */
446 unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1;
447 unsigned long hsp, vsp, ht, vt;
448
449 dev_dbg(par->dev, "using bootloader's disp. mode\n");
450 fbi->var.pixclock = (sc * 1000000) / par->refclk;
451 fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1;
452 reg = inreg(disp, GC_VDP_VSP);
453 fbi->var.yres = ((reg >> 16) & 0x0fff) + 1;
454 vsp = (reg & 0x0fff) + 1;
455 fbi->var.xres_virtual = fbi->var.xres;
456 fbi->var.yres_virtual = fbi->var.yres;
457 reg = inreg(disp, GC_L0EM);
458 if (reg & GC_L0EM_L0EC_24) {
459 fbi->var.bits_per_pixel = 32;
460 } else {
461 reg = inreg(disp, GC_L0M);
462 if (reg & GC_L0M_L0C_16)
463 fbi->var.bits_per_pixel = 16;
464 else
465 fbi->var.bits_per_pixel = 8;
466 }
467 reg = inreg(disp, GC_VSW_HSW_HSP);
468 fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1;
469 fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1;
470 hsp = (reg & 0xffff) + 1;
471 ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1;
472 fbi->var.right_margin = hsp - fbi->var.xres;
473 fbi->var.left_margin = ht - hsp - fbi->var.hsync_len;
474 vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1;
475 fbi->var.lower_margin = vsp - fbi->var.yres;
476 fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len;
477 } else if (mode) {
478 dev_dbg(par->dev, "using supplied mode\n");
479 fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode);
480 fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8;
481 } else {
482 int ret;
483
484 ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60",
485 NULL, 0, NULL, 16);
486 if (ret == 0 || ret == 4) {
487 dev_err(par->dev,
488 "failed to get initial mode\n");
489 return -EINVAL;
490 }
491 }
492
493 fbi->var.xoffset = 0;
494 fbi->var.yoffset = 0;
495 fbi->var.grayscale = 0;
496 fbi->var.nonstd = 0;
497 fbi->var.height = -1;
498 fbi->var.width = -1;
499 fbi->var.accel_flags = 0;
500 fbi->var.vmode = FB_VMODE_NONINTERLACED;
501 fbi->var.activate = FB_ACTIVATE_NOW;
502 fbi->flags =
503 #ifdef __BIG_ENDIAN
504 FBINFO_FOREIGN_ENDIAN |
505 #endif
506 FBINFO_HWACCEL_XPAN |
507 FBINFO_HWACCEL_YPAN;
508
509 /* check and possibly fix bpp */
510 if ((fbi->fbops->fb_check_var)(&fbi->var, fbi))
511 dev_err(par->dev, "check_var() failed on initial setup?\n");
512
513 fbi->fix.visual = fbi->var.bits_per_pixel == 8 ?
514 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
515 fbi->fix.line_length = (fbi->var.xres_virtual *
516 fbi->var.bits_per_pixel) / 8;
517 fbi->fix.smem_len = fbi->fix.line_length * fbi->var.yres_virtual;
518
519 /*
520 * reserve space for capture buffers and two cursors
521 * at the end of vram: 720x576 * 2 * 2.2 + 64x64 * 16.
522 */
523 par->cap_buf = par->mapped_vram - 0x1bd800 - 0x10000;
524 par->cap_len = 0x1bd800;
525 par->l1_cfg.sx = 0;
526 par->l1_cfg.sy = 0;
527 par->l1_cfg.sw = 720;
528 par->l1_cfg.sh = 576;
529 par->l1_cfg.dx = 0;
530 par->l1_cfg.dy = 0;
531 par->l1_cfg.dw = 720;
532 par->l1_cfg.dh = 576;
533 stride = par->l1_cfg.sw * (fbi->var.bits_per_pixel / 8);
534 par->l1_stride = stride / 64 + ((stride % 64) ? 1 : 0);
535 outreg(cap, GC_CAP_CBM, GC_CBM_OO | GC_CBM_CBST |
536 (par->l1_stride << 16));
537 outreg(cap, GC_CAP_CBOA, par->cap_buf);
538 outreg(cap, GC_CAP_CBLA, par->cap_buf + par->cap_len);
539 return 0;
540 }
541
542 /*
543 * show some display controller and cursor registers
544 */
dispregs_show(struct device * dev,struct device_attribute * attr,char * buf)545 static ssize_t dispregs_show(struct device *dev,
546 struct device_attribute *attr, char *buf)
547 {
548 struct fb_info *fbi = dev_get_drvdata(dev);
549 struct mb862xxfb_par *par = fbi->par;
550 char *ptr = buf;
551 unsigned int reg;
552
553 for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4)
554 ptr += sprintf(ptr, "%08x = %08x\n",
555 reg, inreg(disp, reg));
556
557 for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4)
558 ptr += sprintf(ptr, "%08x = %08x\n",
559 reg, inreg(disp, reg));
560
561 for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4)
562 ptr += sprintf(ptr, "%08x = %08x\n",
563 reg, inreg(disp, reg));
564
565 for (reg = 0x400; reg <= 0x410; reg += 4)
566 ptr += sprintf(ptr, "geo %08x = %08x\n",
567 reg, inreg(geo, reg));
568
569 for (reg = 0x400; reg <= 0x410; reg += 4)
570 ptr += sprintf(ptr, "draw %08x = %08x\n",
571 reg, inreg(draw, reg));
572
573 for (reg = 0x440; reg <= 0x450; reg += 4)
574 ptr += sprintf(ptr, "draw %08x = %08x\n",
575 reg, inreg(draw, reg));
576
577 return ptr - buf;
578 }
579
580 static DEVICE_ATTR_RO(dispregs);
581
mb862xx_intr(int irq,void * dev_id)582 static irqreturn_t mb862xx_intr(int irq, void *dev_id)
583 {
584 struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id;
585 unsigned long reg_ist, mask;
586
587 if (!par)
588 return IRQ_NONE;
589
590 if (par->type == BT_CARMINE) {
591 /* Get Interrupt Status */
592 reg_ist = inreg(ctrl, GC_CTRL_STATUS);
593 mask = inreg(ctrl, GC_CTRL_INT_MASK);
594 if (reg_ist == 0)
595 return IRQ_HANDLED;
596
597 reg_ist &= mask;
598 if (reg_ist == 0)
599 return IRQ_HANDLED;
600
601 /* Clear interrupt status */
602 outreg(ctrl, 0x0, reg_ist);
603 } else {
604 /* Get status */
605 reg_ist = inreg(host, GC_IST);
606 mask = inreg(host, GC_IMASK);
607
608 reg_ist &= mask;
609 if (reg_ist == 0)
610 return IRQ_HANDLED;
611
612 /* Clear status */
613 outreg(host, GC_IST, ~reg_ist);
614 }
615 return IRQ_HANDLED;
616 }
617
618 #if defined(CONFIG_FB_MB862XX_LIME)
619 /*
620 * GDC (Lime, Coral(B/Q), Mint, ...) on host bus
621 */
mb862xx_gdc_init(struct mb862xxfb_par * par)622 static int mb862xx_gdc_init(struct mb862xxfb_par *par)
623 {
624 unsigned long ccf, mmr;
625 unsigned long ver, rev;
626
627 if (!par)
628 return -ENODEV;
629
630 #if defined(CONFIG_FB_PRE_INIT_FB)
631 par->pre_init = 1;
632 #endif
633 par->host = par->mmio_base;
634 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
635 par->disp = par->mmio_base + MB862XX_DISP_BASE;
636 par->cap = par->mmio_base + MB862XX_CAP_BASE;
637 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
638 par->geo = par->mmio_base + MB862XX_GEO_BASE;
639 par->pio = par->mmio_base + MB862XX_PIO_BASE;
640
641 par->refclk = GC_DISP_REFCLK_400;
642
643 ver = inreg(host, GC_CID);
644 rev = inreg(pio, GC_REVISION);
645 if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) {
646 dev_info(par->dev, "Fujitsu Lime v1.%d found\n",
647 (int)rev & 0xff);
648 par->type = BT_LIME;
649 ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100;
650 mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2;
651 } else {
652 dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev);
653 return -ENODEV;
654 }
655
656 if (!par->pre_init) {
657 outreg(host, GC_CCF, ccf);
658 udelay(200);
659 outreg(host, GC_MMR, mmr);
660 udelay(10);
661 }
662
663 /* interrupt status */
664 outreg(host, GC_IST, 0);
665 outreg(host, GC_IMASK, GC_INT_EN);
666 return 0;
667 }
668
of_platform_mb862xx_probe(struct platform_device * ofdev)669 static int of_platform_mb862xx_probe(struct platform_device *ofdev)
670 {
671 struct device_node *np = ofdev->dev.of_node;
672 struct device *dev = &ofdev->dev;
673 struct mb862xxfb_par *par;
674 struct fb_info *info;
675 struct resource res;
676 resource_size_t res_size;
677 unsigned long ret = -ENODEV;
678
679 if (of_address_to_resource(np, 0, &res)) {
680 dev_err(dev, "Invalid address\n");
681 return -ENXIO;
682 }
683
684 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
685 if (!info)
686 return -ENOMEM;
687
688 par = info->par;
689 par->info = info;
690 par->dev = dev;
691
692 par->irq = irq_of_parse_and_map(np, 0);
693 if (!par->irq) {
694 dev_err(dev, "failed to map irq\n");
695 ret = -ENODEV;
696 goto fbrel;
697 }
698
699 res_size = resource_size(&res);
700 par->res = request_mem_region(res.start, res_size, DRV_NAME);
701 if (par->res == NULL) {
702 dev_err(dev, "Cannot claim framebuffer/mmio\n");
703 ret = -ENXIO;
704 goto irqdisp;
705 }
706
707 #if defined(CONFIG_SOCRATES)
708 par->gc_mode = &socrates_gc_mode;
709 #endif
710
711 par->fb_base_phys = res.start;
712 par->mmio_base_phys = res.start + MB862XX_MMIO_BASE;
713 par->mmio_len = MB862XX_MMIO_SIZE;
714 if (par->gc_mode)
715 par->mapped_vram = par->gc_mode->max_vram;
716 else
717 par->mapped_vram = MB862XX_MEM_SIZE;
718
719 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
720 if (par->fb_base == NULL) {
721 dev_err(dev, "Cannot map framebuffer\n");
722 goto rel_reg;
723 }
724
725 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
726 if (par->mmio_base == NULL) {
727 dev_err(dev, "Cannot map registers\n");
728 goto fb_unmap;
729 }
730
731 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
732 (u64)par->fb_base_phys, (ulong)par->mapped_vram);
733 dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n",
734 (u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq);
735
736 if (mb862xx_gdc_init(par))
737 goto io_unmap;
738
739 if (request_irq(par->irq, mb862xx_intr, 0,
740 DRV_NAME, (void *)par)) {
741 dev_err(dev, "Cannot request irq\n");
742 goto io_unmap;
743 }
744
745 mb862xxfb_init_fbinfo(info);
746
747 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
748 dev_err(dev, "Could not allocate cmap for fb_info.\n");
749 goto free_irq;
750 }
751
752 if ((info->fbops->fb_set_par)(info))
753 dev_err(dev, "set_var() failed on initial setup?\n");
754
755 if (register_framebuffer(info)) {
756 dev_err(dev, "failed to register framebuffer\n");
757 goto rel_cmap;
758 }
759
760 dev_set_drvdata(dev, info);
761
762 if (device_create_file(dev, &dev_attr_dispregs))
763 dev_err(dev, "Can't create sysfs regdump file\n");
764 return 0;
765
766 rel_cmap:
767 fb_dealloc_cmap(&info->cmap);
768 free_irq:
769 outreg(host, GC_IMASK, 0);
770 free_irq(par->irq, (void *)par);
771 io_unmap:
772 iounmap(par->mmio_base);
773 fb_unmap:
774 iounmap(par->fb_base);
775 rel_reg:
776 release_mem_region(res.start, res_size);
777 irqdisp:
778 irq_dispose_mapping(par->irq);
779 fbrel:
780 framebuffer_release(info);
781 return ret;
782 }
783
of_platform_mb862xx_remove(struct platform_device * ofdev)784 static void of_platform_mb862xx_remove(struct platform_device *ofdev)
785 {
786 struct fb_info *fbi = dev_get_drvdata(&ofdev->dev);
787 struct mb862xxfb_par *par = fbi->par;
788 resource_size_t res_size = resource_size(par->res);
789 unsigned long reg;
790
791 fb_dbg(fbi, "%s release\n", fbi->fix.id);
792
793 /* display off */
794 reg = inreg(disp, GC_DCM1);
795 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
796 outreg(disp, GC_DCM1, reg);
797
798 /* disable interrupts */
799 outreg(host, GC_IMASK, 0);
800
801 free_irq(par->irq, (void *)par);
802 irq_dispose_mapping(par->irq);
803
804 device_remove_file(&ofdev->dev, &dev_attr_dispregs);
805
806 unregister_framebuffer(fbi);
807 fb_dealloc_cmap(&fbi->cmap);
808
809 iounmap(par->mmio_base);
810 iounmap(par->fb_base);
811
812 release_mem_region(par->res->start, res_size);
813 framebuffer_release(fbi);
814 }
815
816 /*
817 * common types
818 */
819 static struct of_device_id of_platform_mb862xx_tbl[] = {
820 { .compatible = "fujitsu,MB86276", },
821 { .compatible = "fujitsu,lime", },
822 { .compatible = "fujitsu,MB86277", },
823 { .compatible = "fujitsu,mint", },
824 { .compatible = "fujitsu,MB86293", },
825 { .compatible = "fujitsu,MB86294", },
826 { .compatible = "fujitsu,coral", },
827 { /* end */ }
828 };
829 MODULE_DEVICE_TABLE(of, of_platform_mb862xx_tbl);
830
831 static struct platform_driver of_platform_mb862xxfb_driver = {
832 .driver = {
833 .name = DRV_NAME,
834 .of_match_table = of_platform_mb862xx_tbl,
835 },
836 .probe = of_platform_mb862xx_probe,
837 .remove_new = of_platform_mb862xx_remove,
838 };
839 #endif
840
841 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
coralp_init(struct mb862xxfb_par * par)842 static int coralp_init(struct mb862xxfb_par *par)
843 {
844 int cn, ver;
845
846 par->host = par->mmio_base;
847 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
848 par->disp = par->mmio_base + MB862XX_DISP_BASE;
849 par->cap = par->mmio_base + MB862XX_CAP_BASE;
850 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
851 par->geo = par->mmio_base + MB862XX_GEO_BASE;
852 par->pio = par->mmio_base + MB862XX_PIO_BASE;
853
854 par->refclk = GC_DISP_REFCLK_400;
855
856 if (par->mapped_vram >= 0x2000000) {
857 /* relocate gdc registers space */
858 writel(1, par->fb_base + MB862XX_MMIO_BASE + GC_RSW);
859 udelay(1); /* wait at least 20 bus cycles */
860 }
861
862 ver = inreg(host, GC_CID);
863 cn = (ver & GC_CID_CNAME_MSK) >> 8;
864 ver = ver & GC_CID_VERSION_MSK;
865 if (cn == 3) {
866 unsigned long reg;
867
868 dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
869 (ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
870 par->pdev->revision);
871 reg = inreg(disp, GC_DCM1);
872 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E)
873 par->pre_init = 1;
874
875 if (!par->pre_init) {
876 outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
877 udelay(200);
878 outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
879 udelay(10);
880 }
881 /* Clear interrupt status */
882 outreg(host, GC_IST, 0);
883 } else {
884 return -ENODEV;
885 }
886
887 mb862xx_i2c_init(par);
888 return 0;
889 }
890
init_dram_ctrl(struct mb862xxfb_par * par)891 static int init_dram_ctrl(struct mb862xxfb_par *par)
892 {
893 unsigned long i = 0;
894
895 /*
896 * Set io mode first! Spec. says IC may be destroyed
897 * if not set to SSTL2/LVCMOS before init.
898 */
899 outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0);
900
901 /* DRAM init */
902 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD);
903 outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE);
904 outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2,
905 GC_EVB_DCTL_REFRESH_SETTIME2);
906 outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1);
907 outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1);
908 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES);
909
910 /* DLL reset done? */
911 while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) {
912 udelay(GC_DCTL_INIT_WAIT_INTERVAL);
913 if (i++ > GC_DCTL_INIT_WAIT_CNT) {
914 dev_err(par->dev, "VRAM init failed.\n");
915 return -EINVAL;
916 }
917 }
918 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST);
919 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST);
920 return 0;
921 }
922
carmine_init(struct mb862xxfb_par * par)923 static int carmine_init(struct mb862xxfb_par *par)
924 {
925 unsigned long reg;
926
927 par->ctrl = par->mmio_base + MB86297_CTRL_BASE;
928 par->i2c = par->mmio_base + MB86297_I2C_BASE;
929 par->disp = par->mmio_base + MB86297_DISP0_BASE;
930 par->disp1 = par->mmio_base + MB86297_DISP1_BASE;
931 par->cap = par->mmio_base + MB86297_CAP0_BASE;
932 par->cap1 = par->mmio_base + MB86297_CAP1_BASE;
933 par->draw = par->mmio_base + MB86297_DRAW_BASE;
934 par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;
935 par->wrback = par->mmio_base + MB86297_WRBACK_BASE;
936
937 par->refclk = GC_DISP_REFCLK_533;
938
939 /* warm up */
940 reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0;
941 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
942
943 /* check for engine module revision */
944 if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION)
945 dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n",
946 par->pdev->revision);
947 else
948 goto err_init;
949
950 reg &= ~GC_CTRL_CLK_EN_2D3D;
951 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
952
953 /* set up vram */
954 if (init_dram_ctrl(par) < 0)
955 goto err_init;
956
957 outreg(ctrl, GC_CTRL_INT_MASK, 0);
958 return 0;
959
960 err_init:
961 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
962 return -EINVAL;
963 }
964
mb862xx_pci_gdc_init(struct mb862xxfb_par * par)965 static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par)
966 {
967 switch (par->type) {
968 case BT_CORALP:
969 return coralp_init(par);
970 case BT_CARMINE:
971 return carmine_init(par);
972 default:
973 return -ENODEV;
974 }
975 }
976
977 #define CHIP_ID(id) \
978 { PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) }
979
980 static const struct pci_device_id mb862xx_pci_tbl[] = {
981 /* MB86295/MB86296 */
982 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP),
983 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA),
984 /* MB86297 */
985 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE),
986 { 0, }
987 };
988
989 MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl);
990
mb862xx_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)991 static int mb862xx_pci_probe(struct pci_dev *pdev,
992 const struct pci_device_id *ent)
993 {
994 struct mb862xxfb_par *par;
995 struct fb_info *info;
996 struct device *dev = &pdev->dev;
997 int ret;
998
999 ret = aperture_remove_conflicting_pci_devices(pdev, "mb862xxfb");
1000 if (ret)
1001 return ret;
1002
1003 ret = pci_enable_device(pdev);
1004 if (ret < 0) {
1005 dev_err(dev, "Cannot enable PCI device\n");
1006 goto out;
1007 }
1008
1009 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
1010 if (!info) {
1011 ret = -ENOMEM;
1012 goto dis_dev;
1013 }
1014
1015 par = info->par;
1016 par->info = info;
1017 par->dev = dev;
1018 par->pdev = pdev;
1019 par->irq = pdev->irq;
1020
1021 ret = pci_request_regions(pdev, DRV_NAME);
1022 if (ret < 0) {
1023 dev_err(dev, "Cannot reserve region(s) for PCI device\n");
1024 goto rel_fb;
1025 }
1026
1027 switch (pdev->device) {
1028 case PCI_DEVICE_ID_FUJITSU_CORALP:
1029 case PCI_DEVICE_ID_FUJITSU_CORALPA:
1030 par->fb_base_phys = pci_resource_start(par->pdev, 0);
1031 par->mapped_vram = CORALP_MEM_SIZE;
1032 if (par->mapped_vram >= 0x2000000) {
1033 par->mmio_base_phys = par->fb_base_phys +
1034 MB862XX_MMIO_HIGH_BASE;
1035 } else {
1036 par->mmio_base_phys = par->fb_base_phys +
1037 MB862XX_MMIO_BASE;
1038 }
1039 par->mmio_len = MB862XX_MMIO_SIZE;
1040 par->type = BT_CORALP;
1041 break;
1042 case PCI_DEVICE_ID_FUJITSU_CARMINE:
1043 par->fb_base_phys = pci_resource_start(par->pdev, 2);
1044 par->mmio_base_phys = pci_resource_start(par->pdev, 3);
1045 par->mmio_len = pci_resource_len(par->pdev, 3);
1046 par->mapped_vram = CARMINE_MEM_SIZE;
1047 par->type = BT_CARMINE;
1048 break;
1049 default:
1050 /* should never occur */
1051 ret = -EIO;
1052 goto rel_reg;
1053 }
1054
1055 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
1056 if (par->fb_base == NULL) {
1057 dev_err(dev, "Cannot map framebuffer\n");
1058 ret = -EIO;
1059 goto rel_reg;
1060 }
1061
1062 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
1063 if (par->mmio_base == NULL) {
1064 dev_err(dev, "Cannot map registers\n");
1065 ret = -EIO;
1066 goto fb_unmap;
1067 }
1068
1069 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
1070 (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
1071 dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
1072 (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
1073
1074 ret = mb862xx_pci_gdc_init(par);
1075 if (ret)
1076 goto io_unmap;
1077
1078 ret = request_irq(par->irq, mb862xx_intr, IRQF_SHARED,
1079 DRV_NAME, (void *)par);
1080 if (ret) {
1081 dev_err(dev, "Cannot request irq\n");
1082 goto io_unmap;
1083 }
1084
1085 mb862xxfb_init_fbinfo(info);
1086
1087 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
1088 dev_err(dev, "Could not allocate cmap for fb_info.\n");
1089 ret = -ENOMEM;
1090 goto free_irq;
1091 }
1092
1093 if ((info->fbops->fb_set_par)(info))
1094 dev_err(dev, "set_var() failed on initial setup?\n");
1095
1096 ret = register_framebuffer(info);
1097 if (ret < 0) {
1098 dev_err(dev, "failed to register framebuffer\n");
1099 goto rel_cmap;
1100 }
1101
1102 pci_set_drvdata(pdev, info);
1103
1104 if (device_create_file(dev, &dev_attr_dispregs))
1105 dev_err(dev, "Can't create sysfs regdump file\n");
1106
1107 if (par->type == BT_CARMINE)
1108 outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN);
1109 else
1110 outreg(host, GC_IMASK, GC_INT_EN);
1111
1112 return 0;
1113
1114 rel_cmap:
1115 fb_dealloc_cmap(&info->cmap);
1116 free_irq:
1117 free_irq(par->irq, (void *)par);
1118 io_unmap:
1119 iounmap(par->mmio_base);
1120 fb_unmap:
1121 iounmap(par->fb_base);
1122 rel_reg:
1123 pci_release_regions(pdev);
1124 rel_fb:
1125 framebuffer_release(info);
1126 dis_dev:
1127 pci_disable_device(pdev);
1128 out:
1129 return ret;
1130 }
1131
mb862xx_pci_remove(struct pci_dev * pdev)1132 static void mb862xx_pci_remove(struct pci_dev *pdev)
1133 {
1134 struct fb_info *fbi = pci_get_drvdata(pdev);
1135 struct mb862xxfb_par *par = fbi->par;
1136 unsigned long reg;
1137
1138 fb_dbg(fbi, "%s release\n", fbi->fix.id);
1139
1140 /* display off */
1141 reg = inreg(disp, GC_DCM1);
1142 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
1143 outreg(disp, GC_DCM1, reg);
1144
1145 if (par->type == BT_CARMINE) {
1146 outreg(ctrl, GC_CTRL_INT_MASK, 0);
1147 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
1148 } else {
1149 outreg(host, GC_IMASK, 0);
1150 }
1151
1152 mb862xx_i2c_exit(par);
1153
1154 device_remove_file(&pdev->dev, &dev_attr_dispregs);
1155
1156 unregister_framebuffer(fbi);
1157 fb_dealloc_cmap(&fbi->cmap);
1158
1159 free_irq(par->irq, (void *)par);
1160 iounmap(par->mmio_base);
1161 iounmap(par->fb_base);
1162
1163 pci_release_regions(pdev);
1164 framebuffer_release(fbi);
1165 pci_disable_device(pdev);
1166 }
1167
1168 static struct pci_driver mb862xxfb_pci_driver = {
1169 .name = DRV_NAME,
1170 .id_table = mb862xx_pci_tbl,
1171 .probe = mb862xx_pci_probe,
1172 .remove = mb862xx_pci_remove,
1173 };
1174 #endif
1175
mb862xxfb_init(void)1176 static int mb862xxfb_init(void)
1177 {
1178 int ret = -ENODEV;
1179
1180 if (fb_modesetting_disabled(DRV_NAME))
1181 return -ENODEV;
1182
1183 #if defined(CONFIG_FB_MB862XX_LIME)
1184 ret = platform_driver_register(&of_platform_mb862xxfb_driver);
1185 #endif
1186 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1187 ret = pci_register_driver(&mb862xxfb_pci_driver);
1188 #endif
1189 return ret;
1190 }
1191
mb862xxfb_exit(void)1192 static void __exit mb862xxfb_exit(void)
1193 {
1194 #if defined(CONFIG_FB_MB862XX_LIME)
1195 platform_driver_unregister(&of_platform_mb862xxfb_driver);
1196 #endif
1197 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1198 pci_unregister_driver(&mb862xxfb_pci_driver);
1199 #endif
1200 }
1201
1202 module_init(mb862xxfb_init);
1203 module_exit(mb862xxfb_exit);
1204
1205 MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver");
1206 MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
1207 MODULE_LICENSE("GPL v2");
1208