1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2022 MediaTek Inc.
4  * Author: Garmin Chang <garmin.chang@mediatek.com>
5  */
6 
7 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
8 #include <linux/mod_devicetable.h>
9 #include <linux/platform_device.h>
10 
11 #include "clk-gate.h"
12 #include "clk-mtk.h"
13 #include "clk-mux.h"
14 
15 static DEFINE_SPINLOCK(mt8188_clk_lock);
16 
17 static const struct mtk_fixed_clk top_fixed_clks[] = {
18 	FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc_ck1", NULL, 260000000),
19 	FIXED_CLK(CLK_TOP_MPHONE_SLAVE_BCK, "mphone_slave_bck", NULL, 49152000),
20 	FIXED_CLK(CLK_TOP_PAD_FPC, "pad_fpc_ck", NULL, 50000000),
21 	FIXED_CLK(CLK_TOP_466M_FMEM, "hd_466m_fmem_ck", NULL, 533000000),
22 	FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL, 250000000),
23 	FIXED_CLK(CLK_TOP_DSI_PHY, "dsi_phy", NULL, 500000000),
24 };
25 
26 static const struct mtk_fixed_factor top_divs[] = {
27 	FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
28 	FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
29 	FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
30 	FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
31 	FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
32 	FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
33 	FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
34 	FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
35 	FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
36 	FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
37 	FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
38 	FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
39 	FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8),
40 	FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
41 	FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
42 	FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
43 	FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
44 	FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9),
45 	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
46 	FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
47 	FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
48 	FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
49 	FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
50 	FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
51 	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
52 	FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
53 	FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
54 	FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
55 	FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
56 	FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
57 	FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
58 	FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
59 	FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
60 	FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
61 	FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
62 	FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
63 	FACTOR(CLK_TOP_UNIVPLL_192M_D10, "univpll_192m_d10", "univpll_192m", 1, 10),
64 	FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
65 	FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
66 	FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3),
67 	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
68 	FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3),
69 	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
70 	FACTOR(CLK_TOP_APLL3_D4, "apll3_d4", "apll3", 1, 4),
71 	FACTOR(CLK_TOP_APLL4_D4, "apll4_d4", "apll4", 1, 4),
72 	FACTOR(CLK_TOP_APLL5_D4, "apll5_d4", "apll5", 1, 4),
73 	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
74 	FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
75 	FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
76 	FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
77 	FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
78 	FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
79 	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
80 	FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
81 	FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9),
82 	FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2),
83 	FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4),
84 	FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8),
85 	FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1, 16),
86 	FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2),
87 	FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4),
88 	FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8),
89 	FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 1, 16),
90 	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
91 	FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
92 	FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll", 1, 2),
93 	FACTOR(CLK_TOP_ETHPLL_D4, "ethpll_d4", "ethpll", 1, 4),
94 	FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll", 1, 8),
95 	FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll", 1, 10),
96 	FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll", 1, 2),
97 	FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
98 	FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll", 1, 8),
99 	FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc_ck1", 1, 2),
100 	FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc_ck1", 1, 4),
101 	FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc_ck1", 1, 8),
102 	FACTOR(CLK_TOP_ULPOSC1_D7, "ulposc1_d7", "ulposc_ck1", 1, 7),
103 	FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc_ck1", 1, 10),
104 	FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc_ck1", 1, 16),
105 };
106 
107 static const char * const axi_parents[] = {
108 	"clk26m",
109 	"mainpll_d4_d4",
110 	"mainpll_d7_d2",
111 	"mainpll_d4_d2",
112 	"mainpll_d5_d2",
113 	"mainpll_d6_d2",
114 	"ulposc1_d4"
115 };
116 
117 static const char * const spm_parents[] = {
118 	"clk26m",
119 	"ulposc1_d10",
120 	"mainpll_d7_d4",
121 	"clk32k"
122 };
123 
124 static const char * const scp_parents[] = {
125 	"clk26m",
126 	"univpll_d4",
127 	"mainpll_d6",
128 	"univpll_d6",
129 	"univpll_d4_d2",
130 	"mainpll_d4_d2",
131 	"univpll_d3",
132 	"mainpll_d3"
133 };
134 
135 static const char * const bus_aximem_parents[] = {
136 	"clk26m",
137 	"mainpll_d7_d2",
138 	"mainpll_d4_d2",
139 	"mainpll_d5_d2",
140 	"mainpll_d6"
141 };
142 
143 static const char * const vpp_parents[] = {
144 	"clk26m",
145 	"univpll_d6_d2",
146 	"mainpll_d5_d2",
147 	"mmpll_d6_d2",
148 	"univpll_d5_d2",
149 	"univpll_d4_d2",
150 	"mmpll_d4_d2",
151 	"mmpll_d7",
152 	"univpll_d6",
153 	"mainpll_d4",
154 	"mmpll_d5",
155 	"tvdpll1",
156 	"tvdpll2",
157 	"univpll_d4",
158 	"mmpll_d4"
159 };
160 
161 static const char * const ethdr_parents[] = {
162 	"clk26m",
163 	"univpll_d6_d2",
164 	"mainpll_d5_d2",
165 	"mmpll_d6_d2",
166 	"univpll_d5_d2",
167 	"univpll_d4_d2",
168 	"mmpll_d4_d2",
169 	"mmpll_d7",
170 	"univpll_d6",
171 	"mainpll_d4",
172 	"mmpll_d5_d4",
173 	"tvdpll1",
174 	"tvdpll2",
175 	"univpll_d4",
176 	"mmpll_d4"
177 };
178 
179 static const char * const ipe_parents[] = {
180 	"clk26m",
181 	"imgpll",
182 	"mainpll_d4",
183 	"mmpll_d6",
184 	"univpll_d6",
185 	"mainpll_d6",
186 	"mmpll_d4_d2",
187 	"univpll_d4_d2",
188 	"mainpll_d4_d2",
189 	"mmpll_d6_d2",
190 	"univpll_d5_d2",
191 	"mainpll_d7"
192 };
193 
194 static const char * const cam_parents[] = {
195 	"clk26m",
196 	"tvdpll1",
197 	"mainpll_d4",
198 	"mmpll_d4",
199 	"univpll_d4",
200 	"univpll_d5",
201 	"univpll_d6",
202 	"mmpll_d7",
203 	"univpll_d4_d2",
204 	"mainpll_d4_d2",
205 	"imgpll"
206 };
207 
208 static const char * const ccu_parents[] = {
209 	"clk26m",
210 	"univpll_d6",
211 	"mainpll_d4_d2",
212 	"mainpll_d4",
213 	"univpll_d5",
214 	"mainpll_d6",
215 	"mmpll_d6",
216 	"mmpll_d7",
217 	"univpll_d4_d2",
218 	"univpll_d7"
219 };
220 
221 static const char * const ccu_ahb_parents[] = {
222 	"clk26m",
223 	"univpll_d6",
224 	"mainpll_d4_d2",
225 	"mainpll_d4",
226 	"univpll_d5",
227 	"mainpll_d6",
228 	"mmpll_d6",
229 	"mmpll_d7",
230 	"univpll_d4_d2",
231 	"univpll_d7"
232 };
233 
234 static const char * const img_parents[] = {
235 	"clk26m",
236 	"imgpll",
237 	"univpll_d4",
238 	"mainpll_d4",
239 	"univpll_d5",
240 	"mmpll_d6",
241 	"mmpll_d7",
242 	"univpll_d6",
243 	"mainpll_d6",
244 	"mmpll_d4_d2",
245 	"univpll_d4_d2",
246 	"mainpll_d4_d2",
247 	"univpll_d5_d2"
248 };
249 
250 static const char * const camtm_parents[] = {
251 	"clk26m",
252 	"univpll_d4_d4",
253 	"univpll_d6_d2",
254 	"univpll_d6_d4"
255 };
256 
257 static const char * const dsp_parents[] = {
258 	"clk26m",
259 	"univpll_d6_d2",
260 	"univpll_d4_d2",
261 	"univpll_d5",
262 	"univpll_d4",
263 	"mmpll_d4",
264 	"mainpll_d3",
265 	"univpll_d3"
266 };
267 
268 static const char * const dsp1_parents[] = {
269 	"clk26m",
270 	"univpll_d6_d2",
271 	"mainpll_d4_d2",
272 	"univpll_d5",
273 	"mmpll_d5",
274 	"univpll_d4",
275 	"mainpll_d3",
276 	"univpll_d3"
277 };
278 
279 static const char * const dsp2_parents[] = {
280 	"clk26m",
281 	"univpll_d6_d2",
282 	"mainpll_d4_d2",
283 	"univpll_d5",
284 	"mmpll_d5",
285 	"univpll_d4",
286 	"mainpll_d3",
287 	"univpll_d3"
288 };
289 
290 static const char * const dsp3_parents[] = {
291 	"clk26m",
292 	"univpll_d6_d2",
293 	"mainpll_d4_d2",
294 	"univpll_d5",
295 	"mmpll_d5",
296 	"univpll_d4",
297 	"mainpll_d3",
298 	"univpll_d3"
299 };
300 
301 static const char * const dsp4_parents[] = {
302 	"clk26m",
303 	"univpll_d6_d2",
304 	"univpll_d4_d2",
305 	"mainpll_d4",
306 	"univpll_d4",
307 	"mmpll_d4",
308 	"mainpll_d3",
309 	"univpll_d3"
310 };
311 
312 static const char * const dsp5_parents[] = {
313 	"clk26m",
314 	"univpll_d6_d2",
315 	"univpll_d4_d2",
316 	"mainpll_d4",
317 	"univpll_d4",
318 	"mmpll_d4",
319 	"mainpll_d3",
320 	"univpll_d3"
321 };
322 
323 static const char * const dsp6_parents[] = {
324 	"clk26m",
325 	"univpll_d6_d2",
326 	"univpll_d4_d2",
327 	"mainpll_d4",
328 	"univpll_d4",
329 	"mmpll_d4",
330 	"mainpll_d3",
331 	"univpll_d3"
332 };
333 
334 static const char * const dsp7_parents[] = {
335 	"clk26m",
336 	"univpll_d6_d2",
337 	"univpll_d4_d2",
338 	"univpll_d5",
339 	"univpll_d4",
340 	"mmpll_d4",
341 	"mainpll_d3",
342 	"univpll_d3"
343 };
344 
345 static const char * const mfg_core_tmp_parents[] = {
346 	"clk26m",
347 	"mainpll_d5_d2",
348 	"univpll_d6",
349 	"univpll_d7"
350 };
351 
352 static const char * const camtg_parents[] = {
353 	"clk26m",
354 	"univpll_192m_d8",
355 	"univpll_d6_d8",
356 	"univpll_192m_d4",
357 	"univpll_192m_d10",
358 	"clk13m",
359 	"univpll_192m_d16",
360 	"univpll_192m_d32"
361 };
362 
363 static const char * const camtg2_parents[] = {
364 	"clk26m",
365 	"univpll_192m_d8",
366 	"univpll_d6_d8",
367 	"univpll_192m_d4",
368 	"univpll_192m_d10",
369 	"clk13m",
370 	"univpll_192m_d16",
371 	"univpll_192m_d32"
372 };
373 
374 static const char * const camtg3_parents[] = {
375 	"clk26m",
376 	"univpll_192m_d8",
377 	"univpll_d6_d8",
378 	"univpll_192m_d4",
379 	"univpll_192m_d10",
380 	"clk13m",
381 	"univpll_192m_d16",
382 	"univpll_192m_d32"
383 };
384 
385 static const char * const uart_parents[] = {
386 	"clk26m",
387 	"univpll_d6_d8"
388 };
389 
390 static const char * const spi_parents[] = {
391 	"clk26m",
392 	"mainpll_d5_d4",
393 	"mainpll_d6_d4",
394 	"univpll_d6_d4",
395 	"univpll_d6_d2",
396 	"mainpll_d6_d2",
397 	"mainpll_d4_d4",
398 	"univpll_d5_d4"
399 };
400 
401 static const char * const msdc5hclk_parents[] = {
402 	"clk26m",
403 	"mainpll_d4_d2",
404 	"mainpll_d6_d2"
405 };
406 
407 static const char * const msdc50_0_parents[] = {
408 	"clk26m",
409 	"msdcpll",
410 	"msdcpll_d2",
411 	"univpll_d4_d4",
412 	"mainpll_d6_d2",
413 	"univpll_d4_d2"
414 };
415 
416 static const char * const msdc30_1_parents[] = {
417 	"clk26m",
418 	"univpll_d6_d2",
419 	"mainpll_d6_d2",
420 	"mainpll_d7_d2",
421 	"msdcpll_d2"
422 };
423 
424 static const char * const msdc30_2_parents[] = {
425 	"clk26m",
426 	"univpll_d6_d2",
427 	"mainpll_d6_d2",
428 	"mainpll_d7_d2",
429 	"msdcpll_d2"
430 };
431 
432 static const char * const intdir_parents[] = {
433 	"clk26m",
434 	"univpll_d6",
435 	"mainpll_d4",
436 	"univpll_d4"
437 };
438 
439 static const char * const aud_intbus_parents[] = {
440 	"clk26m",
441 	"mainpll_d4_d4",
442 	"mainpll_d7_d4"
443 };
444 
445 static const char * const audio_h_parents[] = {
446 	"clk26m",
447 	"univpll_d7",
448 	"apll1",
449 	"apll2"
450 };
451 
452 static const char * const pwrap_ulposc_parents[] = {
453 	"clk26m",
454 	"ulposc1_d10",
455 	"ulposc1_d7",
456 	"ulposc1_d8",
457 	"ulposc1_d16",
458 	"mainpll_d4_d8",
459 	"univpll_d5_d8",
460 	"tvdpll1_d16"
461 };
462 
463 static const char * const atb_parents[] = {
464 	"clk26m",
465 	"mainpll_d4_d2",
466 	"mainpll_d5_d2"
467 };
468 
469 static const char * const sspm_parents[] = {
470 	"clk26m",
471 	"mainpll_d7_d2",
472 	"mainpll_d6_d2",
473 	"mainpll_d5_d2",
474 	"mainpll_d9",
475 	"mainpll_d4_d2"
476 };
477 
478 static const char * const dp_parents[] = {
479 	"clk26m",
480 	"tvdpll1_d2",
481 	"tvdpll2_d2",
482 	"tvdpll1_d4",
483 	"tvdpll2_d4",
484 	"tvdpll1_d8",
485 	"tvdpll2_d8",
486 	"tvdpll1_d16",
487 	"tvdpll2_d16"
488 };
489 
490 static const char * const edp_parents[] = {
491 	"clk26m",
492 	"tvdpll1_d2",
493 	"tvdpll2_d2",
494 	"tvdpll1_d4",
495 	"tvdpll2_d4",
496 	"tvdpll1_d8",
497 	"tvdpll2_d8",
498 	"tvdpll1_d16",
499 	"tvdpll2_d16"
500 };
501 
502 static const char * const dpi_parents[] = {
503 	"clk26m",
504 	"tvdpll1_d2",
505 	"tvdpll2_d2",
506 	"tvdpll1_d4",
507 	"tvdpll2_d4",
508 	"tvdpll1_d8",
509 	"tvdpll2_d8",
510 	"tvdpll1_d16",
511 	"tvdpll2_d16"
512 };
513 
514 static const char * const disp_pwm0_parents[] = {
515 	"clk26m",
516 	"univpll_d6_d4",
517 	"ulposc1_d2",
518 	"ulposc1_d4",
519 	"ulposc1_d16",
520 	"ethpll_d4"
521 };
522 
523 static const char * const disp_pwm1_parents[] = {
524 	"clk26m",
525 	"univpll_d6_d4",
526 	"ulposc1_d2",
527 	"ulposc1_d4",
528 	"ulposc1_d16"
529 };
530 
531 static const char * const usb_parents[] = {
532 	"clk26m",
533 	"univpll_d5_d4",
534 	"univpll_d6_d4",
535 	"univpll_d5_d2"
536 };
537 
538 static const char * const ssusb_xhci_parents[] = {
539 	"clk26m",
540 	"univpll_d5_d4",
541 	"univpll_d6_d4",
542 	"univpll_d5_d2"
543 };
544 
545 static const char * const usb_2p_parents[] = {
546 	"clk26m",
547 	"univpll_d5_d4",
548 	"univpll_d6_d4",
549 	"univpll_d5_d2"
550 };
551 
552 static const char * const ssusb_xhci_2p_parents[] = {
553 	"clk26m",
554 	"univpll_d5_d4",
555 	"univpll_d6_d4",
556 	"univpll_d5_d2"
557 };
558 
559 static const char * const usb_3p_parents[] = {
560 	"clk26m",
561 	"univpll_d5_d4",
562 	"univpll_d6_d4",
563 	"univpll_d5_d2"
564 };
565 
566 static const char * const ssusb_xhci_3p_parents[] = {
567 	"clk26m",
568 	"univpll_d5_d4",
569 	"univpll_d6_d4",
570 	"univpll_d5_d2"
571 };
572 
573 static const char * const i2c_parents[] = {
574 	"clk26m",
575 	"mainpll_d4_d8",
576 	"univpll_d5_d4"
577 };
578 
579 static const char * const seninf_parents[] = {
580 	"clk26m",
581 	"univpll_d4_d4",
582 	"univpll_d6_d2",
583 	"mainpll_d4_d2",
584 	"univpll_d7",
585 	"univpll_d6",
586 	"mmpll_d6",
587 	"univpll_d5"
588 };
589 
590 static const char * const seninf1_parents[] = {
591 	"clk26m",
592 	"univpll_d4_d4",
593 	"univpll_d6_d2",
594 	"mainpll_d4_d2",
595 	"univpll_d7",
596 	"univpll_d6",
597 	"mmpll_d6",
598 	"univpll_d5"
599 };
600 
601 static const char * const gcpu_parents[] = {
602 	"clk26m",
603 	"mainpll_d6",
604 	"univpll_d4_d2",
605 	"mmpll_d5_d2",
606 	"univpll_d5_d2"
607 };
608 
609 static const char * const venc_parents[] = {
610 	"clk26m",
611 	"mmpll_d4_d2",
612 	"mainpll_d6",
613 	"univpll_d4_d2",
614 	"mainpll_d4_d2",
615 	"univpll_d6",
616 	"mmpll_d6",
617 	"mainpll_d5_d2",
618 	"mainpll_d6_d2",
619 	"mmpll_d9",
620 	"univpll_d4_d4",
621 	"mainpll_d4",
622 	"univpll_d4",
623 	"univpll_d5",
624 	"univpll_d5_d2",
625 	"mainpll_d5"
626 };
627 
628 static const char * const vdec_parents[] = {
629 	"clk26m",
630 	"mainpll_d5_d2",
631 	"mmpll_d6_d2",
632 	"univpll_d5_d2",
633 	"univpll_d4_d2",
634 	"mmpll_d4_d2",
635 	"univpll_d6",
636 	"mainpll_d5",
637 	"univpll_d5",
638 	"mmpll_d6",
639 	"mainpll_d4",
640 	"tvdpll2",
641 	"univpll_d4",
642 	"imgpll",
643 	"univpll_d6_d2",
644 	"mmpll_d9"
645 };
646 
647 static const char * const pwm_parents[] = {
648 	"clk32k",
649 	"clk26m",
650 	"univpll_d4_d8",
651 	"univpll_d6_d4"
652 };
653 
654 static const char * const mcupm_parents[] = {
655 	"clk26m",
656 	"mainpll_d6_d2",
657 	"mainpll_d7_d4"
658 };
659 
660 static const char * const spmi_p_mst_parents[] = {
661 	"clk26m",
662 	"clk13m",
663 	"ulposc1_d8",
664 	"ulposc1_d10",
665 	"ulposc1_d16",
666 	"ulposc1_d7",
667 	"clk32k",
668 	"mainpll_d7_d8",
669 	"mainpll_d6_d8",
670 	"mainpll_d5_d8"
671 };
672 
673 static const char * const spmi_m_mst_parents[] = {
674 	"clk26m",
675 	"clk13m",
676 	"ulposc1_d8",
677 	"ulposc1_d10",
678 	"ulposc1_d16",
679 	"ulposc1_d7",
680 	"clk32k",
681 	"mainpll_d7_d8",
682 	"mainpll_d6_d8",
683 	"mainpll_d5_d8"
684 };
685 
686 static const char * const dvfsrc_parents[] = {
687 	"clk26m",
688 	"ulposc1_d10",
689 	"univpll_d6_d8",
690 	"msdcpll_d16"
691 };
692 
693 static const char * const tl_parents[] = {
694 	"clk26m",
695 	"univpll_d5_d4",
696 	"mainpll_d4_d4"
697 };
698 
699 static const char * const aes_msdcfde_parents[] = {
700 	"clk26m",
701 	"mainpll_d4_d2",
702 	"mainpll_d6",
703 	"mainpll_d4_d4",
704 	"univpll_d4_d2",
705 	"univpll_d6"
706 };
707 
708 static const char * const dsi_occ_parents[] = {
709 	"clk26m",
710 	"univpll_d6_d2",
711 	"univpll_d5_d2",
712 	"univpll_d4_d2"
713 };
714 
715 static const char * const wpe_vpp_parents[] = {
716 	"clk26m",
717 	"mainpll_d5_d2",
718 	"mmpll_d6_d2",
719 	"univpll_d5_d2",
720 	"mainpll_d4_d2",
721 	"univpll_d4_d2",
722 	"mmpll_d4_d2",
723 	"mainpll_d6",
724 	"mmpll_d7",
725 	"univpll_d6",
726 	"mainpll_d5",
727 	"univpll_d5",
728 	"mainpll_d4",
729 	"tvdpll1",
730 	"univpll_d4"
731 };
732 
733 static const char * const hdcp_parents[] = {
734 	"clk26m",
735 	"univpll_d4_d8",
736 	"mainpll_d5_d8",
737 	"univpll_d6_d4"
738 };
739 
740 static const char * const hdcp_24m_parents[] = {
741 	"clk26m",
742 	"univpll_192m_d4",
743 	"univpll_192m_d8",
744 	"univpll_d6_d8"
745 };
746 
747 static const char * const hdmi_apb_parents[] = {
748 	"clk26m",
749 	"univpll_d6_d4",
750 	"msdcpll_d2"
751 };
752 
753 static const char * const snps_eth_250m_parents[] = {
754 	"clk26m",
755 	"ethpll_d2"
756 };
757 
758 static const char * const snps_eth_62p4m_ptp_parents[] = {
759 	"apll2_d3",
760 	"apll1_d3",
761 	"clk26m",
762 	"ethpll_d8"
763 };
764 
765 static const char * const snps_eth_50m_rmii_parents[] = {
766 	"clk26m",
767 	"ethpll_d10"
768 };
769 
770 static const char * const adsp_parents[] = {
771 	"clk26m",
772 	"clk13m",
773 	"mainpll_d6",
774 	"mainpll_d5_d2",
775 	"univpll_d4_d4",
776 	"univpll_d4",
777 	"ulposc1_d2",
778 	"ulposc1_ck1",
779 	"adsppll",
780 	"adsppll_d2",
781 	"adsppll_d4",
782 	"adsppll_d8"
783 };
784 
785 static const char * const audio_local_bus_parents[] = {
786 	"clk26m",
787 	"clk13m",
788 	"mainpll_d4_d4",
789 	"mainpll_d7_d2",
790 	"mainpll_d5_d2",
791 	"mainpll_d4_d2",
792 	"mainpll_d7",
793 	"mainpll_d4",
794 	"univpll_d6",
795 	"ulposc1_ck1",
796 	"ulposc1_d4",
797 	"ulposc1_d2"
798 };
799 
800 static const char * const asm_h_parents[] = {
801 	"clk26m",
802 	"univpll_d6_d4",
803 	"univpll_d6_d2",
804 	"mainpll_d5_d2"
805 };
806 
807 static const char * const asm_l_parents[] = {
808 	"clk26m",
809 	"univpll_d6_d4",
810 	"univpll_d6_d2",
811 	"mainpll_d5_d2"
812 };
813 
814 static const char * const apll1_parents[] = {
815 	"clk26m",
816 	"apll1_d4"
817 };
818 
819 static const char * const apll2_parents[] = {
820 	"clk26m",
821 	"apll2_d4"
822 };
823 
824 static const char * const apll3_parents[] = {
825 	"clk26m",
826 	"apll3_d4"
827 };
828 
829 static const char * const apll4_parents[] = {
830 	"clk26m",
831 	"apll4_d4"
832 };
833 
834 static const char * const apll5_parents[] = {
835 	"clk26m",
836 	"apll5_d4"
837 };
838 
839 static const char * const i2so1_parents[] = {
840 	"clk26m",
841 	"apll1",
842 	"apll2",
843 	"apll3",
844 	"apll4",
845 	"apll5"
846 };
847 
848 static const char * const i2so2_parents[] = {
849 	"clk26m",
850 	"apll1",
851 	"apll2",
852 	"apll3",
853 	"apll4",
854 	"apll5"
855 };
856 
857 static const char * const i2si1_parents[] = {
858 	"clk26m",
859 	"apll1",
860 	"apll2",
861 	"apll3",
862 	"apll4",
863 	"apll5"
864 };
865 
866 static const char * const i2si2_parents[] = {
867 	"clk26m",
868 	"apll1",
869 	"apll2",
870 	"apll3",
871 	"apll4",
872 	"apll5"
873 };
874 
875 static const char * const dptx_parents[] = {
876 	"clk26m",
877 	"apll1",
878 	"apll2",
879 	"apll3",
880 	"apll4",
881 	"apll5"
882 };
883 
884 static const char * const aud_iec_parents[] = {
885 	"clk26m",
886 	"apll1",
887 	"apll2",
888 	"apll3",
889 	"apll4",
890 	"apll5"
891 };
892 
893 static const char * const a1sys_hp_parents[] = {
894 	"clk26m",
895 	"apll1_d4"
896 };
897 
898 static const char * const a2sys_parents[] = {
899 	"clk26m",
900 	"apll2_d4"
901 };
902 
903 static const char * const a3sys_parents[] = {
904 	"clk26m",
905 	"apll3_d4",
906 	"apll4_d4",
907 	"apll5_d4"
908 };
909 
910 static const char * const a4sys_parents[] = {
911 	"clk26m",
912 	"apll3_d4",
913 	"apll4_d4",
914 	"apll5_d4"
915 };
916 
917 static const char * const ecc_parents[] = {
918 	"clk26m",
919 	"mainpll_d4_d4",
920 	"mainpll_d5_d2",
921 	"mainpll_d4_d2",
922 	"mainpll_d6",
923 	"univpll_d6"
924 };
925 
926 static const char * const spinor_parents[] = {
927 	"clk26m",
928 	"clk13m",
929 	"mainpll_d7_d8",
930 	"univpll_d6_d8"
931 };
932 
933 static const char * const ulposc_parents[] = {
934 	"ulposc_ck1",
935 	"ethpll_d2",
936 	"mainpll_d4_d2",
937 	"ethpll_d10"
938 };
939 
940 static const char * const srck_parents[] = {
941 	"ulposc1_d10",
942 	"clk26m"
943 };
944 
945 static const char * const mfg_fast_ref_parents[] = {
946 	"top_mfg_core_tmp",
947 	"mfgpll"
948 };
949 
950 static const struct mtk_mux top_mtk_muxes[] = {
951 	/*
952 	 * CLK_CFG_0
953 	 * axi_sel and bus_aximem_sel are bus clocks, should not be closed by Linux.
954 	 * spm_sel and scp_sel are main clocks in always-on co-processor.
955 	 */
956 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi", axi_parents,
957 				   0x020, 0x024, 0x028, 0, 4, 7, 0x04, 0,
958 				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
959 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm", spm_parents,
960 				   0x020, 0x024, 0x028, 8, 4, 15, 0x04, 1,
961 				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
962 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp", scp_parents,
963 				   0x020, 0x024, 0x028, 16, 4, 23, 0x04, 2,
964 				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
965 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem", bus_aximem_parents,
966 				   0x020, 0x024, 0x028, 24, 4, 31, 0x04, 3,
967 				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
968 	/* CLK_CFG_1 */
969 	MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
970 			     vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4),
971 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
972 			     ethdr_parents, 0x02C, 0x030, 0x034, 8, 4, 15, 0x04, 5),
973 	MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
974 			     ipe_parents, 0x02C, 0x030, 0x034, 16, 4, 23, 0x04, 6),
975 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
976 			     cam_parents, 0x02C, 0x030, 0x034, 24, 4, 31, 0x04, 7),
977 	/* CLK_CFG_2 */
978 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
979 			     ccu_parents, 0x038, 0x03C, 0x040, 0, 4, 7, 0x04, 8),
980 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_AHB, "top_ccu_ahb",
981 			     ccu_ahb_parents, 0x038, 0x03C, 0x040, 8, 4, 15, 0x04, 9),
982 	MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
983 			     img_parents, 0x038, 0x03C, 0x040, 16, 4, 23, 0x04, 10),
984 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
985 			     camtm_parents, 0x038, 0x03C, 0x040, 24, 4, 31, 0x04, 11),
986 	/* CLK_CFG_3 */
987 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
988 			     dsp_parents, 0x044, 0x048, 0x04C, 0, 4, 7, 0x04, 12),
989 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1",
990 			     dsp1_parents, 0x044, 0x048, 0x04C, 8, 4, 15, 0x04, 13),
991 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "top_dsp2",
992 			     dsp2_parents, 0x044, 0x048, 0x04C, 16, 4, 23, 0x04, 14),
993 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "top_dsp3",
994 			     dsp3_parents, 0x044, 0x048, 0x04C, 24, 4, 31, 0x04, 15),
995 	/* CLK_CFG_4 */
996 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4, "top_dsp4",
997 			     dsp4_parents, 0x050, 0x054, 0x058, 0, 4, 7, 0x04, 16),
998 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5, "top_dsp5",
999 			     dsp5_parents, 0x050, 0x054, 0x058, 8, 4, 15, 0x04, 17),
1000 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6, "top_dsp6",
1001 			     dsp6_parents, 0x050, 0x054, 0x058, 16, 4, 23, 0x04, 18),
1002 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7, "top_dsp7",
1003 			     dsp7_parents, 0x050, 0x054, 0x058, 24, 4, 31, 0x04, 19),
1004 	/* CLK_CFG_5 */
1005 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_CORE_TMP, "top_mfg_core_tmp",
1006 			     mfg_core_tmp_parents, 0x05C, 0x060, 0x064, 0, 4, 7, 0x04, 20),
1007 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
1008 			     camtg_parents, 0x05C, 0x060, 0x064, 8, 4, 15, 0x04, 21),
1009 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
1010 			     camtg2_parents, 0x05C, 0x060, 0x064, 16, 4, 23, 0x04, 22),
1011 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
1012 			     camtg3_parents, 0x05C, 0x060, 0x064, 24, 4, 31, 0x04, 23),
1013 	/* CLK_CFG_6 */
1014 	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
1015 			     uart_parents, 0x068, 0x06C, 0x070, 0, 4, 7, 0x04, 24),
1016 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
1017 			     spi_parents, 0x068, 0x06C, 0x070, 8, 4, 15, 0x04, 25),
1018 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
1019 				   msdc5hclk_parents, 0x068, 0x06C, 0x070, 16, 4, 23, 0x04, 26, 0),
1020 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
1021 				   msdc50_0_parents, 0x068, 0x06C, 0x070, 24, 4, 31, 0x04, 27, 0),
1022 	/* CLK_CFG_7 */
1023 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1",
1024 				   msdc30_1_parents, 0x074, 0x078, 0x07C, 0, 4, 7, 0x04, 28, 0),
1025 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2, "top_msdc30_2",
1026 				   msdc30_2_parents, 0x074, 0x078, 0x07C, 8, 4, 15, 0x04, 29, 0),
1027 	MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
1028 			     intdir_parents, 0x074, 0x078, 0x07C, 16, 4, 23, 0x04, 30),
1029 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
1030 			     aud_intbus_parents, 0x074, 0x078, 0x07C, 24, 4, 31, 0x04, 31),
1031 	/* CLK_CFG_8 */
1032 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
1033 			     audio_h_parents, 0x080, 0x084, 0x088, 0, 4, 7, 0x08, 0),
1034 	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
1035 			     pwrap_ulposc_parents, 0x080, 0x084, 0x088, 8, 4, 15, 0x08, 1),
1036 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb",
1037 			     atb_parents, 0x080, 0x084, 0x088, 16, 4, 23, 0x08, 2),
1038 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM, "top_sspm",
1039 			     sspm_parents, 0x080, 0x084, 0x088, 24, 4, 31, 0x08, 3),
1040 	/* CLK_CFG_9 */
1041 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",
1042 			     dp_parents, 0x08C, 0x090, 0x094, 0, 4, 7, 0x08, 4),
1043 	MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp",
1044 			     edp_parents, 0x08C, 0x090, 0x094, 8, 4, 15, 0x08, 5),
1045 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
1046 			     dpi_parents, 0x08C, 0x090, 0x094, 16, 4, 23, 0x08, 6),
1047 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",
1048 			     disp_pwm0_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),
1049 	/* CLK_CFG_10 */
1050 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1, "top_disp_pwm1",
1051 			     disp_pwm1_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),
1052 	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb_top",
1053 			     usb_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9),
1054 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
1055 			     ssusb_xhci_parents, 0x098, 0x09C, 0x0A0, 16, 4, 23, 0x08, 10),
1056 	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_2P, "top_usb_top_2p",
1057 			     usb_2p_parents, 0x098, 0x09C, 0x0A0, 24, 4, 31, 0x08, 11),
1058 	/* CLK_CFG_11 */
1059 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P, "top_ssusb_xhci_2p",
1060 			     ssusb_xhci_2p_parents, 0x0A4, 0x0A8, 0x0AC, 0, 4, 7, 0x08, 12),
1061 	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_3P, "top_usb_top_3p",
1062 			     usb_3p_parents, 0x0A4, 0x0A8, 0x0AC, 8, 4, 15, 0x08, 13),
1063 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P, "top_ssusb_xhci_3p",
1064 			     ssusb_xhci_3p_parents, 0x0A4, 0x0A8, 0x0AC, 16, 4, 23, 0x08, 14),
1065 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
1066 			     i2c_parents, 0x0A4, 0x0A8, 0x0AC, 24, 4, 31, 0x08, 15),
1067 	/* CLK_CFG_12 */
1068 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
1069 			     seninf_parents, 0x0B0, 0x0B4, 0x0B8, 0, 4, 7, 0x08, 16),
1070 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
1071 			     seninf1_parents, 0x0B0, 0x0B4, 0x0B8, 8, 4, 15, 0x08, 17),
1072 	MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU, "top_gcpu",
1073 			     gcpu_parents, 0x0B0, 0x0B4, 0x0B8, 16, 4, 23, 0x08, 18),
1074 	MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
1075 			     venc_parents, 0x0B0, 0x0B4, 0x0B8, 24, 4, 31, 0x08, 19),
1076 	/*
1077 	 * CLK_CFG_13
1078 	 * top_mcupm is main clock in co-processor, should not be handled by Linux.
1079 	 */
1080 	MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
1081 			     vdec_parents, 0x0BC, 0x0C0, 0x0C4, 0, 4, 7, 0x08, 20),
1082 	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
1083 			     pwm_parents, 0x0BC, 0x0C0, 0x0C4, 8, 4, 15, 0x08, 21),
1084 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm", mcupm_parents,
1085 				   0x0BC, 0x0C0, 0x0C4, 16, 4, 23, 0x08, 22,
1086 				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1087 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst",
1088 			     spmi_p_mst_parents, 0x0BC, 0x0C0, 0x0C4, 24, 4, 31, 0x08, 23),
1089 	/*
1090 	 * CLK_CFG_14
1091 	 * dvfsrc_sel is for internal DVFS usage, should not be handled by Linux.
1092 	 */
1093 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst",
1094 			     spmi_m_mst_parents, 0x0C8, 0x0CC, 0x0D0, 0, 4, 7, 0x08, 24),
1095 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc", dvfsrc_parents,
1096 				   0x0C8, 0x0CC, 0x0D0, 8, 4, 15, 0x08, 25,
1097 				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1098 	MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl",
1099 			     tl_parents, 0x0C8, 0x0CC, 0x0D0, 16, 4, 23, 0x08, 26),
1100 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
1101 			     aes_msdcfde_parents, 0x0C8, 0x0CC, 0x0D0, 24, 4, 31, 0x08, 27),
1102 	/* CLK_CFG_15 */
1103 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
1104 			     dsi_occ_parents, 0x0D4, 0x0D8, 0x0DC, 0, 4, 7, 0x08, 28),
1105 	MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP, "top_wpe_vpp",
1106 			     wpe_vpp_parents, 0x0D4, 0x0D8, 0x0DC, 8, 4, 15, 0x08, 29),
1107 	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP, "top_hdcp",
1108 			     hdcp_parents, 0x0D4, 0x0D8, 0x0DC, 16, 4, 23, 0x08, 30),
1109 	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M, "top_hdcp_24m",
1110 			     hdcp_24m_parents, 0x0D4, 0x0D8, 0x0DC, 24, 4, 31, 0x08, 31),
1111 	/* CLK_CFG_16 */
1112 	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB, "top_hdmi_apb",
1113 			     hdmi_apb_parents, 0x0E0, 0x0E4, 0x0E8, 0, 4, 7, 0x0C, 0),
1114 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M, "top_snps_eth_250m",
1115 			     snps_eth_250m_parents, 0x0E0, 0x0E4, 0x0E8, 8, 4, 15, 0x0C, 1),
1116 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP, "top_snps_eth_62p4m_ptp",
1117 			     snps_eth_62p4m_ptp_parents, 0x0E0, 0x0E4, 0x0E8, 16, 4, 23, 0x0C, 2),
1118 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii",
1119 			     snps_eth_50m_rmii_parents, 0x0E0, 0x0E4, 0x0E8, 24, 4, 31, 0x0C, 3),
1120 	/* CLK_CFG_17 */
1121 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "top_adsp",
1122 			     adsp_parents, 0x0EC, 0x0F0, 0x0F4, 0, 4, 7, 0x0C, 4),
1123 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS, "top_audio_local_bus",
1124 			     audio_local_bus_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5),
1125 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H, "top_asm_h",
1126 			     asm_h_parents, 0x0EC, 0x0F0, 0x0F4, 16, 4, 23, 0x0C, 6),
1127 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L, "top_asm_l",
1128 			     asm_l_parents, 0x0EC, 0x0F0, 0x0F4, 24, 4, 31, 0x0C, 7),
1129 	/* CLK_CFG_18 */
1130 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
1131 			     apll1_parents, 0x0F8, 0x0FC, 0x100, 0, 4, 7, 0x0C, 8),
1132 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
1133 			     apll2_parents, 0x0F8, 0x0FC, 0x100, 8, 4, 15, 0x0C, 9),
1134 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3, "top_apll3",
1135 			     apll3_parents, 0x0F8, 0x0FC, 0x100, 16, 4, 23, 0x0C, 10),
1136 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4, "top_apll4",
1137 			     apll4_parents, 0x0F8, 0x0FC, 0x100, 24, 4, 31, 0x0C, 11),
1138 	/* CLK_CFG_19 */
1139 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5",
1140 			     apll5_parents, 0x0104, 0x0108, 0x010C, 0, 4, 7, 0x0C, 12),
1141 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1, "top_i2so1",
1142 			     i2so1_parents, 0x0104, 0x0108, 0x010C, 8, 4, 15, 0x0C, 13),
1143 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2, "top_i2so2",
1144 			     i2so2_parents, 0x0104, 0x0108, 0x010C, 16, 4, 23, 0x0C, 14),
1145 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1, "top_i2si1",
1146 			     i2si1_parents, 0x0104, 0x0108, 0x010C, 24, 4, 31, 0x0C, 15),
1147 	/* CLK_CFG_20 */
1148 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2, "top_i2si2",
1149 			     i2si2_parents, 0x0110, 0x0114, 0x0118, 0, 4, 7, 0x0C, 16),
1150 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX, "top_dptx",
1151 			     dptx_parents, 0x0110, 0x0114, 0x0118, 8, 4, 15, 0x0C, 17),
1152 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC, "top_aud_iec",
1153 			     aud_iec_parents, 0x0110, 0x0114, 0x0118, 16, 4, 23, 0x0C, 18),
1154 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP, "top_a1sys_hp",
1155 			     a1sys_hp_parents, 0x0110, 0x0114, 0x0118, 24, 4, 31, 0x0C, 19),
1156 	/* CLK_CFG_21 */
1157 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS, "top_a2sys",
1158 			     a2sys_parents, 0x011C, 0x0120, 0x0124, 0, 4, 7, 0x0C, 20),
1159 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS, "top_a3sys",
1160 			     a3sys_parents, 0x011C, 0x0120, 0x0124, 8, 4, 15, 0x0C, 21),
1161 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS, "top_a4sys",
1162 			     a4sys_parents, 0x011C, 0x0120, 0x0124, 16, 4, 23, 0x0C, 22),
1163 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC, "top_ecc",
1164 			     ecc_parents, 0x011C, 0x0120, 0x0124, 24, 4, 31, 0x0C, 23),
1165 	/*
1166 	 * CLK_CFG_22
1167 	 * top_ulposc/top_srck are clock source of always on co-processor,
1168 	 * should not be closed by Linux.
1169 	 */
1170 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
1171 			     spinor_parents, 0x0128, 0x012C, 0x0130, 0, 4, 7, 0x0C, 24),
1172 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc", ulposc_parents,
1173 				   0x0128, 0x012C, 0x0130, 8, 4, 15, 0x0C, 25,
1174 				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1175 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck", srck_parents,
1176 				   0x0128, 0x012C, 0x0130, 16, 4, 23, 0x0C, 26,
1177 				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1178 };
1179 
1180 static const struct mtk_composite top_adj_divs[] = {
1181 	DIV_GATE(CLK_TOP_APLL12_CK_DIV0, "apll12_div0", "top_i2si1", 0x0320, 0, 0x0328, 8, 0),
1182 	DIV_GATE(CLK_TOP_APLL12_CK_DIV1, "apll12_div1", "top_i2si2", 0x0320, 1, 0x0328, 8, 8),
1183 	DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "top_i2so1", 0x0320, 2, 0x0328, 8, 16),
1184 	DIV_GATE(CLK_TOP_APLL12_CK_DIV3, "apll12_div3", "top_i2so2", 0x0320, 3, 0x0328, 8, 24),
1185 	DIV_GATE(CLK_TOP_APLL12_CK_DIV4, "apll12_div4", "top_aud_iec", 0x0320, 4, 0x0334, 8, 0),
1186 	DIV_GATE(CLK_TOP_APLL12_CK_DIV9, "apll12_div9", "top_dptx", 0x0320, 9, 0x0338, 8, 8),
1187 };
1188 static const struct mtk_gate_regs top0_cg_regs = {
1189 	.set_ofs = 0x238,
1190 	.clr_ofs = 0x238,
1191 	.sta_ofs = 0x238,
1192 };
1193 
1194 static const struct mtk_gate_regs top1_cg_regs = {
1195 	.set_ofs = 0x250,
1196 	.clr_ofs = 0x250,
1197 	.sta_ofs = 0x250,
1198 };
1199 
1200 #define GATE_TOP0(_id, _name, _parent, _shift)			\
1201 	GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
1202 
1203 #define GATE_TOP1(_id, _name, _parent, _shift)			\
1204 	GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
1205 
1206 static const struct mtk_gate top_clks[] = {
1207 	/* TOP0 */
1208 	GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP0, "cfgreg_clock_vpp0", "top_vpp", 0),
1209 	GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP1, "cfgreg_clock_vpp1", "top_vpp", 1),
1210 	GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO0, "cfgreg_clock_vdo0", "top_vpp", 2),
1211 	GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO1, "cfgreg_clock_vdo1", "top_vpp", 3),
1212 	GATE_TOP0(CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS, "cfgreg_clock_isp_axi_gals", "top_vpp", 4),
1213 	GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP0, "cfgreg_f26m_vpp0", "clk26m", 5),
1214 	GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP1, "cfgreg_f26m_vpp1", "clk26m", 6),
1215 	GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO0, "cfgreg_f26m_vdo0", "clk26m", 7),
1216 	GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO1, "cfgreg_f26m_vdo1", "clk26m", 8),
1217 	GATE_TOP0(CLK_TOP_CFGREG_AUD_F26M_AUD, "cfgreg_aud_f26m_aud", "clk26m", 9),
1218 	GATE_TOP0(CLK_TOP_CFGREG_UNIPLL_SES, "cfgreg_unipll_ses", "univpll_d2", 15),
1219 	GATE_TOP0(CLK_TOP_CFGREG_F_PCIE_PHY_REF, "cfgreg_f_pcie_phy_ref", "clk26m", 18),
1220 	/* TOP1 */
1221 	GATE_TOP1(CLK_TOP_SSUSB_TOP_REF, "ssusb_ref", "clk26m", 0),
1222 	GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 1),
1223 	GATE_TOP1(CLK_TOP_SSUSB_TOP_P1_REF, "ssusb_p1_ref", "clk26m", 2),
1224 	GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref", "clk26m", 3),
1225 	GATE_TOP1(CLK_TOP_SSUSB_TOP_P2_REF, "ssusb_p2_ref", "clk26m", 4),
1226 	GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref", "clk26m", 5),
1227 	GATE_TOP1(CLK_TOP_SSUSB_TOP_P3_REF, "ssusb_p3_ref", "clk26m", 6),
1228 	GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref", "clk26m", 7),
1229 };
1230 
1231 static const struct of_device_id of_match_clk_mt8188_topck[] = {
1232 	{ .compatible = "mediatek,mt8188-topckgen" },
1233 	{ /* sentinel */ }
1234 };
1235 MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_topck);
1236 
1237 /* Register mux notifier for MFG mux */
clk_mt8188_reg_mfg_mux_notifier(struct device * dev,struct clk * clk)1238 static int clk_mt8188_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
1239 {
1240 	struct mtk_mux_nb *mfg_mux_nb;
1241 
1242 	mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
1243 	if (!mfg_mux_nb)
1244 		return -ENOMEM;
1245 
1246 	mfg_mux_nb->ops = &clk_mux_ops;
1247 	mfg_mux_nb->bypass_index = 0; /* Bypass to TOP_MFG_CORE_TMP */
1248 
1249 	return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
1250 }
1251 
clk_mt8188_topck_probe(struct platform_device * pdev)1252 static int clk_mt8188_topck_probe(struct platform_device *pdev)
1253 {
1254 	struct clk_hw_onecell_data *top_clk_data;
1255 	struct device_node *node = pdev->dev.of_node;
1256 	struct clk_hw *hw;
1257 	int r;
1258 	void __iomem *base;
1259 
1260 	top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1261 	if (!top_clk_data)
1262 		return -ENOMEM;
1263 
1264 	base = devm_platform_ioremap_resource(pdev, 0);
1265 	if (IS_ERR(base)) {
1266 		r = PTR_ERR(base);
1267 		goto free_top_data;
1268 	}
1269 
1270 	r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1271 					top_clk_data);
1272 	if (r)
1273 		goto free_top_data;
1274 
1275 	r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1276 	if (r)
1277 		goto unregister_fixed_clks;
1278 
1279 	r = mtk_clk_register_muxes(&pdev->dev, top_mtk_muxes,
1280 				   ARRAY_SIZE(top_mtk_muxes), node,
1281 				   &mt8188_clk_lock, top_clk_data);
1282 	if (r)
1283 		goto unregister_factors;
1284 
1285 	hw = devm_clk_hw_register_mux(&pdev->dev, "mfg_ck_fast_ref", mfg_fast_ref_parents,
1286 				      ARRAY_SIZE(mfg_fast_ref_parents), CLK_SET_RATE_PARENT,
1287 				      (base + 0x250), 8, 1, 0, &mt8188_clk_lock);
1288 	if (IS_ERR(hw)) {
1289 		r = PTR_ERR(hw);
1290 		goto unregister_muxes;
1291 	}
1292 	top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF] = hw;
1293 
1294 	r = clk_mt8188_reg_mfg_mux_notifier(&pdev->dev,
1295 					    top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF]->clk);
1296 	if (r)
1297 		goto unregister_muxes;
1298 
1299 	r = mtk_clk_register_composites(&pdev->dev, top_adj_divs,
1300 					ARRAY_SIZE(top_adj_divs), base,
1301 					&mt8188_clk_lock, top_clk_data);
1302 	if (r)
1303 		goto unregister_muxes;
1304 
1305 	r = mtk_clk_register_gates(&pdev->dev, node, top_clks,
1306 				   ARRAY_SIZE(top_clks), top_clk_data);
1307 	if (r)
1308 		goto unregister_composite_divs;
1309 
1310 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
1311 	if (r)
1312 		goto unregister_gates;
1313 
1314 	platform_set_drvdata(pdev, top_clk_data);
1315 
1316 	return r;
1317 
1318 unregister_gates:
1319 	mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
1320 unregister_composite_divs:
1321 	mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
1322 unregister_muxes:
1323 	mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
1324 unregister_factors:
1325 	mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1326 unregister_fixed_clks:
1327 	mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
1328 free_top_data:
1329 	mtk_free_clk_data(top_clk_data);
1330 	return r;
1331 }
1332 
clk_mt8188_topck_remove(struct platform_device * pdev)1333 static void clk_mt8188_topck_remove(struct platform_device *pdev)
1334 {
1335 	struct clk_hw_onecell_data *top_clk_data = platform_get_drvdata(pdev);
1336 	struct device_node *node = pdev->dev.of_node;
1337 
1338 	of_clk_del_provider(node);
1339 	mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
1340 	mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
1341 	mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
1342 	mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1343 	mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
1344 	mtk_free_clk_data(top_clk_data);
1345 }
1346 
1347 static struct platform_driver clk_mt8188_topck_drv = {
1348 	.probe = clk_mt8188_topck_probe,
1349 	.remove_new = clk_mt8188_topck_remove,
1350 	.driver = {
1351 		.name = "clk-mt8188-topck",
1352 		.of_match_table = of_match_clk_mt8188_topck,
1353 	},
1354 };
1355 module_platform_driver(clk_mt8188_topck_drv);
1356 MODULE_LICENSE("GPL");
1357