xref: /openbmc/linux/drivers/clk/qcom/dispcc-sm8550.c (revision 676bf8fc)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2023, Linaro Ltd.
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/err.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/pm_runtime.h>
16 
17 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
18 
19 #include "common.h"
20 #include "clk-alpha-pll.h"
21 #include "clk-branch.h"
22 #include "clk-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-regmap.h"
25 #include "clk-regmap-divider.h"
26 #include "clk-regmap-mux.h"
27 #include "reset.h"
28 #include "gdsc.h"
29 
30 /* Need to match the order of clocks in DT binding */
31 enum {
32 	DT_BI_TCXO,
33 	DT_BI_TCXO_AO,
34 	DT_AHB_CLK,
35 	DT_SLEEP_CLK,
36 
37 	DT_DSI0_PHY_PLL_OUT_BYTECLK,
38 	DT_DSI0_PHY_PLL_OUT_DSICLK,
39 	DT_DSI1_PHY_PLL_OUT_BYTECLK,
40 	DT_DSI1_PHY_PLL_OUT_DSICLK,
41 
42 	DT_DP0_PHY_PLL_LINK_CLK,
43 	DT_DP0_PHY_PLL_VCO_DIV_CLK,
44 	DT_DP1_PHY_PLL_LINK_CLK,
45 	DT_DP1_PHY_PLL_VCO_DIV_CLK,
46 	DT_DP2_PHY_PLL_LINK_CLK,
47 	DT_DP2_PHY_PLL_VCO_DIV_CLK,
48 	DT_DP3_PHY_PLL_LINK_CLK,
49 	DT_DP3_PHY_PLL_VCO_DIV_CLK,
50 };
51 
52 #define DISP_CC_MISC_CMD	0xF000
53 
54 enum {
55 	P_BI_TCXO,
56 	P_DISP_CC_PLL0_OUT_MAIN,
57 	P_DISP_CC_PLL1_OUT_EVEN,
58 	P_DISP_CC_PLL1_OUT_MAIN,
59 	P_DP0_PHY_PLL_LINK_CLK,
60 	P_DP0_PHY_PLL_VCO_DIV_CLK,
61 	P_DP1_PHY_PLL_LINK_CLK,
62 	P_DP1_PHY_PLL_VCO_DIV_CLK,
63 	P_DP2_PHY_PLL_LINK_CLK,
64 	P_DP2_PHY_PLL_VCO_DIV_CLK,
65 	P_DP3_PHY_PLL_LINK_CLK,
66 	P_DP3_PHY_PLL_VCO_DIV_CLK,
67 	P_DSI0_PHY_PLL_OUT_BYTECLK,
68 	P_DSI0_PHY_PLL_OUT_DSICLK,
69 	P_DSI1_PHY_PLL_OUT_BYTECLK,
70 	P_DSI1_PHY_PLL_OUT_DSICLK,
71 	P_SLEEP_CLK,
72 };
73 
74 static struct pll_vco lucid_ole_vco[] = {
75 	{ 249600000, 2000000000, 0 },
76 };
77 
78 static const struct alpha_pll_config disp_cc_pll0_config = {
79 	.l = 0xd,
80 	.alpha = 0x6492,
81 	.config_ctl_val = 0x20485699,
82 	.config_ctl_hi_val = 0x00182261,
83 	.config_ctl_hi1_val = 0x82aa299c,
84 	.test_ctl_val = 0x00000000,
85 	.test_ctl_hi_val = 0x00000003,
86 	.test_ctl_hi1_val = 0x00009000,
87 	.test_ctl_hi2_val = 0x00000034,
88 	.user_ctl_val = 0x00000000,
89 	.user_ctl_hi_val = 0x00000005,
90 };
91 
92 static struct clk_alpha_pll disp_cc_pll0 = {
93 	.offset = 0x0,
94 	.vco_table = lucid_ole_vco,
95 	.num_vco = ARRAY_SIZE(lucid_ole_vco),
96 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
97 	.clkr = {
98 		.hw.init = &(struct clk_init_data) {
99 			.name = "disp_cc_pll0",
100 			.parent_data = &(const struct clk_parent_data) {
101 				.index = DT_BI_TCXO,
102 			},
103 			.num_parents = 1,
104 			.ops = &clk_alpha_pll_reset_lucid_ole_ops,
105 		},
106 	},
107 };
108 
109 static const struct alpha_pll_config disp_cc_pll1_config = {
110 	.l = 0x1f,
111 	.alpha = 0x4000,
112 	.config_ctl_val = 0x20485699,
113 	.config_ctl_hi_val = 0x00182261,
114 	.config_ctl_hi1_val = 0x82aa299c,
115 	.test_ctl_val = 0x00000000,
116 	.test_ctl_hi_val = 0x00000003,
117 	.test_ctl_hi1_val = 0x00009000,
118 	.test_ctl_hi2_val = 0x00000034,
119 	.user_ctl_val = 0x00000000,
120 	.user_ctl_hi_val = 0x00000005,
121 };
122 
123 static struct clk_alpha_pll disp_cc_pll1 = {
124 	.offset = 0x1000,
125 	.vco_table = lucid_ole_vco,
126 	.num_vco = ARRAY_SIZE(lucid_ole_vco),
127 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
128 	.clkr = {
129 		.hw.init = &(struct clk_init_data) {
130 			.name = "disp_cc_pll1",
131 			.parent_data = &(const struct clk_parent_data) {
132 				.index = DT_BI_TCXO,
133 			},
134 			.num_parents = 1,
135 			.ops = &clk_alpha_pll_reset_lucid_ole_ops,
136 		},
137 	},
138 };
139 
140 static const struct parent_map disp_cc_parent_map_0[] = {
141 	{ P_BI_TCXO, 0 },
142 };
143 
144 static const struct clk_parent_data disp_cc_parent_data_0[] = {
145 	{ .index = DT_BI_TCXO },
146 };
147 
148 static const struct clk_parent_data disp_cc_parent_data_0_ao[] = {
149 	{ .index = DT_BI_TCXO_AO },
150 };
151 
152 static const struct parent_map disp_cc_parent_map_1[] = {
153 	{ P_BI_TCXO, 0 },
154 	{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
155 	{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
156 	{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
157 };
158 
159 static const struct clk_parent_data disp_cc_parent_data_1[] = {
160 	{ .index = DT_BI_TCXO },
161 	{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
162 	{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
163 	{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
164 };
165 
166 static const struct parent_map disp_cc_parent_map_2[] = {
167 	{ P_BI_TCXO, 0 },
168 	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
169 	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
170 	{ P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
171 	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
172 };
173 
174 static const struct clk_parent_data disp_cc_parent_data_2[] = {
175 	{ .index = DT_BI_TCXO },
176 	{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
177 	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
178 	{ .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
179 	{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
180 };
181 
182 static const struct parent_map disp_cc_parent_map_3[] = {
183 	{ P_BI_TCXO, 0 },
184 	{ P_DP1_PHY_PLL_LINK_CLK, 2 },
185 	{ P_DP2_PHY_PLL_LINK_CLK, 3 },
186 	{ P_DP3_PHY_PLL_LINK_CLK, 4 },
187 };
188 
189 static const struct clk_parent_data disp_cc_parent_data_3[] = {
190 	{ .index = DT_BI_TCXO },
191 	{ .index = DT_DP1_PHY_PLL_LINK_CLK },
192 	{ .index = DT_DP2_PHY_PLL_LINK_CLK },
193 	{ .index = DT_DP3_PHY_PLL_LINK_CLK },
194 };
195 
196 static const struct parent_map disp_cc_parent_map_4[] = {
197 	{ P_BI_TCXO, 0 },
198 	{ P_DP0_PHY_PLL_LINK_CLK, 1 },
199 	{ P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
200 	{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
201 	{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
202 	{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
203 };
204 
205 static const struct clk_parent_data disp_cc_parent_data_4[] = {
206 	{ .index = DT_BI_TCXO },
207 	{ .index = DT_DP0_PHY_PLL_LINK_CLK },
208 	{ .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
209 	{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
210 	{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
211 	{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
212 };
213 
214 static const struct parent_map disp_cc_parent_map_5[] = {
215 	{ P_BI_TCXO, 0 },
216 	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
217 	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
218 };
219 
220 static const struct clk_parent_data disp_cc_parent_data_5[] = {
221 	{ .index = DT_BI_TCXO },
222 	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
223 	{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
224 };
225 
226 static const struct parent_map disp_cc_parent_map_6[] = {
227 	{ P_BI_TCXO, 0 },
228 	{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
229 	{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
230 };
231 
232 static const struct clk_parent_data disp_cc_parent_data_6[] = {
233 	{ .index = DT_BI_TCXO },
234 	{ .hw = &disp_cc_pll1.clkr.hw },
235 	{ .hw = &disp_cc_pll1.clkr.hw },
236 };
237 
238 static const struct parent_map disp_cc_parent_map_7[] = {
239 	{ P_BI_TCXO, 0 },
240 	{ P_DP0_PHY_PLL_LINK_CLK, 1 },
241 	{ P_DP1_PHY_PLL_LINK_CLK, 2 },
242 	{ P_DP2_PHY_PLL_LINK_CLK, 3 },
243 	{ P_DP3_PHY_PLL_LINK_CLK, 4 },
244 };
245 
246 static const struct clk_parent_data disp_cc_parent_data_7[] = {
247 	{ .index = DT_BI_TCXO },
248 	{ .index = DT_DP0_PHY_PLL_LINK_CLK },
249 	{ .index = DT_DP1_PHY_PLL_LINK_CLK },
250 	{ .index = DT_DP2_PHY_PLL_LINK_CLK },
251 	{ .index = DT_DP3_PHY_PLL_LINK_CLK },
252 };
253 
254 static const struct parent_map disp_cc_parent_map_8[] = {
255 	{ P_BI_TCXO, 0 },
256 	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
257 	{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
258 	{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
259 };
260 
261 static const struct clk_parent_data disp_cc_parent_data_8[] = {
262 	{ .index = DT_BI_TCXO },
263 	{ .hw = &disp_cc_pll0.clkr.hw },
264 	{ .hw = &disp_cc_pll1.clkr.hw },
265 	{ .hw = &disp_cc_pll1.clkr.hw },
266 };
267 
268 static const struct parent_map disp_cc_parent_map_9[] = {
269 	{ P_SLEEP_CLK, 0 },
270 };
271 
272 static const struct clk_parent_data disp_cc_parent_data_9[] = {
273 	{ .index = DT_SLEEP_CLK },
274 };
275 
276 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
277 	F(19200000, P_BI_TCXO, 1, 0, 0),
278 	F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
279 	F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
280 	{ }
281 };
282 
283 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
284 	.cmd_rcgr = 0x82e8,
285 	.mnd_width = 0,
286 	.hid_width = 5,
287 	.parent_map = disp_cc_parent_map_6,
288 	.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
289 	.clkr.hw.init = &(struct clk_init_data) {
290 		.name = "disp_cc_mdss_ahb_clk_src",
291 		.parent_data = disp_cc_parent_data_6,
292 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
293 		.flags = CLK_SET_RATE_PARENT,
294 		.ops = &clk_rcg2_shared_ops,
295 	},
296 };
297 
298 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
299 	F(19200000, P_BI_TCXO, 1, 0, 0),
300 	{ }
301 };
302 
303 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
304 	.cmd_rcgr = 0x8108,
305 	.mnd_width = 0,
306 	.hid_width = 5,
307 	.parent_map = disp_cc_parent_map_2,
308 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
309 	.clkr.hw.init = &(struct clk_init_data) {
310 		.name = "disp_cc_mdss_byte0_clk_src",
311 		.parent_data = disp_cc_parent_data_2,
312 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
313 		.flags = CLK_SET_RATE_PARENT,
314 		.ops = &clk_byte2_ops,
315 	},
316 };
317 
318 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
319 	.cmd_rcgr = 0x8124,
320 	.mnd_width = 0,
321 	.hid_width = 5,
322 	.parent_map = disp_cc_parent_map_2,
323 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
324 	.clkr.hw.init = &(struct clk_init_data) {
325 		.name = "disp_cc_mdss_byte1_clk_src",
326 		.parent_data = disp_cc_parent_data_2,
327 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
328 		.flags = CLK_SET_RATE_PARENT,
329 		.ops = &clk_byte2_ops,
330 	},
331 };
332 
333 static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
334 	.cmd_rcgr = 0x81bc,
335 	.mnd_width = 0,
336 	.hid_width = 5,
337 	.parent_map = disp_cc_parent_map_0,
338 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
339 	.clkr.hw.init = &(struct clk_init_data) {
340 		.name = "disp_cc_mdss_dptx0_aux_clk_src",
341 		.parent_data = disp_cc_parent_data_0,
342 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
343 		.flags = CLK_SET_RATE_PARENT,
344 		.ops = &clk_rcg2_ops,
345 	},
346 };
347 
348 static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
349 	.cmd_rcgr = 0x8170,
350 	.mnd_width = 0,
351 	.hid_width = 5,
352 	.parent_map = disp_cc_parent_map_7,
353 	.clkr.hw.init = &(struct clk_init_data) {
354 		.name = "disp_cc_mdss_dptx0_link_clk_src",
355 		.parent_data = disp_cc_parent_data_7,
356 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
357 		.flags = CLK_SET_RATE_PARENT,
358 		.ops = &clk_byte2_ops,
359 	},
360 };
361 
362 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {
363 	.cmd_rcgr = 0x818c,
364 	.mnd_width = 16,
365 	.hid_width = 5,
366 	.parent_map = disp_cc_parent_map_4,
367 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
368 	.clkr.hw.init = &(struct clk_init_data) {
369 		.name = "disp_cc_mdss_dptx0_pixel0_clk_src",
370 		.parent_data = disp_cc_parent_data_4,
371 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
372 		.flags = CLK_SET_RATE_PARENT,
373 		.ops = &clk_dp_ops,
374 	},
375 };
376 
377 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {
378 	.cmd_rcgr = 0x81a4,
379 	.mnd_width = 16,
380 	.hid_width = 5,
381 	.parent_map = disp_cc_parent_map_4,
382 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
383 	.clkr.hw.init = &(struct clk_init_data) {
384 		.name = "disp_cc_mdss_dptx0_pixel1_clk_src",
385 		.parent_data = disp_cc_parent_data_4,
386 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
387 		.flags = CLK_SET_RATE_PARENT,
388 		.ops = &clk_dp_ops,
389 	},
390 };
391 
392 static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {
393 	.cmd_rcgr = 0x8220,
394 	.mnd_width = 0,
395 	.hid_width = 5,
396 	.parent_map = disp_cc_parent_map_0,
397 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
398 	.clkr.hw.init = &(struct clk_init_data) {
399 		.name = "disp_cc_mdss_dptx1_aux_clk_src",
400 		.parent_data = disp_cc_parent_data_0,
401 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
402 		.flags = CLK_SET_RATE_PARENT,
403 		.ops = &clk_rcg2_ops,
404 	},
405 };
406 
407 static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
408 	.cmd_rcgr = 0x8204,
409 	.mnd_width = 0,
410 	.hid_width = 5,
411 	.parent_map = disp_cc_parent_map_3,
412 	.clkr.hw.init = &(struct clk_init_data) {
413 		.name = "disp_cc_mdss_dptx1_link_clk_src",
414 		.parent_data = disp_cc_parent_data_3,
415 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
416 		.flags = CLK_SET_RATE_PARENT,
417 		.ops = &clk_byte2_ops,
418 	},
419 };
420 
421 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {
422 	.cmd_rcgr = 0x81d4,
423 	.mnd_width = 16,
424 	.hid_width = 5,
425 	.parent_map = disp_cc_parent_map_1,
426 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
427 	.clkr.hw.init = &(struct clk_init_data) {
428 		.name = "disp_cc_mdss_dptx1_pixel0_clk_src",
429 		.parent_data = disp_cc_parent_data_1,
430 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
431 		.flags = CLK_SET_RATE_PARENT,
432 		.ops = &clk_dp_ops,
433 	},
434 };
435 
436 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {
437 	.cmd_rcgr = 0x81ec,
438 	.mnd_width = 16,
439 	.hid_width = 5,
440 	.parent_map = disp_cc_parent_map_1,
441 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
442 	.clkr.hw.init = &(struct clk_init_data) {
443 		.name = "disp_cc_mdss_dptx1_pixel1_clk_src",
444 		.parent_data = disp_cc_parent_data_1,
445 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
446 		.flags = CLK_SET_RATE_PARENT,
447 		.ops = &clk_dp_ops,
448 	},
449 };
450 
451 static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {
452 	.cmd_rcgr = 0x8284,
453 	.mnd_width = 0,
454 	.hid_width = 5,
455 	.parent_map = disp_cc_parent_map_0,
456 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
457 	.clkr.hw.init = &(struct clk_init_data) {
458 		.name = "disp_cc_mdss_dptx2_aux_clk_src",
459 		.parent_data = disp_cc_parent_data_0,
460 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
461 		.flags = CLK_SET_RATE_PARENT,
462 		.ops = &clk_rcg2_ops,
463 	},
464 };
465 
466 static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
467 	.cmd_rcgr = 0x8238,
468 	.mnd_width = 0,
469 	.hid_width = 5,
470 	.parent_map = disp_cc_parent_map_3,
471 	.clkr.hw.init = &(struct clk_init_data) {
472 		.name = "disp_cc_mdss_dptx2_link_clk_src",
473 		.parent_data = disp_cc_parent_data_3,
474 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
475 		.flags = CLK_SET_RATE_PARENT,
476 		.ops = &clk_byte2_ops,
477 	},
478 };
479 
480 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {
481 	.cmd_rcgr = 0x8254,
482 	.mnd_width = 16,
483 	.hid_width = 5,
484 	.parent_map = disp_cc_parent_map_1,
485 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
486 	.clkr.hw.init = &(struct clk_init_data) {
487 		.name = "disp_cc_mdss_dptx2_pixel0_clk_src",
488 		.parent_data = disp_cc_parent_data_1,
489 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
490 		.flags = CLK_SET_RATE_PARENT,
491 		.ops = &clk_dp_ops,
492 	},
493 };
494 
495 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {
496 	.cmd_rcgr = 0x826c,
497 	.mnd_width = 16,
498 	.hid_width = 5,
499 	.parent_map = disp_cc_parent_map_1,
500 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
501 	.clkr.hw.init = &(struct clk_init_data) {
502 		.name = "disp_cc_mdss_dptx2_pixel1_clk_src",
503 		.parent_data = disp_cc_parent_data_1,
504 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
505 		.flags = CLK_SET_RATE_PARENT,
506 		.ops = &clk_dp_ops,
507 	},
508 };
509 
510 static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {
511 	.cmd_rcgr = 0x82d0,
512 	.mnd_width = 0,
513 	.hid_width = 5,
514 	.parent_map = disp_cc_parent_map_0,
515 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
516 	.clkr.hw.init = &(struct clk_init_data) {
517 		.name = "disp_cc_mdss_dptx3_aux_clk_src",
518 		.parent_data = disp_cc_parent_data_0,
519 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
520 		.flags = CLK_SET_RATE_PARENT,
521 		.ops = &clk_rcg2_ops,
522 	},
523 };
524 
525 static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
526 	.cmd_rcgr = 0x82b4,
527 	.mnd_width = 0,
528 	.hid_width = 5,
529 	.parent_map = disp_cc_parent_map_3,
530 	.clkr.hw.init = &(struct clk_init_data) {
531 		.name = "disp_cc_mdss_dptx3_link_clk_src",
532 		.parent_data = disp_cc_parent_data_3,
533 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
534 		.flags = CLK_SET_RATE_PARENT,
535 		.ops = &clk_byte2_ops,
536 	},
537 };
538 
539 static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {
540 	.cmd_rcgr = 0x829c,
541 	.mnd_width = 16,
542 	.hid_width = 5,
543 	.parent_map = disp_cc_parent_map_1,
544 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
545 	.clkr.hw.init = &(struct clk_init_data) {
546 		.name = "disp_cc_mdss_dptx3_pixel0_clk_src",
547 		.parent_data = disp_cc_parent_data_1,
548 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
549 		.flags = CLK_SET_RATE_PARENT,
550 		.ops = &clk_dp_ops,
551 	},
552 };
553 
554 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
555 	.cmd_rcgr = 0x8140,
556 	.mnd_width = 0,
557 	.hid_width = 5,
558 	.parent_map = disp_cc_parent_map_5,
559 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
560 	.clkr.hw.init = &(struct clk_init_data) {
561 		.name = "disp_cc_mdss_esc0_clk_src",
562 		.parent_data = disp_cc_parent_data_5,
563 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
564 		.flags = CLK_SET_RATE_PARENT,
565 		.ops = &clk_rcg2_shared_ops,
566 	},
567 };
568 
569 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
570 	.cmd_rcgr = 0x8158,
571 	.mnd_width = 0,
572 	.hid_width = 5,
573 	.parent_map = disp_cc_parent_map_5,
574 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
575 	.clkr.hw.init = &(struct clk_init_data) {
576 		.name = "disp_cc_mdss_esc1_clk_src",
577 		.parent_data = disp_cc_parent_data_5,
578 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
579 		.flags = CLK_SET_RATE_PARENT,
580 		.ops = &clk_rcg2_shared_ops,
581 	},
582 };
583 
584 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
585 	F(19200000, P_BI_TCXO, 1, 0, 0),
586 	F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
587 	F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
588 	F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
589 	F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
590 	F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
591 	F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
592 	F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
593 	F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
594 	{ }
595 };
596 
597 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
598 	.cmd_rcgr = 0x80d8,
599 	.mnd_width = 0,
600 	.hid_width = 5,
601 	.parent_map = disp_cc_parent_map_8,
602 	.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
603 	.clkr.hw.init = &(struct clk_init_data) {
604 		.name = "disp_cc_mdss_mdp_clk_src",
605 		.parent_data = disp_cc_parent_data_8,
606 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_8),
607 		.flags = CLK_SET_RATE_PARENT,
608 		.ops = &clk_rcg2_shared_ops,
609 	},
610 };
611 
612 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
613 	.cmd_rcgr = 0x80a8,
614 	.mnd_width = 8,
615 	.hid_width = 5,
616 	.parent_map = disp_cc_parent_map_2,
617 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
618 	.clkr.hw.init = &(struct clk_init_data) {
619 		.name = "disp_cc_mdss_pclk0_clk_src",
620 		.parent_data = disp_cc_parent_data_2,
621 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
622 		.flags = CLK_SET_RATE_PARENT,
623 		.ops = &clk_pixel_ops,
624 	},
625 };
626 
627 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
628 	.cmd_rcgr = 0x80c0,
629 	.mnd_width = 8,
630 	.hid_width = 5,
631 	.parent_map = disp_cc_parent_map_2,
632 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
633 	.clkr.hw.init = &(struct clk_init_data) {
634 		.name = "disp_cc_mdss_pclk1_clk_src",
635 		.parent_data = disp_cc_parent_data_2,
636 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
637 		.flags = CLK_SET_RATE_PARENT,
638 		.ops = &clk_pixel_ops,
639 	},
640 };
641 
642 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
643 	.cmd_rcgr = 0x80f0,
644 	.mnd_width = 0,
645 	.hid_width = 5,
646 	.parent_map = disp_cc_parent_map_0,
647 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
648 	.clkr.hw.init = &(struct clk_init_data) {
649 		.name = "disp_cc_mdss_vsync_clk_src",
650 		.parent_data = disp_cc_parent_data_0,
651 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
652 		.flags = CLK_SET_RATE_PARENT,
653 		.ops = &clk_rcg2_ops,
654 	},
655 };
656 
657 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
658 	F(32000, P_SLEEP_CLK, 1, 0, 0),
659 	{ }
660 };
661 
662 static struct clk_rcg2 disp_cc_sleep_clk_src = {
663 	.cmd_rcgr = 0xe05c,
664 	.mnd_width = 0,
665 	.hid_width = 5,
666 	.parent_map = disp_cc_parent_map_9,
667 	.freq_tbl = ftbl_disp_cc_sleep_clk_src,
668 	.clkr.hw.init = &(struct clk_init_data) {
669 		.name = "disp_cc_sleep_clk_src",
670 		.parent_data = disp_cc_parent_data_9,
671 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_9),
672 		.flags = CLK_SET_RATE_PARENT,
673 		.ops = &clk_rcg2_ops,
674 	},
675 };
676 
677 static struct clk_rcg2 disp_cc_xo_clk_src = {
678 	.cmd_rcgr = 0xe03c,
679 	.mnd_width = 0,
680 	.hid_width = 5,
681 	.parent_map = disp_cc_parent_map_0,
682 	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
683 	.clkr.hw.init = &(struct clk_init_data) {
684 		.name = "disp_cc_xo_clk_src",
685 		.parent_data = disp_cc_parent_data_0_ao,
686 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao),
687 		.flags = CLK_SET_RATE_PARENT,
688 		.ops = &clk_rcg2_ops,
689 	},
690 };
691 
692 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
693 	.reg = 0x8120,
694 	.shift = 0,
695 	.width = 4,
696 	.clkr.hw.init = &(struct clk_init_data) {
697 		.name = "disp_cc_mdss_byte0_div_clk_src",
698 		.parent_hws = (const struct clk_hw*[]) {
699 			&disp_cc_mdss_byte0_clk_src.clkr.hw,
700 		},
701 		.num_parents = 1,
702 		.ops = &clk_regmap_div_ops,
703 	},
704 };
705 
706 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
707 	.reg = 0x813c,
708 	.shift = 0,
709 	.width = 4,
710 	.clkr.hw.init = &(struct clk_init_data) {
711 		.name = "disp_cc_mdss_byte1_div_clk_src",
712 		.parent_hws = (const struct clk_hw*[]) {
713 			&disp_cc_mdss_byte1_clk_src.clkr.hw,
714 		},
715 		.num_parents = 1,
716 		.ops = &clk_regmap_div_ops,
717 	},
718 };
719 
720 static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {
721 	.reg = 0x8188,
722 	.shift = 0,
723 	.width = 4,
724 	.clkr.hw.init = &(struct clk_init_data) {
725 		.name = "disp_cc_mdss_dptx0_link_div_clk_src",
726 		.parent_hws = (const struct clk_hw*[]) {
727 			&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
728 		},
729 		.num_parents = 1,
730 		.flags = CLK_SET_RATE_PARENT,
731 		.ops = &clk_regmap_div_ro_ops,
732 	},
733 };
734 
735 static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {
736 	.reg = 0x821c,
737 	.shift = 0,
738 	.width = 4,
739 	.clkr.hw.init = &(struct clk_init_data) {
740 		.name = "disp_cc_mdss_dptx1_link_div_clk_src",
741 		.parent_hws = (const struct clk_hw*[]) {
742 			&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
743 		},
744 		.num_parents = 1,
745 		.flags = CLK_SET_RATE_PARENT,
746 		.ops = &clk_regmap_div_ro_ops,
747 	},
748 };
749 
750 static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {
751 	.reg = 0x8250,
752 	.shift = 0,
753 	.width = 4,
754 	.clkr.hw.init = &(struct clk_init_data) {
755 		.name = "disp_cc_mdss_dptx2_link_div_clk_src",
756 		.parent_hws = (const struct clk_hw*[]) {
757 			&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
758 		},
759 		.num_parents = 1,
760 		.flags = CLK_SET_RATE_PARENT,
761 		.ops = &clk_regmap_div_ro_ops,
762 	},
763 };
764 
765 static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {
766 	.reg = 0x82cc,
767 	.shift = 0,
768 	.width = 4,
769 	.clkr.hw.init = &(struct clk_init_data) {
770 		.name = "disp_cc_mdss_dptx3_link_div_clk_src",
771 		.parent_hws = (const struct clk_hw*[]) {
772 			&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
773 		},
774 		.num_parents = 1,
775 		.flags = CLK_SET_RATE_PARENT,
776 		.ops = &clk_regmap_div_ro_ops,
777 	},
778 };
779 
780 static struct clk_branch disp_cc_mdss_accu_clk = {
781 	.halt_reg = 0xe058,
782 	.halt_check = BRANCH_HALT_VOTED,
783 	.clkr = {
784 		.enable_reg = 0xe058,
785 		.enable_mask = BIT(0),
786 		.hw.init = &(struct clk_init_data){
787 			.name = "disp_cc_mdss_accu_clk",
788 			.parent_hws = (const struct clk_hw*[]) {
789 				&disp_cc_xo_clk_src.clkr.hw,
790 			},
791 			.num_parents = 1,
792 			.flags = CLK_SET_RATE_PARENT,
793 			.ops = &clk_branch2_ops,
794 		},
795 	},
796 };
797 
798 static struct clk_branch disp_cc_mdss_ahb1_clk = {
799 	.halt_reg = 0xa020,
800 	.halt_check = BRANCH_HALT,
801 	.clkr = {
802 		.enable_reg = 0xa020,
803 		.enable_mask = BIT(0),
804 		.hw.init = &(struct clk_init_data) {
805 			.name = "disp_cc_mdss_ahb1_clk",
806 			.parent_hws = (const struct clk_hw*[]) {
807 				&disp_cc_mdss_ahb_clk_src.clkr.hw,
808 			},
809 			.num_parents = 1,
810 			.flags = CLK_SET_RATE_PARENT,
811 			.ops = &clk_branch2_ops,
812 		},
813 	},
814 };
815 
816 static struct clk_branch disp_cc_mdss_ahb_clk = {
817 	.halt_reg = 0x80a4,
818 	.halt_check = BRANCH_HALT,
819 	.clkr = {
820 		.enable_reg = 0x80a4,
821 		.enable_mask = BIT(0),
822 		.hw.init = &(struct clk_init_data) {
823 			.name = "disp_cc_mdss_ahb_clk",
824 			.parent_hws = (const struct clk_hw*[]) {
825 				&disp_cc_mdss_ahb_clk_src.clkr.hw,
826 			},
827 			.num_parents = 1,
828 			.flags = CLK_SET_RATE_PARENT,
829 			.ops = &clk_branch2_ops,
830 		},
831 	},
832 };
833 
834 static struct clk_branch disp_cc_mdss_byte0_clk = {
835 	.halt_reg = 0x8028,
836 	.halt_check = BRANCH_HALT,
837 	.clkr = {
838 		.enable_reg = 0x8028,
839 		.enable_mask = BIT(0),
840 		.hw.init = &(struct clk_init_data) {
841 			.name = "disp_cc_mdss_byte0_clk",
842 			.parent_hws = (const struct clk_hw*[]) {
843 				&disp_cc_mdss_byte0_clk_src.clkr.hw,
844 			},
845 			.num_parents = 1,
846 			.flags = CLK_SET_RATE_PARENT,
847 			.ops = &clk_branch2_ops,
848 		},
849 	},
850 };
851 
852 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
853 	.halt_reg = 0x802c,
854 	.halt_check = BRANCH_HALT,
855 	.clkr = {
856 		.enable_reg = 0x802c,
857 		.enable_mask = BIT(0),
858 		.hw.init = &(struct clk_init_data) {
859 			.name = "disp_cc_mdss_byte0_intf_clk",
860 			.parent_hws = (const struct clk_hw*[]) {
861 				&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
862 			},
863 			.num_parents = 1,
864 			.flags = CLK_SET_RATE_PARENT,
865 			.ops = &clk_branch2_ops,
866 		},
867 	},
868 };
869 
870 static struct clk_branch disp_cc_mdss_byte1_clk = {
871 	.halt_reg = 0x8030,
872 	.halt_check = BRANCH_HALT,
873 	.clkr = {
874 		.enable_reg = 0x8030,
875 		.enable_mask = BIT(0),
876 		.hw.init = &(struct clk_init_data) {
877 			.name = "disp_cc_mdss_byte1_clk",
878 			.parent_hws = (const struct clk_hw*[]) {
879 				&disp_cc_mdss_byte1_clk_src.clkr.hw,
880 			},
881 			.num_parents = 1,
882 			.flags = CLK_SET_RATE_PARENT,
883 			.ops = &clk_branch2_ops,
884 		},
885 	},
886 };
887 
888 static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
889 	.halt_reg = 0x8034,
890 	.halt_check = BRANCH_HALT,
891 	.clkr = {
892 		.enable_reg = 0x8034,
893 		.enable_mask = BIT(0),
894 		.hw.init = &(struct clk_init_data) {
895 			.name = "disp_cc_mdss_byte1_intf_clk",
896 			.parent_hws = (const struct clk_hw*[]) {
897 				&disp_cc_mdss_byte1_div_clk_src.clkr.hw,
898 			},
899 			.num_parents = 1,
900 			.flags = CLK_SET_RATE_PARENT,
901 			.ops = &clk_branch2_ops,
902 		},
903 	},
904 };
905 
906 static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {
907 	.halt_reg = 0x8058,
908 	.halt_check = BRANCH_HALT,
909 	.clkr = {
910 		.enable_reg = 0x8058,
911 		.enable_mask = BIT(0),
912 		.hw.init = &(struct clk_init_data) {
913 			.name = "disp_cc_mdss_dptx0_aux_clk",
914 			.parent_hws = (const struct clk_hw*[]) {
915 				&disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
916 			},
917 			.num_parents = 1,
918 			.flags = CLK_SET_RATE_PARENT,
919 			.ops = &clk_branch2_ops,
920 		},
921 	},
922 };
923 
924 static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = {
925 	.halt_reg = 0x804c,
926 	.halt_check = BRANCH_HALT,
927 	.clkr = {
928 		.enable_reg = 0x804c,
929 		.enable_mask = BIT(0),
930 		.hw.init = &(struct clk_init_data) {
931 			.name = "disp_cc_mdss_dptx0_crypto_clk",
932 			.parent_hws = (const struct clk_hw*[]) {
933 				&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
934 			},
935 			.num_parents = 1,
936 			.flags = CLK_SET_RATE_PARENT,
937 			.ops = &clk_branch2_ops,
938 		},
939 	},
940 };
941 
942 static struct clk_branch disp_cc_mdss_dptx0_link_clk = {
943 	.halt_reg = 0x8040,
944 	.halt_check = BRANCH_HALT,
945 	.clkr = {
946 		.enable_reg = 0x8040,
947 		.enable_mask = BIT(0),
948 		.hw.init = &(struct clk_init_data) {
949 			.name = "disp_cc_mdss_dptx0_link_clk",
950 			.parent_hws = (const struct clk_hw*[]) {
951 				&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
952 			},
953 			.num_parents = 1,
954 			.flags = CLK_SET_RATE_PARENT,
955 			.ops = &clk_branch2_ops,
956 		},
957 	},
958 };
959 
960 static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {
961 	.halt_reg = 0x8048,
962 	.halt_check = BRANCH_HALT,
963 	.clkr = {
964 		.enable_reg = 0x8048,
965 		.enable_mask = BIT(0),
966 		.hw.init = &(struct clk_init_data) {
967 			.name = "disp_cc_mdss_dptx0_link_intf_clk",
968 			.parent_hws = (const struct clk_hw*[]) {
969 				&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
970 			},
971 			.num_parents = 1,
972 			.flags = CLK_SET_RATE_PARENT,
973 			.ops = &clk_branch2_ops,
974 		},
975 	},
976 };
977 
978 static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {
979 	.halt_reg = 0x8050,
980 	.halt_check = BRANCH_HALT,
981 	.clkr = {
982 		.enable_reg = 0x8050,
983 		.enable_mask = BIT(0),
984 		.hw.init = &(struct clk_init_data) {
985 			.name = "disp_cc_mdss_dptx0_pixel0_clk",
986 			.parent_hws = (const struct clk_hw*[]) {
987 				&disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
988 			},
989 			.num_parents = 1,
990 			.flags = CLK_SET_RATE_PARENT,
991 			.ops = &clk_branch2_ops,
992 		},
993 	},
994 };
995 
996 static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {
997 	.halt_reg = 0x8054,
998 	.halt_check = BRANCH_HALT,
999 	.clkr = {
1000 		.enable_reg = 0x8054,
1001 		.enable_mask = BIT(0),
1002 		.hw.init = &(struct clk_init_data) {
1003 			.name = "disp_cc_mdss_dptx0_pixel1_clk",
1004 			.parent_hws = (const struct clk_hw*[]) {
1005 				&disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
1006 			},
1007 			.num_parents = 1,
1008 			.flags = CLK_SET_RATE_PARENT,
1009 			.ops = &clk_branch2_ops,
1010 		},
1011 	},
1012 };
1013 
1014 static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
1015 	.halt_reg = 0x8044,
1016 	.halt_check = BRANCH_HALT,
1017 	.clkr = {
1018 		.enable_reg = 0x8044,
1019 		.enable_mask = BIT(0),
1020 		.hw.init = &(struct clk_init_data) {
1021 			.name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",
1022 			.parent_hws = (const struct clk_hw*[]) {
1023 				&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1024 			},
1025 			.num_parents = 1,
1026 			.flags = CLK_SET_RATE_PARENT,
1027 			.ops = &clk_branch2_ops,
1028 		},
1029 	},
1030 };
1031 
1032 static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {
1033 	.halt_reg = 0x8074,
1034 	.halt_check = BRANCH_HALT,
1035 	.clkr = {
1036 		.enable_reg = 0x8074,
1037 		.enable_mask = BIT(0),
1038 		.hw.init = &(struct clk_init_data) {
1039 			.name = "disp_cc_mdss_dptx1_aux_clk",
1040 			.parent_hws = (const struct clk_hw*[]) {
1041 				&disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
1042 			},
1043 			.num_parents = 1,
1044 			.flags = CLK_SET_RATE_PARENT,
1045 			.ops = &clk_branch2_ops,
1046 		},
1047 	},
1048 };
1049 
1050 static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = {
1051 	.halt_reg = 0x8070,
1052 	.halt_check = BRANCH_HALT,
1053 	.clkr = {
1054 		.enable_reg = 0x8070,
1055 		.enable_mask = BIT(0),
1056 		.hw.init = &(struct clk_init_data) {
1057 			.name = "disp_cc_mdss_dptx1_crypto_clk",
1058 			.parent_hws = (const struct clk_hw*[]) {
1059 				&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1060 			},
1061 			.num_parents = 1,
1062 			.flags = CLK_SET_RATE_PARENT,
1063 			.ops = &clk_branch2_ops,
1064 		},
1065 	},
1066 };
1067 
1068 static struct clk_branch disp_cc_mdss_dptx1_link_clk = {
1069 	.halt_reg = 0x8064,
1070 	.halt_check = BRANCH_HALT,
1071 	.clkr = {
1072 		.enable_reg = 0x8064,
1073 		.enable_mask = BIT(0),
1074 		.hw.init = &(struct clk_init_data) {
1075 			.name = "disp_cc_mdss_dptx1_link_clk",
1076 			.parent_hws = (const struct clk_hw*[]) {
1077 				&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1078 			},
1079 			.num_parents = 1,
1080 			.flags = CLK_SET_RATE_PARENT,
1081 			.ops = &clk_branch2_ops,
1082 		},
1083 	},
1084 };
1085 
1086 static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {
1087 	.halt_reg = 0x806c,
1088 	.halt_check = BRANCH_HALT,
1089 	.clkr = {
1090 		.enable_reg = 0x806c,
1091 		.enable_mask = BIT(0),
1092 		.hw.init = &(struct clk_init_data) {
1093 			.name = "disp_cc_mdss_dptx1_link_intf_clk",
1094 			.parent_hws = (const struct clk_hw*[]) {
1095 				&disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1096 			},
1097 			.num_parents = 1,
1098 			.flags = CLK_SET_RATE_PARENT,
1099 			.ops = &clk_branch2_ops,
1100 		},
1101 	},
1102 };
1103 
1104 static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {
1105 	.halt_reg = 0x805c,
1106 	.halt_check = BRANCH_HALT,
1107 	.clkr = {
1108 		.enable_reg = 0x805c,
1109 		.enable_mask = BIT(0),
1110 		.hw.init = &(struct clk_init_data) {
1111 			.name = "disp_cc_mdss_dptx1_pixel0_clk",
1112 			.parent_hws = (const struct clk_hw*[]) {
1113 				&disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
1114 			},
1115 			.num_parents = 1,
1116 			.flags = CLK_SET_RATE_PARENT,
1117 			.ops = &clk_branch2_ops,
1118 		},
1119 	},
1120 };
1121 
1122 static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {
1123 	.halt_reg = 0x8060,
1124 	.halt_check = BRANCH_HALT,
1125 	.clkr = {
1126 		.enable_reg = 0x8060,
1127 		.enable_mask = BIT(0),
1128 		.hw.init = &(struct clk_init_data) {
1129 			.name = "disp_cc_mdss_dptx1_pixel1_clk",
1130 			.parent_hws = (const struct clk_hw*[]) {
1131 				&disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
1132 			},
1133 			.num_parents = 1,
1134 			.flags = CLK_SET_RATE_PARENT,
1135 			.ops = &clk_branch2_ops,
1136 		},
1137 	},
1138 };
1139 
1140 static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
1141 	.halt_reg = 0x8068,
1142 	.halt_check = BRANCH_HALT,
1143 	.clkr = {
1144 		.enable_reg = 0x8068,
1145 		.enable_mask = BIT(0),
1146 		.hw.init = &(struct clk_init_data) {
1147 			.name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",
1148 			.parent_hws = (const struct clk_hw*[]) {
1149 				&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1150 			},
1151 			.num_parents = 1,
1152 			.flags = CLK_SET_RATE_PARENT,
1153 			.ops = &clk_branch2_ops,
1154 		},
1155 	},
1156 };
1157 
1158 static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {
1159 	.halt_reg = 0x808c,
1160 	.halt_check = BRANCH_HALT,
1161 	.clkr = {
1162 		.enable_reg = 0x808c,
1163 		.enable_mask = BIT(0),
1164 		.hw.init = &(struct clk_init_data) {
1165 			.name = "disp_cc_mdss_dptx2_aux_clk",
1166 			.parent_hws = (const struct clk_hw*[]) {
1167 				&disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,
1168 			},
1169 			.num_parents = 1,
1170 			.flags = CLK_SET_RATE_PARENT,
1171 			.ops = &clk_branch2_ops,
1172 		},
1173 	},
1174 };
1175 
1176 static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = {
1177 	.halt_reg = 0x8088,
1178 	.halt_check = BRANCH_HALT,
1179 	.clkr = {
1180 		.enable_reg = 0x8088,
1181 		.enable_mask = BIT(0),
1182 		.hw.init = &(struct clk_init_data) {
1183 			.name = "disp_cc_mdss_dptx2_crypto_clk",
1184 			.parent_hws = (const struct clk_hw*[]) {
1185 				&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1186 			},
1187 			.num_parents = 1,
1188 			.flags = CLK_SET_RATE_PARENT,
1189 			.ops = &clk_branch2_ops,
1190 		},
1191 	},
1192 };
1193 
1194 static struct clk_branch disp_cc_mdss_dptx2_link_clk = {
1195 	.halt_reg = 0x8080,
1196 	.halt_check = BRANCH_HALT,
1197 	.clkr = {
1198 		.enable_reg = 0x8080,
1199 		.enable_mask = BIT(0),
1200 		.hw.init = &(struct clk_init_data) {
1201 			.name = "disp_cc_mdss_dptx2_link_clk",
1202 			.parent_hws = (const struct clk_hw*[]) {
1203 				&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1204 			},
1205 			.num_parents = 1,
1206 			.flags = CLK_SET_RATE_PARENT,
1207 			.ops = &clk_branch2_ops,
1208 		},
1209 	},
1210 };
1211 
1212 static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {
1213 	.halt_reg = 0x8084,
1214 	.halt_check = BRANCH_HALT,
1215 	.clkr = {
1216 		.enable_reg = 0x8084,
1217 		.enable_mask = BIT(0),
1218 		.hw.init = &(struct clk_init_data) {
1219 			.name = "disp_cc_mdss_dptx2_link_intf_clk",
1220 			.parent_hws = (const struct clk_hw*[]) {
1221 				&disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
1222 			},
1223 			.num_parents = 1,
1224 			.flags = CLK_SET_RATE_PARENT,
1225 			.ops = &clk_branch2_ops,
1226 		},
1227 	},
1228 };
1229 
1230 static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {
1231 	.halt_reg = 0x8078,
1232 	.halt_check = BRANCH_HALT,
1233 	.clkr = {
1234 		.enable_reg = 0x8078,
1235 		.enable_mask = BIT(0),
1236 		.hw.init = &(struct clk_init_data) {
1237 			.name = "disp_cc_mdss_dptx2_pixel0_clk",
1238 			.parent_hws = (const struct clk_hw*[]) {
1239 				&disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
1240 			},
1241 			.num_parents = 1,
1242 			.flags = CLK_SET_RATE_PARENT,
1243 			.ops = &clk_branch2_ops,
1244 		},
1245 	},
1246 };
1247 
1248 static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {
1249 	.halt_reg = 0x807c,
1250 	.halt_check = BRANCH_HALT,
1251 	.clkr = {
1252 		.enable_reg = 0x807c,
1253 		.enable_mask = BIT(0),
1254 		.hw.init = &(struct clk_init_data) {
1255 			.name = "disp_cc_mdss_dptx2_pixel1_clk",
1256 			.parent_hws = (const struct clk_hw*[]) {
1257 				&disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
1258 			},
1259 			.num_parents = 1,
1260 			.flags = CLK_SET_RATE_PARENT,
1261 			.ops = &clk_branch2_ops,
1262 		},
1263 	},
1264 };
1265 
1266 static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {
1267 	.halt_reg = 0x809c,
1268 	.halt_check = BRANCH_HALT,
1269 	.clkr = {
1270 		.enable_reg = 0x809c,
1271 		.enable_mask = BIT(0),
1272 		.hw.init = &(struct clk_init_data) {
1273 			.name = "disp_cc_mdss_dptx3_aux_clk",
1274 			.parent_hws = (const struct clk_hw*[]) {
1275 				&disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,
1276 			},
1277 			.num_parents = 1,
1278 			.flags = CLK_SET_RATE_PARENT,
1279 			.ops = &clk_branch2_ops,
1280 		},
1281 	},
1282 };
1283 
1284 static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = {
1285 	.halt_reg = 0x80a0,
1286 	.halt_check = BRANCH_HALT,
1287 	.clkr = {
1288 		.enable_reg = 0x80a0,
1289 		.enable_mask = BIT(0),
1290 		.hw.init = &(struct clk_init_data) {
1291 			.name = "disp_cc_mdss_dptx3_crypto_clk",
1292 			.parent_hws = (const struct clk_hw*[]) {
1293 				&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1294 			},
1295 			.num_parents = 1,
1296 			.flags = CLK_SET_RATE_PARENT,
1297 			.ops = &clk_branch2_ops,
1298 		},
1299 	},
1300 };
1301 
1302 static struct clk_branch disp_cc_mdss_dptx3_link_clk = {
1303 	.halt_reg = 0x8094,
1304 	.halt_check = BRANCH_HALT,
1305 	.clkr = {
1306 		.enable_reg = 0x8094,
1307 		.enable_mask = BIT(0),
1308 		.hw.init = &(struct clk_init_data) {
1309 			.name = "disp_cc_mdss_dptx3_link_clk",
1310 			.parent_hws = (const struct clk_hw*[]) {
1311 				&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1312 			},
1313 			.num_parents = 1,
1314 			.flags = CLK_SET_RATE_PARENT,
1315 			.ops = &clk_branch2_ops,
1316 		},
1317 	},
1318 };
1319 
1320 static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {
1321 	.halt_reg = 0x8098,
1322 	.halt_check = BRANCH_HALT,
1323 	.clkr = {
1324 		.enable_reg = 0x8098,
1325 		.enable_mask = BIT(0),
1326 		.hw.init = &(struct clk_init_data) {
1327 			.name = "disp_cc_mdss_dptx3_link_intf_clk",
1328 			.parent_hws = (const struct clk_hw*[]) {
1329 				&disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
1330 			},
1331 			.num_parents = 1,
1332 			.flags = CLK_SET_RATE_PARENT,
1333 			.ops = &clk_branch2_ops,
1334 		},
1335 	},
1336 };
1337 
1338 static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {
1339 	.halt_reg = 0x8090,
1340 	.halt_check = BRANCH_HALT,
1341 	.clkr = {
1342 		.enable_reg = 0x8090,
1343 		.enable_mask = BIT(0),
1344 		.hw.init = &(struct clk_init_data) {
1345 			.name = "disp_cc_mdss_dptx3_pixel0_clk",
1346 			.parent_hws = (const struct clk_hw*[]) {
1347 				&disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
1348 			},
1349 			.num_parents = 1,
1350 			.flags = CLK_SET_RATE_PARENT,
1351 			.ops = &clk_branch2_ops,
1352 		},
1353 	},
1354 };
1355 
1356 static struct clk_branch disp_cc_mdss_esc0_clk = {
1357 	.halt_reg = 0x8038,
1358 	.halt_check = BRANCH_HALT,
1359 	.clkr = {
1360 		.enable_reg = 0x8038,
1361 		.enable_mask = BIT(0),
1362 		.hw.init = &(struct clk_init_data) {
1363 			.name = "disp_cc_mdss_esc0_clk",
1364 			.parent_hws = (const struct clk_hw*[]) {
1365 				&disp_cc_mdss_esc0_clk_src.clkr.hw,
1366 			},
1367 			.num_parents = 1,
1368 			.flags = CLK_SET_RATE_PARENT,
1369 			.ops = &clk_branch2_ops,
1370 		},
1371 	},
1372 };
1373 
1374 static struct clk_branch disp_cc_mdss_esc1_clk = {
1375 	.halt_reg = 0x803c,
1376 	.halt_check = BRANCH_HALT,
1377 	.clkr = {
1378 		.enable_reg = 0x803c,
1379 		.enable_mask = BIT(0),
1380 		.hw.init = &(struct clk_init_data) {
1381 			.name = "disp_cc_mdss_esc1_clk",
1382 			.parent_hws = (const struct clk_hw*[]) {
1383 				&disp_cc_mdss_esc1_clk_src.clkr.hw,
1384 			},
1385 			.num_parents = 1,
1386 			.flags = CLK_SET_RATE_PARENT,
1387 			.ops = &clk_branch2_ops,
1388 		},
1389 	},
1390 };
1391 
1392 static struct clk_branch disp_cc_mdss_mdp1_clk = {
1393 	.halt_reg = 0xa004,
1394 	.halt_check = BRANCH_HALT,
1395 	.clkr = {
1396 		.enable_reg = 0xa004,
1397 		.enable_mask = BIT(0),
1398 		.hw.init = &(struct clk_init_data) {
1399 			.name = "disp_cc_mdss_mdp1_clk",
1400 			.parent_hws = (const struct clk_hw*[]) {
1401 				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1402 			},
1403 			.num_parents = 1,
1404 			.flags = CLK_SET_RATE_PARENT,
1405 			.ops = &clk_branch2_ops,
1406 		},
1407 	},
1408 };
1409 
1410 static struct clk_branch disp_cc_mdss_mdp_clk = {
1411 	.halt_reg = 0x800c,
1412 	.halt_check = BRANCH_HALT,
1413 	.clkr = {
1414 		.enable_reg = 0x800c,
1415 		.enable_mask = BIT(0),
1416 		.hw.init = &(struct clk_init_data) {
1417 			.name = "disp_cc_mdss_mdp_clk",
1418 			.parent_hws = (const struct clk_hw*[]) {
1419 				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1420 			},
1421 			.num_parents = 1,
1422 			.flags = CLK_SET_RATE_PARENT,
1423 			.ops = &clk_branch2_ops,
1424 		},
1425 	},
1426 };
1427 
1428 static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
1429 	.halt_reg = 0xa010,
1430 	.halt_check = BRANCH_HALT,
1431 	.clkr = {
1432 		.enable_reg = 0xa010,
1433 		.enable_mask = BIT(0),
1434 		.hw.init = &(struct clk_init_data) {
1435 			.name = "disp_cc_mdss_mdp_lut1_clk",
1436 			.parent_hws = (const struct clk_hw*[]) {
1437 				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1438 			},
1439 			.num_parents = 1,
1440 			.flags = CLK_SET_RATE_PARENT,
1441 			.ops = &clk_branch2_ops,
1442 		},
1443 	},
1444 };
1445 
1446 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
1447 	.halt_reg = 0x8018,
1448 	.halt_check = BRANCH_HALT_VOTED,
1449 	.clkr = {
1450 		.enable_reg = 0x8018,
1451 		.enable_mask = BIT(0),
1452 		.hw.init = &(struct clk_init_data) {
1453 			.name = "disp_cc_mdss_mdp_lut_clk",
1454 			.parent_hws = (const struct clk_hw*[]) {
1455 				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1456 			},
1457 			.num_parents = 1,
1458 			.flags = CLK_SET_RATE_PARENT,
1459 			.ops = &clk_branch2_ops,
1460 		},
1461 	},
1462 };
1463 
1464 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
1465 	.halt_reg = 0xc004,
1466 	.halt_check = BRANCH_HALT_VOTED,
1467 	.clkr = {
1468 		.enable_reg = 0xc004,
1469 		.enable_mask = BIT(0),
1470 		.hw.init = &(struct clk_init_data) {
1471 			.name = "disp_cc_mdss_non_gdsc_ahb_clk",
1472 			.parent_hws = (const struct clk_hw*[]) {
1473 				&disp_cc_mdss_ahb_clk_src.clkr.hw,
1474 			},
1475 			.num_parents = 1,
1476 			.flags = CLK_SET_RATE_PARENT,
1477 			.ops = &clk_branch2_ops,
1478 		},
1479 	},
1480 };
1481 
1482 static struct clk_branch disp_cc_mdss_pclk0_clk = {
1483 	.halt_reg = 0x8004,
1484 	.halt_check = BRANCH_HALT,
1485 	.clkr = {
1486 		.enable_reg = 0x8004,
1487 		.enable_mask = BIT(0),
1488 		.hw.init = &(struct clk_init_data) {
1489 			.name = "disp_cc_mdss_pclk0_clk",
1490 			.parent_hws = (const struct clk_hw*[]) {
1491 				&disp_cc_mdss_pclk0_clk_src.clkr.hw,
1492 			},
1493 			.num_parents = 1,
1494 			.flags = CLK_SET_RATE_PARENT,
1495 			.ops = &clk_branch2_ops,
1496 		},
1497 	},
1498 };
1499 
1500 static struct clk_branch disp_cc_mdss_pclk1_clk = {
1501 	.halt_reg = 0x8008,
1502 	.halt_check = BRANCH_HALT,
1503 	.clkr = {
1504 		.enable_reg = 0x8008,
1505 		.enable_mask = BIT(0),
1506 		.hw.init = &(struct clk_init_data) {
1507 			.name = "disp_cc_mdss_pclk1_clk",
1508 			.parent_hws = (const struct clk_hw*[]) {
1509 				&disp_cc_mdss_pclk1_clk_src.clkr.hw,
1510 			},
1511 			.num_parents = 1,
1512 			.flags = CLK_SET_RATE_PARENT,
1513 			.ops = &clk_branch2_ops,
1514 		},
1515 	},
1516 };
1517 
1518 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
1519 	.halt_reg = 0xc00c,
1520 	.halt_check = BRANCH_HALT,
1521 	.clkr = {
1522 		.enable_reg = 0xc00c,
1523 		.enable_mask = BIT(0),
1524 		.hw.init = &(struct clk_init_data) {
1525 			.name = "disp_cc_mdss_rscc_ahb_clk",
1526 			.parent_hws = (const struct clk_hw*[]) {
1527 				&disp_cc_mdss_ahb_clk_src.clkr.hw,
1528 			},
1529 			.num_parents = 1,
1530 			.flags = CLK_SET_RATE_PARENT,
1531 			.ops = &clk_branch2_ops,
1532 		},
1533 	},
1534 };
1535 
1536 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
1537 	.halt_reg = 0xc008,
1538 	.halt_check = BRANCH_HALT,
1539 	.clkr = {
1540 		.enable_reg = 0xc008,
1541 		.enable_mask = BIT(0),
1542 		.hw.init = &(struct clk_init_data) {
1543 			.name = "disp_cc_mdss_rscc_vsync_clk",
1544 			.parent_hws = (const struct clk_hw*[]) {
1545 				&disp_cc_mdss_vsync_clk_src.clkr.hw,
1546 			},
1547 			.num_parents = 1,
1548 			.flags = CLK_SET_RATE_PARENT,
1549 			.ops = &clk_branch2_ops,
1550 		},
1551 	},
1552 };
1553 
1554 static struct clk_branch disp_cc_mdss_vsync1_clk = {
1555 	.halt_reg = 0xa01c,
1556 	.halt_check = BRANCH_HALT,
1557 	.clkr = {
1558 		.enable_reg = 0xa01c,
1559 		.enable_mask = BIT(0),
1560 		.hw.init = &(struct clk_init_data) {
1561 			.name = "disp_cc_mdss_vsync1_clk",
1562 			.parent_hws = (const struct clk_hw*[]) {
1563 				&disp_cc_mdss_vsync_clk_src.clkr.hw,
1564 			},
1565 			.num_parents = 1,
1566 			.flags = CLK_SET_RATE_PARENT,
1567 			.ops = &clk_branch2_ops,
1568 		},
1569 	},
1570 };
1571 
1572 static struct clk_branch disp_cc_mdss_vsync_clk = {
1573 	.halt_reg = 0x8024,
1574 	.halt_check = BRANCH_HALT,
1575 	.clkr = {
1576 		.enable_reg = 0x8024,
1577 		.enable_mask = BIT(0),
1578 		.hw.init = &(struct clk_init_data) {
1579 			.name = "disp_cc_mdss_vsync_clk",
1580 			.parent_hws = (const struct clk_hw*[]) {
1581 				&disp_cc_mdss_vsync_clk_src.clkr.hw,
1582 			},
1583 			.num_parents = 1,
1584 			.flags = CLK_SET_RATE_PARENT,
1585 			.ops = &clk_branch2_ops,
1586 		},
1587 	},
1588 };
1589 
1590 static struct clk_branch disp_cc_sleep_clk = {
1591 	.halt_reg = 0xe074,
1592 	.halt_check = BRANCH_HALT,
1593 	.clkr = {
1594 		.enable_reg = 0xe074,
1595 		.enable_mask = BIT(0),
1596 		.hw.init = &(struct clk_init_data) {
1597 			.name = "disp_cc_sleep_clk",
1598 			.parent_hws = (const struct clk_hw*[]) {
1599 				&disp_cc_sleep_clk_src.clkr.hw,
1600 			},
1601 			.num_parents = 1,
1602 			.flags = CLK_SET_RATE_PARENT,
1603 			.ops = &clk_branch2_ops,
1604 		},
1605 	},
1606 };
1607 
1608 static struct gdsc mdss_gdsc = {
1609 	.gdscr = 0x9000,
1610 	.pd = {
1611 		.name = "mdss_gdsc",
1612 	},
1613 	.pwrsts = PWRSTS_OFF_ON,
1614 	.flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
1615 };
1616 
1617 static struct gdsc mdss_int2_gdsc = {
1618 	.gdscr = 0xb000,
1619 	.pd = {
1620 		.name = "mdss_int2_gdsc",
1621 	},
1622 	.pwrsts = PWRSTS_OFF_ON,
1623 	.flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
1624 };
1625 
1626 static struct clk_regmap *disp_cc_sm8550_clocks[] = {
1627 	[DISP_CC_MDSS_ACCU_CLK] = &disp_cc_mdss_accu_clk.clkr,
1628 	[DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,
1629 	[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
1630 	[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
1631 	[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
1632 	[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
1633 	[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
1634 	[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
1635 	[DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
1636 	[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
1637 	[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
1638 	[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
1639 	[DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr,
1640 	[DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr,
1641 	[DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr,
1642 	[DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr,
1643 	[DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr,
1644 	[DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr,
1645 	[DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr,
1646 	[DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr,
1647 	[DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
1648 	[DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,
1649 	[DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
1650 	[DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
1651 		&disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
1652 	[DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr,
1653 	[DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr,
1654 	[DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr,
1655 	[DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr,
1656 	[DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr,
1657 	[DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr,
1658 	[DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr,
1659 	[DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr,
1660 	[DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
1661 	[DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,
1662 	[DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
1663 	[DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
1664 		&disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
1665 	[DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr,
1666 	[DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr,
1667 	[DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr,
1668 	[DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr,
1669 	[DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr,
1670 	[DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr,
1671 	[DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr,
1672 	[DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr,
1673 	[DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr,
1674 	[DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,
1675 	[DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,
1676 	[DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr,
1677 	[DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr,
1678 	[DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr,
1679 	[DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr,
1680 	[DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr,
1681 	[DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr,
1682 	[DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr,
1683 	[DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr,
1684 	[DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr,
1685 	[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
1686 	[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
1687 	[DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
1688 	[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
1689 	[DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,
1690 	[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
1691 	[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
1692 	[DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,
1693 	[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
1694 	[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1695 	[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
1696 	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
1697 	[DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
1698 	[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
1699 	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
1700 	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
1701 	[DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,
1702 	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
1703 	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
1704 	[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
1705 	[DISP_CC_PLL1] = &disp_cc_pll1.clkr,
1706 	[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
1707 	[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
1708 	[DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
1709 };
1710 
1711 static const struct qcom_reset_map disp_cc_sm8550_resets[] = {
1712 	[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1713 	[DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
1714 	[DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
1715 };
1716 
1717 static struct gdsc *disp_cc_sm8550_gdscs[] = {
1718 	[MDSS_GDSC] = &mdss_gdsc,
1719 	[MDSS_INT2_GDSC] = &mdss_int2_gdsc,
1720 };
1721 
1722 static const struct regmap_config disp_cc_sm8550_regmap_config = {
1723 	.reg_bits = 32,
1724 	.reg_stride = 4,
1725 	.val_bits = 32,
1726 	.max_register = 0x11008,
1727 	.fast_io = true,
1728 };
1729 
1730 static struct qcom_cc_desc disp_cc_sm8550_desc = {
1731 	.config = &disp_cc_sm8550_regmap_config,
1732 	.clks = disp_cc_sm8550_clocks,
1733 	.num_clks = ARRAY_SIZE(disp_cc_sm8550_clocks),
1734 	.resets = disp_cc_sm8550_resets,
1735 	.num_resets = ARRAY_SIZE(disp_cc_sm8550_resets),
1736 	.gdscs = disp_cc_sm8550_gdscs,
1737 	.num_gdscs = ARRAY_SIZE(disp_cc_sm8550_gdscs),
1738 };
1739 
1740 static const struct of_device_id disp_cc_sm8550_match_table[] = {
1741 	{ .compatible = "qcom,sm8550-dispcc" },
1742 	{ }
1743 };
1744 MODULE_DEVICE_TABLE(of, disp_cc_sm8550_match_table);
1745 
disp_cc_sm8550_probe(struct platform_device * pdev)1746 static int disp_cc_sm8550_probe(struct platform_device *pdev)
1747 {
1748 	struct regmap *regmap;
1749 	int ret;
1750 
1751 	ret = devm_pm_runtime_enable(&pdev->dev);
1752 	if (ret)
1753 		return ret;
1754 
1755 	ret = pm_runtime_resume_and_get(&pdev->dev);
1756 	if (ret)
1757 		return ret;
1758 
1759 	regmap = qcom_cc_map(pdev, &disp_cc_sm8550_desc);
1760 	if (IS_ERR(regmap)) {
1761 		ret = PTR_ERR(regmap);
1762 		goto err_put_rpm;
1763 	}
1764 
1765 	clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1766 	clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1767 
1768 	/* Enable clock gating for MDP clocks */
1769 	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
1770 
1771 	/*
1772 	 * Keep clocks always enabled:
1773 	 *	disp_cc_xo_clk
1774 	 */
1775 	regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0));
1776 
1777 	ret = qcom_cc_really_probe(pdev, &disp_cc_sm8550_desc, regmap);
1778 	if (ret)
1779 		goto err_put_rpm;
1780 
1781 	pm_runtime_put(&pdev->dev);
1782 
1783 	return 0;
1784 
1785 err_put_rpm:
1786 	pm_runtime_put_sync(&pdev->dev);
1787 
1788 	return ret;
1789 }
1790 
1791 static struct platform_driver disp_cc_sm8550_driver = {
1792 	.probe = disp_cc_sm8550_probe,
1793 	.driver = {
1794 		.name = "disp_cc-sm8550",
1795 		.of_match_table = disp_cc_sm8550_match_table,
1796 	},
1797 };
1798 
disp_cc_sm8550_init(void)1799 static int __init disp_cc_sm8550_init(void)
1800 {
1801 	return platform_driver_register(&disp_cc_sm8550_driver);
1802 }
1803 subsys_initcall(disp_cc_sm8550_init);
1804 
disp_cc_sm8550_exit(void)1805 static void __exit disp_cc_sm8550_exit(void)
1806 {
1807 	platform_driver_unregister(&disp_cc_sm8550_driver);
1808 }
1809 module_exit(disp_cc_sm8550_exit);
1810 
1811 MODULE_DESCRIPTION("QTI DISPCC SM8550 Driver");
1812 MODULE_LICENSE("GPL");
1813