1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018-2020, 2022, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/regmap.h>
11 #include <linux/reset-controller.h>
12
13 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
14
15 #include "clk-alpha-pll.h"
16 #include "clk-branch.h"
17 #include "clk-rcg.h"
18 #include "clk-regmap-divider.h"
19 #include "common.h"
20 #include "gdsc.h"
21 #include "reset.h"
22
23 enum {
24 P_BI_TCXO,
25 P_DISP_CC_PLL0_OUT_MAIN,
26 P_DISP_CC_PLL1_OUT_EVEN,
27 P_DISP_CC_PLL1_OUT_MAIN,
28 P_DP_PHY_PLL_LINK_CLK,
29 P_DP_PHY_PLL_VCO_DIV_CLK,
30 P_DPTX1_PHY_PLL_LINK_CLK,
31 P_DPTX1_PHY_PLL_VCO_DIV_CLK,
32 P_DPTX2_PHY_PLL_LINK_CLK,
33 P_DPTX2_PHY_PLL_VCO_DIV_CLK,
34 P_EDP_PHY_PLL_LINK_CLK,
35 P_EDP_PHY_PLL_VCO_DIV_CLK,
36 P_DSI0_PHY_PLL_OUT_BYTECLK,
37 P_DSI0_PHY_PLL_OUT_DSICLK,
38 P_DSI1_PHY_PLL_OUT_BYTECLK,
39 P_DSI1_PHY_PLL_OUT_DSICLK,
40 };
41
42 static struct pll_vco vco_table[] = {
43 { 249600000, 2000000000, 0 },
44 };
45
46 static struct pll_vco lucid_5lpe_vco[] = {
47 { 249600000, 1750000000, 0 },
48 };
49
50 static struct alpha_pll_config disp_cc_pll0_config = {
51 .l = 0x47,
52 .alpha = 0xE000,
53 .config_ctl_val = 0x20485699,
54 .config_ctl_hi_val = 0x00002261,
55 .config_ctl_hi1_val = 0x329A699C,
56 .user_ctl_val = 0x00000000,
57 .user_ctl_hi_val = 0x00000805,
58 .user_ctl_hi1_val = 0x00000000,
59 };
60
61 static struct clk_init_data disp_cc_pll0_init = {
62 .name = "disp_cc_pll0",
63 .parent_data = &(const struct clk_parent_data){
64 .fw_name = "bi_tcxo",
65 },
66 .num_parents = 1,
67 .ops = &clk_alpha_pll_lucid_ops,
68 };
69
70 static struct clk_alpha_pll disp_cc_pll0 = {
71 .offset = 0x0,
72 .vco_table = vco_table,
73 .num_vco = ARRAY_SIZE(vco_table),
74 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
75 .clkr.hw.init = &disp_cc_pll0_init
76 };
77
78 static struct alpha_pll_config disp_cc_pll1_config = {
79 .l = 0x1F,
80 .alpha = 0x4000,
81 .config_ctl_val = 0x20485699,
82 .config_ctl_hi_val = 0x00002261,
83 .config_ctl_hi1_val = 0x329A699C,
84 .user_ctl_val = 0x00000000,
85 .user_ctl_hi_val = 0x00000805,
86 .user_ctl_hi1_val = 0x00000000,
87 };
88
89 static struct clk_init_data disp_cc_pll1_init = {
90 .name = "disp_cc_pll1",
91 .parent_data = &(const struct clk_parent_data){
92 .fw_name = "bi_tcxo",
93 },
94 .num_parents = 1,
95 .ops = &clk_alpha_pll_lucid_ops,
96 };
97
98 static struct clk_alpha_pll disp_cc_pll1 = {
99 .offset = 0x1000,
100 .vco_table = vco_table,
101 .num_vco = ARRAY_SIZE(vco_table),
102 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
103 .clkr.hw.init = &disp_cc_pll1_init
104 };
105
106 static const struct parent_map disp_cc_parent_map_0[] = {
107 { P_BI_TCXO, 0 },
108 { P_DP_PHY_PLL_LINK_CLK, 1 },
109 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
110 { P_DPTX1_PHY_PLL_LINK_CLK, 3 },
111 { P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 },
112 { P_DPTX2_PHY_PLL_LINK_CLK, 5 },
113 { P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 },
114 };
115
116 static const struct clk_parent_data disp_cc_parent_data_0[] = {
117 { .fw_name = "bi_tcxo" },
118 { .fw_name = "dp_phy_pll_link_clk" },
119 { .fw_name = "dp_phy_pll_vco_div_clk" },
120 { .fw_name = "dptx1_phy_pll_link_clk" },
121 { .fw_name = "dptx1_phy_pll_vco_div_clk" },
122 { .fw_name = "dptx2_phy_pll_link_clk" },
123 { .fw_name = "dptx2_phy_pll_vco_div_clk" },
124 };
125
126 static const struct parent_map disp_cc_parent_map_1[] = {
127 { P_BI_TCXO, 0 },
128 };
129
130 static const struct clk_parent_data disp_cc_parent_data_1[] = {
131 { .fw_name = "bi_tcxo" },
132 };
133
134 static const struct parent_map disp_cc_parent_map_2[] = {
135 { P_BI_TCXO, 0 },
136 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
137 { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
138 };
139
140 static const struct clk_parent_data disp_cc_parent_data_2[] = {
141 { .fw_name = "bi_tcxo" },
142 { .fw_name = "dsi0_phy_pll_out_byteclk" },
143 { .fw_name = "dsi1_phy_pll_out_byteclk" },
144 };
145
146 static const struct parent_map disp_cc_parent_map_3[] = {
147 { P_BI_TCXO, 0 },
148 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
149 };
150
151 static const struct clk_parent_data disp_cc_parent_data_3[] = {
152 { .fw_name = "bi_tcxo" },
153 { .hw = &disp_cc_pll1.clkr.hw },
154 };
155
156 static const struct parent_map disp_cc_parent_map_4[] = {
157 { P_BI_TCXO, 0 },
158 { P_EDP_PHY_PLL_LINK_CLK, 1 },
159 { P_EDP_PHY_PLL_VCO_DIV_CLK, 2},
160 };
161
162 static const struct clk_parent_data disp_cc_parent_data_4[] = {
163 { .fw_name = "bi_tcxo" },
164 { .fw_name = "edp_phy_pll_link_clk" },
165 { .fw_name = "edp_phy_pll_vco_div_clk" },
166 };
167
168 static const struct parent_map disp_cc_parent_map_5[] = {
169 { P_BI_TCXO, 0 },
170 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
171 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
172 };
173
174 static const struct clk_parent_data disp_cc_parent_data_5[] = {
175 { .fw_name = "bi_tcxo" },
176 { .hw = &disp_cc_pll0.clkr.hw },
177 { .hw = &disp_cc_pll1.clkr.hw },
178 };
179
180 static const struct parent_map disp_cc_parent_map_6[] = {
181 { P_BI_TCXO, 0 },
182 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
183 { P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
184 };
185
186 static const struct clk_parent_data disp_cc_parent_data_6[] = {
187 { .fw_name = "bi_tcxo" },
188 { .fw_name = "dsi0_phy_pll_out_dsiclk" },
189 { .fw_name = "dsi1_phy_pll_out_dsiclk" },
190 };
191
192 static const struct parent_map disp_cc_parent_map_7[] = {
193 { P_BI_TCXO, 0 },
194 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
195 /* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */
196 };
197
198 static const struct clk_parent_data disp_cc_parent_data_7[] = {
199 { .fw_name = "bi_tcxo" },
200 { .hw = &disp_cc_pll1.clkr.hw },
201 /* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */
202 };
203
204 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
205 F(19200000, P_BI_TCXO, 1, 0, 0),
206 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
207 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
208 { }
209 };
210
211 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
212 .cmd_rcgr = 0x22bc,
213 .mnd_width = 0,
214 .hid_width = 5,
215 .parent_map = disp_cc_parent_map_3,
216 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
217 .clkr.hw.init = &(struct clk_init_data){
218 .name = "disp_cc_mdss_ahb_clk_src",
219 .parent_data = disp_cc_parent_data_3,
220 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
221 .flags = CLK_SET_RATE_PARENT,
222 .ops = &clk_rcg2_shared_ops,
223 },
224 };
225
226 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
227 F(19200000, P_BI_TCXO, 1, 0, 0),
228 { }
229 };
230
231 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
232 .cmd_rcgr = 0x2110,
233 .mnd_width = 0,
234 .hid_width = 5,
235 .parent_map = disp_cc_parent_map_2,
236 .clkr.hw.init = &(struct clk_init_data){
237 .name = "disp_cc_mdss_byte0_clk_src",
238 .parent_data = disp_cc_parent_data_2,
239 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
240 .flags = CLK_SET_RATE_PARENT,
241 .ops = &clk_byte2_ops,
242 },
243 };
244
245 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
246 .cmd_rcgr = 0x212c,
247 .mnd_width = 0,
248 .hid_width = 5,
249 .parent_map = disp_cc_parent_map_2,
250 .clkr.hw.init = &(struct clk_init_data){
251 .name = "disp_cc_mdss_byte1_clk_src",
252 .parent_data = disp_cc_parent_data_2,
253 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
254 .flags = CLK_SET_RATE_PARENT,
255 .ops = &clk_byte2_ops,
256 },
257 };
258
259 static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = {
260 .cmd_rcgr = 0x2240,
261 .mnd_width = 0,
262 .hid_width = 5,
263 .parent_map = disp_cc_parent_map_1,
264 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
265 .clkr.hw.init = &(struct clk_init_data){
266 .name = "disp_cc_mdss_dp_aux1_clk_src",
267 .parent_data = disp_cc_parent_data_1,
268 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
269 .flags = CLK_SET_RATE_PARENT,
270 .ops = &clk_rcg2_ops,
271 },
272 };
273
274 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
275 .cmd_rcgr = 0x21dc,
276 .mnd_width = 0,
277 .hid_width = 5,
278 .parent_map = disp_cc_parent_map_1,
279 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
280 .clkr.hw.init = &(struct clk_init_data){
281 .name = "disp_cc_mdss_dp_aux_clk_src",
282 .parent_data = disp_cc_parent_data_1,
283 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
284 .flags = CLK_SET_RATE_PARENT,
285 .ops = &clk_rcg2_ops,
286 },
287 };
288
289 static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
290 .cmd_rcgr = 0x220c,
291 .mnd_width = 0,
292 .hid_width = 5,
293 .parent_map = disp_cc_parent_map_0,
294 .clkr.hw.init = &(struct clk_init_data){
295 .name = "disp_cc_mdss_dp_link1_clk_src",
296 .parent_data = disp_cc_parent_data_0,
297 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
298 .ops = &clk_byte2_ops,
299 },
300 };
301
302 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
303 .cmd_rcgr = 0x2178,
304 .mnd_width = 0,
305 .hid_width = 5,
306 .parent_map = disp_cc_parent_map_0,
307 .clkr.hw.init = &(struct clk_init_data){
308 .name = "disp_cc_mdss_dp_link_clk_src",
309 .parent_data = disp_cc_parent_data_0,
310 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
311 .ops = &clk_byte2_ops,
312 },
313 };
314
315 static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
316 .cmd_rcgr = 0x21c4,
317 .mnd_width = 16,
318 .hid_width = 5,
319 .parent_map = disp_cc_parent_map_0,
320 .clkr.hw.init = &(struct clk_init_data){
321 .name = "disp_cc_mdss_dp_pixel1_clk_src",
322 .parent_data = disp_cc_parent_data_0,
323 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
324 .ops = &clk_dp_ops,
325 },
326 };
327
328 static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = {
329 .cmd_rcgr = 0x21f4,
330 .mnd_width = 16,
331 .hid_width = 5,
332 .parent_map = disp_cc_parent_map_0,
333 .clkr.hw.init = &(struct clk_init_data){
334 .name = "disp_cc_mdss_dp_pixel2_clk_src",
335 .parent_data = disp_cc_parent_data_0,
336 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
337 .ops = &clk_dp_ops,
338 },
339 };
340
341 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
342 .cmd_rcgr = 0x21ac,
343 .mnd_width = 16,
344 .hid_width = 5,
345 .parent_map = disp_cc_parent_map_0,
346 .clkr.hw.init = &(struct clk_init_data){
347 .name = "disp_cc_mdss_dp_pixel_clk_src",
348 .parent_data = disp_cc_parent_data_0,
349 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
350 .ops = &clk_dp_ops,
351 },
352 };
353
354 static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = {
355 .cmd_rcgr = 0x228c,
356 .mnd_width = 0,
357 .hid_width = 5,
358 .parent_map = disp_cc_parent_map_1,
359 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
360 .clkr.hw.init = &(struct clk_init_data){
361 .name = "disp_cc_mdss_edp_aux_clk_src",
362 .parent_data = disp_cc_parent_data_1,
363 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
364 .flags = CLK_SET_RATE_PARENT,
365 .ops = &clk_rcg2_ops,
366 },
367 };
368
369 static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = {
370 .cmd_rcgr = 0x22a4,
371 .mnd_width = 0,
372 .hid_width = 5,
373 .parent_map = disp_cc_parent_map_7,
374 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
375 .clkr.hw.init = &(struct clk_init_data){
376 .name = "disp_cc_mdss_edp_gtc_clk_src",
377 .parent_data = disp_cc_parent_data_7,
378 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
379 .flags = CLK_SET_RATE_PARENT,
380 .ops = &clk_rcg2_ops,
381 },
382 };
383
384 static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = {
385 .cmd_rcgr = 0x2270,
386 .mnd_width = 0,
387 .hid_width = 5,
388 .parent_map = disp_cc_parent_map_4,
389 .clkr.hw.init = &(struct clk_init_data){
390 .name = "disp_cc_mdss_edp_link_clk_src",
391 .parent_data = disp_cc_parent_data_4,
392 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
393 .flags = CLK_SET_RATE_PARENT,
394 .ops = &clk_byte2_ops,
395 },
396 };
397
398 static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = {
399 .cmd_rcgr = 0x2258,
400 .mnd_width = 16,
401 .hid_width = 5,
402 .parent_map = disp_cc_parent_map_4,
403 .clkr.hw.init = &(struct clk_init_data){
404 .name = "disp_cc_mdss_edp_pixel_clk_src",
405 .parent_data = disp_cc_parent_data_4,
406 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
407 .ops = &clk_dp_ops,
408 },
409 };
410
411 static struct clk_branch disp_cc_mdss_edp_aux_clk = {
412 .halt_reg = 0x2078,
413 .halt_check = BRANCH_HALT,
414 .clkr = {
415 .enable_reg = 0x2078,
416 .enable_mask = BIT(0),
417 .hw.init = &(struct clk_init_data){
418 .name = "disp_cc_mdss_edp_aux_clk",
419 .parent_hws = (const struct clk_hw*[]){
420 &disp_cc_mdss_edp_aux_clk_src.clkr.hw,
421 },
422 .num_parents = 1,
423 .flags = CLK_SET_RATE_PARENT,
424 .ops = &clk_branch2_ops,
425 },
426 },
427 };
428
429 static struct clk_branch disp_cc_mdss_edp_gtc_clk = {
430 .halt_reg = 0x207c,
431 .halt_check = BRANCH_HALT,
432 .clkr = {
433 .enable_reg = 0x207c,
434 .enable_mask = BIT(0),
435 .hw.init = &(struct clk_init_data){
436 .name = "disp_cc_mdss_edp_gtc_clk",
437 .parent_hws = (const struct clk_hw*[]){
438 &disp_cc_mdss_edp_gtc_clk_src.clkr.hw,
439 },
440 .num_parents = 1,
441 .flags = CLK_SET_RATE_PARENT,
442 .ops = &clk_branch2_ops,
443 },
444 },
445 };
446
447 static struct clk_branch disp_cc_mdss_edp_link_clk = {
448 .halt_reg = 0x2070,
449 .halt_check = BRANCH_HALT,
450 .clkr = {
451 .enable_reg = 0x2070,
452 .enable_mask = BIT(0),
453 .hw.init = &(struct clk_init_data){
454 .name = "disp_cc_mdss_edp_link_clk",
455 .parent_hws = (const struct clk_hw*[]){
456 &disp_cc_mdss_edp_link_clk_src.clkr.hw,
457 },
458 .num_parents = 1,
459 .flags = CLK_SET_RATE_PARENT,
460 .ops = &clk_branch2_ops,
461 },
462 },
463 };
464
465 static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = {
466 .reg = 0x2288,
467 .shift = 0,
468 .width = 2,
469 .clkr.hw.init = &(struct clk_init_data) {
470 .name = "disp_cc_mdss_edp_link_div_clk_src",
471 .parent_hws = (const struct clk_hw*[]){
472 &disp_cc_mdss_edp_link_clk_src.clkr.hw,
473 },
474 .num_parents = 1,
475 .ops = &clk_regmap_div_ro_ops,
476 },
477 };
478
479 static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
480 .halt_reg = 0x2074,
481 .halt_check = BRANCH_HALT,
482 .clkr = {
483 .enable_reg = 0x2074,
484 .enable_mask = BIT(0),
485 .hw.init = &(struct clk_init_data){
486 .name = "disp_cc_mdss_edp_link_intf_clk",
487 .parent_hws = (const struct clk_hw*[]){
488 &disp_cc_mdss_edp_link_div_clk_src.clkr.hw,
489 },
490 .num_parents = 1,
491 .flags = CLK_GET_RATE_NOCACHE,
492 .ops = &clk_branch2_ops,
493 },
494 },
495 };
496
497 static struct clk_branch disp_cc_mdss_edp_pixel_clk = {
498 .halt_reg = 0x206c,
499 .halt_check = BRANCH_HALT,
500 .clkr = {
501 .enable_reg = 0x206c,
502 .enable_mask = BIT(0),
503 .hw.init = &(struct clk_init_data){
504 .name = "disp_cc_mdss_edp_pixel_clk",
505 .parent_hws = (const struct clk_hw*[]){
506 &disp_cc_mdss_edp_pixel_clk_src.clkr.hw,
507 },
508 .num_parents = 1,
509 .flags = CLK_SET_RATE_PARENT,
510 .ops = &clk_branch2_ops,
511 },
512 },
513 };
514
515 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
516 .cmd_rcgr = 0x2148,
517 .mnd_width = 0,
518 .hid_width = 5,
519 .parent_map = disp_cc_parent_map_2,
520 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
521 .clkr.hw.init = &(struct clk_init_data){
522 .name = "disp_cc_mdss_esc0_clk_src",
523 .parent_data = disp_cc_parent_data_2,
524 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
525 .flags = CLK_SET_RATE_PARENT,
526 .ops = &clk_rcg2_ops,
527 },
528 };
529
530 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
531 .cmd_rcgr = 0x2160,
532 .mnd_width = 0,
533 .hid_width = 5,
534 .parent_map = disp_cc_parent_map_2,
535 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
536 .clkr.hw.init = &(struct clk_init_data){
537 .name = "disp_cc_mdss_esc1_clk_src",
538 .parent_data = disp_cc_parent_data_2,
539 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
540 .flags = CLK_SET_RATE_PARENT,
541 .ops = &clk_rcg2_ops,
542 },
543 };
544
545 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
546 F(19200000, P_BI_TCXO, 1, 0, 0),
547 F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0),
548 F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0),
549 F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0),
550 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
551 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
552 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
553 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
554 { }
555 };
556
557 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
558 .cmd_rcgr = 0x20c8,
559 .mnd_width = 0,
560 .hid_width = 5,
561 .parent_map = disp_cc_parent_map_5,
562 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
563 .clkr.hw.init = &(struct clk_init_data){
564 .name = "disp_cc_mdss_mdp_clk_src",
565 .parent_data = disp_cc_parent_data_5,
566 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
567 .flags = CLK_SET_RATE_PARENT,
568 .ops = &clk_rcg2_shared_ops,
569 },
570 };
571
572 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
573 .cmd_rcgr = 0x2098,
574 .mnd_width = 8,
575 .hid_width = 5,
576 .parent_map = disp_cc_parent_map_6,
577 .clkr.hw.init = &(struct clk_init_data){
578 .name = "disp_cc_mdss_pclk0_clk_src",
579 .parent_data = disp_cc_parent_data_6,
580 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
581 .flags = CLK_SET_RATE_PARENT,
582 .ops = &clk_pixel_ops,
583 },
584 };
585
586 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
587 .cmd_rcgr = 0x20b0,
588 .mnd_width = 8,
589 .hid_width = 5,
590 .parent_map = disp_cc_parent_map_6,
591 .clkr.hw.init = &(struct clk_init_data){
592 .name = "disp_cc_mdss_pclk1_clk_src",
593 .parent_data = disp_cc_parent_data_6,
594 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
595 .flags = CLK_SET_RATE_PARENT,
596 .ops = &clk_pixel_ops,
597 },
598 };
599
600 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
601 F(19200000, P_BI_TCXO, 1, 0, 0),
602 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
603 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
604 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
605 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
606 { }
607 };
608
609 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
610 .cmd_rcgr = 0x20e0,
611 .mnd_width = 0,
612 .hid_width = 5,
613 .parent_map = disp_cc_parent_map_5,
614 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
615 .clkr.hw.init = &(struct clk_init_data){
616 .name = "disp_cc_mdss_rot_clk_src",
617 .parent_data = disp_cc_parent_data_5,
618 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
619 .flags = CLK_SET_RATE_PARENT,
620 .ops = &clk_rcg2_shared_ops,
621 },
622 };
623
624 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
625 .cmd_rcgr = 0x20f8,
626 .mnd_width = 0,
627 .hid_width = 5,
628 .parent_map = disp_cc_parent_map_1,
629 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
630 .clkr.hw.init = &(struct clk_init_data){
631 .name = "disp_cc_mdss_vsync_clk_src",
632 .parent_data = disp_cc_parent_data_1,
633 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
634 .flags = CLK_SET_RATE_PARENT,
635 .ops = &clk_rcg2_ops,
636 },
637 };
638
639 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
640 .reg = 0x2128,
641 .shift = 0,
642 .width = 2,
643 .clkr.hw.init = &(struct clk_init_data) {
644 .name = "disp_cc_mdss_byte0_div_clk_src",
645 .parent_hws = (const struct clk_hw*[]){
646 &disp_cc_mdss_byte0_clk_src.clkr.hw,
647 },
648 .num_parents = 1,
649 .ops = &clk_regmap_div_ops,
650 },
651 };
652
653
654 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
655 .reg = 0x2144,
656 .shift = 0,
657 .width = 2,
658 .clkr.hw.init = &(struct clk_init_data) {
659 .name = "disp_cc_mdss_byte1_div_clk_src",
660 .parent_hws = (const struct clk_hw*[]){
661 &disp_cc_mdss_byte1_clk_src.clkr.hw,
662 },
663 .num_parents = 1,
664 .ops = &clk_regmap_div_ops,
665 },
666 };
667
668
669 static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = {
670 .reg = 0x2224,
671 .shift = 0,
672 .width = 2,
673 .clkr.hw.init = &(struct clk_init_data) {
674 .name = "disp_cc_mdss_dp_link1_div_clk_src",
675 .parent_hws = (const struct clk_hw*[]){
676 &disp_cc_mdss_dp_link1_clk_src.clkr.hw,
677 },
678 .num_parents = 1,
679 .ops = &clk_regmap_div_ro_ops,
680 },
681 };
682
683
684 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
685 .reg = 0x2190,
686 .shift = 0,
687 .width = 2,
688 .clkr.hw.init = &(struct clk_init_data) {
689 .name = "disp_cc_mdss_dp_link_div_clk_src",
690 .parent_hws = (const struct clk_hw*[]){
691 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
692 },
693 .num_parents = 1,
694 .ops = &clk_regmap_div_ro_ops,
695 },
696 };
697
698 static struct clk_branch disp_cc_mdss_ahb_clk = {
699 .halt_reg = 0x2080,
700 .halt_check = BRANCH_HALT,
701 .clkr = {
702 .enable_reg = 0x2080,
703 .enable_mask = BIT(0),
704 .hw.init = &(struct clk_init_data){
705 .name = "disp_cc_mdss_ahb_clk",
706 .parent_hws = (const struct clk_hw*[]){
707 &disp_cc_mdss_ahb_clk_src.clkr.hw,
708 },
709 .num_parents = 1,
710 .flags = CLK_SET_RATE_PARENT,
711 .ops = &clk_branch2_ops,
712 },
713 },
714 };
715
716 static struct clk_branch disp_cc_mdss_byte0_clk = {
717 .halt_reg = 0x2028,
718 .halt_check = BRANCH_HALT,
719 .clkr = {
720 .enable_reg = 0x2028,
721 .enable_mask = BIT(0),
722 .hw.init = &(struct clk_init_data){
723 .name = "disp_cc_mdss_byte0_clk",
724 .parent_hws = (const struct clk_hw*[]){
725 &disp_cc_mdss_byte0_clk_src.clkr.hw,
726 },
727 .num_parents = 1,
728 .flags = CLK_SET_RATE_PARENT,
729 .ops = &clk_branch2_ops,
730 },
731 },
732 };
733
734 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
735 .halt_reg = 0x202c,
736 .halt_check = BRANCH_HALT,
737 .clkr = {
738 .enable_reg = 0x202c,
739 .enable_mask = BIT(0),
740 .hw.init = &(struct clk_init_data){
741 .name = "disp_cc_mdss_byte0_intf_clk",
742 .parent_hws = (const struct clk_hw*[]){
743 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
744 },
745 .num_parents = 1,
746 .flags = CLK_SET_RATE_PARENT,
747 .ops = &clk_branch2_ops,
748 },
749 },
750 };
751
752 static struct clk_branch disp_cc_mdss_byte1_clk = {
753 .halt_reg = 0x2030,
754 .halt_check = BRANCH_HALT,
755 .clkr = {
756 .enable_reg = 0x2030,
757 .enable_mask = BIT(0),
758 .hw.init = &(struct clk_init_data){
759 .name = "disp_cc_mdss_byte1_clk",
760 .parent_hws = (const struct clk_hw*[]){
761 &disp_cc_mdss_byte1_clk_src.clkr.hw,
762 },
763 .num_parents = 1,
764 .flags = CLK_SET_RATE_PARENT,
765 .ops = &clk_branch2_ops,
766 },
767 },
768 };
769
770 static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
771 .halt_reg = 0x2034,
772 .halt_check = BRANCH_HALT,
773 .clkr = {
774 .enable_reg = 0x2034,
775 .enable_mask = BIT(0),
776 .hw.init = &(struct clk_init_data){
777 .name = "disp_cc_mdss_byte1_intf_clk",
778 .parent_hws = (const struct clk_hw*[]){
779 &disp_cc_mdss_byte1_div_clk_src.clkr.hw,
780 },
781 .num_parents = 1,
782 .flags = CLK_SET_RATE_PARENT,
783 .ops = &clk_branch2_ops,
784 },
785 },
786 };
787
788 static struct clk_branch disp_cc_mdss_dp_aux1_clk = {
789 .halt_reg = 0x2068,
790 .halt_check = BRANCH_HALT,
791 .clkr = {
792 .enable_reg = 0x2068,
793 .enable_mask = BIT(0),
794 .hw.init = &(struct clk_init_data){
795 .name = "disp_cc_mdss_dp_aux1_clk",
796 .parent_hws = (const struct clk_hw*[]){
797 &disp_cc_mdss_dp_aux1_clk_src.clkr.hw,
798 },
799 .num_parents = 1,
800 .flags = CLK_SET_RATE_PARENT,
801 .ops = &clk_branch2_ops,
802 },
803 },
804 };
805
806 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
807 .halt_reg = 0x2054,
808 .halt_check = BRANCH_HALT,
809 .clkr = {
810 .enable_reg = 0x2054,
811 .enable_mask = BIT(0),
812 .hw.init = &(struct clk_init_data){
813 .name = "disp_cc_mdss_dp_aux_clk",
814 .parent_hws = (const struct clk_hw*[]){
815 &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
816 },
817 .num_parents = 1,
818 .flags = CLK_SET_RATE_PARENT,
819 .ops = &clk_branch2_ops,
820 },
821 },
822 };
823
824 static struct clk_branch disp_cc_mdss_dp_link1_clk = {
825 .halt_reg = 0x205c,
826 .halt_check = BRANCH_HALT,
827 .clkr = {
828 .enable_reg = 0x205c,
829 .enable_mask = BIT(0),
830 .hw.init = &(struct clk_init_data){
831 .name = "disp_cc_mdss_dp_link1_clk",
832 .parent_hws = (const struct clk_hw*[]){
833 &disp_cc_mdss_dp_link1_clk_src.clkr.hw,
834 },
835 .num_parents = 1,
836 .flags = CLK_SET_RATE_PARENT,
837 .ops = &clk_branch2_ops,
838 },
839 },
840 };
841
842 static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = {
843 .halt_reg = 0x2060,
844 .halt_check = BRANCH_HALT,
845 .clkr = {
846 .enable_reg = 0x2060,
847 .enable_mask = BIT(0),
848 .hw.init = &(struct clk_init_data){
849 .name = "disp_cc_mdss_dp_link1_intf_clk",
850 .parent_hws = (const struct clk_hw*[]){
851 &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw,
852 },
853 .num_parents = 1,
854 .flags = CLK_SET_RATE_PARENT,
855 .ops = &clk_branch2_ops,
856 },
857 },
858 };
859
860 static struct clk_branch disp_cc_mdss_dp_link_clk = {
861 .halt_reg = 0x2040,
862 .halt_check = BRANCH_HALT,
863 .clkr = {
864 .enable_reg = 0x2040,
865 .enable_mask = BIT(0),
866 .hw.init = &(struct clk_init_data){
867 .name = "disp_cc_mdss_dp_link_clk",
868 .parent_hws = (const struct clk_hw*[]){
869 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
870 },
871 .num_parents = 1,
872 .flags = CLK_SET_RATE_PARENT,
873 .ops = &clk_branch2_ops,
874 },
875 },
876 };
877
878 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
879 .halt_reg = 0x2044,
880 .halt_check = BRANCH_HALT,
881 .clkr = {
882 .enable_reg = 0x2044,
883 .enable_mask = BIT(0),
884 .hw.init = &(struct clk_init_data){
885 .name = "disp_cc_mdss_dp_link_intf_clk",
886 .parent_hws = (const struct clk_hw*[]){
887 &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
888 },
889 .num_parents = 1,
890 .flags = CLK_SET_RATE_PARENT,
891 .ops = &clk_branch2_ops,
892 },
893 },
894 };
895
896 static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
897 .halt_reg = 0x2050,
898 .halt_check = BRANCH_HALT,
899 .clkr = {
900 .enable_reg = 0x2050,
901 .enable_mask = BIT(0),
902 .hw.init = &(struct clk_init_data){
903 .name = "disp_cc_mdss_dp_pixel1_clk",
904 .parent_hws = (const struct clk_hw*[]){
905 &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
906 },
907 .num_parents = 1,
908 .flags = CLK_SET_RATE_PARENT,
909 .ops = &clk_branch2_ops,
910 },
911 },
912 };
913
914 static struct clk_branch disp_cc_mdss_dp_pixel2_clk = {
915 .halt_reg = 0x2058,
916 .halt_check = BRANCH_HALT,
917 .clkr = {
918 .enable_reg = 0x2058,
919 .enable_mask = BIT(0),
920 .hw.init = &(struct clk_init_data){
921 .name = "disp_cc_mdss_dp_pixel2_clk",
922 .parent_hws = (const struct clk_hw*[]){
923 &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw,
924 },
925 .num_parents = 1,
926 .flags = CLK_SET_RATE_PARENT,
927 .ops = &clk_branch2_ops,
928 },
929 },
930 };
931
932 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
933 .halt_reg = 0x204c,
934 .halt_check = BRANCH_HALT,
935 .clkr = {
936 .enable_reg = 0x204c,
937 .enable_mask = BIT(0),
938 .hw.init = &(struct clk_init_data){
939 .name = "disp_cc_mdss_dp_pixel_clk",
940 .parent_hws = (const struct clk_hw*[]){
941 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
942 },
943 .num_parents = 1,
944 .flags = CLK_SET_RATE_PARENT,
945 .ops = &clk_branch2_ops,
946 },
947 },
948 };
949
950 static struct clk_branch disp_cc_mdss_esc0_clk = {
951 .halt_reg = 0x2038,
952 .halt_check = BRANCH_HALT,
953 .clkr = {
954 .enable_reg = 0x2038,
955 .enable_mask = BIT(0),
956 .hw.init = &(struct clk_init_data){
957 .name = "disp_cc_mdss_esc0_clk",
958 .parent_hws = (const struct clk_hw*[]){
959 &disp_cc_mdss_esc0_clk_src.clkr.hw,
960 },
961 .num_parents = 1,
962 .flags = CLK_SET_RATE_PARENT,
963 .ops = &clk_branch2_ops,
964 },
965 },
966 };
967
968 static struct clk_branch disp_cc_mdss_esc1_clk = {
969 .halt_reg = 0x203c,
970 .halt_check = BRANCH_HALT,
971 .clkr = {
972 .enable_reg = 0x203c,
973 .enable_mask = BIT(0),
974 .hw.init = &(struct clk_init_data){
975 .name = "disp_cc_mdss_esc1_clk",
976 .parent_hws = (const struct clk_hw*[]){
977 &disp_cc_mdss_esc1_clk_src.clkr.hw,
978 },
979 .num_parents = 1,
980 .flags = CLK_SET_RATE_PARENT,
981 .ops = &clk_branch2_ops,
982 },
983 },
984 };
985
986 static struct clk_branch disp_cc_mdss_mdp_clk = {
987 .halt_reg = 0x200c,
988 .halt_check = BRANCH_HALT,
989 .clkr = {
990 .enable_reg = 0x200c,
991 .enable_mask = BIT(0),
992 .hw.init = &(struct clk_init_data){
993 .name = "disp_cc_mdss_mdp_clk",
994 .parent_hws = (const struct clk_hw*[]){
995 &disp_cc_mdss_mdp_clk_src.clkr.hw,
996 },
997 .num_parents = 1,
998 .flags = CLK_SET_RATE_PARENT,
999 .ops = &clk_branch2_ops,
1000 },
1001 },
1002 };
1003
1004 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
1005 .halt_reg = 0x201c,
1006 .halt_check = BRANCH_VOTED,
1007 .clkr = {
1008 .enable_reg = 0x201c,
1009 .enable_mask = BIT(0),
1010 .hw.init = &(struct clk_init_data){
1011 .name = "disp_cc_mdss_mdp_lut_clk",
1012 .parent_hws = (const struct clk_hw*[]){
1013 &disp_cc_mdss_mdp_clk_src.clkr.hw,
1014 },
1015 .num_parents = 1,
1016 .flags = CLK_SET_RATE_PARENT,
1017 .ops = &clk_branch2_ops,
1018 },
1019 },
1020 };
1021
1022 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
1023 .halt_reg = 0x4004,
1024 .halt_check = BRANCH_VOTED,
1025 .clkr = {
1026 .enable_reg = 0x4004,
1027 .enable_mask = BIT(0),
1028 .hw.init = &(struct clk_init_data){
1029 .name = "disp_cc_mdss_non_gdsc_ahb_clk",
1030 .parent_hws = (const struct clk_hw*[]){
1031 &disp_cc_mdss_ahb_clk_src.clkr.hw,
1032 },
1033 .num_parents = 1,
1034 .flags = CLK_SET_RATE_PARENT,
1035 .ops = &clk_branch2_ops,
1036 },
1037 },
1038 };
1039
1040 static struct clk_branch disp_cc_mdss_pclk0_clk = {
1041 .halt_reg = 0x2004,
1042 .halt_check = BRANCH_HALT,
1043 .clkr = {
1044 .enable_reg = 0x2004,
1045 .enable_mask = BIT(0),
1046 .hw.init = &(struct clk_init_data){
1047 .name = "disp_cc_mdss_pclk0_clk",
1048 .parent_hws = (const struct clk_hw*[]){
1049 &disp_cc_mdss_pclk0_clk_src.clkr.hw,
1050 },
1051 .num_parents = 1,
1052 .flags = CLK_SET_RATE_PARENT,
1053 .ops = &clk_branch2_ops,
1054 },
1055 },
1056 };
1057
1058 static struct clk_branch disp_cc_mdss_pclk1_clk = {
1059 .halt_reg = 0x2008,
1060 .halt_check = BRANCH_HALT,
1061 .clkr = {
1062 .enable_reg = 0x2008,
1063 .enable_mask = BIT(0),
1064 .hw.init = &(struct clk_init_data){
1065 .name = "disp_cc_mdss_pclk1_clk",
1066 .parent_hws = (const struct clk_hw*[]){
1067 &disp_cc_mdss_pclk1_clk_src.clkr.hw,
1068 },
1069 .num_parents = 1,
1070 .flags = CLK_SET_RATE_PARENT,
1071 .ops = &clk_branch2_ops,
1072 },
1073 },
1074 };
1075
1076 static struct clk_branch disp_cc_mdss_rot_clk = {
1077 .halt_reg = 0x2014,
1078 .halt_check = BRANCH_HALT,
1079 .clkr = {
1080 .enable_reg = 0x2014,
1081 .enable_mask = BIT(0),
1082 .hw.init = &(struct clk_init_data){
1083 .name = "disp_cc_mdss_rot_clk",
1084 .parent_hws = (const struct clk_hw*[]){
1085 &disp_cc_mdss_rot_clk_src.clkr.hw,
1086 },
1087 .num_parents = 1,
1088 .flags = CLK_SET_RATE_PARENT,
1089 .ops = &clk_branch2_ops,
1090 },
1091 },
1092 };
1093
1094 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
1095 .halt_reg = 0x400c,
1096 .halt_check = BRANCH_HALT,
1097 .clkr = {
1098 .enable_reg = 0x400c,
1099 .enable_mask = BIT(0),
1100 .hw.init = &(struct clk_init_data){
1101 .name = "disp_cc_mdss_rscc_ahb_clk",
1102 .parent_hws = (const struct clk_hw*[]){
1103 &disp_cc_mdss_ahb_clk_src.clkr.hw,
1104 },
1105 .num_parents = 1,
1106 .flags = CLK_SET_RATE_PARENT,
1107 .ops = &clk_branch2_ops,
1108 },
1109 },
1110 };
1111
1112 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
1113 .halt_reg = 0x4008,
1114 .halt_check = BRANCH_HALT,
1115 .clkr = {
1116 .enable_reg = 0x4008,
1117 .enable_mask = BIT(0),
1118 .hw.init = &(struct clk_init_data){
1119 .name = "disp_cc_mdss_rscc_vsync_clk",
1120 .parent_hws = (const struct clk_hw*[]){
1121 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1122 },
1123 .num_parents = 1,
1124 .flags = CLK_SET_RATE_PARENT,
1125 .ops = &clk_branch2_ops,
1126 },
1127 },
1128 };
1129
1130 static struct clk_branch disp_cc_mdss_vsync_clk = {
1131 .halt_reg = 0x2024,
1132 .halt_check = BRANCH_HALT,
1133 .clkr = {
1134 .enable_reg = 0x2024,
1135 .enable_mask = BIT(0),
1136 .hw.init = &(struct clk_init_data){
1137 .name = "disp_cc_mdss_vsync_clk",
1138 .parent_hws = (const struct clk_hw*[]){
1139 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1140 },
1141 .num_parents = 1,
1142 .flags = CLK_SET_RATE_PARENT,
1143 .ops = &clk_branch2_ops,
1144 },
1145 },
1146 };
1147
1148 static struct gdsc mdss_gdsc = {
1149 .gdscr = 0x3000,
1150 .en_rest_wait_val = 0x2,
1151 .en_few_wait_val = 0x2,
1152 .clk_dis_wait_val = 0xf,
1153 .pd = {
1154 .name = "mdss_gdsc",
1155 },
1156 .pwrsts = PWRSTS_OFF_ON,
1157 .flags = HW_CTRL | RETAIN_FF_ENABLE,
1158 };
1159
1160 static struct clk_regmap *disp_cc_sm8250_clocks[] = {
1161 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
1162 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
1163 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
1164 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
1165 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
1166 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
1167 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
1168 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
1169 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
1170 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
1171 [DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr,
1172 [DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr,
1173 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
1174 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
1175 [DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr,
1176 [DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr,
1177 [DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr,
1178 [DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr,
1179 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
1180 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
1181 [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr,
1182 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
1183 [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
1184 [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr,
1185 [DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr,
1186 [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr,
1187 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
1188 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
1189 [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr,
1190 [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr,
1191 [DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr,
1192 [DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr,
1193 [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr,
1194 [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr,
1195 [DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_edp_link_div_clk_src.clkr,
1196 [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr,
1197 [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr,
1198 [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr,
1199 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
1200 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
1201 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
1202 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
1203 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
1204 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
1205 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
1206 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1207 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
1208 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
1209 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
1210 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
1211 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
1212 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
1213 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
1214 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
1215 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
1216 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
1217 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
1218 [DISP_CC_PLL1] = &disp_cc_pll1.clkr,
1219 };
1220
1221 static const struct qcom_reset_map disp_cc_sm8250_resets[] = {
1222 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
1223 [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 },
1224 };
1225
1226 static struct gdsc *disp_cc_sm8250_gdscs[] = {
1227 [MDSS_GDSC] = &mdss_gdsc,
1228 };
1229
1230 static const struct regmap_config disp_cc_sm8250_regmap_config = {
1231 .reg_bits = 32,
1232 .reg_stride = 4,
1233 .val_bits = 32,
1234 .max_register = 0x10000,
1235 .fast_io = true,
1236 };
1237
1238 static const struct qcom_cc_desc disp_cc_sm8250_desc = {
1239 .config = &disp_cc_sm8250_regmap_config,
1240 .clks = disp_cc_sm8250_clocks,
1241 .num_clks = ARRAY_SIZE(disp_cc_sm8250_clocks),
1242 .resets = disp_cc_sm8250_resets,
1243 .num_resets = ARRAY_SIZE(disp_cc_sm8250_resets),
1244 .gdscs = disp_cc_sm8250_gdscs,
1245 .num_gdscs = ARRAY_SIZE(disp_cc_sm8250_gdscs),
1246 };
1247
1248 static const struct of_device_id disp_cc_sm8250_match_table[] = {
1249 { .compatible = "qcom,sc8180x-dispcc" },
1250 { .compatible = "qcom,sm8150-dispcc" },
1251 { .compatible = "qcom,sm8250-dispcc" },
1252 { .compatible = "qcom,sm8350-dispcc" },
1253 { }
1254 };
1255 MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
1256
disp_cc_sm8250_probe(struct platform_device * pdev)1257 static int disp_cc_sm8250_probe(struct platform_device *pdev)
1258 {
1259 struct regmap *regmap;
1260 int ret;
1261
1262 ret = devm_pm_runtime_enable(&pdev->dev);
1263 if (ret)
1264 return ret;
1265
1266 ret = pm_runtime_resume_and_get(&pdev->dev);
1267 if (ret)
1268 return ret;
1269
1270 regmap = qcom_cc_map(pdev, &disp_cc_sm8250_desc);
1271 if (IS_ERR(regmap)) {
1272 pm_runtime_put(&pdev->dev);
1273 return PTR_ERR(regmap);
1274 }
1275
1276 /* Apply differences for SM8150 and SM8350 */
1277 BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
1278 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") ||
1279 of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
1280 disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
1281 disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
1282 disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;
1283 disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops;
1284 disp_cc_pll1_config.config_ctl_hi_val = 0x00002267;
1285 disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
1286 disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
1287 disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
1288
1289 disp_cc_mdss_dp_link_intf_clk.clkr.hw.init->parent_hws[0] =
1290 &disp_cc_mdss_dp_link_clk_src.clkr.hw;
1291 disp_cc_mdss_dp_link1_intf_clk.clkr.hw.init->parent_hws[0] =
1292 &disp_cc_mdss_dp_link1_clk_src.clkr.hw;
1293 disp_cc_mdss_edp_link_intf_clk.clkr.hw.init->parent_hws[0] =
1294 &disp_cc_mdss_edp_link_clk_src.clkr.hw;
1295
1296 disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = NULL;
1297 disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = NULL;
1298 disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = NULL;
1299 } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
1300 static struct clk_rcg2 * const rcgs[] = {
1301 &disp_cc_mdss_byte0_clk_src,
1302 &disp_cc_mdss_byte1_clk_src,
1303 &disp_cc_mdss_dp_aux1_clk_src,
1304 &disp_cc_mdss_dp_aux_clk_src,
1305 &disp_cc_mdss_dp_link1_clk_src,
1306 &disp_cc_mdss_dp_link_clk_src,
1307 &disp_cc_mdss_dp_pixel1_clk_src,
1308 &disp_cc_mdss_dp_pixel2_clk_src,
1309 &disp_cc_mdss_dp_pixel_clk_src,
1310 &disp_cc_mdss_edp_aux_clk_src,
1311 &disp_cc_mdss_edp_link_clk_src,
1312 &disp_cc_mdss_edp_pixel_clk_src,
1313 &disp_cc_mdss_esc0_clk_src,
1314 &disp_cc_mdss_esc1_clk_src,
1315 &disp_cc_mdss_mdp_clk_src,
1316 &disp_cc_mdss_pclk0_clk_src,
1317 &disp_cc_mdss_pclk1_clk_src,
1318 &disp_cc_mdss_rot_clk_src,
1319 &disp_cc_mdss_vsync_clk_src,
1320 };
1321 static struct clk_regmap_div * const divs[] = {
1322 &disp_cc_mdss_byte0_div_clk_src,
1323 &disp_cc_mdss_byte1_div_clk_src,
1324 &disp_cc_mdss_dp_link1_div_clk_src,
1325 &disp_cc_mdss_dp_link_div_clk_src,
1326 &disp_cc_mdss_edp_link_div_clk_src,
1327 };
1328 unsigned int i;
1329 static bool offset_applied;
1330
1331 /*
1332 * note: trion == lucid, except for the prepare() op
1333 * only apply the offsets once (in case of deferred probe)
1334 */
1335 if (!offset_applied) {
1336 for (i = 0; i < ARRAY_SIZE(rcgs); i++)
1337 rcgs[i]->cmd_rcgr -= 4;
1338
1339 for (i = 0; i < ARRAY_SIZE(divs); i++) {
1340 divs[i]->reg -= 4;
1341 divs[i]->width = 4;
1342 }
1343
1344 disp_cc_mdss_ahb_clk.halt_reg -= 4;
1345 disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;
1346
1347 offset_applied = true;
1348 }
1349
1350 disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;
1351
1352 disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c;
1353 disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;
1354 disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
1355 disp_cc_pll0.vco_table = lucid_5lpe_vco;
1356 disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c;
1357 disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
1358 disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
1359 disp_cc_pll1.vco_table = lucid_5lpe_vco;
1360
1361 disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK] = NULL;
1362 disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL;
1363 }
1364
1365 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
1366 clk_lucid_5lpe_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1367 clk_lucid_5lpe_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1368 } else {
1369 clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1370 clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1371 }
1372
1373 /* Enable clock gating for MDP clocks */
1374 regmap_update_bits(regmap, 0x8000, 0x10, 0x10);
1375
1376 /* DISP_CC_XO_CLK always-on */
1377 regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0));
1378
1379 ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap);
1380
1381 pm_runtime_put(&pdev->dev);
1382
1383 return ret;
1384 }
1385
1386 static struct platform_driver disp_cc_sm8250_driver = {
1387 .probe = disp_cc_sm8250_probe,
1388 .driver = {
1389 .name = "disp_cc-sm8250",
1390 .of_match_table = disp_cc_sm8250_match_table,
1391 },
1392 };
1393
disp_cc_sm8250_init(void)1394 static int __init disp_cc_sm8250_init(void)
1395 {
1396 return platform_driver_register(&disp_cc_sm8250_driver);
1397 }
1398 subsys_initcall(disp_cc_sm8250_init);
1399
disp_cc_sm8250_exit(void)1400 static void __exit disp_cc_sm8250_exit(void)
1401 {
1402 platform_driver_unregister(&disp_cc_sm8250_driver);
1403 }
1404 module_exit(disp_cc_sm8250_exit);
1405
1406 MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver");
1407 MODULE_LICENSE("GPL v2");
1408