1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // CS42L43 CODEC driver
4 //
5 // Copyright (C) 2022-2023 Cirrus Logic, Inc. and
6 // Cirrus Logic International Semiconductor Ltd.
7
8 #include <linux/bitops.h>
9 #include <linux/err.h>
10 #include <linux/errno.h>
11 #include <linux/gcd.h>
12 #include <linux/irq.h>
13 #include <linux/jiffies.h>
14 #include <linux/mfd/cs42l43.h>
15 #include <linux/mfd/cs42l43-regs.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/string.h>
19 #include <sound/control.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc-component.h>
23 #include <sound/soc-dapm.h>
24 #include <sound/soc-dai.h>
25 #include <sound/soc.h>
26 #include <sound/tlv.h>
27
28 #include "cs42l43.h"
29
30 #define CS42L43_DECL_MUX(name, reg) \
31 static SOC_VALUE_ENUM_SINGLE_DECL(cs42l43_##name##_enum, reg, \
32 0, CS42L43_MIXER_SRC_MASK, \
33 cs42l43_mixer_texts, cs42l43_mixer_values); \
34 static const struct snd_kcontrol_new cs42l43_##name##_mux = \
35 SOC_DAPM_ENUM("Route", cs42l43_##name##_enum)
36
37 #define CS42L43_DECL_MIXER(name, reg) \
38 CS42L43_DECL_MUX(name##_in1, reg); \
39 CS42L43_DECL_MUX(name##_in2, reg + 0x4); \
40 CS42L43_DECL_MUX(name##_in3, reg + 0x8); \
41 CS42L43_DECL_MUX(name##_in4, reg + 0xC)
42
43 #define CS42L43_DAPM_MUX(name_str, name) \
44 SND_SOC_DAPM_MUX(name_str " Input", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_mux)
45
46 #define CS42L43_DAPM_MIXER(name_str, name) \
47 SND_SOC_DAPM_MUX(name_str " Input 1", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in1_mux), \
48 SND_SOC_DAPM_MUX(name_str " Input 2", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in2_mux), \
49 SND_SOC_DAPM_MUX(name_str " Input 3", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in3_mux), \
50 SND_SOC_DAPM_MUX(name_str " Input 4", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in4_mux), \
51 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
52
53 #define CS42L43_BASE_ROUTES(name_str) \
54 { name_str, "Tone Generator 1", "Tone 1" }, \
55 { name_str, "Tone Generator 2", "Tone 2" }, \
56 { name_str, "Decimator 1", "Decimator 1" }, \
57 { name_str, "Decimator 2", "Decimator 2" }, \
58 { name_str, "Decimator 3", "Decimator 3" }, \
59 { name_str, "Decimator 4", "Decimator 4" }, \
60 { name_str, "ASPRX1", "ASPRX1" }, \
61 { name_str, "ASPRX2", "ASPRX2" }, \
62 { name_str, "ASPRX3", "ASPRX3" }, \
63 { name_str, "ASPRX4", "ASPRX4" }, \
64 { name_str, "ASPRX5", "ASPRX5" }, \
65 { name_str, "ASPRX6", "ASPRX6" }, \
66 { name_str, "DP5RX1", "DP5RX1" }, \
67 { name_str, "DP5RX2", "DP5RX2" }, \
68 { name_str, "DP6RX1", "DP6RX1" }, \
69 { name_str, "DP6RX2", "DP6RX2" }, \
70 { name_str, "DP7RX1", "DP7RX1" }, \
71 { name_str, "DP7RX2", "DP7RX2" }, \
72 { name_str, "ASRC INT1", "ASRC_INT1" }, \
73 { name_str, "ASRC INT2", "ASRC_INT2" }, \
74 { name_str, "ASRC INT3", "ASRC_INT3" }, \
75 { name_str, "ASRC INT4", "ASRC_INT4" }, \
76 { name_str, "ASRC DEC1", "ASRC_DEC1" }, \
77 { name_str, "ASRC DEC2", "ASRC_DEC2" }, \
78 { name_str, "ASRC DEC3", "ASRC_DEC3" }, \
79 { name_str, "ASRC DEC4", "ASRC_DEC4" }, \
80 { name_str, "ISRC1 INT1", "ISRC1INT1" }, \
81 { name_str, "ISRC1 INT2", "ISRC1INT2" }, \
82 { name_str, "ISRC1 DEC1", "ISRC1DEC1" }, \
83 { name_str, "ISRC1 DEC2", "ISRC1DEC2" }, \
84 { name_str, "ISRC2 INT1", "ISRC2INT1" }, \
85 { name_str, "ISRC2 INT2", "ISRC2INT2" }, \
86 { name_str, "ISRC2 DEC1", "ISRC2DEC1" }, \
87 { name_str, "ISRC2 DEC2", "ISRC2DEC2" }, \
88 { name_str, "EQ1", "EQ" }, \
89 { name_str, "EQ2", "EQ" }
90
91 #define CS42L43_MUX_ROUTES(name_str, widget) \
92 { widget, NULL, name_str " Input" }, \
93 { name_str " Input", NULL, "Mixer Core" }, \
94 CS42L43_BASE_ROUTES(name_str " Input")
95
96 #define CS42L43_MIXER_ROUTES(name_str, widget) \
97 { name_str " Mixer", NULL, name_str " Input 1" }, \
98 { name_str " Mixer", NULL, name_str " Input 2" }, \
99 { name_str " Mixer", NULL, name_str " Input 3" }, \
100 { name_str " Mixer", NULL, name_str " Input 4" }, \
101 { widget, NULL, name_str " Mixer" }, \
102 { name_str " Mixer", NULL, "Mixer Core" }, \
103 CS42L43_BASE_ROUTES(name_str " Input 1"), \
104 CS42L43_BASE_ROUTES(name_str " Input 2"), \
105 CS42L43_BASE_ROUTES(name_str " Input 3"), \
106 CS42L43_BASE_ROUTES(name_str " Input 4")
107
108 #define CS42L43_MIXER_VOLUMES(name_str, base) \
109 SOC_SINGLE_RANGE_TLV(name_str " Input 1 Volume", base, \
110 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
111 cs42l43_mixer_tlv), \
112 SOC_SINGLE_RANGE_TLV(name_str " Input 2 Volume", base + 4, \
113 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
114 cs42l43_mixer_tlv), \
115 SOC_SINGLE_RANGE_TLV(name_str " Input 3 Volume", base + 8, \
116 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
117 cs42l43_mixer_tlv), \
118 SOC_SINGLE_RANGE_TLV(name_str " Input 4 Volume", base + 12, \
119 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
120 cs42l43_mixer_tlv)
121
122 #define CS42L43_IRQ_ERROR(name) \
123 static irqreturn_t cs42l43_##name(int irq, void *data) \
124 { \
125 struct cs42l43_codec *priv = data; \
126 dev_err(priv->dev, "Error " #name " IRQ\n"); \
127 return IRQ_HANDLED; \
128 }
129
130 CS42L43_IRQ_ERROR(pll_lost_lock)
CS42L43_IRQ_ERROR(spkr_clock_stop)131 CS42L43_IRQ_ERROR(spkr_clock_stop)
132 CS42L43_IRQ_ERROR(spkl_clock_stop)
133 CS42L43_IRQ_ERROR(spkr_brown_out)
134 CS42L43_IRQ_ERROR(spkl_brown_out)
135 CS42L43_IRQ_ERROR(spkr_therm_shutdown)
136 CS42L43_IRQ_ERROR(spkl_therm_shutdown)
137 CS42L43_IRQ_ERROR(spkr_therm_warm)
138 CS42L43_IRQ_ERROR(spkl_therm_warm)
139 CS42L43_IRQ_ERROR(spkr_sc_detect)
140 CS42L43_IRQ_ERROR(spkl_sc_detect)
141 CS42L43_IRQ_ERROR(hp_ilimit)
142
143 #define CS42L43_IRQ_COMPLETE(name) \
144 static irqreturn_t cs42l43_##name(int irq, void *data) \
145 { \
146 struct cs42l43_codec *priv = data; \
147 dev_dbg(priv->dev, #name " completed\n"); \
148 complete(&priv->name); \
149 return IRQ_HANDLED; \
150 }
151
152 CS42L43_IRQ_COMPLETE(pll_ready)
153 CS42L43_IRQ_COMPLETE(hp_startup)
154 CS42L43_IRQ_COMPLETE(hp_shutdown)
155 CS42L43_IRQ_COMPLETE(type_detect)
156 CS42L43_IRQ_COMPLETE(spkr_shutdown)
157 CS42L43_IRQ_COMPLETE(spkl_shutdown)
158 CS42L43_IRQ_COMPLETE(spkr_startup)
159 CS42L43_IRQ_COMPLETE(spkl_startup)
160 CS42L43_IRQ_COMPLETE(load_detect)
161
162 static irqreturn_t cs42l43_mic_shutter(int irq, void *data)
163 {
164 struct cs42l43_codec *priv = data;
165 const char * const controls[] = {
166 "Decimator 1 Switch",
167 "Decimator 2 Switch",
168 "Decimator 3 Switch",
169 "Decimator 4 Switch",
170 };
171 int i, ret;
172
173 dev_dbg(priv->dev, "Microphone shutter changed\n");
174
175 if (!priv->component)
176 return IRQ_NONE;
177
178 for (i = 0; i < ARRAY_SIZE(controls); i++) {
179 ret = snd_soc_component_notify_control(priv->component,
180 controls[i]);
181 if (ret)
182 return IRQ_NONE;
183 }
184
185 return IRQ_HANDLED;
186 }
187
cs42l43_spk_shutter(int irq,void * data)188 static irqreturn_t cs42l43_spk_shutter(int irq, void *data)
189 {
190 struct cs42l43_codec *priv = data;
191 int ret;
192
193 dev_dbg(priv->dev, "Speaker shutter changed\n");
194
195 if (!priv->component)
196 return IRQ_NONE;
197
198 ret = snd_soc_component_notify_control(priv->component,
199 "Speaker Digital Switch");
200 if (ret)
201 return IRQ_NONE;
202
203 return IRQ_HANDLED;
204 }
205
206 static const unsigned int cs42l43_sample_rates[] = {
207 8000, 16000, 24000, 32000, 44100, 48000, 96000, 192000,
208 };
209
210 #define CS42L43_CONSUMER_RATE_MASK 0xFF
211 #define CS42L43_PROVIDER_RATE_MASK 0xEF // 44.1k only supported as consumer
212
213 static const struct snd_pcm_hw_constraint_list cs42l43_constraint = {
214 .count = ARRAY_SIZE(cs42l43_sample_rates),
215 .list = cs42l43_sample_rates,
216 };
217
cs42l43_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)218 static int cs42l43_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
219 {
220 struct snd_soc_component *component = dai->component;
221 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
222 struct cs42l43 *cs42l43 = priv->core;
223 int provider = !dai->id || !!regmap_test_bits(cs42l43->regmap,
224 CS42L43_ASP_CLK_CONFIG2,
225 CS42L43_ASP_MASTER_MODE_MASK);
226
227 if (provider)
228 priv->constraint.mask = CS42L43_PROVIDER_RATE_MASK;
229 else
230 priv->constraint.mask = CS42L43_CONSUMER_RATE_MASK;
231
232 return snd_pcm_hw_constraint_list(substream->runtime, 0,
233 SNDRV_PCM_HW_PARAM_RATE,
234 &priv->constraint);
235 }
236
cs42l43_convert_sample_rate(unsigned int rate)237 static int cs42l43_convert_sample_rate(unsigned int rate)
238 {
239 switch (rate) {
240 case 8000:
241 return 0x11;
242 case 16000:
243 return 0x12;
244 case 24000:
245 return 0x02;
246 case 32000:
247 return 0x13;
248 case 44100:
249 return 0x0B;
250 case 48000:
251 return 0x03;
252 case 96000:
253 return 0x04;
254 case 192000:
255 return 0x05;
256 default:
257 return -EINVAL;
258 }
259 }
260
cs42l43_set_sample_rate(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)261 static int cs42l43_set_sample_rate(struct snd_pcm_substream *substream,
262 struct snd_pcm_hw_params *params,
263 struct snd_soc_dai *dai)
264 {
265 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component);
266 struct cs42l43 *cs42l43 = priv->core;
267 int ret;
268
269 ret = cs42l43_convert_sample_rate(params_rate(params));
270 if (ret < 0) {
271 dev_err(priv->dev, "Failed to convert sample rate: %d\n", ret);
272 return ret;
273 }
274
275 //FIXME: For now lets just set sample rate 1, this needs expanded in the future
276 regmap_update_bits(cs42l43->regmap, CS42L43_SAMPLE_RATE1,
277 CS42L43_SAMPLE_RATE_MASK, ret);
278
279 return 0;
280 }
281
cs42l43_asp_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)282 static int cs42l43_asp_hw_params(struct snd_pcm_substream *substream,
283 struct snd_pcm_hw_params *params,
284 struct snd_soc_dai *dai)
285 {
286 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component);
287 struct cs42l43 *cs42l43 = priv->core;
288 int dsp_mode = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CTRL,
289 CS42L43_ASP_FSYNC_MODE_MASK);
290 int provider = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
291 CS42L43_ASP_MASTER_MODE_MASK);
292 int n_chans = params_channels(params);
293 int data_width = params_width(params);
294 int n_slots = n_chans;
295 int slot_width = data_width;
296 int frame, bclk_target, i;
297 unsigned int reg;
298 int *slots;
299
300 if (priv->n_slots) {
301 n_slots = priv->n_slots;
302 slot_width = priv->slot_width;
303 }
304
305 if (!dsp_mode && (n_slots & 0x1)) {
306 dev_dbg(priv->dev, "Forcing balanced channels on ASP\n");
307 n_slots++;
308 }
309
310 frame = n_slots * slot_width;
311 bclk_target = params_rate(params) * frame;
312
313 if (provider) {
314 unsigned int gcd_nm = gcd(bclk_target, CS42L43_INTERNAL_SYSCLK);
315 int n = bclk_target / gcd_nm;
316 int m = CS42L43_INTERNAL_SYSCLK / gcd_nm;
317
318 if (n > (CS42L43_ASP_BCLK_N_MASK >> CS42L43_ASP_BCLK_N_SHIFT) ||
319 m > CS42L43_ASP_BCLK_M_MASK) {
320 dev_err(priv->dev, "Can't produce %dHz bclk\n", bclk_target);
321 return -EINVAL;
322 }
323
324 dev_dbg(priv->dev, "bclk %d/%d = %dHz, with %dx%d frame\n",
325 n, m, bclk_target, n_slots, slot_width);
326
327 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG1,
328 CS42L43_ASP_BCLK_N_MASK | CS42L43_ASP_BCLK_M_MASK,
329 n << CS42L43_ASP_BCLK_N_SHIFT |
330 m << CS42L43_ASP_BCLK_M_SHIFT);
331 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL1,
332 CS42L43_ASP_FSYNC_M_MASK, frame);
333 }
334
335 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL4,
336 CS42L43_ASP_NUM_BCLKS_PER_FSYNC_MASK,
337 frame << CS42L43_ASP_NUM_BCLKS_PER_FSYNC_SHIFT);
338
339 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
340 reg = CS42L43_ASP_TX_CH1_CTRL;
341 slots = priv->tx_slots;
342 } else {
343 reg = CS42L43_ASP_RX_CH1_CTRL;
344 slots = priv->rx_slots;
345 }
346
347 for (i = 0; i < n_chans; i++, reg += 4) {
348 int slot_phase = dsp_mode | (i & CS42L43_ASP_CH_SLOT_PHASE_MASK);
349 int slot_pos;
350
351 if (dsp_mode)
352 slot_pos = slots[i] * slot_width;
353 else
354 slot_pos = (slots[i] / 2) * slot_width;
355
356 dev_dbg(priv->dev, "Configure channel %d at slot %d (%d,%d)\n",
357 i, slots[i], slot_pos, slot_phase);
358
359 regmap_update_bits(cs42l43->regmap, reg,
360 CS42L43_ASP_CH_WIDTH_MASK |
361 CS42L43_ASP_CH_SLOT_MASK |
362 CS42L43_ASP_CH_SLOT_PHASE_MASK,
363 ((data_width - 1) << CS42L43_ASP_CH_WIDTH_SHIFT) |
364 (slot_pos << CS42L43_ASP_CH_SLOT_SHIFT) |
365 slot_phase);
366 }
367
368 return cs42l43_set_sample_rate(substream, params, dai);
369 }
370
cs42l43_asp_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)371 static int cs42l43_asp_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
372 {
373 struct snd_soc_component *component = dai->component;
374 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
375 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
376 struct cs42l43 *cs42l43 = priv->core;
377 int provider = regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
378 CS42L43_ASP_MASTER_MODE_MASK);
379 struct snd_soc_dapm_route routes[] = {
380 { "BCLK", NULL, "FSYNC" },
381 };
382 unsigned int asp_ctrl = 0;
383 unsigned int data_ctrl = 0;
384 unsigned int fsync_ctrl = 0;
385 unsigned int clk_config = 0;
386
387 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
388 case SND_SOC_DAIFMT_DSP_A:
389 data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT;
390 fallthrough;
391 case SND_SOC_DAIFMT_DSP_B:
392 asp_ctrl |= CS42L43_ASP_FSYNC_MODE_MASK;
393 data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK;
394 break;
395 case SND_SOC_DAIFMT_I2S:
396 data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT;
397 break;
398 case SND_SOC_DAIFMT_LEFT_J:
399 data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK;
400 break;
401 default:
402 dev_err(priv->dev, "Unsupported DAI format 0x%x\n",
403 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
404 return -EINVAL;
405 }
406
407 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
408 case SND_SOC_DAIFMT_CBC_CFC:
409 if (provider)
410 snd_soc_dapm_del_routes(dapm, routes, ARRAY_SIZE(routes));
411 break;
412 case SND_SOC_DAIFMT_CBP_CFP:
413 if (!provider)
414 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
415 clk_config |= CS42L43_ASP_MASTER_MODE_MASK;
416 break;
417 default:
418 dev_err(priv->dev, "Unsupported ASP mode 0x%x\n",
419 fmt & SND_SOC_DAIFMT_MASTER_MASK);
420 return -EINVAL;
421 }
422
423 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
424 case SND_SOC_DAIFMT_NB_NF:
425 clk_config |= CS42L43_ASP_BCLK_INV_MASK; /* Yes BCLK_INV = NB */
426 break;
427 case SND_SOC_DAIFMT_IB_NF:
428 break;
429 case SND_SOC_DAIFMT_NB_IF:
430 clk_config |= CS42L43_ASP_BCLK_INV_MASK;
431 fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK |
432 CS42L43_ASP_FSYNC_OUT_INV_MASK;
433 break;
434 case SND_SOC_DAIFMT_IB_IF:
435 fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK |
436 CS42L43_ASP_FSYNC_OUT_INV_MASK;
437 break;
438 default:
439 dev_err(priv->dev, "Unsupported invert mode 0x%x\n",
440 fmt & SND_SOC_DAIFMT_INV_MASK);
441 return -EINVAL;
442 }
443
444 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CTRL,
445 CS42L43_ASP_FSYNC_MODE_MASK,
446 asp_ctrl);
447 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_DATA_CTRL,
448 CS42L43_ASP_FSYNC_FRAME_START_DLY_MASK |
449 CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK,
450 data_ctrl);
451 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
452 CS42L43_ASP_MASTER_MODE_MASK |
453 CS42L43_ASP_BCLK_INV_MASK,
454 clk_config);
455 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL3,
456 CS42L43_ASP_FSYNC_IN_INV_MASK |
457 CS42L43_ASP_FSYNC_OUT_INV_MASK,
458 fsync_ctrl);
459
460 return 0;
461 }
462
cs42l43_mask_to_slots(struct cs42l43_codec * priv,unsigned int mask,int * slots)463 static void cs42l43_mask_to_slots(struct cs42l43_codec *priv, unsigned int mask, int *slots)
464 {
465 int i;
466
467 for (i = 0; i < CS42L43_ASP_MAX_CHANNELS; ++i) {
468 int slot = ffs(mask) - 1;
469
470 if (slot < 0)
471 return;
472
473 slots[i] = slot;
474
475 mask &= ~(1 << slot);
476 }
477
478 if (mask)
479 dev_warn(priv->dev, "Too many channels in TDM mask\n");
480 }
481
cs42l43_asp_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)482 static int cs42l43_asp_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
483 unsigned int rx_mask, int slots, int slot_width)
484 {
485 struct snd_soc_component *component = dai->component;
486 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
487
488 priv->n_slots = slots;
489 priv->slot_width = slot_width;
490
491 if (!slots) {
492 tx_mask = CS42L43_DEFAULT_SLOTS;
493 rx_mask = CS42L43_DEFAULT_SLOTS;
494 }
495
496 cs42l43_mask_to_slots(priv, tx_mask, priv->tx_slots);
497 cs42l43_mask_to_slots(priv, rx_mask, priv->rx_slots);
498
499 return 0;
500 }
501
502 static const struct snd_soc_dai_ops cs42l43_asp_ops = {
503 .startup = cs42l43_startup,
504 .hw_params = cs42l43_asp_hw_params,
505 .set_fmt = cs42l43_asp_set_fmt,
506 .set_tdm_slot = cs42l43_asp_set_tdm_slot,
507 };
508
cs42l43_sdw_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)509 static int cs42l43_sdw_hw_params(struct snd_pcm_substream *substream,
510 struct snd_pcm_hw_params *params,
511 struct snd_soc_dai *dai)
512 {
513 int ret;
514
515 ret = cs42l43_sdw_add_peripheral(substream, params, dai);
516 if (ret)
517 return ret;
518
519 return cs42l43_set_sample_rate(substream, params, dai);
520 };
521
522 static const struct snd_soc_dai_ops cs42l43_sdw_ops = {
523 .startup = cs42l43_startup,
524 .set_stream = cs42l43_sdw_set_stream,
525 .hw_params = cs42l43_sdw_hw_params,
526 .hw_free = cs42l43_sdw_remove_peripheral,
527 };
528
529 #define CS42L43_ASP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
530 SNDRV_PCM_FMTBIT_S32_LE)
531 #define CS42L43_SDW_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
532
533 static struct snd_soc_dai_driver cs42l43_dais[] = {
534 {
535 .name = "cs42l43-asp",
536 .ops = &cs42l43_asp_ops,
537 .symmetric_rate = 1,
538 .capture = {
539 .stream_name = "ASP Capture",
540 .channels_min = 1,
541 .channels_max = CS42L43_ASP_MAX_CHANNELS,
542 .rates = SNDRV_PCM_RATE_KNOT,
543 .formats = CS42L43_ASP_FORMATS,
544 },
545 .playback = {
546 .stream_name = "ASP Playback",
547 .channels_min = 1,
548 .channels_max = CS42L43_ASP_MAX_CHANNELS,
549 .rates = SNDRV_PCM_RATE_KNOT,
550 .formats = CS42L43_ASP_FORMATS,
551 },
552 },
553 {
554 .name = "cs42l43-dp1",
555 .id = 1,
556 .ops = &cs42l43_sdw_ops,
557 .capture = {
558 .stream_name = "DP1 Capture",
559 .channels_min = 1,
560 .channels_max = 4,
561 .rates = SNDRV_PCM_RATE_KNOT,
562 .formats = CS42L43_SDW_FORMATS,
563 },
564 },
565 {
566 .name = "cs42l43-dp2",
567 .id = 2,
568 .ops = &cs42l43_sdw_ops,
569 .capture = {
570 .stream_name = "DP2 Capture",
571 .channels_min = 1,
572 .channels_max = 2,
573 .rates = SNDRV_PCM_RATE_KNOT,
574 .formats = CS42L43_SDW_FORMATS,
575 },
576 },
577 {
578 .name = "cs42l43-dp3",
579 .id = 3,
580 .ops = &cs42l43_sdw_ops,
581 .capture = {
582 .stream_name = "DP3 Capture",
583 .channels_min = 1,
584 .channels_max = 2,
585 .rates = SNDRV_PCM_RATE_KNOT,
586 .formats = CS42L43_SDW_FORMATS,
587 },
588 },
589 {
590 .name = "cs42l43-dp4",
591 .id = 4,
592 .ops = &cs42l43_sdw_ops,
593 .capture = {
594 .stream_name = "DP4 Capture",
595 .channels_min = 1,
596 .channels_max = 2,
597 .rates = SNDRV_PCM_RATE_KNOT,
598 .formats = CS42L43_SDW_FORMATS,
599 },
600 },
601 {
602 .name = "cs42l43-dp5",
603 .id = 5,
604 .ops = &cs42l43_sdw_ops,
605 .playback = {
606 .stream_name = "DP5 Playback",
607 .channels_min = 1,
608 .channels_max = 2,
609 .rates = SNDRV_PCM_RATE_KNOT,
610 .formats = CS42L43_SDW_FORMATS,
611 },
612 },
613 {
614 .name = "cs42l43-dp6",
615 .id = 6,
616 .ops = &cs42l43_sdw_ops,
617 .playback = {
618 .stream_name = "DP6 Playback",
619 .channels_min = 1,
620 .channels_max = 2,
621 .rates = SNDRV_PCM_RATE_KNOT,
622 .formats = CS42L43_SDW_FORMATS,
623 },
624 },
625 {
626 .name = "cs42l43-dp7",
627 .id = 7,
628 .ops = &cs42l43_sdw_ops,
629 .playback = {
630 .stream_name = "DP7 Playback",
631 .channels_min = 1,
632 .channels_max = 2,
633 .rates = SNDRV_PCM_RATE_KNOT,
634 .formats = CS42L43_SDW_FORMATS,
635 },
636 },
637 };
638
639 static const DECLARE_TLV_DB_SCALE(cs42l43_mixer_tlv, -3200, 100, 0);
640
641 static const char * const cs42l43_ramp_text[] = {
642 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
643 "15ms/6dB", "30ms/6dB",
644 };
645
646 static const char * const cs42l43_adc1_input_text[] = { "IN1", "IN2" };
647
648 static SOC_ENUM_SINGLE_DECL(cs42l43_adc1_input, CS42L43_ADC_B_CTRL1,
649 CS42L43_ADC_AIN_SEL_SHIFT,
650 cs42l43_adc1_input_text);
651
652 static const struct snd_kcontrol_new cs42l43_adc1_input_ctl =
653 SOC_DAPM_ENUM("ADC1 Input", cs42l43_adc1_input);
654
655 static const char * const cs42l43_dec_mode_text[] = { "ADC", "PDM" };
656
657 static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec1_mode, cs42l43_dec_mode_text);
658 static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec2_mode, cs42l43_dec_mode_text);
659
660 static const struct snd_kcontrol_new cs42l43_dec_mode_ctl[] = {
661 SOC_DAPM_ENUM("Decimator 1 Mode", cs42l43_dec1_mode),
662 SOC_DAPM_ENUM("Decimator 2 Mode", cs42l43_dec2_mode),
663 };
664
665 static const char * const cs42l43_pdm_clk_text[] = {
666 "3.072MHz", "1.536MHz", "768kHz",
667 };
668
669 static SOC_ENUM_SINGLE_DECL(cs42l43_pdm1_clk, CS42L43_PDM_CONTROL,
670 CS42L43_PDM1_CLK_DIV_SHIFT, cs42l43_pdm_clk_text);
671 static SOC_ENUM_SINGLE_DECL(cs42l43_pdm2_clk, CS42L43_PDM_CONTROL,
672 CS42L43_PDM2_CLK_DIV_SHIFT, cs42l43_pdm_clk_text);
673
674 static DECLARE_TLV_DB_SCALE(cs42l43_adc_tlv, -600, 600, 0);
675 static DECLARE_TLV_DB_SCALE(cs42l43_dec_tlv, -6400, 50, 0);
676
677 static const char * const cs42l43_wnf_corner_text[] = {
678 "160Hz", "180Hz", "200Hz", "220Hz", "240Hz", "260Hz", "280Hz", "300Hz",
679 };
680
681 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL1,
682 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
683 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL2,
684 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
685 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL3,
686 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
687 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL4,
688 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
689
690 static const char * const cs42l43_hpf_corner_text[] = {
691 "3Hz", "12Hz", "48Hz", "96Hz",
692 };
693
694 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL1,
695 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
696 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL2,
697 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
698 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL3,
699 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
700 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL4,
701 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
702
703 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
704 CS42L43_DECIM1_VI_RAMP_SHIFT, cs42l43_ramp_text);
705 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
706 CS42L43_DECIM1_VD_RAMP_SHIFT, cs42l43_ramp_text);
707 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
708 CS42L43_DECIM2_VI_RAMP_SHIFT, cs42l43_ramp_text);
709 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
710 CS42L43_DECIM2_VD_RAMP_SHIFT, cs42l43_ramp_text);
711 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
712 CS42L43_DECIM3_VI_RAMP_SHIFT, cs42l43_ramp_text);
713 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
714 CS42L43_DECIM3_VD_RAMP_SHIFT, cs42l43_ramp_text);
715 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
716 CS42L43_DECIM4_VI_RAMP_SHIFT, cs42l43_ramp_text);
717 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
718 CS42L43_DECIM4_VD_RAMP_SHIFT, cs42l43_ramp_text);
719
720 static DECLARE_TLV_DB_SCALE(cs42l43_speaker_tlv, -6400, 50, 0);
721
722 static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_up, CS42L43_AMP1_2_VOL_RAMP,
723 CS42L43_AMP1_2_VI_RAMP_SHIFT, cs42l43_ramp_text);
724
725 static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_down, CS42L43_AMP1_2_VOL_RAMP,
726 CS42L43_AMP1_2_VD_RAMP_SHIFT, cs42l43_ramp_text);
727
728 static DECLARE_TLV_DB_SCALE(cs42l43_headphone_tlv, -11450, 50, 1);
729
730 static const char * const cs42l43_headphone_ramp_text[] = {
731 "1", "2", "4", "6", "8", "11", "12", "16", "22", "24", "33", "36", "44",
732 "48", "66", "72",
733 };
734
735 static SOC_ENUM_SINGLE_DECL(cs42l43_headphone_ramp, CS42L43_PGAVOL,
736 CS42L43_HP_PATH_VOL_RAMP_SHIFT,
737 cs42l43_headphone_ramp_text);
738
739 static const char * const cs42l43_tone_freq_text[] = {
740 "1kHz", "2kHz", "4kHz", "6kHz", "8kHz",
741 };
742
743 static SOC_ENUM_SINGLE_DECL(cs42l43_tone1_freq, CS42L43_TONE_CH1_CTRL,
744 CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text);
745
746 static SOC_ENUM_SINGLE_DECL(cs42l43_tone2_freq, CS42L43_TONE_CH2_CTRL,
747 CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text);
748
749 static const char * const cs42l43_mixer_texts[] = {
750 "None",
751 "Tone Generator 1", "Tone Generator 2",
752 "Decimator 1", "Decimator 2", "Decimator 3", "Decimator 4",
753 "ASPRX1", "ASPRX2", "ASPRX3", "ASPRX4", "ASPRX5", "ASPRX6",
754 "DP5RX1", "DP5RX2", "DP6RX1", "DP6RX2", "DP7RX1", "DP7RX2",
755 "ASRC INT1", "ASRC INT2", "ASRC INT3", "ASRC INT4",
756 "ASRC DEC1", "ASRC DEC2", "ASRC DEC3", "ASRC DEC4",
757 "ISRC1 INT1", "ISRC1 INT2",
758 "ISRC1 DEC1", "ISRC1 DEC2",
759 "ISRC2 INT1", "ISRC2 INT2",
760 "ISRC2 DEC1", "ISRC2 DEC2",
761 "EQ1", "EQ2",
762 };
763
764 static const unsigned int cs42l43_mixer_values[] = {
765 0x00, // None
766 0x04, 0x05, // Tone Generator 1, 2
767 0x10, 0x11, 0x12, 0x13, // Decimator 1, 2, 3, 4
768 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, // ASPRX1,2,3,4,5,6
769 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, // DP5, 6, 7RX1, 2
770 0x40, 0x41, 0x42, 0x43, // ASRC INT1, 2, 3, 4
771 0x44, 0x45, 0x46, 0x47, // ASRC DEC1, 2, 3, 4
772 0x50, 0x51, // ISRC1 INT1, 2
773 0x52, 0x53, // ISRC1 DEC1, 2
774 0x54, 0x55, // ISRC2 INT1, 2
775 0x56, 0x57, // ISRC2 DEC1, 2
776 0x58, 0x59, // EQ1, 2
777 };
778
779 CS42L43_DECL_MUX(asptx1, CS42L43_ASPTX1_INPUT);
780 CS42L43_DECL_MUX(asptx2, CS42L43_ASPTX2_INPUT);
781 CS42L43_DECL_MUX(asptx3, CS42L43_ASPTX3_INPUT);
782 CS42L43_DECL_MUX(asptx4, CS42L43_ASPTX4_INPUT);
783 CS42L43_DECL_MUX(asptx5, CS42L43_ASPTX5_INPUT);
784 CS42L43_DECL_MUX(asptx6, CS42L43_ASPTX6_INPUT);
785
786 CS42L43_DECL_MUX(dp1tx1, CS42L43_SWIRE_DP1_CH1_INPUT);
787 CS42L43_DECL_MUX(dp1tx2, CS42L43_SWIRE_DP1_CH2_INPUT);
788 CS42L43_DECL_MUX(dp1tx3, CS42L43_SWIRE_DP1_CH3_INPUT);
789 CS42L43_DECL_MUX(dp1tx4, CS42L43_SWIRE_DP1_CH4_INPUT);
790 CS42L43_DECL_MUX(dp2tx1, CS42L43_SWIRE_DP2_CH1_INPUT);
791 CS42L43_DECL_MUX(dp2tx2, CS42L43_SWIRE_DP2_CH2_INPUT);
792 CS42L43_DECL_MUX(dp3tx1, CS42L43_SWIRE_DP3_CH1_INPUT);
793 CS42L43_DECL_MUX(dp3tx2, CS42L43_SWIRE_DP3_CH2_INPUT);
794 CS42L43_DECL_MUX(dp4tx1, CS42L43_SWIRE_DP4_CH1_INPUT);
795 CS42L43_DECL_MUX(dp4tx2, CS42L43_SWIRE_DP4_CH2_INPUT);
796
797 CS42L43_DECL_MUX(asrcint1, CS42L43_ASRC_INT1_INPUT1);
798 CS42L43_DECL_MUX(asrcint2, CS42L43_ASRC_INT2_INPUT1);
799 CS42L43_DECL_MUX(asrcint3, CS42L43_ASRC_INT3_INPUT1);
800 CS42L43_DECL_MUX(asrcint4, CS42L43_ASRC_INT4_INPUT1);
801 CS42L43_DECL_MUX(asrcdec1, CS42L43_ASRC_DEC1_INPUT1);
802 CS42L43_DECL_MUX(asrcdec2, CS42L43_ASRC_DEC2_INPUT1);
803 CS42L43_DECL_MUX(asrcdec3, CS42L43_ASRC_DEC3_INPUT1);
804 CS42L43_DECL_MUX(asrcdec4, CS42L43_ASRC_DEC4_INPUT1);
805
806 CS42L43_DECL_MUX(isrc1int1, CS42L43_ISRC1INT1_INPUT1);
807 CS42L43_DECL_MUX(isrc1int2, CS42L43_ISRC1INT2_INPUT1);
808 CS42L43_DECL_MUX(isrc1dec1, CS42L43_ISRC1DEC1_INPUT1);
809 CS42L43_DECL_MUX(isrc1dec2, CS42L43_ISRC1DEC2_INPUT1);
810 CS42L43_DECL_MUX(isrc2int1, CS42L43_ISRC2INT1_INPUT1);
811 CS42L43_DECL_MUX(isrc2int2, CS42L43_ISRC2INT2_INPUT1);
812 CS42L43_DECL_MUX(isrc2dec1, CS42L43_ISRC2DEC1_INPUT1);
813 CS42L43_DECL_MUX(isrc2dec2, CS42L43_ISRC2DEC2_INPUT1);
814
815 CS42L43_DECL_MUX(spdif1, CS42L43_SPDIF1_INPUT1);
816 CS42L43_DECL_MUX(spdif2, CS42L43_SPDIF2_INPUT1);
817
818 CS42L43_DECL_MIXER(eq1, CS42L43_EQ1MIX_INPUT1);
819 CS42L43_DECL_MIXER(eq2, CS42L43_EQ2MIX_INPUT1);
820
821 CS42L43_DECL_MIXER(amp1, CS42L43_AMP1MIX_INPUT1);
822 CS42L43_DECL_MIXER(amp2, CS42L43_AMP2MIX_INPUT1);
823
824 CS42L43_DECL_MIXER(amp3, CS42L43_AMP3MIX_INPUT1);
825 CS42L43_DECL_MIXER(amp4, CS42L43_AMP4MIX_INPUT1);
826
cs42l43_dapm_get_volsw(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)827 static int cs42l43_dapm_get_volsw(struct snd_kcontrol *kcontrol,
828 struct snd_ctl_elem_value *ucontrol)
829 {
830 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
831 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
832 int ret;
833
834 snd_soc_dapm_mutex_lock(dapm);
835 ret = snd_soc_get_volsw(kcontrol, ucontrol);
836 snd_soc_dapm_mutex_unlock(dapm);
837
838 return ret;
839 }
840
cs42l43_dapm_put_volsw(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)841 static int cs42l43_dapm_put_volsw(struct snd_kcontrol *kcontrol,
842 struct snd_ctl_elem_value *ucontrol)
843 {
844 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
845 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
846 int ret;
847
848 snd_soc_dapm_mutex_lock(dapm);
849 ret = snd_soc_put_volsw(kcontrol, ucontrol);
850 snd_soc_dapm_mutex_unlock(dapm);
851
852 return ret;
853 }
854
cs42l43_dapm_get_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)855 static int cs42l43_dapm_get_enum(struct snd_kcontrol *kcontrol,
856 struct snd_ctl_elem_value *ucontrol)
857 {
858 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
859 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
860 int ret;
861
862 snd_soc_dapm_mutex_lock(dapm);
863 ret = snd_soc_get_enum_double(kcontrol, ucontrol);
864 snd_soc_dapm_mutex_unlock(dapm);
865
866 return ret;
867 }
868
cs42l43_dapm_put_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)869 static int cs42l43_dapm_put_enum(struct snd_kcontrol *kcontrol,
870 struct snd_ctl_elem_value *ucontrol)
871 {
872 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
873 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
874 int ret;
875
876 snd_soc_dapm_mutex_lock(dapm);
877 ret = snd_soc_put_enum_double(kcontrol, ucontrol);
878 snd_soc_dapm_mutex_unlock(dapm);
879
880 return ret;
881 }
882
cs42l43_eq_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)883 static int cs42l43_eq_get(struct snd_kcontrol *kcontrol,
884 struct snd_ctl_elem_value *ucontrol)
885 {
886 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
887 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
888
889 memcpy(ucontrol->value.integer.value, priv->eq_coeffs, sizeof(priv->eq_coeffs));
890
891 return 0;
892 }
893
cs42l43_eq_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)894 static int cs42l43_eq_put(struct snd_kcontrol *kcontrol,
895 struct snd_ctl_elem_value *ucontrol)
896 {
897 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
898 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
899 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
900
901 snd_soc_dapm_mutex_lock(dapm);
902
903 memcpy(priv->eq_coeffs, ucontrol->value.integer.value, sizeof(priv->eq_coeffs));
904
905 snd_soc_dapm_mutex_unlock(dapm);
906
907 return 0;
908 }
909
cs42l43_spk_vu_sync(struct cs42l43_codec * priv)910 static void cs42l43_spk_vu_sync(struct cs42l43_codec *priv)
911 {
912 struct cs42l43 *cs42l43 = priv->core;
913
914 mutex_lock(&priv->spk_vu_lock);
915
916 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1,
917 CS42L43_AMP1_2_VU_MASK, CS42L43_AMP1_2_VU_MASK);
918 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1,
919 CS42L43_AMP1_2_VU_MASK, 0);
920
921 mutex_unlock(&priv->spk_vu_lock);
922 }
923
cs42l43_shutter_get(struct cs42l43_codec * priv,unsigned int shift)924 static int cs42l43_shutter_get(struct cs42l43_codec *priv, unsigned int shift)
925 {
926 struct cs42l43 *cs42l43 = priv->core;
927 unsigned int val;
928 int ret;
929
930 ret = pm_runtime_resume_and_get(priv->dev);
931 if (ret) {
932 dev_err(priv->dev, "Failed to resume for shutters: %d\n", ret);
933 return ret;
934 }
935
936 /*
937 * SHUTTER_CONTROL is a mix of volatile and non-volatile bits, so must
938 * be cached for the non-volatiles, so drop it from the cache here so
939 * we force a read.
940 */
941 ret = regcache_drop_region(cs42l43->regmap, CS42L43_SHUTTER_CONTROL,
942 CS42L43_SHUTTER_CONTROL);
943 if (ret) {
944 dev_err(priv->dev, "Failed to drop shutter from cache: %d\n", ret);
945 goto error;
946 }
947
948 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val);
949 if (ret) {
950 dev_err(priv->dev, "Failed to check shutter status: %d\n", ret);
951 goto error;
952 }
953
954 ret = !(val & BIT(shift));
955
956 dev_dbg(priv->dev, "%s shutter is %s\n",
957 BIT(shift) == CS42L43_STATUS_MIC_SHUTTER_MUTE_MASK ? "Mic" : "Speaker",
958 ret ? "open" : "closed");
959
960 error:
961 pm_runtime_mark_last_busy(priv->dev);
962 pm_runtime_put_autosuspend(priv->dev);
963
964 return ret;
965 }
966
cs42l43_decim_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)967 static int cs42l43_decim_get(struct snd_kcontrol *kcontrol,
968 struct snd_ctl_elem_value *ucontrol)
969 {
970 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
971 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
972 int ret;
973
974 ret = cs42l43_shutter_get(priv, CS42L43_STATUS_MIC_SHUTTER_MUTE_SHIFT);
975 if (ret < 0)
976 return ret;
977 else if (!ret)
978 ucontrol->value.integer.value[0] = ret;
979 else
980 ret = cs42l43_dapm_get_volsw(kcontrol, ucontrol);
981
982 return ret;
983 }
984
cs42l43_spk_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)985 static int cs42l43_spk_get(struct snd_kcontrol *kcontrol,
986 struct snd_ctl_elem_value *ucontrol)
987 {
988 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
989 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
990 int ret;
991
992 ret = cs42l43_shutter_get(priv, CS42L43_STATUS_SPK_SHUTTER_MUTE_SHIFT);
993 if (ret < 0)
994 return ret;
995 else if (!ret)
996 ucontrol->value.integer.value[0] = ret;
997 else
998 ret = snd_soc_get_volsw(kcontrol, ucontrol);
999
1000 return ret;
1001 }
1002
cs42l43_spk_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1003 static int cs42l43_spk_put(struct snd_kcontrol *kcontrol,
1004 struct snd_ctl_elem_value *ucontrol)
1005 {
1006 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1007 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1008 int ret;
1009
1010 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1011 if (ret > 0)
1012 cs42l43_spk_vu_sync(priv);
1013
1014 return ret;
1015 }
1016
1017 static const struct snd_kcontrol_new cs42l43_controls[] = {
1018 SOC_ENUM_EXT("Jack Override", cs42l43_jack_enum,
1019 cs42l43_jack_get, cs42l43_jack_put),
1020
1021 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L43_ADC_B_CTRL1, CS42L43_ADC_B_CTRL2,
1022 CS42L43_ADC_PGA_GAIN_SHIFT,
1023 0xF, 5, cs42l43_adc_tlv),
1024
1025 SOC_DOUBLE("PDM1 Invert Switch", CS42L43_DMIC_PDM_CTRL,
1026 CS42L43_PDM1L_INV_SHIFT, CS42L43_PDM1R_INV_SHIFT, 1, 0),
1027 SOC_DOUBLE("PDM2 Invert Switch", CS42L43_DMIC_PDM_CTRL,
1028 CS42L43_PDM2L_INV_SHIFT, CS42L43_PDM2R_INV_SHIFT, 1, 0),
1029 SOC_ENUM("PDM1 Clock", cs42l43_pdm1_clk),
1030 SOC_ENUM("PDM2 Clock", cs42l43_pdm2_clk),
1031
1032 SOC_SINGLE("Decimator 1 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL1,
1033 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1034 SOC_SINGLE("Decimator 2 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL2,
1035 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1036 SOC_SINGLE("Decimator 3 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL3,
1037 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1038 SOC_SINGLE("Decimator 4 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL4,
1039 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1040
1041 SOC_ENUM("Decimator 1 WNF Corner Frequency", cs42l43_dec1_wnf_corner),
1042 SOC_ENUM("Decimator 2 WNF Corner Frequency", cs42l43_dec2_wnf_corner),
1043 SOC_ENUM("Decimator 3 WNF Corner Frequency", cs42l43_dec3_wnf_corner),
1044 SOC_ENUM("Decimator 4 WNF Corner Frequency", cs42l43_dec4_wnf_corner),
1045
1046 SOC_SINGLE("Decimator 1 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL1,
1047 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1048 SOC_SINGLE("Decimator 2 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL2,
1049 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1050 SOC_SINGLE("Decimator 3 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL3,
1051 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1052 SOC_SINGLE("Decimator 4 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL4,
1053 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1054
1055 SOC_ENUM("Decimator 1 HPF Corner Frequency", cs42l43_dec1_hpf_corner),
1056 SOC_ENUM("Decimator 2 HPF Corner Frequency", cs42l43_dec2_hpf_corner),
1057 SOC_ENUM("Decimator 3 HPF Corner Frequency", cs42l43_dec3_hpf_corner),
1058 SOC_ENUM("Decimator 4 HPF Corner Frequency", cs42l43_dec4_hpf_corner),
1059
1060 SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
1061 CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
1062 SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
1063 CS42L43_DECIM1_MUTE_SHIFT, 1, 1,
1064 cs42l43_decim_get, cs42l43_dapm_put_volsw),
1065 SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
1066 CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
1067 SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
1068 CS42L43_DECIM2_MUTE_SHIFT, 1, 1,
1069 cs42l43_decim_get, cs42l43_dapm_put_volsw),
1070 SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
1071 CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
1072 SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
1073 CS42L43_DECIM3_MUTE_SHIFT, 1, 1,
1074 cs42l43_decim_get, cs42l43_dapm_put_volsw),
1075 SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
1076 CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
1077 SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
1078 CS42L43_DECIM4_MUTE_SHIFT, 1, 1,
1079 cs42l43_decim_get, cs42l43_dapm_put_volsw),
1080
1081 SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43_dec1_ramp_up,
1082 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1083 SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43_dec1_ramp_down,
1084 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1085 SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43_dec2_ramp_up,
1086 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1087 SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43_dec2_ramp_down,
1088 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1089 SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43_dec3_ramp_up,
1090 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1091 SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43_dec3_ramp_down,
1092 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1093 SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43_dec4_ramp_up,
1094 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1095 SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43_dec4_ramp_down,
1096 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1097
1098 SOC_DOUBLE_R_EXT("Speaker Digital Switch",
1099 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2,
1100 CS42L43_AMP_MUTE_SHIFT, 1, 1,
1101 cs42l43_spk_get, cs42l43_spk_put),
1102
1103 SOC_DOUBLE_R_EXT_TLV("Speaker Digital Volume",
1104 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2,
1105 CS42L43_AMP_VOL_SHIFT,
1106 0xBF, 0, snd_soc_get_volsw, cs42l43_spk_put,
1107 cs42l43_speaker_tlv),
1108
1109 SOC_ENUM("Speaker Ramp Up", cs42l43_speaker_ramp_up),
1110 SOC_ENUM("Speaker Ramp Down", cs42l43_speaker_ramp_down),
1111
1112 CS42L43_MIXER_VOLUMES("Speaker L", CS42L43_AMP1MIX_INPUT1),
1113 CS42L43_MIXER_VOLUMES("Speaker R", CS42L43_AMP2MIX_INPUT1),
1114
1115 SOC_DOUBLE_SX_TLV("Headphone Digital Volume", CS42L43_HPPATHVOL,
1116 CS42L43_AMP3_PATH_VOL_SHIFT, CS42L43_AMP4_PATH_VOL_SHIFT,
1117 0x11B, 229, cs42l43_headphone_tlv),
1118
1119 SOC_DOUBLE("Headphone Invert Switch", CS42L43_DACCNFG1,
1120 CS42L43_AMP3_INV_SHIFT, CS42L43_AMP4_INV_SHIFT, 1, 0),
1121
1122 SOC_SINGLE("Headphone Zero Cross Switch", CS42L43_PGAVOL,
1123 CS42L43_HP_PATH_VOL_ZC_SHIFT, 1, 0),
1124 SOC_SINGLE("Headphone Ramp Switch", CS42L43_PGAVOL,
1125 CS42L43_HP_PATH_VOL_SFT_SHIFT, 1, 0),
1126 SOC_ENUM("Headphone Ramp Rate", cs42l43_headphone_ramp),
1127
1128 CS42L43_MIXER_VOLUMES("Headphone L", CS42L43_AMP3MIX_INPUT1),
1129 CS42L43_MIXER_VOLUMES("Headphone R", CS42L43_AMP4MIX_INPUT1),
1130
1131 SOC_ENUM("Tone 1 Frequency", cs42l43_tone1_freq),
1132 SOC_ENUM("Tone 2 Frequency", cs42l43_tone2_freq),
1133
1134 SOC_DOUBLE_EXT("EQ Switch",
1135 CS42L43_MUTE_EQ_IN0, CS42L43_MUTE_EQ_CH1_SHIFT,
1136 CS42L43_MUTE_EQ_CH2_SHIFT, 1, 1,
1137 cs42l43_dapm_get_volsw, cs42l43_dapm_put_volsw),
1138
1139 SND_SOC_BYTES_E("EQ Coefficients", 0, CS42L43_N_EQ_COEFFS,
1140 cs42l43_eq_get, cs42l43_eq_put),
1141
1142 CS42L43_MIXER_VOLUMES("EQ1", CS42L43_EQ1MIX_INPUT1),
1143 CS42L43_MIXER_VOLUMES("EQ2", CS42L43_EQ2MIX_INPUT1),
1144 };
1145
cs42l43_eq_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1146 static int cs42l43_eq_ev(struct snd_soc_dapm_widget *w,
1147 struct snd_kcontrol *kcontrol, int event)
1148 {
1149 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1150 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1151 struct cs42l43 *cs42l43 = priv->core;
1152 unsigned int val;
1153 int i, ret;
1154
1155 switch (event) {
1156 case SND_SOC_DAPM_PRE_PMU:
1157 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0,
1158 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK,
1159 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK);
1160
1161 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0,
1162 CS42L43_WRITE_MODE_MASK, CS42L43_WRITE_MODE_MASK);
1163
1164 for (i = 0; i < CS42L43_N_EQ_COEFFS; i++)
1165 regmap_write(cs42l43->regmap, CS42L43_COEFF_DATA_IN0,
1166 priv->eq_coeffs[i]);
1167
1168 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0,
1169 CS42L43_WRITE_MODE_MASK, 0);
1170
1171 return 0;
1172 case SND_SOC_DAPM_POST_PMU:
1173 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_INIT_DONE0,
1174 val, (val & CS42L43_INITIALIZE_DONE_MASK),
1175 2000, 10000);
1176 if (ret)
1177 dev_err(priv->dev, "Failed to start EQs: %d\n", ret);
1178
1179 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0,
1180 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK, 0);
1181 return ret;
1182 default:
1183 return 0;
1184 }
1185 }
1186
1187 struct cs42l43_pll_config {
1188 unsigned int freq;
1189
1190 unsigned int div;
1191 unsigned int mode;
1192 unsigned int cal;
1193 };
1194
1195 static const struct cs42l43_pll_config cs42l43_pll_configs[] = {
1196 { 2400000, 0x50000000, 0x1, 0xA4 },
1197 { 3000000, 0x40000000, 0x1, 0x83 },
1198 { 3072000, 0x40000000, 0x3, 0x80 },
1199 };
1200
cs42l43_set_pll(struct cs42l43_codec * priv,unsigned int src,unsigned int freq)1201 static int cs42l43_set_pll(struct cs42l43_codec *priv, unsigned int src,
1202 unsigned int freq)
1203 {
1204 struct cs42l43 *cs42l43 = priv->core;
1205
1206 lockdep_assert_held(&cs42l43->pll_lock);
1207
1208 if (priv->refclk_src == src && priv->refclk_freq == freq)
1209 return 0;
1210
1211 if (regmap_test_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK)) {
1212 dev_err(priv->dev, "PLL active, can't change configuration\n");
1213 return -EBUSY;
1214 }
1215
1216 switch (src) {
1217 case CS42L43_SYSCLK_MCLK:
1218 case CS42L43_SYSCLK_SDW:
1219 dev_dbg(priv->dev, "Source PLL from %s at %uHz\n",
1220 src ? "SoundWire" : "MCLK", freq);
1221
1222 priv->refclk_src = src;
1223 priv->refclk_freq = freq;
1224
1225 return 0;
1226 default:
1227 dev_err(priv->dev, "Invalid PLL source: 0x%x\n", src);
1228 return -EINVAL;
1229 }
1230 }
1231
cs42l43_enable_pll(struct cs42l43_codec * priv)1232 static int cs42l43_enable_pll(struct cs42l43_codec *priv)
1233 {
1234 static const struct reg_sequence enable_seq[] = {
1235 { CS42L43_OSC_DIV_SEL, 0x0, },
1236 { CS42L43_MCLK_SRC_SEL, CS42L43_OSC_PLL_MCLK_SEL_MASK, 5, },
1237 };
1238 struct cs42l43 *cs42l43 = priv->core;
1239 const struct cs42l43_pll_config *config = NULL;
1240 unsigned int div = 0;
1241 unsigned int freq = priv->refclk_freq;
1242 unsigned long time_left;
1243
1244 lockdep_assert_held(&cs42l43->pll_lock);
1245
1246 if (priv->refclk_src == CS42L43_SYSCLK_SDW) {
1247 if (!freq)
1248 freq = cs42l43->sdw_freq;
1249 else if (!cs42l43->sdw_freq)
1250 cs42l43->sdw_freq = freq;
1251 }
1252
1253 dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq);
1254
1255 while (freq > cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq) {
1256 div++;
1257 freq /= 2;
1258 }
1259
1260 if (div <= CS42L43_PLL_REFCLK_DIV_MASK) {
1261 int i;
1262
1263 for (i = 0; i < ARRAY_SIZE(cs42l43_pll_configs); i++) {
1264 if (freq == cs42l43_pll_configs[i].freq) {
1265 config = &cs42l43_pll_configs[i];
1266 break;
1267 }
1268 }
1269 }
1270
1271 if (!config) {
1272 dev_err(priv->dev, "No suitable PLL config: 0x%x, %uHz\n", div, freq);
1273 return -EINVAL;
1274 }
1275
1276 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1277 CS42L43_PLL_REFCLK_DIV_MASK | CS42L43_PLL_REFCLK_SRC_MASK,
1278 div << CS42L43_PLL_REFCLK_DIV_SHIFT |
1279 priv->refclk_src << CS42L43_PLL_REFCLK_SRC_SHIFT);
1280 regmap_write(cs42l43->regmap, CS42L43_FDIV_FRAC, config->div);
1281 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1282 CS42L43_PLL_MODE_BYPASS_500_MASK |
1283 CS42L43_PLL_MODE_BYPASS_1029_MASK,
1284 config->mode << CS42L43_PLL_MODE_BYPASS_1029_SHIFT);
1285 regmap_update_bits(cs42l43->regmap, CS42L43_CAL_RATIO,
1286 CS42L43_PLL_CAL_RATIO_MASK, config->cal);
1287 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1288 CS42L43_PLL_REFCLK_EN_MASK, CS42L43_PLL_REFCLK_EN_MASK);
1289
1290 reinit_completion(&priv->pll_ready);
1291
1292 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1293 CS42L43_PLL_EN_MASK, CS42L43_PLL_EN_MASK);
1294
1295 time_left = wait_for_completion_timeout(&priv->pll_ready,
1296 msecs_to_jiffies(CS42L43_PLL_TIMEOUT_MS));
1297 if (!time_left) {
1298 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1299 CS42L43_PLL_EN_MASK, 0);
1300 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1301 CS42L43_PLL_REFCLK_EN_MASK, 0);
1302
1303 dev_err(priv->dev, "Timeout out waiting for PLL\n");
1304 return -ETIMEDOUT;
1305 }
1306
1307 if (priv->refclk_src == CS42L43_SYSCLK_SDW)
1308 cs42l43->sdw_pll_active = true;
1309
1310 dev_dbg(priv->dev, "PLL locked in %ums\n", 200 - jiffies_to_msecs(time_left));
1311
1312 /*
1313 * Reads are not allowed over Soundwire without OSC_DIV2_EN or the PLL,
1314 * but you can not change to PLL with OSC_DIV2_EN set. So ensure the whole
1315 * change over happens under the regmap lock to prevent any reads.
1316 */
1317 regmap_multi_reg_write(cs42l43->regmap, enable_seq, ARRAY_SIZE(enable_seq));
1318
1319 return 0;
1320 }
1321
cs42l43_disable_pll(struct cs42l43_codec * priv)1322 static int cs42l43_disable_pll(struct cs42l43_codec *priv)
1323 {
1324 static const struct reg_sequence disable_seq[] = {
1325 { CS42L43_MCLK_SRC_SEL, 0x0, 5, },
1326 { CS42L43_OSC_DIV_SEL, CS42L43_OSC_DIV2_EN_MASK, },
1327 };
1328 struct cs42l43 *cs42l43 = priv->core;
1329
1330 dev_dbg(priv->dev, "Disabling PLL\n");
1331
1332 lockdep_assert_held(&cs42l43->pll_lock);
1333
1334 regmap_multi_reg_write(cs42l43->regmap, disable_seq, ARRAY_SIZE(disable_seq));
1335 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK, 0);
1336 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1337 CS42L43_PLL_REFCLK_EN_MASK, 0);
1338
1339 cs42l43->sdw_pll_active = false;
1340
1341 return 0;
1342 }
1343
cs42l43_pll_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1344 static int cs42l43_pll_ev(struct snd_soc_dapm_widget *w,
1345 struct snd_kcontrol *kcontrol, int event)
1346 {
1347 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1348 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1349 struct cs42l43 *cs42l43 = priv->core;
1350 int ret;
1351
1352 mutex_lock(&cs42l43->pll_lock);
1353
1354 switch (event) {
1355 case SND_SOC_DAPM_PRE_PMU:
1356 if (priv->refclk_src == CS42L43_SYSCLK_MCLK) {
1357 ret = clk_prepare_enable(priv->mclk);
1358 if (ret) {
1359 dev_err(priv->dev, "Failed to enable MCLK: %d\n", ret);
1360 break;
1361 }
1362 }
1363
1364 ret = cs42l43_enable_pll(priv);
1365 break;
1366 case SND_SOC_DAPM_POST_PMD:
1367 ret = cs42l43_disable_pll(priv);
1368
1369 if (priv->refclk_src == CS42L43_SYSCLK_MCLK)
1370 clk_disable_unprepare(priv->mclk);
1371 break;
1372 default:
1373 ret = 0;
1374 break;
1375 }
1376
1377 mutex_unlock(&cs42l43->pll_lock);
1378
1379 return ret;
1380 }
1381
cs42l43_dapm_wait_completion(struct completion * pmu,struct completion * pmd,int event,int timeout_ms)1382 static int cs42l43_dapm_wait_completion(struct completion *pmu, struct completion *pmd,
1383 int event, int timeout_ms)
1384 {
1385 unsigned long time_left;
1386
1387 switch (event) {
1388 case SND_SOC_DAPM_PRE_PMU:
1389 reinit_completion(pmu);
1390 return 0;
1391 case SND_SOC_DAPM_PRE_PMD:
1392 reinit_completion(pmd);
1393 return 0;
1394 case SND_SOC_DAPM_POST_PMU:
1395 time_left = wait_for_completion_timeout(pmu, msecs_to_jiffies(timeout_ms));
1396 break;
1397 case SND_SOC_DAPM_POST_PMD:
1398 time_left = wait_for_completion_timeout(pmd, msecs_to_jiffies(timeout_ms));
1399 break;
1400 default:
1401 return 0;
1402 }
1403
1404 if (!time_left)
1405 return -ETIMEDOUT;
1406 else
1407 return 0;
1408 }
1409
cs42l43_spkr_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1410 static int cs42l43_spkr_ev(struct snd_soc_dapm_widget *w,
1411 struct snd_kcontrol *kcontrol, int event)
1412 {
1413 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1414 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1415
1416 return cs42l43_dapm_wait_completion(&priv->spkr_startup,
1417 &priv->spkr_shutdown, event,
1418 CS42L43_SPK_TIMEOUT_MS);
1419 }
1420
cs42l43_spkl_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1421 static int cs42l43_spkl_ev(struct snd_soc_dapm_widget *w,
1422 struct snd_kcontrol *kcontrol, int event)
1423 {
1424 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1425 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1426
1427 return cs42l43_dapm_wait_completion(&priv->spkl_startup,
1428 &priv->spkl_shutdown, event,
1429 CS42L43_SPK_TIMEOUT_MS);
1430 }
1431
cs42l43_hp_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1432 static int cs42l43_hp_ev(struct snd_soc_dapm_widget *w,
1433 struct snd_kcontrol *kcontrol, int event)
1434 {
1435 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1436 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1437 struct cs42l43 *cs42l43 = priv->core;
1438 unsigned int mask = 1 << w->shift;
1439 unsigned int val = 0;
1440 int ret;
1441
1442 switch (event) {
1443 case SND_SOC_DAPM_PRE_PMU:
1444 val = mask;
1445 fallthrough;
1446 case SND_SOC_DAPM_PRE_PMD:
1447 priv->hp_ena &= ~mask;
1448 priv->hp_ena |= val;
1449
1450 ret = cs42l43_dapm_wait_completion(&priv->hp_startup,
1451 &priv->hp_shutdown, event,
1452 CS42L43_HP_TIMEOUT_MS);
1453 if (ret)
1454 return ret;
1455
1456 if (!priv->load_detect_running)
1457 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
1458 mask, val);
1459 break;
1460 case SND_SOC_DAPM_POST_PMU:
1461 case SND_SOC_DAPM_POST_PMD:
1462 if (priv->load_detect_running)
1463 break;
1464
1465 ret = cs42l43_dapm_wait_completion(&priv->hp_startup,
1466 &priv->hp_shutdown, event,
1467 CS42L43_HP_TIMEOUT_MS);
1468 if (ret)
1469 return ret;
1470 break;
1471 default:
1472 break;
1473 }
1474
1475 return 0;
1476 }
1477
cs42l43_mic_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1478 static int cs42l43_mic_ev(struct snd_soc_dapm_widget *w,
1479 struct snd_kcontrol *kcontrol, int event)
1480 {
1481 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1482 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1483 struct cs42l43 *cs42l43 = priv->core;
1484 unsigned int reg, ramp, mute;
1485 unsigned int *val;
1486 int ret;
1487
1488 switch (w->shift) {
1489 case CS42L43_ADC1_EN_SHIFT:
1490 case CS42L43_PDM1_DIN_L_EN_SHIFT:
1491 reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2;
1492 ramp = CS42L43_DECIM1_VD_RAMP_MASK;
1493 mute = CS42L43_DECIM1_MUTE_MASK;
1494 val = &priv->decim_cache[0];
1495 break;
1496 case CS42L43_ADC2_EN_SHIFT:
1497 case CS42L43_PDM1_DIN_R_EN_SHIFT:
1498 reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2;
1499 ramp = CS42L43_DECIM2_VD_RAMP_MASK;
1500 mute = CS42L43_DECIM2_MUTE_MASK;
1501 val = &priv->decim_cache[1];
1502 break;
1503 case CS42L43_PDM2_DIN_L_EN_SHIFT:
1504 reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4;
1505 ramp = CS42L43_DECIM3_VD_RAMP_MASK;
1506 mute = CS42L43_DECIM3_MUTE_MASK;
1507 val = &priv->decim_cache[2];
1508 break;
1509 case CS42L43_PDM2_DIN_R_EN_SHIFT:
1510 reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4;
1511 ramp = CS42L43_DECIM4_VD_RAMP_MASK;
1512 mute = CS42L43_DECIM4_MUTE_MASK;
1513 val = &priv->decim_cache[3];
1514 break;
1515 default:
1516 dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift);
1517 return -EINVAL;
1518 }
1519
1520 switch (event) {
1521 case SND_SOC_DAPM_PRE_PMU:
1522 ret = regmap_read(cs42l43->regmap, reg, val);
1523 if (ret) {
1524 dev_err(priv->dev,
1525 "Failed to cache decimator settings: %d\n",
1526 ret);
1527 return ret;
1528 }
1529
1530 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, mute);
1531 break;
1532 case SND_SOC_DAPM_POST_PMU:
1533 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, *val);
1534 break;
1535 default:
1536 break;
1537 }
1538
1539 return 0;
1540 }
1541
cs42l43_adc_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1542 static int cs42l43_adc_ev(struct snd_soc_dapm_widget *w,
1543 struct snd_kcontrol *kcontrol, int event)
1544 {
1545 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1546 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
1547 struct cs42l43 *cs42l43 = priv->core;
1548 unsigned int mask = 1 << w->shift;
1549 unsigned int val = 0;
1550 int ret;
1551
1552 ret = cs42l43_mic_ev(w, kcontrol, event);
1553 if (ret)
1554 return ret;
1555
1556 switch (event) {
1557 case SND_SOC_DAPM_PRE_PMU:
1558 val = mask;
1559 fallthrough;
1560 case SND_SOC_DAPM_PRE_PMD:
1561 priv->adc_ena &= ~mask;
1562 priv->adc_ena |= val;
1563
1564 if (!priv->load_detect_running)
1565 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN3,
1566 mask, val);
1567 fallthrough;
1568 default:
1569 return 0;
1570 }
1571 }
1572
1573 static const struct snd_soc_dapm_widget cs42l43_widgets[] = {
1574 SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, cs42l43_pll_ev,
1575 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1576
1577 SND_SOC_DAPM_INPUT("ADC1_IN1_P"),
1578 SND_SOC_DAPM_INPUT("ADC1_IN1_N"),
1579 SND_SOC_DAPM_INPUT("ADC1_IN2_P"),
1580 SND_SOC_DAPM_INPUT("ADC1_IN2_N"),
1581 SND_SOC_DAPM_INPUT("ADC2_IN_P"),
1582 SND_SOC_DAPM_INPUT("ADC2_IN_N"),
1583
1584 SND_SOC_DAPM_INPUT("PDM1_DIN"),
1585 SND_SOC_DAPM_INPUT("PDM2_DIN"),
1586
1587 SND_SOC_DAPM_MUX("ADC1 Input", SND_SOC_NOPM, 0, 0, &cs42l43_adc1_input_ctl),
1588
1589 SND_SOC_DAPM_PGA_E("ADC1", SND_SOC_NOPM, CS42L43_ADC1_EN_SHIFT, 0, NULL, 0,
1590 cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1591 SND_SOC_DAPM_PRE_PMD),
1592 SND_SOC_DAPM_PGA_E("ADC2", SND_SOC_NOPM, CS42L43_ADC2_EN_SHIFT, 0, NULL, 0,
1593 cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1594 SND_SOC_DAPM_PRE_PMD),
1595
1596 SND_SOC_DAPM_PGA_E("PDM1L", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_L_EN_SHIFT,
1597 0, NULL, 0, cs42l43_mic_ev,
1598 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1599 SND_SOC_DAPM_PGA_E("PDM1R", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_R_EN_SHIFT,
1600 0, NULL, 0, cs42l43_mic_ev,
1601 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1602 SND_SOC_DAPM_PGA_E("PDM2L", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_L_EN_SHIFT,
1603 0, NULL, 0, cs42l43_mic_ev,
1604 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1605 SND_SOC_DAPM_PGA_E("PDM2R", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_R_EN_SHIFT,
1606 0, NULL, 0, cs42l43_mic_ev,
1607 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1608
1609 SND_SOC_DAPM_MUX("Decimator 1 Mode", SND_SOC_NOPM, 0, 0,
1610 &cs42l43_dec_mode_ctl[0]),
1611 SND_SOC_DAPM_MUX("Decimator 2 Mode", SND_SOC_NOPM, 0, 0,
1612 &cs42l43_dec_mode_ctl[1]),
1613
1614 SND_SOC_DAPM_PGA("Decimator 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1615 SND_SOC_DAPM_PGA("Decimator 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1616 SND_SOC_DAPM_PGA("Decimator 3", SND_SOC_NOPM, 0, 0, NULL, 0),
1617 SND_SOC_DAPM_PGA("Decimator 4", SND_SOC_NOPM, 0, 0, NULL, 0),
1618
1619 SND_SOC_DAPM_SUPPLY_S("FSYNC", 0, CS42L43_ASP_CTRL, CS42L43_ASP_FSYNC_EN_SHIFT,
1620 0, NULL, 0),
1621 SND_SOC_DAPM_SUPPLY_S("BCLK", 1, CS42L43_ASP_CTRL, CS42L43_ASP_BCLK_EN_SHIFT,
1622 0, NULL, 0),
1623
1624 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0,
1625 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH1_EN_SHIFT, 0),
1626 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 1,
1627 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH2_EN_SHIFT, 0),
1628 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 2,
1629 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH3_EN_SHIFT, 0),
1630 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 3,
1631 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH4_EN_SHIFT, 0),
1632 SND_SOC_DAPM_AIF_OUT("ASPTX5", NULL, 4,
1633 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH5_EN_SHIFT, 0),
1634 SND_SOC_DAPM_AIF_OUT("ASPTX6", NULL, 5,
1635 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH6_EN_SHIFT, 0),
1636
1637 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0,
1638 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH1_EN_SHIFT, 0),
1639 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 1,
1640 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH2_EN_SHIFT, 0),
1641 SND_SOC_DAPM_AIF_IN("ASPRX3", NULL, 2,
1642 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH3_EN_SHIFT, 0),
1643 SND_SOC_DAPM_AIF_IN("ASPRX4", NULL, 3,
1644 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH4_EN_SHIFT, 0),
1645 SND_SOC_DAPM_AIF_IN("ASPRX5", NULL, 4,
1646 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH5_EN_SHIFT, 0),
1647 SND_SOC_DAPM_AIF_IN("ASPRX6", NULL, 5,
1648 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH6_EN_SHIFT, 0),
1649
1650 SND_SOC_DAPM_AIF_OUT("DP1TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1651 SND_SOC_DAPM_AIF_OUT("DP1TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1652 SND_SOC_DAPM_AIF_OUT("DP1TX3", NULL, 2, SND_SOC_NOPM, 0, 0),
1653 SND_SOC_DAPM_AIF_OUT("DP1TX4", NULL, 3, SND_SOC_NOPM, 0, 0),
1654
1655 SND_SOC_DAPM_AIF_OUT("DP2TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1656 SND_SOC_DAPM_AIF_OUT("DP2TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1657
1658 SND_SOC_DAPM_AIF_OUT("DP3TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1659 SND_SOC_DAPM_AIF_OUT("DP3TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1660
1661 SND_SOC_DAPM_AIF_OUT("DP4TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1662 SND_SOC_DAPM_AIF_OUT("DP4TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1663
1664 SND_SOC_DAPM_AIF_IN("DP5RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1665 SND_SOC_DAPM_AIF_IN("DP5RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1666
1667 SND_SOC_DAPM_AIF_IN("DP6RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1668 SND_SOC_DAPM_AIF_IN("DP6RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1669
1670 SND_SOC_DAPM_AIF_IN("DP7RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1671 SND_SOC_DAPM_AIF_IN("DP7RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1672
1673 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-amp", 0, 0),
1674
1675 SND_SOC_DAPM_PGA_E("AMP1", CS42L43_BLOCK_EN10, CS42L43_AMP1_EN_SHIFT, 0, NULL, 0,
1676 cs42l43_spkl_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1677 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1678 SND_SOC_DAPM_PGA_E("AMP2", CS42L43_BLOCK_EN10, CS42L43_AMP2_EN_SHIFT, 0, NULL, 0,
1679 cs42l43_spkr_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1680 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1681
1682 SND_SOC_DAPM_OUTPUT("AMP1_OUT_P"),
1683 SND_SOC_DAPM_OUTPUT("AMP1_OUT_N"),
1684 SND_SOC_DAPM_OUTPUT("AMP2_OUT_P"),
1685 SND_SOC_DAPM_OUTPUT("AMP2_OUT_N"),
1686
1687 SND_SOC_DAPM_PGA("SPDIF", CS42L43_BLOCK_EN11, CS42L43_SPDIF_EN_SHIFT,
1688 0, NULL, 0),
1689 SND_SOC_DAPM_OUTPUT("SPDIF_TX"),
1690
1691 SND_SOC_DAPM_PGA_E("HP", SND_SOC_NOPM, CS42L43_HP_EN_SHIFT, 0, NULL, 0,
1692 cs42l43_hp_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1693 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1694 SND_SOC_DAPM_OUTPUT("AMP3_OUT"),
1695 SND_SOC_DAPM_OUTPUT("AMP4_OUT"),
1696
1697 SND_SOC_DAPM_SIGGEN("Tone"),
1698 SND_SOC_DAPM_SUPPLY("Tone Generator", CS42L43_BLOCK_EN9, CS42L43_TONE_EN_SHIFT,
1699 0, NULL, 0),
1700 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 1", CS42L43_TONE_CH1_CTRL,
1701 CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0),
1702 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 2", CS42L43_TONE_CH2_CTRL,
1703 CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0),
1704
1705 SND_SOC_DAPM_SUPPLY("ISRC1", CS42L43_BLOCK_EN5, CS42L43_ISRC1_BANK_EN_SHIFT,
1706 0, NULL, 0),
1707 SND_SOC_DAPM_SUPPLY("ISRC2", CS42L43_BLOCK_EN5, CS42L43_ISRC2_BANK_EN_SHIFT,
1708 0, NULL, 0),
1709
1710 SND_SOC_DAPM_PGA("ISRC1INT2", CS42L43_ISRC1_CTRL,
1711 CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0),
1712 SND_SOC_DAPM_PGA("ISRC1INT1", CS42L43_ISRC1_CTRL,
1713 CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0),
1714 SND_SOC_DAPM_PGA("ISRC1DEC2", CS42L43_ISRC1_CTRL,
1715 CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0),
1716 SND_SOC_DAPM_PGA("ISRC1DEC1", CS42L43_ISRC1_CTRL,
1717 CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0),
1718
1719 SND_SOC_DAPM_PGA("ISRC2INT2", CS42L43_ISRC2_CTRL,
1720 CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0),
1721 SND_SOC_DAPM_PGA("ISRC2INT1", CS42L43_ISRC2_CTRL,
1722 CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0),
1723 SND_SOC_DAPM_PGA("ISRC2DEC2", CS42L43_ISRC2_CTRL,
1724 CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0),
1725 SND_SOC_DAPM_PGA("ISRC2DEC1", CS42L43_ISRC2_CTRL,
1726 CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0),
1727
1728 SND_SOC_DAPM_SUPPLY("ASRC_INT", CS42L43_BLOCK_EN4,
1729 CS42L43_ASRC_INT_BANK_EN_SHIFT, 0, NULL, 0),
1730 SND_SOC_DAPM_SUPPLY("ASRC_DEC", CS42L43_BLOCK_EN4,
1731 CS42L43_ASRC_DEC_BANK_EN_SHIFT, 0, NULL, 0),
1732
1733 SND_SOC_DAPM_PGA("ASRC_INT1", CS42L43_ASRC_INT_ENABLES,
1734 CS42L43_ASRC_INT1_EN_SHIFT, 0, NULL, 0),
1735 SND_SOC_DAPM_PGA("ASRC_INT2", CS42L43_ASRC_INT_ENABLES,
1736 CS42L43_ASRC_INT2_EN_SHIFT, 0, NULL, 0),
1737 SND_SOC_DAPM_PGA("ASRC_INT3", CS42L43_ASRC_INT_ENABLES,
1738 CS42L43_ASRC_INT3_EN_SHIFT, 0, NULL, 0),
1739 SND_SOC_DAPM_PGA("ASRC_INT4", CS42L43_ASRC_INT_ENABLES,
1740 CS42L43_ASRC_INT4_EN_SHIFT, 0, NULL, 0),
1741 SND_SOC_DAPM_PGA("ASRC_DEC1", CS42L43_ASRC_DEC_ENABLES,
1742 CS42L43_ASRC_DEC1_EN_SHIFT, 0, NULL, 0),
1743 SND_SOC_DAPM_PGA("ASRC_DEC2", CS42L43_ASRC_DEC_ENABLES,
1744 CS42L43_ASRC_DEC2_EN_SHIFT, 0, NULL, 0),
1745 SND_SOC_DAPM_PGA("ASRC_DEC3", CS42L43_ASRC_DEC_ENABLES,
1746 CS42L43_ASRC_DEC3_EN_SHIFT, 0, NULL, 0),
1747 SND_SOC_DAPM_PGA("ASRC_DEC4", CS42L43_ASRC_DEC_ENABLES,
1748 CS42L43_ASRC_DEC4_EN_SHIFT, 0, NULL, 0),
1749
1750 SND_SOC_DAPM_SUPPLY("EQ Clock", CS42L43_BLOCK_EN7, CS42L43_EQ_EN_SHIFT,
1751 0, NULL, 0),
1752 SND_SOC_DAPM_PGA_E("EQ", CS42L43_START_EQZ0, CS42L43_START_FILTER_SHIFT,
1753 0, NULL, 0, cs42l43_eq_ev,
1754 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1755
1756 SND_SOC_DAPM_SUPPLY("Mixer Core", CS42L43_BLOCK_EN6, CS42L43_MIXER_EN_SHIFT,
1757 0, NULL, 0),
1758 CS42L43_DAPM_MUX("ASPTX1", asptx1),
1759 CS42L43_DAPM_MUX("ASPTX2", asptx2),
1760 CS42L43_DAPM_MUX("ASPTX3", asptx3),
1761 CS42L43_DAPM_MUX("ASPTX4", asptx4),
1762 CS42L43_DAPM_MUX("ASPTX5", asptx5),
1763 CS42L43_DAPM_MUX("ASPTX6", asptx6),
1764
1765 CS42L43_DAPM_MUX("DP1TX1", dp1tx1),
1766 CS42L43_DAPM_MUX("DP1TX2", dp1tx2),
1767 CS42L43_DAPM_MUX("DP1TX3", dp1tx3),
1768 CS42L43_DAPM_MUX("DP1TX4", dp1tx4),
1769 CS42L43_DAPM_MUX("DP2TX1", dp2tx1),
1770 CS42L43_DAPM_MUX("DP2TX2", dp2tx2),
1771 CS42L43_DAPM_MUX("DP3TX1", dp3tx1),
1772 CS42L43_DAPM_MUX("DP3TX2", dp3tx2),
1773 CS42L43_DAPM_MUX("DP4TX1", dp4tx1),
1774 CS42L43_DAPM_MUX("DP4TX2", dp4tx2),
1775
1776 CS42L43_DAPM_MUX("ASRC INT1", asrcint1),
1777 CS42L43_DAPM_MUX("ASRC INT2", asrcint2),
1778 CS42L43_DAPM_MUX("ASRC INT3", asrcint3),
1779 CS42L43_DAPM_MUX("ASRC INT4", asrcint4),
1780 CS42L43_DAPM_MUX("ASRC DEC1", asrcdec1),
1781 CS42L43_DAPM_MUX("ASRC DEC2", asrcdec2),
1782 CS42L43_DAPM_MUX("ASRC DEC3", asrcdec3),
1783 CS42L43_DAPM_MUX("ASRC DEC4", asrcdec4),
1784
1785 CS42L43_DAPM_MUX("ISRC1INT1", isrc1int1),
1786 CS42L43_DAPM_MUX("ISRC1INT2", isrc1int2),
1787 CS42L43_DAPM_MUX("ISRC1DEC1", isrc1dec1),
1788 CS42L43_DAPM_MUX("ISRC1DEC2", isrc1dec2),
1789 CS42L43_DAPM_MUX("ISRC2INT1", isrc2int1),
1790 CS42L43_DAPM_MUX("ISRC2INT2", isrc2int2),
1791 CS42L43_DAPM_MUX("ISRC2DEC1", isrc2dec1),
1792 CS42L43_DAPM_MUX("ISRC2DEC2", isrc2dec2),
1793
1794 CS42L43_DAPM_MUX("SPDIF1", spdif1),
1795 CS42L43_DAPM_MUX("SPDIF2", spdif2),
1796
1797 CS42L43_DAPM_MIXER("EQ1", eq1),
1798 CS42L43_DAPM_MIXER("EQ2", eq2),
1799
1800 CS42L43_DAPM_MIXER("Speaker L", amp1),
1801 CS42L43_DAPM_MIXER("Speaker R", amp2),
1802
1803 CS42L43_DAPM_MIXER("Headphone L", amp3),
1804 CS42L43_DAPM_MIXER("Headphone R", amp4),
1805 };
1806
1807 static const struct snd_soc_dapm_route cs42l43_routes[] = {
1808 { "ADC1_IN1_P", NULL, "PLL" },
1809 { "ADC1_IN1_N", NULL, "PLL" },
1810 { "ADC1_IN2_P", NULL, "PLL" },
1811 { "ADC1_IN2_N", NULL, "PLL" },
1812 { "ADC2_IN_P", NULL, "PLL" },
1813 { "ADC2_IN_N", NULL, "PLL" },
1814 { "PDM1_DIN", NULL, "PLL" },
1815 { "PDM2_DIN", NULL, "PLL" },
1816 { "AMP1_OUT_P", NULL, "PLL" },
1817 { "AMP1_OUT_N", NULL, "PLL" },
1818 { "AMP2_OUT_P", NULL, "PLL" },
1819 { "AMP2_OUT_N", NULL, "PLL" },
1820 { "SPDIF_TX", NULL, "PLL" },
1821 { "HP", NULL, "PLL" },
1822 { "AMP3_OUT", NULL, "PLL" },
1823 { "AMP4_OUT", NULL, "PLL" },
1824 { "Tone 1", NULL, "PLL" },
1825 { "Tone 2", NULL, "PLL" },
1826 { "ASP Playback", NULL, "PLL" },
1827 { "ASP Capture", NULL, "PLL" },
1828 { "DP1 Capture", NULL, "PLL" },
1829 { "DP2 Capture", NULL, "PLL" },
1830 { "DP3 Capture", NULL, "PLL" },
1831 { "DP4 Capture", NULL, "PLL" },
1832 { "DP5 Playback", NULL, "PLL" },
1833 { "DP6 Playback", NULL, "PLL" },
1834 { "DP7 Playback", NULL, "PLL" },
1835
1836 { "ADC1 Input", "IN1", "ADC1_IN1_P" },
1837 { "ADC1 Input", "IN1", "ADC1_IN1_N" },
1838 { "ADC1 Input", "IN2", "ADC1_IN2_P" },
1839 { "ADC1 Input", "IN2", "ADC1_IN2_N" },
1840
1841 { "ADC1", NULL, "ADC1 Input" },
1842 { "ADC2", NULL, "ADC2_IN_P" },
1843 { "ADC2", NULL, "ADC2_IN_N" },
1844
1845 { "PDM1L", NULL, "PDM1_DIN" },
1846 { "PDM1R", NULL, "PDM1_DIN" },
1847 { "PDM2L", NULL, "PDM2_DIN" },
1848 { "PDM2R", NULL, "PDM2_DIN" },
1849
1850 { "Decimator 1 Mode", "PDM", "PDM1L" },
1851 { "Decimator 1 Mode", "ADC", "ADC1" },
1852 { "Decimator 2 Mode", "PDM", "PDM1R" },
1853 { "Decimator 2 Mode", "ADC", "ADC2" },
1854
1855 { "Decimator 1", NULL, "Decimator 1 Mode" },
1856 { "Decimator 2", NULL, "Decimator 2 Mode" },
1857 { "Decimator 3", NULL, "PDM2L" },
1858 { "Decimator 4", NULL, "PDM2R" },
1859
1860 { "ASP Capture", NULL, "ASPTX1" },
1861 { "ASP Capture", NULL, "ASPTX2" },
1862 { "ASP Capture", NULL, "ASPTX3" },
1863 { "ASP Capture", NULL, "ASPTX4" },
1864 { "ASP Capture", NULL, "ASPTX5" },
1865 { "ASP Capture", NULL, "ASPTX6" },
1866 { "ASPTX1", NULL, "BCLK" },
1867 { "ASPTX2", NULL, "BCLK" },
1868 { "ASPTX3", NULL, "BCLK" },
1869 { "ASPTX4", NULL, "BCLK" },
1870 { "ASPTX5", NULL, "BCLK" },
1871 { "ASPTX6", NULL, "BCLK" },
1872
1873 { "ASPRX1", NULL, "ASP Playback" },
1874 { "ASPRX2", NULL, "ASP Playback" },
1875 { "ASPRX3", NULL, "ASP Playback" },
1876 { "ASPRX4", NULL, "ASP Playback" },
1877 { "ASPRX5", NULL, "ASP Playback" },
1878 { "ASPRX6", NULL, "ASP Playback" },
1879 { "ASPRX1", NULL, "BCLK" },
1880 { "ASPRX2", NULL, "BCLK" },
1881 { "ASPRX3", NULL, "BCLK" },
1882 { "ASPRX4", NULL, "BCLK" },
1883 { "ASPRX5", NULL, "BCLK" },
1884 { "ASPRX6", NULL, "BCLK" },
1885
1886 { "DP1 Capture", NULL, "DP1TX1" },
1887 { "DP1 Capture", NULL, "DP1TX2" },
1888 { "DP1 Capture", NULL, "DP1TX3" },
1889 { "DP1 Capture", NULL, "DP1TX4" },
1890
1891 { "DP2 Capture", NULL, "DP2TX1" },
1892 { "DP2 Capture", NULL, "DP2TX2" },
1893
1894 { "DP3 Capture", NULL, "DP3TX1" },
1895 { "DP3 Capture", NULL, "DP3TX2" },
1896
1897 { "DP4 Capture", NULL, "DP4TX1" },
1898 { "DP4 Capture", NULL, "DP4TX2" },
1899
1900 { "DP5RX1", NULL, "DP5 Playback" },
1901 { "DP5RX2", NULL, "DP5 Playback" },
1902
1903 { "DP6RX1", NULL, "DP6 Playback" },
1904 { "DP6RX2", NULL, "DP6 Playback" },
1905
1906 { "DP7RX1", NULL, "DP7 Playback" },
1907 { "DP7RX2", NULL, "DP7 Playback" },
1908
1909 { "AMP1", NULL, "vdd-amp" },
1910 { "AMP2", NULL, "vdd-amp" },
1911
1912 { "AMP1_OUT_P", NULL, "AMP1" },
1913 { "AMP1_OUT_N", NULL, "AMP1" },
1914 { "AMP2_OUT_P", NULL, "AMP2" },
1915 { "AMP2_OUT_N", NULL, "AMP2" },
1916
1917 { "SPDIF_TX", NULL, "SPDIF" },
1918
1919 { "AMP3_OUT", NULL, "HP" },
1920 { "AMP4_OUT", NULL, "HP" },
1921
1922 { "Tone 1", NULL, "Tone" },
1923 { "Tone 1", NULL, "Tone Generator" },
1924 { "Tone 2", NULL, "Tone" },
1925 { "Tone 2", NULL, "Tone Generator" },
1926
1927 { "ISRC1INT2", NULL, "ISRC1" },
1928 { "ISRC1INT1", NULL, "ISRC1" },
1929 { "ISRC1DEC2", NULL, "ISRC1" },
1930 { "ISRC1DEC1", NULL, "ISRC1" },
1931
1932 { "ISRC2INT2", NULL, "ISRC2" },
1933 { "ISRC2INT1", NULL, "ISRC2" },
1934 { "ISRC2DEC2", NULL, "ISRC2" },
1935 { "ISRC2DEC1", NULL, "ISRC2" },
1936
1937 { "ASRC_INT1", NULL, "ASRC_INT" },
1938 { "ASRC_INT2", NULL, "ASRC_INT" },
1939 { "ASRC_INT3", NULL, "ASRC_INT" },
1940 { "ASRC_INT4", NULL, "ASRC_INT" },
1941 { "ASRC_DEC1", NULL, "ASRC_DEC" },
1942 { "ASRC_DEC2", NULL, "ASRC_DEC" },
1943 { "ASRC_DEC3", NULL, "ASRC_DEC" },
1944 { "ASRC_DEC4", NULL, "ASRC_DEC" },
1945
1946 { "EQ", NULL, "EQ Clock" },
1947
1948 CS42L43_MUX_ROUTES("ASPTX1", "ASPTX1"),
1949 CS42L43_MUX_ROUTES("ASPTX2", "ASPTX2"),
1950 CS42L43_MUX_ROUTES("ASPTX3", "ASPTX3"),
1951 CS42L43_MUX_ROUTES("ASPTX4", "ASPTX4"),
1952 CS42L43_MUX_ROUTES("ASPTX5", "ASPTX5"),
1953 CS42L43_MUX_ROUTES("ASPTX6", "ASPTX6"),
1954
1955 CS42L43_MUX_ROUTES("DP1TX1", "DP1TX1"),
1956 CS42L43_MUX_ROUTES("DP1TX2", "DP1TX2"),
1957 CS42L43_MUX_ROUTES("DP1TX3", "DP1TX3"),
1958 CS42L43_MUX_ROUTES("DP1TX4", "DP1TX4"),
1959 CS42L43_MUX_ROUTES("DP2TX1", "DP2TX1"),
1960 CS42L43_MUX_ROUTES("DP2TX2", "DP2TX2"),
1961 CS42L43_MUX_ROUTES("DP3TX1", "DP3TX1"),
1962 CS42L43_MUX_ROUTES("DP3TX2", "DP3TX2"),
1963 CS42L43_MUX_ROUTES("DP4TX1", "DP4TX1"),
1964 CS42L43_MUX_ROUTES("DP4TX2", "DP4TX2"),
1965
1966 CS42L43_MUX_ROUTES("ASRC INT1", "ASRC_INT1"),
1967 CS42L43_MUX_ROUTES("ASRC INT2", "ASRC_INT2"),
1968 CS42L43_MUX_ROUTES("ASRC INT3", "ASRC_INT3"),
1969 CS42L43_MUX_ROUTES("ASRC INT4", "ASRC_INT4"),
1970 CS42L43_MUX_ROUTES("ASRC DEC1", "ASRC_DEC1"),
1971 CS42L43_MUX_ROUTES("ASRC DEC2", "ASRC_DEC2"),
1972 CS42L43_MUX_ROUTES("ASRC DEC3", "ASRC_DEC3"),
1973 CS42L43_MUX_ROUTES("ASRC DEC4", "ASRC_DEC4"),
1974
1975 CS42L43_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
1976 CS42L43_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
1977 CS42L43_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
1978 CS42L43_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
1979 CS42L43_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
1980 CS42L43_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
1981 CS42L43_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
1982 CS42L43_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
1983
1984 CS42L43_MUX_ROUTES("SPDIF1", "SPDIF"),
1985 CS42L43_MUX_ROUTES("SPDIF2", "SPDIF"),
1986
1987 CS42L43_MIXER_ROUTES("EQ1", "EQ"),
1988 CS42L43_MIXER_ROUTES("EQ2", "EQ"),
1989
1990 CS42L43_MIXER_ROUTES("Speaker L", "AMP1"),
1991 CS42L43_MIXER_ROUTES("Speaker R", "AMP2"),
1992
1993 CS42L43_MIXER_ROUTES("Headphone L", "HP"),
1994 CS42L43_MIXER_ROUTES("Headphone R", "HP"),
1995 };
1996
cs42l43_set_sysclk(struct snd_soc_component * component,int clk_id,int src,unsigned int freq,int dir)1997 static int cs42l43_set_sysclk(struct snd_soc_component *component, int clk_id,
1998 int src, unsigned int freq, int dir)
1999 {
2000 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
2001 struct cs42l43 *cs42l43 = priv->core;
2002 int ret;
2003
2004 mutex_lock(&cs42l43->pll_lock);
2005 ret = cs42l43_set_pll(priv, src, freq);
2006 mutex_unlock(&cs42l43->pll_lock);
2007
2008 return ret;
2009 }
2010
cs42l43_component_probe(struct snd_soc_component * component)2011 static int cs42l43_component_probe(struct snd_soc_component *component)
2012 {
2013 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component);
2014 struct cs42l43 *cs42l43 = priv->core;
2015
2016 snd_soc_component_init_regmap(component, cs42l43->regmap);
2017
2018 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->tx_slots);
2019 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->rx_slots);
2020
2021 priv->component = component;
2022 priv->constraint = cs42l43_constraint;
2023
2024 return 0;
2025 }
2026
2027 static const struct snd_soc_component_driver cs42l43_component_drv = {
2028 .name = "cs42l43-codec",
2029
2030 .probe = cs42l43_component_probe,
2031 .set_sysclk = cs42l43_set_sysclk,
2032 .set_jack = cs42l43_set_jack,
2033
2034 .endianness = 1,
2035
2036 .controls = cs42l43_controls,
2037 .num_controls = ARRAY_SIZE(cs42l43_controls),
2038 .dapm_widgets = cs42l43_widgets,
2039 .num_dapm_widgets = ARRAY_SIZE(cs42l43_widgets),
2040 .dapm_routes = cs42l43_routes,
2041 .num_dapm_routes = ARRAY_SIZE(cs42l43_routes),
2042 };
2043
2044 struct cs42l43_irq {
2045 unsigned int irq;
2046 const char *name;
2047 irq_handler_t handler;
2048 };
2049
2050 static const struct cs42l43_irq cs42l43_irqs[] = {
2051 { CS42L43_PLL_LOST_LOCK, "pll lost lock", cs42l43_pll_lost_lock },
2052 { CS42L43_PLL_READY, "pll ready", cs42l43_pll_ready },
2053 { CS42L43_HP_STARTUP_DONE, "hp startup", cs42l43_hp_startup },
2054 { CS42L43_HP_SHUTDOWN_DONE, "hp shutdown", cs42l43_hp_shutdown },
2055 { CS42L43_HSDET_DONE, "type detect", cs42l43_type_detect },
2056 { CS42L43_TIPSENSE_UNPLUG_PDET, "tip sense unplug", cs42l43_tip_sense },
2057 { CS42L43_TIPSENSE_PLUG_PDET, "tip sense plug", cs42l43_tip_sense },
2058 { CS42L43_DC_DETECT1_TRUE, "button press", cs42l43_button_press },
2059 { CS42L43_DC_DETECT1_FALSE, "button release", cs42l43_button_release },
2060 { CS42L43_HSBIAS_CLAMPED, "hsbias detect clamp", cs42l43_bias_detect_clamp },
2061 { CS42L43_AMP2_CLK_STOP_FAULT, "spkr clock stop", cs42l43_spkr_clock_stop },
2062 { CS42L43_AMP1_CLK_STOP_FAULT, "spkl clock stop", cs42l43_spkl_clock_stop },
2063 { CS42L43_AMP2_VDDSPK_FAULT, "spkr brown out", cs42l43_spkr_brown_out },
2064 { CS42L43_AMP1_VDDSPK_FAULT, "spkl brown out", cs42l43_spkl_brown_out },
2065 { CS42L43_AMP2_SHUTDOWN_DONE, "spkr shutdown", cs42l43_spkr_shutdown },
2066 { CS42L43_AMP1_SHUTDOWN_DONE, "spkl shutdown", cs42l43_spkl_shutdown },
2067 { CS42L43_AMP2_STARTUP_DONE, "spkr startup", cs42l43_spkr_startup },
2068 { CS42L43_AMP1_STARTUP_DONE, "spkl startup", cs42l43_spkl_startup },
2069 { CS42L43_AMP2_THERM_SHDN, "spkr thermal shutdown", cs42l43_spkr_therm_shutdown },
2070 { CS42L43_AMP1_THERM_SHDN, "spkl thermal shutdown", cs42l43_spkl_therm_shutdown },
2071 { CS42L43_AMP2_THERM_WARN, "spkr thermal warning", cs42l43_spkr_therm_warm },
2072 { CS42L43_AMP1_THERM_WARN, "spkl thermal warning", cs42l43_spkl_therm_warm },
2073 { CS42L43_AMP2_SCDET, "spkr short circuit", cs42l43_spkr_sc_detect },
2074 { CS42L43_AMP1_SCDET, "spkl short circuit", cs42l43_spkl_sc_detect },
2075 { CS42L43_HP_ILIMIT, "hp ilimit", cs42l43_hp_ilimit },
2076 { CS42L43_HP_LOADDET_DONE, "load detect done", cs42l43_load_detect },
2077 };
2078
cs42l43_request_irq(struct cs42l43_codec * priv,struct irq_domain * dom,const char * const name,unsigned int irq,irq_handler_t handler,unsigned long flags)2079 static int cs42l43_request_irq(struct cs42l43_codec *priv,
2080 struct irq_domain *dom, const char * const name,
2081 unsigned int irq, irq_handler_t handler,
2082 unsigned long flags)
2083 {
2084 int ret;
2085
2086 ret = irq_create_mapping(dom, irq);
2087 if (ret < 0)
2088 return dev_err_probe(priv->dev, ret, "Failed to map IRQ %s\n", name);
2089
2090 dev_dbg(priv->dev, "Request IRQ %d for %s\n", ret, name);
2091
2092 ret = devm_request_threaded_irq(priv->dev, ret, NULL, handler,
2093 IRQF_ONESHOT | flags, name, priv);
2094 if (ret)
2095 return dev_err_probe(priv->dev, ret, "Failed to request IRQ %s\n", name);
2096
2097 return 0;
2098 }
2099
cs42l43_shutter_irq(struct cs42l43_codec * priv,struct irq_domain * dom,unsigned int shutter,const char * const open_name,const char * const close_name,irq_handler_t handler)2100 static int cs42l43_shutter_irq(struct cs42l43_codec *priv,
2101 struct irq_domain *dom, unsigned int shutter,
2102 const char * const open_name,
2103 const char * const close_name,
2104 irq_handler_t handler)
2105 {
2106 unsigned int open_irq, close_irq;
2107 int ret;
2108
2109 switch (shutter) {
2110 case 0x1:
2111 dev_warn(priv->dev, "Manual shutters, notifications not available\n");
2112 return 0;
2113 case 0x2:
2114 open_irq = CS42L43_GPIO1_RISE;
2115 close_irq = CS42L43_GPIO1_FALL;
2116 break;
2117 case 0x4:
2118 open_irq = CS42L43_GPIO2_RISE;
2119 close_irq = CS42L43_GPIO2_FALL;
2120 break;
2121 case 0x8:
2122 open_irq = CS42L43_GPIO3_RISE;
2123 close_irq = CS42L43_GPIO3_FALL;
2124 break;
2125 default:
2126 return 0;
2127 }
2128
2129 ret = cs42l43_request_irq(priv, dom, close_name, close_irq, handler, IRQF_SHARED);
2130 if (ret)
2131 return ret;
2132
2133 return cs42l43_request_irq(priv, dom, open_name, open_irq, handler, IRQF_SHARED);
2134 }
2135
cs42l43_codec_probe(struct platform_device * pdev)2136 static int cs42l43_codec_probe(struct platform_device *pdev)
2137 {
2138 struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);
2139 struct cs42l43_codec *priv;
2140 struct irq_domain *dom;
2141 unsigned int val;
2142 int i, ret;
2143
2144 dom = irq_find_matching_fwnode(dev_fwnode(cs42l43->dev), DOMAIN_BUS_ANY);
2145 if (!dom)
2146 return -EPROBE_DEFER;
2147
2148 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
2149 if (!priv)
2150 return -ENOMEM;
2151
2152 priv->dev = &pdev->dev;
2153 priv->core = cs42l43;
2154
2155 platform_set_drvdata(pdev, priv);
2156
2157 mutex_init(&priv->jack_lock);
2158 mutex_init(&priv->spk_vu_lock);
2159
2160 init_completion(&priv->hp_startup);
2161 init_completion(&priv->hp_shutdown);
2162 init_completion(&priv->spkr_shutdown);
2163 init_completion(&priv->spkl_shutdown);
2164 init_completion(&priv->spkr_startup);
2165 init_completion(&priv->spkl_startup);
2166 init_completion(&priv->pll_ready);
2167 init_completion(&priv->type_detect);
2168 init_completion(&priv->load_detect);
2169
2170 INIT_DELAYED_WORK(&priv->tip_sense_work, cs42l43_tip_sense_work);
2171 INIT_DELAYED_WORK(&priv->bias_sense_timeout, cs42l43_bias_sense_timeout);
2172 INIT_DELAYED_WORK(&priv->button_press_work, cs42l43_button_press_work);
2173 INIT_WORK(&priv->button_release_work, cs42l43_button_release_work);
2174
2175 pm_runtime_set_autosuspend_delay(priv->dev, 100);
2176 pm_runtime_use_autosuspend(priv->dev);
2177 pm_runtime_set_active(priv->dev);
2178 pm_runtime_get_noresume(priv->dev);
2179
2180 ret = devm_pm_runtime_enable(priv->dev);
2181 if (ret)
2182 goto err_pm;
2183
2184 for (i = 0; i < ARRAY_SIZE(cs42l43_irqs); i++) {
2185 ret = cs42l43_request_irq(priv, dom, cs42l43_irqs[i].name,
2186 cs42l43_irqs[i].irq,
2187 cs42l43_irqs[i].handler, 0);
2188 if (ret)
2189 goto err_pm;
2190 }
2191
2192 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val);
2193 if (ret) {
2194 dev_err(priv->dev, "Failed to check shutter source: %d\n", ret);
2195 goto err_pm;
2196 }
2197
2198 ret = cs42l43_shutter_irq(priv, dom, val & CS42L43_MIC_SHUTTER_CFG_MASK,
2199 "mic shutter open", "mic shutter close",
2200 cs42l43_mic_shutter);
2201 if (ret)
2202 goto err_pm;
2203
2204 ret = cs42l43_shutter_irq(priv, dom, (val & CS42L43_SPK_SHUTTER_CFG_MASK) >>
2205 CS42L43_SPK_SHUTTER_CFG_SHIFT,
2206 "spk shutter open", "spk shutter close",
2207 cs42l43_spk_shutter);
2208 if (ret)
2209 goto err_pm;
2210
2211 // Don't use devm as we need to get against the MFD device
2212 priv->mclk = clk_get_optional(cs42l43->dev, "mclk");
2213 if (IS_ERR(priv->mclk)) {
2214 ret = PTR_ERR(priv->mclk);
2215 dev_err_probe(priv->dev, ret, "Failed to get mclk\n");
2216 goto err_pm;
2217 }
2218
2219 ret = devm_snd_soc_register_component(priv->dev, &cs42l43_component_drv,
2220 cs42l43_dais, ARRAY_SIZE(cs42l43_dais));
2221 if (ret) {
2222 dev_err_probe(priv->dev, ret, "Failed to register component\n");
2223 goto err_clk;
2224 }
2225
2226 pm_runtime_mark_last_busy(priv->dev);
2227 pm_runtime_put_autosuspend(priv->dev);
2228
2229 return 0;
2230
2231 err_clk:
2232 clk_put(priv->mclk);
2233 err_pm:
2234 pm_runtime_put_sync(priv->dev);
2235
2236 return ret;
2237 }
2238
cs42l43_codec_remove(struct platform_device * pdev)2239 static int cs42l43_codec_remove(struct platform_device *pdev)
2240 {
2241 struct cs42l43_codec *priv = platform_get_drvdata(pdev);
2242
2243 clk_put(priv->mclk);
2244
2245 return 0;
2246 }
2247
cs42l43_codec_runtime_resume(struct device * dev)2248 static int cs42l43_codec_runtime_resume(struct device *dev)
2249 {
2250 struct cs42l43_codec *priv = dev_get_drvdata(dev);
2251
2252 dev_dbg(priv->dev, "Runtime resume\n");
2253
2254 // Toggle the speaker volume update incase the speaker volume was synced
2255 cs42l43_spk_vu_sync(priv);
2256
2257 return 0;
2258 }
2259
2260 DEFINE_RUNTIME_DEV_PM_OPS(cs42l43_codec_pm_ops, NULL,
2261 cs42l43_codec_runtime_resume, NULL);
2262
2263 static const struct platform_device_id cs42l43_codec_id_table[] = {
2264 { "cs42l43-codec", },
2265 {}
2266 };
2267 MODULE_DEVICE_TABLE(platform, cs42l43_codec_id_table);
2268
2269 static struct platform_driver cs42l43_codec_driver = {
2270 .driver = {
2271 .name = "cs42l43-codec",
2272 .pm = &cs42l43_codec_pm_ops,
2273 },
2274
2275 .probe = cs42l43_codec_probe,
2276 .remove = cs42l43_codec_remove,
2277 .id_table = cs42l43_codec_id_table,
2278 };
2279 module_platform_driver(cs42l43_codec_driver);
2280
2281 MODULE_IMPORT_NS(SND_SOC_CS42L43);
2282
2283 MODULE_DESCRIPTION("CS42L43 CODEC Driver");
2284 MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
2285 MODULE_LICENSE("GPL");
2286