1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4  * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
5  */
6 
7 #ifndef _DPU_HW_UTIL_H
8 #define _DPU_HW_UTIL_H
9 
10 #include <linux/io.h>
11 #include <linux/slab.h>
12 #include "dpu_hw_mdss.h"
13 #include "dpu_hw_catalog.h"
14 
15 #define REG_MASK(n)                     ((BIT(n)) - 1)
16 #define MISR_FRAME_COUNT                0x1
17 #define MISR_CTRL_ENABLE                BIT(8)
18 #define MISR_CTRL_STATUS                BIT(9)
19 #define MISR_CTRL_STATUS_CLEAR          BIT(10)
20 #define MISR_CTRL_FREE_RUN_MASK         BIT(31)
21 
22 /*
23  * This is the common struct maintained by each sub block
24  * for mapping the register offsets in this block to the
25  * absoulute IO address
26  * @blk_addr:     hw block register mapped address
27  * @log_mask:     log mask for this block
28  */
29 struct dpu_hw_blk_reg_map {
30 	void __iomem *blk_addr;
31 	u32 log_mask;
32 };
33 
34 /**
35  * struct dpu_hw_blk - opaque hardware block object
36  */
37 struct dpu_hw_blk {
38 	/* opaque */
39 };
40 
41 /**
42  * struct dpu_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration
43  * @enable:         detail enhancer enable/disable
44  * @sharpen_level1: sharpening strength for noise
45  * @sharpen_level2: sharpening strength for signal
46  * @ clip:          clip shift
47  * @ limit:         limit value
48  * @ thr_quiet:     quiet threshold
49  * @ thr_dieout:    dieout threshold
50  * @ thr_high:      low threshold
51  * @ thr_high:      high threshold
52  * @ prec_shift:    precision shift
53  * @ adjust_a:      A-coefficients for mapping curve
54  * @ adjust_b:      B-coefficients for mapping curve
55  * @ adjust_c:      C-coefficients for mapping curve
56  */
57 struct dpu_hw_scaler3_de_cfg {
58 	u32 enable;
59 	int16_t sharpen_level1;
60 	int16_t sharpen_level2;
61 	uint16_t clip;
62 	uint16_t limit;
63 	uint16_t thr_quiet;
64 	uint16_t thr_dieout;
65 	uint16_t thr_low;
66 	uint16_t thr_high;
67 	uint16_t prec_shift;
68 	int16_t adjust_a[DPU_MAX_DE_CURVES];
69 	int16_t adjust_b[DPU_MAX_DE_CURVES];
70 	int16_t adjust_c[DPU_MAX_DE_CURVES];
71 };
72 
73 
74 /**
75  * struct dpu_hw_scaler3_cfg : QSEEDv3 configuration
76  * @enable:        scaler enable
77  * @dir_en:        direction detection block enable
78  * @ init_phase_x: horizontal initial phase
79  * @ phase_step_x: horizontal phase step
80  * @ init_phase_y: vertical initial phase
81  * @ phase_step_y: vertical phase step
82  * @ preload_x:    horizontal preload value
83  * @ preload_y:    vertical preload value
84  * @ src_width:    source width
85  * @ src_height:   source height
86  * @ dst_width:    destination width
87  * @ dst_height:   destination height
88  * @ y_rgb_filter_cfg: y/rgb plane filter configuration
89  * @ uv_filter_cfg: uv plane filter configuration
90  * @ alpha_filter_cfg: alpha filter configuration
91  * @ blend_cfg:    blend coefficients configuration
92  * @ lut_flag:     scaler LUT update flags
93  *                 0x1 swap LUT bank
94  *                 0x2 update 2D filter LUT
95  *                 0x4 update y circular filter LUT
96  *                 0x8 update uv circular filter LUT
97  *                 0x10 update y separable filter LUT
98  *                 0x20 update uv separable filter LUT
99  * @ dir_lut_idx:  2D filter LUT index
100  * @ y_rgb_cir_lut_idx: y circular filter LUT index
101  * @ uv_cir_lut_idx: uv circular filter LUT index
102  * @ y_rgb_sep_lut_idx: y circular filter LUT index
103  * @ uv_sep_lut_idx: uv separable filter LUT index
104  * @ dir_lut:      pointer to 2D LUT
105  * @ cir_lut:      pointer to circular filter LUT
106  * @ sep_lut:      pointer to separable filter LUT
107  * @ de: detail enhancer configuration
108  * @ dir_weight:   Directional weight
109  */
110 struct dpu_hw_scaler3_cfg {
111 	u32 enable;
112 	u32 dir_en;
113 	int32_t init_phase_x[DPU_MAX_PLANES];
114 	int32_t phase_step_x[DPU_MAX_PLANES];
115 	int32_t init_phase_y[DPU_MAX_PLANES];
116 	int32_t phase_step_y[DPU_MAX_PLANES];
117 
118 	u32 preload_x[DPU_MAX_PLANES];
119 	u32 preload_y[DPU_MAX_PLANES];
120 	u32 src_width[DPU_MAX_PLANES];
121 	u32 src_height[DPU_MAX_PLANES];
122 
123 	u32 dst_width;
124 	u32 dst_height;
125 
126 	u32 y_rgb_filter_cfg;
127 	u32 uv_filter_cfg;
128 	u32 alpha_filter_cfg;
129 	u32 blend_cfg;
130 
131 	u32 lut_flag;
132 	u32 dir_lut_idx;
133 
134 	u32 y_rgb_cir_lut_idx;
135 	u32 uv_cir_lut_idx;
136 	u32 y_rgb_sep_lut_idx;
137 	u32 uv_sep_lut_idx;
138 	u32 *dir_lut;
139 	size_t dir_len;
140 	u32 *cir_lut;
141 	size_t cir_len;
142 	u32 *sep_lut;
143 	size_t sep_len;
144 
145 	/*
146 	 * Detail enhancer settings
147 	 */
148 	struct dpu_hw_scaler3_de_cfg de;
149 
150 	u32 dir_weight;
151 };
152 
153 /**
154  * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure
155  * @num_ext_pxls_lr: Number of total horizontal pixels
156  * @num_ext_pxls_tb: Number of total vertical lines
157  * @left_ftch:       Number of extra pixels to overfetch from left
158  * @right_ftch:      Number of extra pixels to overfetch from right
159  * @top_ftch:        Number of extra lines to overfetch from top
160  * @btm_ftch:        Number of extra lines to overfetch from bottom
161  * @left_rpt:        Number of extra pixels to repeat from left
162  * @right_rpt:       Number of extra pixels to repeat from right
163  * @top_rpt:         Number of extra lines to repeat from top
164  * @btm_rpt:         Number of extra lines to repeat from bottom
165  */
166 struct dpu_drm_pix_ext_v1 {
167 	/*
168 	 * Number of pixels ext in left, right, top and bottom direction
169 	 * for all color components.
170 	 */
171 	int32_t num_ext_pxls_lr[DPU_MAX_PLANES];
172 	int32_t num_ext_pxls_tb[DPU_MAX_PLANES];
173 
174 	/*
175 	 * Number of pixels needs to be overfetched in left, right, top
176 	 * and bottom directions from source image for scaling.
177 	 */
178 	int32_t left_ftch[DPU_MAX_PLANES];
179 	int32_t right_ftch[DPU_MAX_PLANES];
180 	int32_t top_ftch[DPU_MAX_PLANES];
181 	int32_t btm_ftch[DPU_MAX_PLANES];
182 	/*
183 	 * Number of pixels needs to be repeated in left, right, top and
184 	 * bottom directions for scaling.
185 	 */
186 	int32_t left_rpt[DPU_MAX_PLANES];
187 	int32_t right_rpt[DPU_MAX_PLANES];
188 	int32_t top_rpt[DPU_MAX_PLANES];
189 	int32_t btm_rpt[DPU_MAX_PLANES];
190 
191 };
192 
193 /**
194  * struct dpu_drm_de_v1 - version 1 of detail enhancer structure
195  * @enable:         Enables/disables detail enhancer
196  * @sharpen_level1: Sharpening strength for noise
197  * @sharpen_level2: Sharpening strength for context
198  * @clip:           Clip coefficient
199  * @limit:          Detail enhancer limit factor
200  * @thr_quiet:      Quite zone threshold
201  * @thr_dieout:     Die-out zone threshold
202  * @thr_low:        Linear zone left threshold
203  * @thr_high:       Linear zone right threshold
204  * @prec_shift:     Detail enhancer precision
205  * @adjust_a:       Mapping curves A coefficients
206  * @adjust_b:       Mapping curves B coefficients
207  * @adjust_c:       Mapping curves C coefficients
208  */
209 struct dpu_drm_de_v1 {
210 	uint32_t enable;
211 	int16_t sharpen_level1;
212 	int16_t sharpen_level2;
213 	uint16_t clip;
214 	uint16_t limit;
215 	uint16_t thr_quiet;
216 	uint16_t thr_dieout;
217 	uint16_t thr_low;
218 	uint16_t thr_high;
219 	uint16_t prec_shift;
220 	int16_t adjust_a[DPU_MAX_DE_CURVES];
221 	int16_t adjust_b[DPU_MAX_DE_CURVES];
222 	int16_t adjust_c[DPU_MAX_DE_CURVES];
223 };
224 
225 /**
226  * struct dpu_drm_scaler_v2 - version 2 of struct dpu_drm_scaler
227  * @enable:            Scaler enable
228  * @dir_en:            Detail enhancer enable
229  * @pe:                Pixel extension settings
230  * @horz_decimate:     Horizontal decimation factor
231  * @vert_decimate:     Vertical decimation factor
232  * @init_phase_x:      Initial scaler phase values for x
233  * @phase_step_x:      Phase step values for x
234  * @init_phase_y:      Initial scaler phase values for y
235  * @phase_step_y:      Phase step values for y
236  * @preload_x:         Horizontal preload value
237  * @preload_y:         Vertical preload value
238  * @src_width:         Source width
239  * @src_height:        Source height
240  * @dst_width:         Destination width
241  * @dst_height:        Destination height
242  * @y_rgb_filter_cfg:  Y/RGB plane filter configuration
243  * @uv_filter_cfg:     UV plane filter configuration
244  * @alpha_filter_cfg:  Alpha filter configuration
245  * @blend_cfg:         Selection of blend coefficients
246  * @lut_flag:          LUT configuration flags
247  * @dir_lut_idx:       2d 4x4 LUT index
248  * @y_rgb_cir_lut_idx: Y/RGB circular LUT index
249  * @uv_cir_lut_idx:    UV circular LUT index
250  * @y_rgb_sep_lut_idx: Y/RGB separable LUT index
251  * @uv_sep_lut_idx:    UV separable LUT index
252  * @de:                Detail enhancer settings
253  */
254 struct dpu_drm_scaler_v2 {
255 	/*
256 	 * General definitions
257 	 */
258 	uint32_t enable;
259 	uint32_t dir_en;
260 
261 	/*
262 	 * Pix ext settings
263 	 */
264 	struct dpu_drm_pix_ext_v1 pe;
265 
266 	/*
267 	 * Decimation settings
268 	 */
269 	uint32_t horz_decimate;
270 	uint32_t vert_decimate;
271 
272 	/*
273 	 * Phase settings
274 	 */
275 	int32_t init_phase_x[DPU_MAX_PLANES];
276 	int32_t phase_step_x[DPU_MAX_PLANES];
277 	int32_t init_phase_y[DPU_MAX_PLANES];
278 	int32_t phase_step_y[DPU_MAX_PLANES];
279 
280 	uint32_t preload_x[DPU_MAX_PLANES];
281 	uint32_t preload_y[DPU_MAX_PLANES];
282 	uint32_t src_width[DPU_MAX_PLANES];
283 	uint32_t src_height[DPU_MAX_PLANES];
284 
285 	uint32_t dst_width;
286 	uint32_t dst_height;
287 
288 	uint32_t y_rgb_filter_cfg;
289 	uint32_t uv_filter_cfg;
290 	uint32_t alpha_filter_cfg;
291 	uint32_t blend_cfg;
292 
293 	uint32_t lut_flag;
294 	uint32_t dir_lut_idx;
295 
296 	/* for Y(RGB) and UV planes*/
297 	uint32_t y_rgb_cir_lut_idx;
298 	uint32_t uv_cir_lut_idx;
299 	uint32_t y_rgb_sep_lut_idx;
300 	uint32_t uv_sep_lut_idx;
301 
302 	/*
303 	 * Detail enhancer settings
304 	 */
305 	struct dpu_drm_de_v1 de;
306 };
307 
308 /**
309  * struct dpu_hw_qos_cfg: pipe QoS configuration
310  * @danger_lut: LUT for generate danger level based on fill level
311  * @safe_lut: LUT for generate safe level based on fill level
312  * @creq_lut: LUT for generate creq level based on fill level
313  * @creq_vblank: creq value generated to vbif during vertical blanking
314  * @danger_vblank: danger value generated during vertical blanking
315  * @vblank_en: enable creq_vblank and danger_vblank during vblank
316  * @danger_safe_en: enable danger safe generation
317  */
318 struct dpu_hw_qos_cfg {
319 	u32 danger_lut;
320 	u32 safe_lut;
321 	u64 creq_lut;
322 	bool danger_safe_en;
323 };
324 
325 u32 *dpu_hw_util_get_log_mask_ptr(void);
326 
327 void dpu_reg_write(struct dpu_hw_blk_reg_map *c,
328 		u32 reg_off,
329 		u32 val,
330 		const char *name);
331 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off);
332 
333 #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off)
334 #define DPU_REG_READ(c, off) dpu_reg_read(c, off)
335 
336 void *dpu_hw_util_get_dir(void);
337 
338 void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
339 		struct dpu_hw_scaler3_cfg *scaler3_cfg,
340 		u32 scaler_offset, u32 scaler_version,
341 		const struct dpu_format *format);
342 
343 u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c,
344 		u32 scaler_offset);
345 
346 void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map  *c,
347 		u32 csc_reg_off,
348 		const struct dpu_csc_cfg *data, bool csc10);
349 
350 void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset,
351 		   const struct dpu_format *fmt, bool enable);
352 
353 u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
354 		u32 total_fl);
355 
356 void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
357 			   bool qos_8lvl,
358 			   const struct dpu_hw_qos_cfg *cfg);
359 
360 void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
361 		u32 misr_ctrl_offset, u8 input_sel);
362 
363 int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
364 		u32 misr_ctrl_offset,
365 		u32 misr_signature_offset,
366 		u32 *misr_value);
367 
368 #endif /* _DPU_HW_UTIL_H */
369