1 /*
2 * QEMU model of the Canon DIGIC SoC.
3 *
4 * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
5 *
6 * This model is based on reverse engineering efforts
7 * made by CHDK (http://chdk.wikia.com) and
8 * Magic Lantern (http://www.magiclantern.fm) projects
9 * contributors.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qemu/module.h"
26 #include "hw/arm/digic.h"
27 #include "hw/qdev-properties.h"
28 #include "sysemu/sysemu.h"
29
30 #define DIGIC4_TIMER_BASE(n) (0xc0210000 + (n) * 0x100)
31
32 #define DIGIC_UART_BASE 0xc0800000
33
digic_init(Object * obj)34 static void digic_init(Object *obj)
35 {
36 DigicState *s = DIGIC(obj);
37 int i;
38
39 object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm946"));
40
41 for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
42 g_autofree char *name = g_strdup_printf("timer[%d]", i);
43 object_initialize_child(obj, name, &s->timer[i], TYPE_DIGIC_TIMER);
44 }
45
46 object_initialize_child(obj, "uart", &s->uart, TYPE_DIGIC_UART);
47 }
48
digic_realize(DeviceState * dev,Error ** errp)49 static void digic_realize(DeviceState *dev, Error **errp)
50 {
51 DigicState *s = DIGIC(dev);
52 SysBusDevice *sbd;
53 int i;
54
55 if (!object_property_set_bool(OBJECT(&s->cpu), "reset-hivecs", true,
56 errp)) {
57 return;
58 }
59
60 if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
61 return;
62 }
63
64 for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
65 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) {
66 return;
67 }
68
69 sbd = SYS_BUS_DEVICE(&s->timer[i]);
70 sysbus_mmio_map(sbd, 0, DIGIC4_TIMER_BASE(i));
71 }
72
73 qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hd(0));
74 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
75 return;
76 }
77
78 sbd = SYS_BUS_DEVICE(&s->uart);
79 sysbus_mmio_map(sbd, 0, DIGIC_UART_BASE);
80 }
81
digic_class_init(ObjectClass * oc,void * data)82 static void digic_class_init(ObjectClass *oc, void *data)
83 {
84 DeviceClass *dc = DEVICE_CLASS(oc);
85
86 dc->realize = digic_realize;
87 /* Reason: Uses serial_hds in the realize function --> not usable twice */
88 dc->user_creatable = false;
89 }
90
91 static const TypeInfo digic_type_info = {
92 .name = TYPE_DIGIC,
93 .parent = TYPE_DEVICE,
94 .instance_size = sizeof(DigicState),
95 .instance_init = digic_init,
96 .class_init = digic_class_init,
97 };
98
digic_register_types(void)99 static void digic_register_types(void)
100 {
101 type_register_static(&digic_type_info);
102 }
103
104 type_init(digic_register_types)
105