1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include "kfd_device_queue_manager.h"
26 #include "gca/gfx_8_0_enum.h"
27 #include "gca/gfx_8_0_sh_mask.h"
28 #include "oss/oss_3_0_sh_mask.h"
29
30 /*
31 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
32 * stay in user mode.
33 */
34 #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
35 /* APE1 limit is inclusive and 64K aligned. */
36 #define APE1_LIMIT_ALIGNMENT 0xFFFF
37
38 static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,
39 struct qcm_process_device *qpd,
40 enum cache_policy default_policy,
41 enum cache_policy alternate_policy,
42 void __user *alternate_aperture_base,
43 uint64_t alternate_aperture_size);
44 static int update_qpd_vi(struct device_queue_manager *dqm,
45 struct qcm_process_device *qpd);
46 static void init_sdma_vm(struct device_queue_manager *dqm,
47 struct queue *q,
48 struct qcm_process_device *qpd);
49
device_queue_manager_init_vi(struct device_queue_manager_asic_ops * asic_ops)50 void device_queue_manager_init_vi(
51 struct device_queue_manager_asic_ops *asic_ops)
52 {
53 asic_ops->set_cache_memory_policy = set_cache_memory_policy_vi;
54 asic_ops->update_qpd = update_qpd_vi;
55 asic_ops->init_sdma_vm = init_sdma_vm;
56 asic_ops->mqd_manager_init = mqd_manager_init_vi;
57 }
58
compute_sh_mem_bases_64bit(unsigned int top_address_nybble)59 static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble)
60 {
61 /* In 64-bit mode, we can only control the top 3 bits of the LDS,
62 * scratch and GPUVM apertures.
63 * The hardware fills in the remaining 59 bits according to the
64 * following pattern:
65 * LDS: X0000000'00000000 - X0000001'00000000 (4GB)
66 * Scratch: X0000001'00000000 - X0000002'00000000 (4GB)
67 * GPUVM: Y0010000'00000000 - Y0020000'00000000 (1TB)
68 *
69 * (where X/Y is the configurable nybble with the low-bit 0)
70 *
71 * LDS and scratch will have the same top nybble programmed in the
72 * top 3 bits of SH_MEM_BASES.PRIVATE_BASE.
73 * GPUVM can have a different top nybble programmed in the
74 * top 3 bits of SH_MEM_BASES.SHARED_BASE.
75 * We don't bother to support different top nybbles
76 * for LDS/Scratch and GPUVM.
77 */
78
79 WARN_ON((top_address_nybble & 1) || top_address_nybble > 0xE ||
80 top_address_nybble == 0);
81
82 return top_address_nybble << 12 |
83 (top_address_nybble << 12) <<
84 SH_MEM_BASES__SHARED_BASE__SHIFT;
85 }
86
set_cache_memory_policy_vi(struct device_queue_manager * dqm,struct qcm_process_device * qpd,enum cache_policy default_policy,enum cache_policy alternate_policy,void __user * alternate_aperture_base,uint64_t alternate_aperture_size)87 static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm,
88 struct qcm_process_device *qpd,
89 enum cache_policy default_policy,
90 enum cache_policy alternate_policy,
91 void __user *alternate_aperture_base,
92 uint64_t alternate_aperture_size)
93 {
94 uint32_t default_mtype;
95 uint32_t ape1_mtype;
96 unsigned int temp;
97 bool retval = true;
98
99 if (alternate_aperture_size == 0) {
100 /* base > limit disables APE1 */
101 qpd->sh_mem_ape1_base = 1;
102 qpd->sh_mem_ape1_limit = 0;
103 } else {
104 /*
105 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
106 * SH_MEM_APE1_BASE[31:0], 0x0000 }
107 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
108 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
109 * Verify that the base and size parameters can be
110 * represented in this format and convert them.
111 * Additionally restrict APE1 to user-mode addresses.
112 */
113
114 uint64_t base = (uintptr_t)alternate_aperture_base;
115 uint64_t limit = base + alternate_aperture_size - 1;
116
117 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 ||
118 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {
119 retval = false;
120 goto out;
121 }
122
123 qpd->sh_mem_ape1_base = base >> 16;
124 qpd->sh_mem_ape1_limit = limit >> 16;
125 }
126
127 default_mtype = (default_policy == cache_policy_coherent) ?
128 MTYPE_UC :
129 MTYPE_NC;
130
131 ape1_mtype = (alternate_policy == cache_policy_coherent) ?
132 MTYPE_UC :
133 MTYPE_NC;
134
135 qpd->sh_mem_config =
136 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
137 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
138 default_mtype << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
139 ape1_mtype << SH_MEM_CONFIG__APE1_MTYPE__SHIFT;
140
141 /* On dGPU we're always in GPUVM64 addressing mode with 64-bit
142 * aperture addresses.
143 */
144 temp = get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd));
145 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp);
146
147 pr_debug("sh_mem_bases nybble: 0x%X and register 0x%X\n",
148 temp, qpd->sh_mem_bases);
149 out:
150 return retval;
151 }
152
update_qpd_vi(struct device_queue_manager * dqm,struct qcm_process_device * qpd)153 static int update_qpd_vi(struct device_queue_manager *dqm,
154 struct qcm_process_device *qpd)
155 {
156 return 0;
157 }
158
init_sdma_vm(struct device_queue_manager * dqm,struct queue * q,struct qcm_process_device * qpd)159 static void init_sdma_vm(struct device_queue_manager *dqm,
160 struct queue *q,
161 struct qcm_process_device *qpd)
162 {
163 /* On dGPU we're always in GPUVM64 addressing mode with 64-bit
164 * aperture addresses.
165 */
166 q->properties.sdma_vm_addr =
167 ((get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd))) <<
168 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT) &
169 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK;
170 }
171