xref: /openbmc/u-boot/board/ti/ks2_evm/board_k2g.c (revision d94604d5)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * K2G EVM : Board initialization
4  *
5  * (C) Copyright 2015
6  *     Texas Instruments Incorporated, <www.ti.com>
7  */
8 #include <common.h>
9 #include <asm/arch/clock.h>
10 #include <asm/ti-common/keystone_net.h>
11 #include <asm/arch/psc_defs.h>
12 #include <asm/arch/mmc_host_def.h>
13 #include <fdtdec.h>
14 #include <i2c.h>
15 #include <remoteproc.h>
16 #include "mux-k2g.h"
17 #include "../common/board_detect.h"
18 
19 #define K2G_GP_AUDIO_CODEC_ADDRESS	0x1B
20 
21 const unsigned int sysclk_array[MAX_SYSCLK] = {
22 	19200000,
23 	24000000,
24 	25000000,
25 	26000000,
26 };
27 
get_external_clk(u32 clk)28 unsigned int get_external_clk(u32 clk)
29 {
30 	unsigned int clk_freq;
31 	u8 sysclk_index = get_sysclk_index();
32 
33 	switch (clk) {
34 	case sys_clk:
35 		clk_freq = sysclk_array[sysclk_index];
36 		break;
37 	case pa_clk:
38 		clk_freq = sysclk_array[sysclk_index];
39 		break;
40 	case tetris_clk:
41 		clk_freq = sysclk_array[sysclk_index];
42 		break;
43 	case ddr3a_clk:
44 		clk_freq = sysclk_array[sysclk_index];
45 		break;
46 	case uart_clk:
47 		clk_freq = sysclk_array[sysclk_index];
48 		break;
49 	default:
50 		clk_freq = 0;
51 		break;
52 	}
53 
54 	return clk_freq;
55 }
56 
57 int speeds[DEVSPEED_NUMSPDS] = {
58 	SPD400,
59 	SPD600,
60 	SPD800,
61 	SPD900,
62 	SPD1000,
63 	SPD900,
64 	SPD800,
65 	SPD600,
66 	SPD400,
67 	SPD200,
68 };
69 
70 static int dev_speeds[DEVSPEED_NUMSPDS] = {
71 	SPD600,
72 	SPD800,
73 	SPD900,
74 	SPD1000,
75 	SPD900,
76 	SPD800,
77 	SPD600,
78 	SPD400,
79 };
80 
81 static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
82 	[SYSCLK_19MHz] = {
83 		[SPD400]	= {MAIN_PLL, 125, 3, 2},
84 		[SPD600]	= {MAIN_PLL, 125, 2, 2},
85 		[SPD800]	= {MAIN_PLL, 250, 3, 2},
86 		[SPD900]	= {MAIN_PLL, 187, 2, 2},
87 		[SPD1000]	= {MAIN_PLL, 104, 1, 2},
88 	},
89 	[SYSCLK_24MHz] = {
90 		[SPD400]	= {MAIN_PLL, 100, 3, 2},
91 		[SPD600]	= {MAIN_PLL, 300, 6, 2},
92 		[SPD800]	= {MAIN_PLL, 200, 3, 2},
93 		[SPD900]	= {MAIN_PLL, 75, 1, 2},
94 		[SPD1000]	= {MAIN_PLL, 250, 3, 2},
95 	},
96 	[SYSCLK_25MHz] = {
97 		[SPD400]	= {MAIN_PLL, 32, 1, 2},
98 		[SPD600]	= {MAIN_PLL, 48, 1, 2},
99 		[SPD800]	= {MAIN_PLL, 64, 1, 2},
100 		[SPD900]	= {MAIN_PLL, 72, 1, 2},
101 		[SPD1000]	= {MAIN_PLL, 80, 1, 2},
102 	},
103 	[SYSCLK_26MHz] = {
104 		[SPD400]	= {MAIN_PLL, 400, 13, 2},
105 		[SPD600]	= {MAIN_PLL, 230, 5, 2},
106 		[SPD800]	= {MAIN_PLL, 123, 2, 2},
107 		[SPD900]	= {MAIN_PLL, 69, 1, 2},
108 		[SPD1000]	= {MAIN_PLL, 384, 5, 2},
109 	},
110 };
111 
112 static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
113 	[SYSCLK_19MHz] = {
114 		[SPD200]	= {TETRIS_PLL, 625, 6, 10},
115 		[SPD400]	= {TETRIS_PLL, 125, 1, 6},
116 		[SPD600]	= {TETRIS_PLL, 125, 1, 4},
117 		[SPD800]	= {TETRIS_PLL, 333, 2, 4},
118 		[SPD900]	= {TETRIS_PLL, 187, 2, 2},
119 		[SPD1000]	= {TETRIS_PLL, 104, 1, 2},
120 	},
121 	[SYSCLK_24MHz] = {
122 		[SPD200]	= {TETRIS_PLL, 250, 3, 10},
123 		[SPD400]	= {TETRIS_PLL, 100, 1, 6},
124 		[SPD600]	= {TETRIS_PLL, 100, 1, 4},
125 		[SPD800]	= {TETRIS_PLL, 400, 3, 4},
126 		[SPD900]	= {TETRIS_PLL, 75, 1, 2},
127 		[SPD1000]	= {TETRIS_PLL, 250, 3, 2},
128 	},
129 	[SYSCLK_25MHz] = {
130 		[SPD200]	= {TETRIS_PLL, 80, 1, 10},
131 		[SPD400]	= {TETRIS_PLL, 96, 1, 6},
132 		[SPD600]	= {TETRIS_PLL, 96, 1, 4},
133 		[SPD800]	= {TETRIS_PLL, 128, 1, 4},
134 		[SPD900]	= {TETRIS_PLL, 72, 1, 2},
135 		[SPD1000]	= {TETRIS_PLL, 80, 1, 2},
136 	},
137 	[SYSCLK_26MHz] = {
138 		[SPD200]	= {TETRIS_PLL, 307, 4, 10},
139 		[SPD400]	= {TETRIS_PLL, 369, 4, 6},
140 		[SPD600]	= {TETRIS_PLL, 369, 4, 4},
141 		[SPD800]	= {TETRIS_PLL, 123, 1, 4},
142 		[SPD900]	= {TETRIS_PLL, 69, 1, 2},
143 		[SPD1000]	= {TETRIS_PLL, 384, 5, 2},
144 	},
145 };
146 
147 static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
148 	[SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
149 	[SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
150 	[SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
151 	[SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
152 };
153 
154 static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
155 	[SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
156 	[SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
157 	[SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
158 	[SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
159 };
160 
161 static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
162 	[SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
163 	[SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
164 	[SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
165 	[SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
166 };
167 
168 static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
169 	[SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
170 	[SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
171 	[SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
172 	[SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
173 };
174 
get_pll_init_data(int pll)175 struct pll_init_data *get_pll_init_data(int pll)
176 {
177 	int speed;
178 	struct pll_init_data *data = NULL;
179 	u8 sysclk_index = get_sysclk_index();
180 
181 	switch (pll) {
182 	case MAIN_PLL:
183 		speed = get_max_dev_speed(dev_speeds);
184 		data = &main_pll_config[sysclk_index][speed];
185 		break;
186 	case TETRIS_PLL:
187 		speed = get_max_arm_speed(speeds);
188 		data = &tetris_pll_config[sysclk_index][speed];
189 		break;
190 	case NSS_PLL:
191 		data = &nss_pll_config[sysclk_index];
192 		break;
193 	case UART_PLL:
194 		data = &uart_pll_config[sysclk_index];
195 		break;
196 	case DDR3_PLL:
197 		if (cpu_revision() & CPU_66AK2G1x) {
198 			speed = get_max_arm_speed(speeds);
199 			if (speed == SPD1000)
200 				data = &ddr3_pll_config_1066[sysclk_index];
201 			else
202 				data = &ddr3_pll_config_800[sysclk_index];
203 		} else {
204 			data = &ddr3_pll_config_800[sysclk_index];
205 		}
206 		break;
207 	default:
208 		data = NULL;
209 	}
210 
211 	return data;
212 }
213 
214 s16 divn_val[16] = {
215 	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
216 };
217 
218 #if defined(CONFIG_MMC)
board_mmc_init(bd_t * bis)219 int board_mmc_init(bd_t *bis)
220 {
221 	if (psc_enable_module(KS2_LPSC_MMC)) {
222 		printf("%s module enabled failed\n", __func__);
223 		return -1;
224 	}
225 
226 	if (board_is_k2g_gp() || board_is_k2g_g1())
227 		omap_mmc_init(0, 0, 0, -1, -1);
228 
229 	omap_mmc_init(1, 0, 0, -1, -1);
230 	return 0;
231 }
232 #endif
233 
234 #if defined(CONFIG_MULTI_DTB_FIT)
board_fit_config_name_match(const char * name)235 int board_fit_config_name_match(const char *name)
236 {
237 	bool eeprom_read = board_ti_was_eeprom_read();
238 
239 	if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
240 		return 0;
241 	else if (!strcmp(name, "keystone-k2g-evm") &&
242 		(board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
243 		return 0;
244 	else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
245 		return 0;
246 	else
247 		return -1;
248 }
249 #endif
250 
251 #if defined(CONFIG_DTB_RESELECT)
k2g_alt_board_detect(void)252 static int k2g_alt_board_detect(void)
253 {
254 #ifndef CONFIG_DM_I2C
255 	int rc;
256 
257 	rc = i2c_set_bus_num(1);
258 	if (rc)
259 		return rc;
260 
261 	rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
262 	if (rc)
263 		return rc;
264 #else
265 	struct udevice *bus, *dev;
266 	int rc;
267 
268 	rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
269 	if (rc)
270 		return rc;
271 	rc = dm_i2c_probe(bus, K2G_GP_AUDIO_CODEC_ADDRESS, 0, &dev);
272 	if (rc)
273 		return rc;
274 #endif
275 	ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
276 
277 	return 0;
278 }
279 
k2g_reset_mux_config(void)280 static void k2g_reset_mux_config(void)
281 {
282 	/* Unlock the reset mux register */
283 	clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
284 
285 	/* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
286 	clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
287 			RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
288 
289 	/* lock the reset mux register to prevent any spurious writes. */
290 	setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
291 }
292 
embedded_dtb_select(void)293 int embedded_dtb_select(void)
294 {
295 	int rc;
296 	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
297 			CONFIG_EEPROM_CHIP_ADDRESS);
298 	if (rc) {
299 		rc = k2g_alt_board_detect();
300 		if (rc) {
301 			printf("Unable to do board detection\n");
302 			return -1;
303 		}
304 	}
305 
306 	fdtdec_setup();
307 
308 	k2g_mux_config();
309 
310 	k2g_reset_mux_config();
311 
312 	if (board_is_k2g_gp() || board_is_k2g_g1()) {
313 		/* deassert FLASH_HOLD */
314 		clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
315 			     BIT(9));
316 		setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
317 			     BIT(9));
318 	}
319 
320 	return 0;
321 }
322 #endif
323 
324 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)325 int board_late_init(void)
326 {
327 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
328 	int rc;
329 
330 	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
331 			CONFIG_EEPROM_CHIP_ADDRESS);
332 	if (rc)
333 		printf("ti_i2c_eeprom_init failed %d\n", rc);
334 
335 	board_ti_set_ethaddr(1);
336 #endif
337 
338 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
339 	if (board_is_k2g_gp())
340 		env_set("board_name", "66AK2GGP\0");
341 	else if (board_is_k2g_g1())
342 		env_set("board_name", "66AK2GG1\0");
343 	else if (board_is_k2g_ice())
344 		env_set("board_name", "66AK2GIC\0");
345 #endif
346 	return 0;
347 }
348 #endif
349 
350 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)351 int board_early_init_f(void)
352 {
353 	init_plls();
354 
355 	k2g_mux_config();
356 
357 	return 0;
358 }
359 #endif
360 
361 #ifdef CONFIG_SPL_BUILD
spl_init_keystone_plls(void)362 void spl_init_keystone_plls(void)
363 {
364 	init_plls();
365 }
366 #endif
367 
368 #ifdef CONFIG_TI_SECURE_DEVICE
board_pmmc_image_process(ulong pmmc_image,size_t pmmc_size)369 void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
370 {
371 	int id = env_get_ulong("dev_pmmc", 10, 0);
372 	int ret;
373 
374 	if (!rproc_is_initialized())
375 		rproc_init();
376 
377 	ret = rproc_load(id, pmmc_image, pmmc_size);
378 	printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
379 	       id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");
380 
381 	if (!ret)
382 		rproc_start(id);
383 }
384 
385 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);
386 #endif
387