1 /*
2 * Copyright (c) 2018, Impinj, Inc.
3 *
4 * Designware PCIe IP block emulation
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/module.h"
24 #include "qemu/log.h"
25 #include "hw/pci/msi.h"
26 #include "hw/pci/pci_bridge.h"
27 #include "hw/pci/pci_host.h"
28 #include "hw/pci/pcie_port.h"
29 #include "hw/qdev-properties.h"
30 #include "migration/vmstate.h"
31 #include "hw/irq.h"
32 #include "hw/pci-host/designware.h"
33
34 #define DESIGNWARE_PCIE_PORT_LINK_CONTROL 0x710
35 #define DESIGNWARE_PCIE_PHY_DEBUG_R1 0x72C
36 #define DESIGNWARE_PCIE_PHY_DEBUG_R1_XMLH_LINK_UP BIT(4)
37 #define DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
38 #define DESIGNWARE_PCIE_PORT_LOGIC_SPEED_CHANGE BIT(17)
39 #define DESIGNWARE_PCIE_MSI_ADDR_LO 0x820
40 #define DESIGNWARE_PCIE_MSI_ADDR_HI 0x824
41 #define DESIGNWARE_PCIE_MSI_INTR0_ENABLE 0x828
42 #define DESIGNWARE_PCIE_MSI_INTR0_MASK 0x82C
43 #define DESIGNWARE_PCIE_MSI_INTR0_STATUS 0x830
44 #define DESIGNWARE_PCIE_ATU_VIEWPORT 0x900
45 #define DESIGNWARE_PCIE_ATU_REGION_INBOUND BIT(31)
46 #define DESIGNWARE_PCIE_ATU_CR1 0x904
47 #define DESIGNWARE_PCIE_ATU_TYPE_MEM (0x0 << 0)
48 #define DESIGNWARE_PCIE_ATU_CR2 0x908
49 #define DESIGNWARE_PCIE_ATU_ENABLE BIT(31)
50 #define DESIGNWARE_PCIE_ATU_LOWER_BASE 0x90C
51 #define DESIGNWARE_PCIE_ATU_UPPER_BASE 0x910
52 #define DESIGNWARE_PCIE_ATU_LIMIT 0x914
53 #define DESIGNWARE_PCIE_ATU_LOWER_TARGET 0x918
54 #define DESIGNWARE_PCIE_ATU_BUS(x) (((x) >> 24) & 0xff)
55 #define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff)
56 #define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C
57
58 #define DESIGNWARE_PCIE_IRQ_MSI 3
59
60 static DesignwarePCIEHost *
designware_pcie_root_to_host(DesignwarePCIERoot * root)61 designware_pcie_root_to_host(DesignwarePCIERoot *root)
62 {
63 BusState *bus = qdev_get_parent_bus(DEVICE(root));
64 return DESIGNWARE_PCIE_HOST(bus->parent);
65 }
66
designware_pcie_root_msi_read(void * opaque,hwaddr addr,unsigned size)67 static uint64_t designware_pcie_root_msi_read(void *opaque, hwaddr addr,
68 unsigned size)
69 {
70 /*
71 * Attempts to read from the MSI address are undefined in
72 * the PCI specifications. For this hardware, the datasheet
73 * specifies that a read from the magic address is simply not
74 * intercepted by the MSI controller, and will go out to the
75 * AHB/AXI bus like any other PCI-device-initiated DMA read.
76 * This is not trivial to implement in QEMU, so since
77 * well-behaved guests won't ever ask a PCI device to DMA from
78 * this address we just log the missing functionality.
79 */
80 qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__);
81 return 0;
82 }
83
designware_pcie_root_msi_write(void * opaque,hwaddr addr,uint64_t val,unsigned len)84 static void designware_pcie_root_msi_write(void *opaque, hwaddr addr,
85 uint64_t val, unsigned len)
86 {
87 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque);
88 DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
89
90 root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable;
91
92 if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {
93 qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1);
94 }
95 }
96
97 static const MemoryRegionOps designware_pci_host_msi_ops = {
98 .read = designware_pcie_root_msi_read,
99 .write = designware_pcie_root_msi_write,
100 .endianness = DEVICE_LITTLE_ENDIAN,
101 .valid = {
102 .min_access_size = 4,
103 .max_access_size = 4,
104 },
105 };
106
designware_pcie_root_update_msi_mapping(DesignwarePCIERoot * root)107 static void designware_pcie_root_update_msi_mapping(DesignwarePCIERoot *root)
108
109 {
110 MemoryRegion *mem = &root->msi.iomem;
111 const uint64_t base = root->msi.base;
112 const bool enable = root->msi.intr[0].enable;
113
114 memory_region_set_address(mem, base);
115 memory_region_set_enabled(mem, enable);
116 }
117
118 static DesignwarePCIEViewport *
designware_pcie_root_get_current_viewport(DesignwarePCIERoot * root)119 designware_pcie_root_get_current_viewport(DesignwarePCIERoot *root)
120 {
121 const unsigned int idx = root->atu_viewport & 0xF;
122 const unsigned int dir =
123 !!(root->atu_viewport & DESIGNWARE_PCIE_ATU_REGION_INBOUND);
124 return &root->viewports[dir][idx];
125 }
126
127 static uint32_t
designware_pcie_root_config_read(PCIDevice * d,uint32_t address,int len)128 designware_pcie_root_config_read(PCIDevice *d, uint32_t address, int len)
129 {
130 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d);
131 DesignwarePCIEViewport *viewport =
132 designware_pcie_root_get_current_viewport(root);
133
134 uint32_t val;
135
136 switch (address) {
137 case DESIGNWARE_PCIE_PORT_LINK_CONTROL:
138 /*
139 * Linux guest uses this register only to configure number of
140 * PCIE lane (which in our case is irrelevant) and doesn't
141 * really care about the value it reads from this register
142 */
143 val = 0xDEADBEEF;
144 break;
145
146 case DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL:
147 /*
148 * To make sure that any code in guest waiting for speed
149 * change does not time out we always report
150 * PORT_LOGIC_SPEED_CHANGE as set
151 */
152 val = DESIGNWARE_PCIE_PORT_LOGIC_SPEED_CHANGE;
153 break;
154
155 case DESIGNWARE_PCIE_MSI_ADDR_LO:
156 val = root->msi.base;
157 break;
158
159 case DESIGNWARE_PCIE_MSI_ADDR_HI:
160 val = root->msi.base >> 32;
161 break;
162
163 case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
164 val = root->msi.intr[0].enable;
165 break;
166
167 case DESIGNWARE_PCIE_MSI_INTR0_MASK:
168 val = root->msi.intr[0].mask;
169 break;
170
171 case DESIGNWARE_PCIE_MSI_INTR0_STATUS:
172 val = root->msi.intr[0].status;
173 break;
174
175 case DESIGNWARE_PCIE_PHY_DEBUG_R1:
176 val = DESIGNWARE_PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
177 break;
178
179 case DESIGNWARE_PCIE_ATU_VIEWPORT:
180 val = root->atu_viewport;
181 break;
182
183 case DESIGNWARE_PCIE_ATU_LOWER_BASE:
184 val = viewport->base;
185 break;
186
187 case DESIGNWARE_PCIE_ATU_UPPER_BASE:
188 val = viewport->base >> 32;
189 break;
190
191 case DESIGNWARE_PCIE_ATU_LOWER_TARGET:
192 val = viewport->target;
193 break;
194
195 case DESIGNWARE_PCIE_ATU_UPPER_TARGET:
196 val = viewport->target >> 32;
197 break;
198
199 case DESIGNWARE_PCIE_ATU_LIMIT:
200 val = viewport->limit;
201 break;
202
203 case DESIGNWARE_PCIE_ATU_CR1:
204 case DESIGNWARE_PCIE_ATU_CR2:
205 val = viewport->cr[(address - DESIGNWARE_PCIE_ATU_CR1) /
206 sizeof(uint32_t)];
207 break;
208
209 default:
210 val = pci_default_read_config(d, address, len);
211 break;
212 }
213
214 return val;
215 }
216
designware_pcie_root_data_access(void * opaque,hwaddr addr,uint64_t * val,unsigned len)217 static uint64_t designware_pcie_root_data_access(void *opaque, hwaddr addr,
218 uint64_t *val, unsigned len)
219 {
220 DesignwarePCIEViewport *viewport = opaque;
221 DesignwarePCIERoot *root = viewport->root;
222
223 const uint8_t busnum = DESIGNWARE_PCIE_ATU_BUS(viewport->target);
224 const uint8_t devfn = DESIGNWARE_PCIE_ATU_DEVFN(viewport->target);
225 PCIBus *pcibus = pci_get_bus(PCI_DEVICE(root));
226 PCIDevice *pcidev = pci_find_device(pcibus, busnum, devfn);
227
228 if (pcidev) {
229 addr &= pci_config_size(pcidev) - 1;
230
231 if (val) {
232 pci_host_config_write_common(pcidev, addr,
233 pci_config_size(pcidev),
234 *val, len);
235 } else {
236 return pci_host_config_read_common(pcidev, addr,
237 pci_config_size(pcidev),
238 len);
239 }
240 }
241
242 return UINT64_MAX;
243 }
244
designware_pcie_root_data_read(void * opaque,hwaddr addr,unsigned len)245 static uint64_t designware_pcie_root_data_read(void *opaque, hwaddr addr,
246 unsigned len)
247 {
248 return designware_pcie_root_data_access(opaque, addr, NULL, len);
249 }
250
designware_pcie_root_data_write(void * opaque,hwaddr addr,uint64_t val,unsigned len)251 static void designware_pcie_root_data_write(void *opaque, hwaddr addr,
252 uint64_t val, unsigned len)
253 {
254 designware_pcie_root_data_access(opaque, addr, &val, len);
255 }
256
257 static const MemoryRegionOps designware_pci_host_conf_ops = {
258 .read = designware_pcie_root_data_read,
259 .write = designware_pcie_root_data_write,
260 .endianness = DEVICE_LITTLE_ENDIAN,
261 .valid = {
262 .min_access_size = 1,
263 .max_access_size = 4,
264 },
265 };
266
designware_pcie_update_viewport(DesignwarePCIERoot * root,DesignwarePCIEViewport * viewport)267 static void designware_pcie_update_viewport(DesignwarePCIERoot *root,
268 DesignwarePCIEViewport *viewport)
269 {
270 const uint64_t target = viewport->target;
271 const uint64_t base = viewport->base;
272 const uint64_t size = (uint64_t)viewport->limit - base + 1;
273 const bool enabled = viewport->cr[1] & DESIGNWARE_PCIE_ATU_ENABLE;
274
275 MemoryRegion *current, *other;
276
277 if (viewport->cr[0] == DESIGNWARE_PCIE_ATU_TYPE_MEM) {
278 current = &viewport->mem;
279 other = &viewport->cfg;
280 memory_region_set_alias_offset(current, target);
281 } else {
282 current = &viewport->cfg;
283 other = &viewport->mem;
284 }
285
286 /*
287 * An outbound viewport can be reconfigure from being MEM to CFG,
288 * to account for that we disable the "other" memory region that
289 * becomes unused due to that fact.
290 */
291 memory_region_set_enabled(other, false);
292 if (enabled) {
293 memory_region_set_size(current, size);
294 memory_region_set_address(current, base);
295 }
296 memory_region_set_enabled(current, enabled);
297 }
298
designware_pcie_root_config_write(PCIDevice * d,uint32_t address,uint32_t val,int len)299 static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
300 uint32_t val, int len)
301 {
302 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d);
303 DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
304 DesignwarePCIEViewport *viewport =
305 designware_pcie_root_get_current_viewport(root);
306
307 switch (address) {
308 case DESIGNWARE_PCIE_PORT_LINK_CONTROL:
309 case DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL:
310 case DESIGNWARE_PCIE_PHY_DEBUG_R1:
311 /* No-op */
312 break;
313
314 case DESIGNWARE_PCIE_MSI_ADDR_LO:
315 root->msi.base &= 0xFFFFFFFF00000000ULL;
316 root->msi.base |= val;
317 designware_pcie_root_update_msi_mapping(root);
318 break;
319
320 case DESIGNWARE_PCIE_MSI_ADDR_HI:
321 root->msi.base &= 0x00000000FFFFFFFFULL;
322 root->msi.base |= (uint64_t)val << 32;
323 designware_pcie_root_update_msi_mapping(root);
324 break;
325
326 case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
327 root->msi.intr[0].enable = val;
328 designware_pcie_root_update_msi_mapping(root);
329 break;
330
331 case DESIGNWARE_PCIE_MSI_INTR0_MASK:
332 root->msi.intr[0].mask = val;
333 break;
334
335 case DESIGNWARE_PCIE_MSI_INTR0_STATUS:
336 root->msi.intr[0].status ^= val;
337 if (!root->msi.intr[0].status) {
338 qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0);
339 }
340 break;
341
342 case DESIGNWARE_PCIE_ATU_VIEWPORT:
343 val &= DESIGNWARE_PCIE_ATU_REGION_INBOUND |
344 (DESIGNWARE_PCIE_NUM_VIEWPORTS - 1);
345 root->atu_viewport = val;
346 break;
347
348 case DESIGNWARE_PCIE_ATU_LOWER_BASE:
349 viewport->base &= 0xFFFFFFFF00000000ULL;
350 viewport->base |= val;
351 break;
352
353 case DESIGNWARE_PCIE_ATU_UPPER_BASE:
354 viewport->base &= 0x00000000FFFFFFFFULL;
355 viewport->base |= (uint64_t)val << 32;
356 break;
357
358 case DESIGNWARE_PCIE_ATU_LOWER_TARGET:
359 viewport->target &= 0xFFFFFFFF00000000ULL;
360 viewport->target |= val;
361 break;
362
363 case DESIGNWARE_PCIE_ATU_UPPER_TARGET:
364 viewport->target &= 0x00000000FFFFFFFFULL;
365 viewport->target |= val;
366 break;
367
368 case DESIGNWARE_PCIE_ATU_LIMIT:
369 viewport->limit = val;
370 break;
371
372 case DESIGNWARE_PCIE_ATU_CR1:
373 viewport->cr[0] = val;
374 break;
375 case DESIGNWARE_PCIE_ATU_CR2:
376 viewport->cr[1] = val;
377 designware_pcie_update_viewport(root, viewport);
378 break;
379
380 default:
381 pci_bridge_write_config(d, address, val, len);
382 break;
383 }
384 }
385
designware_pcie_viewport_name(const char * direction,unsigned int i,const char * type)386 static char *designware_pcie_viewport_name(const char *direction,
387 unsigned int i,
388 const char *type)
389 {
390 return g_strdup_printf("PCI %s Viewport %u [%s]",
391 direction, i, type);
392 }
393
designware_pcie_root_realize(PCIDevice * dev,Error ** errp)394 static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
395 {
396 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev);
397 DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
398 MemoryRegion *host_mem = get_system_memory();
399 MemoryRegion *address_space = &host->pci.memory;
400 PCIBridge *br = PCI_BRIDGE(dev);
401 DesignwarePCIEViewport *viewport;
402 /*
403 * Dummy values used for initial configuration of MemoryRegions
404 * that belong to a given viewport
405 */
406 const hwaddr dummy_offset = 0;
407 const uint64_t dummy_size = 4;
408 size_t i;
409
410 br->bus_name = "dw-pcie";
411
412 pci_set_word(dev->config + PCI_COMMAND,
413 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
414
415 pci_config_set_interrupt_pin(dev->config, 1);
416 pci_bridge_initfn(dev, TYPE_PCIE_BUS);
417
418 pcie_port_init_reg(dev);
419
420 pcie_cap_init(dev, 0x70, PCI_EXP_TYPE_ROOT_PORT,
421 0, &error_fatal);
422
423 msi_nonbroken = true;
424 msi_init(dev, 0x50, 32, true, true, &error_fatal);
425
426 for (i = 0; i < DESIGNWARE_PCIE_NUM_VIEWPORTS; i++) {
427 MemoryRegion *source, *destination, *mem;
428 const char *direction;
429 char *name;
430
431 viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i];
432 viewport->inbound = true;
433 viewport->base = 0x0000000000000000ULL;
434 viewport->target = 0x0000000000000000ULL;
435 viewport->limit = UINT32_MAX;
436 viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM;
437
438 source = &host->pci.address_space_root;
439 destination = host_mem;
440 direction = "Inbound";
441
442 /*
443 * Configure MemoryRegion implementing PCI -> CPU memory
444 * access
445 */
446 mem = &viewport->mem;
447 name = designware_pcie_viewport_name(direction, i, "MEM");
448 memory_region_init_alias(mem, OBJECT(root), name, destination,
449 dummy_offset, dummy_size);
450 memory_region_add_subregion_overlap(source, dummy_offset, mem, -1);
451 memory_region_set_enabled(mem, false);
452 g_free(name);
453
454 viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i];
455 viewport->root = root;
456 viewport->inbound = false;
457 viewport->base = 0x0000000000000000ULL;
458 viewport->target = 0x0000000000000000ULL;
459 viewport->limit = UINT32_MAX;
460 viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM;
461
462 destination = &host->pci.memory;
463 direction = "Outbound";
464 source = host_mem;
465
466 /*
467 * Configure MemoryRegion implementing CPU -> PCI memory
468 * access
469 */
470 mem = &viewport->mem;
471 name = designware_pcie_viewport_name(direction, i, "MEM");
472 memory_region_init_alias(mem, OBJECT(root), name, destination,
473 dummy_offset, dummy_size);
474 memory_region_add_subregion(source, dummy_offset, mem);
475 memory_region_set_enabled(mem, false);
476 g_free(name);
477
478 /*
479 * Configure MemoryRegion implementing access to configuration
480 * space
481 */
482 mem = &viewport->cfg;
483 name = designware_pcie_viewport_name(direction, i, "CFG");
484 memory_region_init_io(&viewport->cfg, OBJECT(root),
485 &designware_pci_host_conf_ops,
486 viewport, name, dummy_size);
487 memory_region_add_subregion(source, dummy_offset, mem);
488 memory_region_set_enabled(mem, false);
489 g_free(name);
490 }
491
492 /*
493 * If no inbound iATU windows are configured, HW defaults to
494 * letting inbound TLPs to pass in. We emulate that by explicitly
495 * configuring first inbound window to cover all of target's
496 * address space.
497 *
498 * NOTE: This will not work correctly for the case when first
499 * configured inbound window is window 0
500 */
501 viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0];
502 viewport->cr[1] = DESIGNWARE_PCIE_ATU_ENABLE;
503 designware_pcie_update_viewport(root, viewport);
504
505 memory_region_init_io(&root->msi.iomem, OBJECT(root),
506 &designware_pci_host_msi_ops,
507 root, "pcie-msi", 0x4);
508 /*
509 * We initially place MSI interrupt I/O region at address 0 and
510 * disable it. It'll be later moved to correct offset and enabled
511 * in designware_pcie_root_update_msi_mapping() as a part of
512 * initialization done by guest OS
513 */
514 memory_region_add_subregion(address_space, dummy_offset, &root->msi.iomem);
515 memory_region_set_enabled(&root->msi.iomem, false);
516 }
517
designware_pcie_set_irq(void * opaque,int irq_num,int level)518 static void designware_pcie_set_irq(void *opaque, int irq_num, int level)
519 {
520 DesignwarePCIEHost *host = DESIGNWARE_PCIE_HOST(opaque);
521
522 qemu_set_irq(host->pci.irqs[irq_num], level);
523 }
524
525 static const char *
designware_pcie_host_root_bus_path(PCIHostState * host_bridge,PCIBus * rootbus)526 designware_pcie_host_root_bus_path(PCIHostState *host_bridge, PCIBus *rootbus)
527 {
528 return "0000:00";
529 }
530
531 static const VMStateDescription vmstate_designware_pcie_msi_bank = {
532 .name = "designware-pcie-msi-bank",
533 .version_id = 1,
534 .minimum_version_id = 1,
535 .fields = (const VMStateField[]) {
536 VMSTATE_UINT32(enable, DesignwarePCIEMSIBank),
537 VMSTATE_UINT32(mask, DesignwarePCIEMSIBank),
538 VMSTATE_UINT32(status, DesignwarePCIEMSIBank),
539 VMSTATE_END_OF_LIST()
540 }
541 };
542
543 static const VMStateDescription vmstate_designware_pcie_msi = {
544 .name = "designware-pcie-msi",
545 .version_id = 1,
546 .minimum_version_id = 1,
547 .fields = (const VMStateField[]) {
548 VMSTATE_UINT64(base, DesignwarePCIEMSI),
549 VMSTATE_STRUCT_ARRAY(intr,
550 DesignwarePCIEMSI,
551 DESIGNWARE_PCIE_NUM_MSI_BANKS,
552 1,
553 vmstate_designware_pcie_msi_bank,
554 DesignwarePCIEMSIBank),
555 VMSTATE_END_OF_LIST()
556 }
557 };
558
559 static const VMStateDescription vmstate_designware_pcie_viewport = {
560 .name = "designware-pcie-viewport",
561 .version_id = 1,
562 .minimum_version_id = 1,
563 .fields = (const VMStateField[]) {
564 VMSTATE_UINT64(base, DesignwarePCIEViewport),
565 VMSTATE_UINT64(target, DesignwarePCIEViewport),
566 VMSTATE_UINT32(limit, DesignwarePCIEViewport),
567 VMSTATE_UINT32_ARRAY(cr, DesignwarePCIEViewport, 2),
568 VMSTATE_END_OF_LIST()
569 }
570 };
571
572 static const VMStateDescription vmstate_designware_pcie_root = {
573 .name = "designware-pcie-root",
574 .version_id = 1,
575 .minimum_version_id = 1,
576 .fields = (const VMStateField[]) {
577 VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
578 VMSTATE_UINT32(atu_viewport, DesignwarePCIERoot),
579 VMSTATE_STRUCT_2DARRAY(viewports,
580 DesignwarePCIERoot,
581 2,
582 DESIGNWARE_PCIE_NUM_VIEWPORTS,
583 1,
584 vmstate_designware_pcie_viewport,
585 DesignwarePCIEViewport),
586 VMSTATE_STRUCT(msi,
587 DesignwarePCIERoot,
588 1,
589 vmstate_designware_pcie_msi,
590 DesignwarePCIEMSI),
591 VMSTATE_END_OF_LIST()
592 }
593 };
594
designware_pcie_root_class_init(ObjectClass * klass,void * data)595 static void designware_pcie_root_class_init(ObjectClass *klass, void *data)
596 {
597 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
598 DeviceClass *dc = DEVICE_CLASS(klass);
599
600 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
601
602 k->vendor_id = PCI_VENDOR_ID_SYNOPSYS;
603 k->device_id = 0xABCD;
604 k->revision = 0;
605 k->class_id = PCI_CLASS_BRIDGE_PCI;
606 k->exit = pci_bridge_exitfn;
607 k->realize = designware_pcie_root_realize;
608 k->config_read = designware_pcie_root_config_read;
609 k->config_write = designware_pcie_root_config_write;
610
611 device_class_set_legacy_reset(dc, pci_bridge_reset);
612 /*
613 * PCI-facing part of the host bridge, not usable without the
614 * host-facing part, which can't be device_add'ed, yet.
615 */
616 dc->user_creatable = false;
617 dc->vmsd = &vmstate_designware_pcie_root;
618 }
619
designware_pcie_host_mmio_read(void * opaque,hwaddr addr,unsigned int size)620 static uint64_t designware_pcie_host_mmio_read(void *opaque, hwaddr addr,
621 unsigned int size)
622 {
623 PCIHostState *pci = PCI_HOST_BRIDGE(opaque);
624 PCIDevice *device = pci_find_device(pci->bus, 0, 0);
625
626 return pci_host_config_read_common(device,
627 addr,
628 pci_config_size(device),
629 size);
630 }
631
designware_pcie_host_mmio_write(void * opaque,hwaddr addr,uint64_t val,unsigned int size)632 static void designware_pcie_host_mmio_write(void *opaque, hwaddr addr,
633 uint64_t val, unsigned int size)
634 {
635 PCIHostState *pci = PCI_HOST_BRIDGE(opaque);
636 PCIDevice *device = pci_find_device(pci->bus, 0, 0);
637
638 return pci_host_config_write_common(device,
639 addr,
640 pci_config_size(device),
641 val, size);
642 }
643
644 static const MemoryRegionOps designware_pci_mmio_ops = {
645 .read = designware_pcie_host_mmio_read,
646 .write = designware_pcie_host_mmio_write,
647 .endianness = DEVICE_LITTLE_ENDIAN,
648 .impl = {
649 /*
650 * Our device would not work correctly if the guest was doing
651 * unaligned access. This might not be a limitation on the real
652 * device but in practice there is no reason for a guest to access
653 * this device unaligned.
654 */
655 .min_access_size = 4,
656 .max_access_size = 4,
657 .unaligned = false,
658 },
659 };
660
designware_pcie_host_set_iommu(PCIBus * bus,void * opaque,int devfn)661 static AddressSpace *designware_pcie_host_set_iommu(PCIBus *bus, void *opaque,
662 int devfn)
663 {
664 DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(opaque);
665
666 return &s->pci.address_space;
667 }
668
669 static const PCIIOMMUOps designware_iommu_ops = {
670 .get_address_space = designware_pcie_host_set_iommu,
671 };
672
designware_pcie_host_realize(DeviceState * dev,Error ** errp)673 static void designware_pcie_host_realize(DeviceState *dev, Error **errp)
674 {
675 PCIHostState *pci = PCI_HOST_BRIDGE(dev);
676 DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(dev);
677 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
678 size_t i;
679
680 for (i = 0; i < ARRAY_SIZE(s->pci.irqs); i++) {
681 sysbus_init_irq(sbd, &s->pci.irqs[i]);
682 }
683
684 memory_region_init_io(&s->mmio,
685 OBJECT(s),
686 &designware_pci_mmio_ops,
687 s,
688 "pcie.reg", 4 * 1024);
689 sysbus_init_mmio(sbd, &s->mmio);
690
691 memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", 16);
692 memory_region_init(&s->pci.memory, OBJECT(s),
693 "pcie-bus-memory",
694 UINT64_MAX);
695
696 pci->bus = pci_register_root_bus(dev, "pcie",
697 designware_pcie_set_irq,
698 pci_swizzle_map_irq_fn,
699 s,
700 &s->pci.memory,
701 &s->pci.io,
702 0, 4,
703 TYPE_PCIE_BUS);
704 pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
705
706 memory_region_init(&s->pci.address_space_root,
707 OBJECT(s),
708 "pcie-bus-address-space-root",
709 UINT64_MAX);
710 memory_region_add_subregion(&s->pci.address_space_root,
711 0x0, &s->pci.memory);
712 address_space_init(&s->pci.address_space,
713 &s->pci.address_space_root,
714 "pcie-bus-address-space");
715 pci_setup_iommu(pci->bus, &designware_iommu_ops, s);
716
717 qdev_realize(DEVICE(&s->root), BUS(pci->bus), &error_fatal);
718 }
719
720 static const VMStateDescription vmstate_designware_pcie_host = {
721 .name = "designware-pcie-host",
722 .version_id = 1,
723 .minimum_version_id = 1,
724 .fields = (const VMStateField[]) {
725 VMSTATE_STRUCT(root,
726 DesignwarePCIEHost,
727 1,
728 vmstate_designware_pcie_root,
729 DesignwarePCIERoot),
730 VMSTATE_END_OF_LIST()
731 }
732 };
733
designware_pcie_host_class_init(ObjectClass * klass,void * data)734 static void designware_pcie_host_class_init(ObjectClass *klass, void *data)
735 {
736 DeviceClass *dc = DEVICE_CLASS(klass);
737 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
738
739 hc->root_bus_path = designware_pcie_host_root_bus_path;
740 dc->realize = designware_pcie_host_realize;
741 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
742 dc->fw_name = "pci";
743 dc->vmsd = &vmstate_designware_pcie_host;
744 }
745
designware_pcie_host_init(Object * obj)746 static void designware_pcie_host_init(Object *obj)
747 {
748 DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(obj);
749 DesignwarePCIERoot *root = &s->root;
750
751 object_initialize_child(obj, "root", root, TYPE_DESIGNWARE_PCIE_ROOT);
752 qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
753 qdev_prop_set_bit(DEVICE(root), "multifunction", false);
754 }
755
756 static const TypeInfo designware_pcie_types[] = {
757 {
758 .name = TYPE_DESIGNWARE_PCIE_HOST,
759 .parent = TYPE_PCI_HOST_BRIDGE,
760 .instance_size = sizeof(DesignwarePCIEHost),
761 .instance_init = designware_pcie_host_init,
762 .class_init = designware_pcie_host_class_init,
763 }, {
764 .name = TYPE_DESIGNWARE_PCIE_ROOT,
765 .parent = TYPE_PCI_BRIDGE,
766 .instance_size = sizeof(DesignwarePCIERoot),
767 .class_init = designware_pcie_root_class_init,
768 .interfaces = (InterfaceInfo[]) {
769 { INTERFACE_PCIE_DEVICE },
770 { }
771 },
772 },
773 };
774
775 DEFINE_TYPES(designware_pcie_types)
776