1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 */
6
7 /*
8 * Designware ethernet IP driver for U-Boot
9 */
10
11 #include <common.h>
12 #include <clk.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <miiphy.h>
16 #include <malloc.h>
17 #include <pci.h>
18 #include <reset.h>
19 #include <linux/compiler.h>
20 #include <linux/err.h>
21 #include <linux/kernel.h>
22 #include <asm/io.h>
23 #include <power/regulator.h>
24 #include "designware.h"
25
dw_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)26 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
27 {
28 #ifdef CONFIG_DM_ETH
29 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
30 struct eth_mac_regs *mac_p = priv->mac_regs_p;
31 #else
32 struct eth_mac_regs *mac_p = bus->priv;
33 #endif
34 ulong start;
35 u16 miiaddr;
36 int timeout = CONFIG_MDIO_TIMEOUT;
37
38 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
39 ((reg << MIIREGSHIFT) & MII_REGMSK);
40
41 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
42
43 start = get_timer(0);
44 while (get_timer(start) < timeout) {
45 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
46 return readl(&mac_p->miidata);
47 udelay(10);
48 };
49
50 return -ETIMEDOUT;
51 }
52
dw_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 val)53 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
54 u16 val)
55 {
56 #ifdef CONFIG_DM_ETH
57 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
58 struct eth_mac_regs *mac_p = priv->mac_regs_p;
59 #else
60 struct eth_mac_regs *mac_p = bus->priv;
61 #endif
62 ulong start;
63 u16 miiaddr;
64 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
65
66 writel(val, &mac_p->miidata);
67 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
68 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
69
70 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
71
72 start = get_timer(0);
73 while (get_timer(start) < timeout) {
74 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
75 ret = 0;
76 break;
77 }
78 udelay(10);
79 };
80
81 return ret;
82 }
83
84 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
dw_mdio_reset(struct mii_dev * bus)85 static int dw_mdio_reset(struct mii_dev *bus)
86 {
87 struct udevice *dev = bus->priv;
88 struct dw_eth_dev *priv = dev_get_priv(dev);
89 struct dw_eth_pdata *pdata = dev_get_platdata(dev);
90 int ret;
91
92 if (!dm_gpio_is_valid(&priv->reset_gpio))
93 return 0;
94
95 /* reset the phy */
96 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
97 if (ret)
98 return ret;
99
100 udelay(pdata->reset_delays[0]);
101
102 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
103 if (ret)
104 return ret;
105
106 udelay(pdata->reset_delays[1]);
107
108 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
109 if (ret)
110 return ret;
111
112 udelay(pdata->reset_delays[2]);
113
114 return 0;
115 }
116 #endif
117
dw_mdio_init(const char * name,void * priv)118 static int dw_mdio_init(const char *name, void *priv)
119 {
120 struct mii_dev *bus = mdio_alloc();
121
122 if (!bus) {
123 printf("Failed to allocate MDIO bus\n");
124 return -ENOMEM;
125 }
126
127 bus->read = dw_mdio_read;
128 bus->write = dw_mdio_write;
129 snprintf(bus->name, sizeof(bus->name), "%s", name);
130 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
131 bus->reset = dw_mdio_reset;
132 #endif
133
134 bus->priv = priv;
135
136 return mdio_register(bus);
137 }
138
tx_descs_init(struct dw_eth_dev * priv)139 static void tx_descs_init(struct dw_eth_dev *priv)
140 {
141 struct eth_dma_regs *dma_p = priv->dma_regs_p;
142 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
143 char *txbuffs = &priv->txbuffs[0];
144 struct dmamacdescr *desc_p;
145 u32 idx;
146
147 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
148 desc_p = &desc_table_p[idx];
149 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
150 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
151
152 #if defined(CONFIG_DW_ALTDESCRIPTOR)
153 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
154 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
155 DESC_TXSTS_TXCHECKINSCTRL |
156 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
157
158 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
159 desc_p->dmamac_cntl = 0;
160 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
161 #else
162 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
163 desc_p->txrx_status = 0;
164 #endif
165 }
166
167 /* Correcting the last pointer of the chain */
168 desc_p->dmamac_next = (ulong)&desc_table_p[0];
169
170 /* Flush all Tx buffer descriptors at once */
171 flush_dcache_range((ulong)priv->tx_mac_descrtable,
172 (ulong)priv->tx_mac_descrtable +
173 sizeof(priv->tx_mac_descrtable));
174
175 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
176 priv->tx_currdescnum = 0;
177 }
178
rx_descs_init(struct dw_eth_dev * priv)179 static void rx_descs_init(struct dw_eth_dev *priv)
180 {
181 struct eth_dma_regs *dma_p = priv->dma_regs_p;
182 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
183 char *rxbuffs = &priv->rxbuffs[0];
184 struct dmamacdescr *desc_p;
185 u32 idx;
186
187 /* Before passing buffers to GMAC we need to make sure zeros
188 * written there right after "priv" structure allocation were
189 * flushed into RAM.
190 * Otherwise there's a chance to get some of them flushed in RAM when
191 * GMAC is already pushing data to RAM via DMA. This way incoming from
192 * GMAC data will be corrupted. */
193 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
194
195 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
196 desc_p = &desc_table_p[idx];
197 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
198 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
199
200 desc_p->dmamac_cntl =
201 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
202 DESC_RXCTRL_RXCHAIN;
203
204 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
205 }
206
207 /* Correcting the last pointer of the chain */
208 desc_p->dmamac_next = (ulong)&desc_table_p[0];
209
210 /* Flush all Rx buffer descriptors at once */
211 flush_dcache_range((ulong)priv->rx_mac_descrtable,
212 (ulong)priv->rx_mac_descrtable +
213 sizeof(priv->rx_mac_descrtable));
214
215 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
216 priv->rx_currdescnum = 0;
217 }
218
_dw_write_hwaddr(struct dw_eth_dev * priv,u8 * mac_id)219 static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
220 {
221 struct eth_mac_regs *mac_p = priv->mac_regs_p;
222 u32 macid_lo, macid_hi;
223
224 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
225 (mac_id[3] << 24);
226 macid_hi = mac_id[4] + (mac_id[5] << 8);
227
228 writel(macid_hi, &mac_p->macaddr0hi);
229 writel(macid_lo, &mac_p->macaddr0lo);
230
231 return 0;
232 }
233
dw_adjust_link(struct dw_eth_dev * priv,struct eth_mac_regs * mac_p,struct phy_device * phydev)234 static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
235 struct phy_device *phydev)
236 {
237 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
238
239 if (!phydev->link) {
240 printf("%s: No link.\n", phydev->dev->name);
241 return 0;
242 }
243
244 if (phydev->speed != 1000)
245 conf |= MII_PORTSELECT;
246 else
247 conf &= ~MII_PORTSELECT;
248
249 if (phydev->speed == 100)
250 conf |= FES_100;
251
252 if (phydev->duplex)
253 conf |= FULLDPLXMODE;
254
255 writel(conf, &mac_p->conf);
256
257 printf("Speed: %d, %s duplex%s\n", phydev->speed,
258 (phydev->duplex) ? "full" : "half",
259 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
260
261 return 0;
262 }
263
_dw_eth_halt(struct dw_eth_dev * priv)264 static void _dw_eth_halt(struct dw_eth_dev *priv)
265 {
266 struct eth_mac_regs *mac_p = priv->mac_regs_p;
267 struct eth_dma_regs *dma_p = priv->dma_regs_p;
268
269 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
270 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
271
272 phy_shutdown(priv->phydev);
273 }
274
designware_eth_init(struct dw_eth_dev * priv,u8 * enetaddr)275 int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
276 {
277 struct eth_mac_regs *mac_p = priv->mac_regs_p;
278 struct eth_dma_regs *dma_p = priv->dma_regs_p;
279 unsigned int start;
280 int ret;
281
282 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
283
284 /*
285 * When a MII PHY is used, we must set the PS bit for the DMA
286 * reset to succeed.
287 */
288 if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
289 writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
290 else
291 writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
292
293 start = get_timer(0);
294 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
295 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
296 printf("DMA reset timeout\n");
297 return -ETIMEDOUT;
298 }
299
300 mdelay(100);
301 };
302
303 /*
304 * Soft reset above clears HW address registers.
305 * So we have to set it here once again.
306 */
307 _dw_write_hwaddr(priv, enetaddr);
308
309 rx_descs_init(priv);
310 tx_descs_init(priv);
311
312 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
313
314 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
315 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
316 &dma_p->opmode);
317 #else
318 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
319 &dma_p->opmode);
320 #endif
321
322 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
323
324 #ifdef CONFIG_DW_AXI_BURST_LEN
325 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
326 #endif
327
328 /* Start up the PHY */
329 ret = phy_startup(priv->phydev);
330 if (ret) {
331 printf("Could not initialize PHY %s\n",
332 priv->phydev->dev->name);
333 return ret;
334 }
335
336 ret = dw_adjust_link(priv, mac_p, priv->phydev);
337 if (ret)
338 return ret;
339
340 return 0;
341 }
342
designware_eth_enable(struct dw_eth_dev * priv)343 int designware_eth_enable(struct dw_eth_dev *priv)
344 {
345 struct eth_mac_regs *mac_p = priv->mac_regs_p;
346
347 if (!priv->phydev->link)
348 return -EIO;
349
350 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
351
352 return 0;
353 }
354
355 #define ETH_ZLEN 60
356
_dw_eth_send(struct dw_eth_dev * priv,void * packet,int length)357 static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
358 {
359 struct eth_dma_regs *dma_p = priv->dma_regs_p;
360 u32 desc_num = priv->tx_currdescnum;
361 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
362 ulong desc_start = (ulong)desc_p;
363 ulong desc_end = desc_start +
364 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
365 ulong data_start = desc_p->dmamac_addr;
366 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
367 /*
368 * Strictly we only need to invalidate the "txrx_status" field
369 * for the following check, but on some platforms we cannot
370 * invalidate only 4 bytes, so we flush the entire descriptor,
371 * which is 16 bytes in total. This is safe because the
372 * individual descriptors in the array are each aligned to
373 * ARCH_DMA_MINALIGN and padded appropriately.
374 */
375 invalidate_dcache_range(desc_start, desc_end);
376
377 /* Check if the descriptor is owned by CPU */
378 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
379 printf("CPU not owner of tx frame\n");
380 return -EPERM;
381 }
382
383 memcpy((void *)data_start, packet, length);
384 if (length < ETH_ZLEN) {
385 memset(&((char *)data_start)[length], 0, ETH_ZLEN - length);
386 length = ETH_ZLEN;
387 }
388
389 /* Flush data to be sent */
390 flush_dcache_range(data_start, data_end);
391
392 #if defined(CONFIG_DW_ALTDESCRIPTOR)
393 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
394 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
395 ((length << DESC_TXCTRL_SIZE1SHFT) &
396 DESC_TXCTRL_SIZE1MASK);
397
398 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
399 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
400 #else
401 desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
402 ((length << DESC_TXCTRL_SIZE1SHFT) &
403 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
404 DESC_TXCTRL_TXFIRST;
405
406 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
407 #endif
408
409 /* Flush modified buffer descriptor */
410 flush_dcache_range(desc_start, desc_end);
411
412 /* Test the wrap-around condition. */
413 if (++desc_num >= CONFIG_TX_DESCR_NUM)
414 desc_num = 0;
415
416 priv->tx_currdescnum = desc_num;
417
418 /* Start the transmission */
419 writel(POLL_DATA, &dma_p->txpolldemand);
420
421 return 0;
422 }
423
_dw_eth_recv(struct dw_eth_dev * priv,uchar ** packetp)424 static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
425 {
426 u32 status, desc_num = priv->rx_currdescnum;
427 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
428 int length = -EAGAIN;
429 ulong desc_start = (ulong)desc_p;
430 ulong desc_end = desc_start +
431 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
432 ulong data_start = desc_p->dmamac_addr;
433 ulong data_end;
434
435 /* Invalidate entire buffer descriptor */
436 invalidate_dcache_range(desc_start, desc_end);
437
438 status = desc_p->txrx_status;
439
440 /* Check if the owner is the CPU */
441 if (!(status & DESC_RXSTS_OWNBYDMA)) {
442
443 length = (status & DESC_RXSTS_FRMLENMSK) >>
444 DESC_RXSTS_FRMLENSHFT;
445
446 /* Invalidate received data */
447 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
448 invalidate_dcache_range(data_start, data_end);
449 *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
450 }
451
452 return length;
453 }
454
_dw_free_pkt(struct dw_eth_dev * priv)455 static int _dw_free_pkt(struct dw_eth_dev *priv)
456 {
457 u32 desc_num = priv->rx_currdescnum;
458 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
459 ulong desc_start = (ulong)desc_p;
460 ulong desc_end = desc_start +
461 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
462
463 /*
464 * Make the current descriptor valid again and go to
465 * the next one
466 */
467 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
468
469 /* Flush only status field - others weren't changed */
470 flush_dcache_range(desc_start, desc_end);
471
472 /* Test the wrap-around condition. */
473 if (++desc_num >= CONFIG_RX_DESCR_NUM)
474 desc_num = 0;
475 priv->rx_currdescnum = desc_num;
476
477 return 0;
478 }
479
dw_phy_init(struct dw_eth_dev * priv,void * dev)480 static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
481 {
482 struct phy_device *phydev;
483 int mask = 0xffffffff, ret;
484
485 #ifdef CONFIG_PHY_ADDR
486 mask = 1 << CONFIG_PHY_ADDR;
487 #endif
488
489 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
490 if (!phydev)
491 return -ENODEV;
492
493 phy_connect_dev(phydev, dev);
494
495 phydev->supported &= PHY_GBIT_FEATURES;
496 if (priv->max_speed) {
497 ret = phy_set_supported(phydev, priv->max_speed);
498 if (ret)
499 return ret;
500 }
501 phydev->advertising = phydev->supported;
502
503 priv->phydev = phydev;
504 phy_config(phydev);
505
506 return 0;
507 }
508
509 #ifndef CONFIG_DM_ETH
dw_eth_init(struct eth_device * dev,bd_t * bis)510 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
511 {
512 int ret;
513
514 ret = designware_eth_init(dev->priv, dev->enetaddr);
515 if (!ret)
516 ret = designware_eth_enable(dev->priv);
517
518 return ret;
519 }
520
dw_eth_send(struct eth_device * dev,void * packet,int length)521 static int dw_eth_send(struct eth_device *dev, void *packet, int length)
522 {
523 return _dw_eth_send(dev->priv, packet, length);
524 }
525
dw_eth_recv(struct eth_device * dev)526 static int dw_eth_recv(struct eth_device *dev)
527 {
528 uchar *packet;
529 int length;
530
531 length = _dw_eth_recv(dev->priv, &packet);
532 if (length == -EAGAIN)
533 return 0;
534 net_process_received_packet(packet, length);
535
536 _dw_free_pkt(dev->priv);
537
538 return 0;
539 }
540
dw_eth_halt(struct eth_device * dev)541 static void dw_eth_halt(struct eth_device *dev)
542 {
543 return _dw_eth_halt(dev->priv);
544 }
545
dw_write_hwaddr(struct eth_device * dev)546 static int dw_write_hwaddr(struct eth_device *dev)
547 {
548 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
549 }
550
designware_initialize(ulong base_addr,u32 interface)551 int designware_initialize(ulong base_addr, u32 interface)
552 {
553 struct eth_device *dev;
554 struct dw_eth_dev *priv;
555
556 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
557 if (!dev)
558 return -ENOMEM;
559
560 /*
561 * Since the priv structure contains the descriptors which need a strict
562 * buswidth alignment, memalign is used to allocate memory
563 */
564 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
565 sizeof(struct dw_eth_dev));
566 if (!priv) {
567 free(dev);
568 return -ENOMEM;
569 }
570
571 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
572 printf("designware: buffers are outside DMA memory\n");
573 return -EINVAL;
574 }
575
576 memset(dev, 0, sizeof(struct eth_device));
577 memset(priv, 0, sizeof(struct dw_eth_dev));
578
579 sprintf(dev->name, "dwmac.%lx", base_addr);
580 dev->iobase = (int)base_addr;
581 dev->priv = priv;
582
583 priv->dev = dev;
584 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
585 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
586 DW_DMA_BASE_OFFSET);
587
588 dev->init = dw_eth_init;
589 dev->send = dw_eth_send;
590 dev->recv = dw_eth_recv;
591 dev->halt = dw_eth_halt;
592 dev->write_hwaddr = dw_write_hwaddr;
593
594 eth_register(dev);
595
596 priv->interface = interface;
597
598 dw_mdio_init(dev->name, priv->mac_regs_p);
599 priv->bus = miiphy_get_dev_by_name(dev->name);
600
601 return dw_phy_init(priv, dev);
602 }
603 #endif
604
605 #ifdef CONFIG_DM_ETH
designware_eth_start(struct udevice * dev)606 static int designware_eth_start(struct udevice *dev)
607 {
608 struct eth_pdata *pdata = dev_get_platdata(dev);
609 struct dw_eth_dev *priv = dev_get_priv(dev);
610 int ret;
611
612 ret = designware_eth_init(priv, pdata->enetaddr);
613 if (ret)
614 return ret;
615 ret = designware_eth_enable(priv);
616 if (ret)
617 return ret;
618
619 return 0;
620 }
621
designware_eth_send(struct udevice * dev,void * packet,int length)622 int designware_eth_send(struct udevice *dev, void *packet, int length)
623 {
624 struct dw_eth_dev *priv = dev_get_priv(dev);
625
626 return _dw_eth_send(priv, packet, length);
627 }
628
designware_eth_recv(struct udevice * dev,int flags,uchar ** packetp)629 int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
630 {
631 struct dw_eth_dev *priv = dev_get_priv(dev);
632
633 return _dw_eth_recv(priv, packetp);
634 }
635
designware_eth_free_pkt(struct udevice * dev,uchar * packet,int length)636 int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
637 {
638 struct dw_eth_dev *priv = dev_get_priv(dev);
639
640 return _dw_free_pkt(priv);
641 }
642
designware_eth_stop(struct udevice * dev)643 void designware_eth_stop(struct udevice *dev)
644 {
645 struct dw_eth_dev *priv = dev_get_priv(dev);
646
647 return _dw_eth_halt(priv);
648 }
649
designware_eth_write_hwaddr(struct udevice * dev)650 int designware_eth_write_hwaddr(struct udevice *dev)
651 {
652 struct eth_pdata *pdata = dev_get_platdata(dev);
653 struct dw_eth_dev *priv = dev_get_priv(dev);
654
655 return _dw_write_hwaddr(priv, pdata->enetaddr);
656 }
657
designware_eth_bind(struct udevice * dev)658 static int designware_eth_bind(struct udevice *dev)
659 {
660 #ifdef CONFIG_DM_PCI
661 static int num_cards;
662 char name[20];
663
664 /* Create a unique device name for PCI type devices */
665 if (device_is_on_pci_bus(dev)) {
666 sprintf(name, "eth_designware#%u", num_cards++);
667 device_set_name(dev, name);
668 }
669 #endif
670
671 return 0;
672 }
673
designware_eth_probe(struct udevice * dev)674 int designware_eth_probe(struct udevice *dev)
675 {
676 struct eth_pdata *pdata = dev_get_platdata(dev);
677 struct dw_eth_dev *priv = dev_get_priv(dev);
678 u32 iobase = pdata->iobase;
679 ulong ioaddr;
680 int ret;
681 struct reset_ctl_bulk reset_bulk;
682 #ifdef CONFIG_CLK
683 int i, err, clock_nb;
684
685 priv->clock_count = 0;
686 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
687 if (clock_nb > 0) {
688 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
689 GFP_KERNEL);
690 if (!priv->clocks)
691 return -ENOMEM;
692
693 for (i = 0; i < clock_nb; i++) {
694 err = clk_get_by_index(dev, i, &priv->clocks[i]);
695 if (err < 0)
696 break;
697
698 err = clk_enable(&priv->clocks[i]);
699 if (err && err != -ENOSYS && err != -ENOTSUPP) {
700 pr_err("failed to enable clock %d\n", i);
701 clk_free(&priv->clocks[i]);
702 goto clk_err;
703 }
704 priv->clock_count++;
705 }
706 } else if (clock_nb != -ENOENT) {
707 pr_err("failed to get clock phandle(%d)\n", clock_nb);
708 return clock_nb;
709 }
710 #endif
711
712 #if defined(CONFIG_DM_REGULATOR)
713 struct udevice *phy_supply;
714
715 ret = device_get_supply_regulator(dev, "phy-supply",
716 &phy_supply);
717 if (ret) {
718 debug("%s: No phy supply\n", dev->name);
719 } else {
720 ret = regulator_set_enable(phy_supply, true);
721 if (ret) {
722 puts("Error enabling phy supply\n");
723 return ret;
724 }
725 }
726 #endif
727
728 ret = reset_get_bulk(dev, &reset_bulk);
729 if (ret)
730 dev_warn(dev, "Can't get reset: %d\n", ret);
731 else
732 reset_deassert_bulk(&reset_bulk);
733
734 #ifdef CONFIG_DM_PCI
735 /*
736 * If we are on PCI bus, either directly attached to a PCI root port,
737 * or via a PCI bridge, fill in platdata before we probe the hardware.
738 */
739 if (device_is_on_pci_bus(dev)) {
740 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
741 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
742 iobase = dm_pci_mem_to_phys(dev, iobase);
743
744 pdata->iobase = iobase;
745 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
746 }
747 #endif
748
749 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
750 ioaddr = iobase;
751 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
752 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
753 priv->interface = pdata->phy_interface;
754 priv->max_speed = pdata->max_speed;
755
756 dw_mdio_init(dev->name, dev);
757 priv->bus = miiphy_get_dev_by_name(dev->name);
758
759 ret = dw_phy_init(priv, dev);
760 debug("%s, ret=%d\n", __func__, ret);
761
762 return ret;
763
764 #ifdef CONFIG_CLK
765 clk_err:
766 ret = clk_release_all(priv->clocks, priv->clock_count);
767 if (ret)
768 pr_err("failed to disable all clocks\n");
769
770 return err;
771 #endif
772 }
773
designware_eth_remove(struct udevice * dev)774 static int designware_eth_remove(struct udevice *dev)
775 {
776 struct dw_eth_dev *priv = dev_get_priv(dev);
777
778 free(priv->phydev);
779 mdio_unregister(priv->bus);
780 mdio_free(priv->bus);
781
782 #ifdef CONFIG_CLK
783 return clk_release_all(priv->clocks, priv->clock_count);
784 #else
785 return 0;
786 #endif
787 }
788
789 const struct eth_ops designware_eth_ops = {
790 .start = designware_eth_start,
791 .send = designware_eth_send,
792 .recv = designware_eth_recv,
793 .free_pkt = designware_eth_free_pkt,
794 .stop = designware_eth_stop,
795 .write_hwaddr = designware_eth_write_hwaddr,
796 };
797
designware_eth_ofdata_to_platdata(struct udevice * dev)798 int designware_eth_ofdata_to_platdata(struct udevice *dev)
799 {
800 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
801 #ifdef CONFIG_DM_GPIO
802 struct dw_eth_dev *priv = dev_get_priv(dev);
803 #endif
804 struct eth_pdata *pdata = &dw_pdata->eth_pdata;
805 const char *phy_mode;
806 #ifdef CONFIG_DM_GPIO
807 int reset_flags = GPIOD_IS_OUT;
808 #endif
809 int ret = 0;
810
811 pdata->iobase = dev_read_addr(dev);
812 pdata->phy_interface = -1;
813 phy_mode = dev_read_string(dev, "phy-mode");
814 if (phy_mode)
815 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
816 if (pdata->phy_interface == -1) {
817 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
818 return -EINVAL;
819 }
820
821 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
822
823 #ifdef CONFIG_DM_GPIO
824 if (dev_read_bool(dev, "snps,reset-active-low"))
825 reset_flags |= GPIOD_ACTIVE_LOW;
826
827 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
828 &priv->reset_gpio, reset_flags);
829 if (ret == 0) {
830 ret = dev_read_u32_array(dev, "snps,reset-delays-us",
831 dw_pdata->reset_delays, 3);
832 } else if (ret == -ENOENT) {
833 ret = 0;
834 }
835 #endif
836
837 return ret;
838 }
839
840 static const struct udevice_id designware_eth_ids[] = {
841 { .compatible = "allwinner,sun7i-a20-gmac" },
842 { .compatible = "altr,socfpga-stmmac" },
843 { .compatible = "amlogic,meson6-dwmac" },
844 { .compatible = "amlogic,meson-gx-dwmac" },
845 { .compatible = "amlogic,meson-gxbb-dwmac" },
846 { .compatible = "amlogic,meson-axg-dwmac" },
847 { .compatible = "st,stm32-dwmac" },
848 { }
849 };
850
851 U_BOOT_DRIVER(eth_designware) = {
852 .name = "eth_designware",
853 .id = UCLASS_ETH,
854 .of_match = designware_eth_ids,
855 .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
856 .bind = designware_eth_bind,
857 .probe = designware_eth_probe,
858 .remove = designware_eth_remove,
859 .ops = &designware_eth_ops,
860 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
861 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
862 .flags = DM_FLAG_ALLOC_PRIV_DMA,
863 };
864
865 static struct pci_device_id supported[] = {
866 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
867 { }
868 };
869
870 U_BOOT_PCI_DEVICE(eth_designware, supported);
871 #endif
872