xref: /openbmc/linux/arch/powerpc/include/asm/cpm2.h (revision c900529f3d9161bfde5cca0754f83b4d3c3e0220)
1  /* SPDX-License-Identifier: GPL-2.0 */
2  /*
3   * Communication Processor Module v2.
4   *
5   * This file contains structures and information for the communication
6   * processor channels found in the dual port RAM or parameter RAM.
7   * All CPM control and status is available through the CPM2 internal
8   * memory map.  See immap_cpm2.h for details.
9   */
10  #ifdef __KERNEL__
11  #ifndef __CPM2__
12  #define __CPM2__
13  
14  #include <asm/immap_cpm2.h>
15  #include <asm/cpm.h>
16  #include <sysdev/fsl_soc.h>
17  
18  /* CPM Command register.
19  */
20  #define CPM_CR_RST	((uint)0x80000000)
21  #define CPM_CR_PAGE	((uint)0x7c000000)
22  #define CPM_CR_SBLOCK	((uint)0x03e00000)
23  #define CPM_CR_FLG	((uint)0x00010000)
24  #define CPM_CR_MCN	((uint)0x00003fc0)
25  #define CPM_CR_OPCODE	((uint)0x0000000f)
26  
27  /* Device sub-block and page codes.
28  */
29  #define CPM_CR_SCC1_SBLOCK	(0x04)
30  #define CPM_CR_SCC2_SBLOCK	(0x05)
31  #define CPM_CR_SCC3_SBLOCK	(0x06)
32  #define CPM_CR_SCC4_SBLOCK	(0x07)
33  #define CPM_CR_SMC1_SBLOCK	(0x08)
34  #define CPM_CR_SMC2_SBLOCK	(0x09)
35  #define CPM_CR_SPI_SBLOCK	(0x0a)
36  #define CPM_CR_I2C_SBLOCK	(0x0b)
37  #define CPM_CR_TIMER_SBLOCK	(0x0f)
38  #define CPM_CR_RAND_SBLOCK	(0x0e)
39  #define CPM_CR_FCC1_SBLOCK	(0x10)
40  #define CPM_CR_FCC2_SBLOCK	(0x11)
41  #define CPM_CR_FCC3_SBLOCK	(0x12)
42  #define CPM_CR_IDMA1_SBLOCK	(0x14)
43  #define CPM_CR_IDMA2_SBLOCK	(0x15)
44  #define CPM_CR_IDMA3_SBLOCK	(0x16)
45  #define CPM_CR_IDMA4_SBLOCK	(0x17)
46  #define CPM_CR_MCC1_SBLOCK	(0x1c)
47  
48  #define CPM_CR_FCC_SBLOCK(x)	(x + 0x10)
49  
50  #define CPM_CR_SCC1_PAGE	(0x00)
51  #define CPM_CR_SCC2_PAGE	(0x01)
52  #define CPM_CR_SCC3_PAGE	(0x02)
53  #define CPM_CR_SCC4_PAGE	(0x03)
54  #define CPM_CR_SMC1_PAGE	(0x07)
55  #define CPM_CR_SMC2_PAGE	(0x08)
56  #define CPM_CR_SPI_PAGE		(0x09)
57  #define CPM_CR_I2C_PAGE		(0x0a)
58  #define CPM_CR_TIMER_PAGE	(0x0a)
59  #define CPM_CR_RAND_PAGE	(0x0a)
60  #define CPM_CR_FCC1_PAGE	(0x04)
61  #define CPM_CR_FCC2_PAGE	(0x05)
62  #define CPM_CR_FCC3_PAGE	(0x06)
63  #define CPM_CR_IDMA1_PAGE	(0x07)
64  #define CPM_CR_IDMA2_PAGE	(0x08)
65  #define CPM_CR_IDMA3_PAGE	(0x09)
66  #define CPM_CR_IDMA4_PAGE	(0x0a)
67  #define CPM_CR_MCC1_PAGE	(0x07)
68  #define CPM_CR_MCC2_PAGE	(0x08)
69  
70  #define CPM_CR_FCC_PAGE(x)	(x + 0x04)
71  
72  /* CPM2-specific opcodes (see cpm.h for common opcodes)
73  */
74  #define CPM_CR_START_IDMA	((ushort)0x0009)
75  
76  #define mk_cr_cmd(PG, SBC, MCN, OP) \
77  	((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
78  
79  /* The number of pages of host memory we allocate for CPM.  This is
80   * done early in kernel initialization to get physically contiguous
81   * pages.
82   */
83  #define NUM_CPM_HOST_PAGES	2
84  
85  /* Export the base address of the communication processor registers
86   * and dual port ram.
87   */
88  extern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */
89  
90  #define cpm_dpalloc cpm_muram_alloc
91  #define cpm_dpfree cpm_muram_free
92  #define cpm_dpram_addr cpm_muram_addr
93  
94  extern void cpm2_reset(void);
95  
96  /* Baud rate generators.
97  */
98  #define CPM_BRG_RST		((uint)0x00020000)
99  #define CPM_BRG_EN		((uint)0x00010000)
100  #define CPM_BRG_EXTC_INT	((uint)0x00000000)
101  #define CPM_BRG_EXTC_CLK3_9	((uint)0x00004000)
102  #define CPM_BRG_EXTC_CLK5_15	((uint)0x00008000)
103  #define CPM_BRG_ATB		((uint)0x00002000)
104  #define CPM_BRG_CD_MASK		((uint)0x00001ffe)
105  #define CPM_BRG_DIV16		((uint)0x00000001)
106  
107  #define CPM2_BRG_INT_CLK	(get_brgfreq())
108  #define CPM2_BRG_UART_CLK	(CPM2_BRG_INT_CLK/16)
109  
110  extern void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src);
111  
112  /* This function is used by UARTS, or anything else that uses a 16x
113   * oversampled clock.
114   */
cpm_setbrg(uint brg,uint rate)115  static inline void cpm_setbrg(uint brg, uint rate)
116  {
117  	__cpm2_setbrg(brg, rate, CPM2_BRG_UART_CLK, 0, CPM_BRG_EXTC_INT);
118  }
119  
120  /* This function is used to set high speed synchronous baud rate
121   * clocks.
122   */
cpm2_fastbrg(uint brg,uint rate,int div16)123  static inline void cpm2_fastbrg(uint brg, uint rate, int div16)
124  {
125  	__cpm2_setbrg(brg, rate, CPM2_BRG_INT_CLK, div16, CPM_BRG_EXTC_INT);
126  }
127  
128  /* Parameter RAM offsets from the base.
129  */
130  #define PROFF_SCC1		((uint)0x8000)
131  #define PROFF_SCC2		((uint)0x8100)
132  #define PROFF_SCC3		((uint)0x8200)
133  #define PROFF_SCC4		((uint)0x8300)
134  #define PROFF_FCC1		((uint)0x8400)
135  #define PROFF_FCC2		((uint)0x8500)
136  #define PROFF_FCC3		((uint)0x8600)
137  #define PROFF_MCC1		((uint)0x8700)
138  #define PROFF_SMC1_BASE		((uint)0x87fc)
139  #define PROFF_IDMA1_BASE	((uint)0x87fe)
140  #define PROFF_MCC2		((uint)0x8800)
141  #define PROFF_SMC2_BASE		((uint)0x88fc)
142  #define PROFF_IDMA2_BASE	((uint)0x88fe)
143  #define PROFF_SPI_BASE		((uint)0x89fc)
144  #define PROFF_IDMA3_BASE	((uint)0x89fe)
145  #define PROFF_TIMERS		((uint)0x8ae0)
146  #define PROFF_REVNUM		((uint)0x8af0)
147  #define PROFF_RAND		((uint)0x8af8)
148  #define PROFF_I2C_BASE		((uint)0x8afc)
149  #define PROFF_IDMA4_BASE	((uint)0x8afe)
150  
151  #define PROFF_SCC_SIZE		((uint)0x100)
152  #define PROFF_FCC_SIZE		((uint)0x100)
153  #define PROFF_SMC_SIZE		((uint)64)
154  
155  /* The SMCs are relocated to any of the first eight DPRAM pages.
156   * We will fix these at the first locations of DPRAM, until we
157   * get some microcode patches :-).
158   * The parameter ram space for the SMCs is fifty-some bytes, and
159   * they are required to start on a 64 byte boundary.
160   */
161  #define PROFF_SMC1	(0)
162  #define PROFF_SMC2	(64)
163  
164  
165  /* Define enough so I can at least use the serial port as a UART.
166   */
167  typedef struct smc_uart {
168  	ushort	smc_rbase;	/* Rx Buffer descriptor base address */
169  	ushort	smc_tbase;	/* Tx Buffer descriptor base address */
170  	u_char	smc_rfcr;	/* Rx function code */
171  	u_char	smc_tfcr;	/* Tx function code */
172  	ushort	smc_mrblr;	/* Max receive buffer length */
173  	uint	smc_rstate;	/* Internal */
174  	uint	smc_idp;	/* Internal */
175  	ushort	smc_rbptr;	/* Internal */
176  	ushort	smc_ibc;	/* Internal */
177  	uint	smc_rxtmp;	/* Internal */
178  	uint	smc_tstate;	/* Internal */
179  	uint	smc_tdp;	/* Internal */
180  	ushort	smc_tbptr;	/* Internal */
181  	ushort	smc_tbc;	/* Internal */
182  	uint	smc_txtmp;	/* Internal */
183  	ushort	smc_maxidl;	/* Maximum idle characters */
184  	ushort	smc_tmpidl;	/* Temporary idle counter */
185  	ushort	smc_brklen;	/* Last received break length */
186  	ushort	smc_brkec;	/* rcv'd break condition counter */
187  	ushort	smc_brkcr;	/* xmt break count register */
188  	ushort	smc_rmask;	/* Temporary bit mask */
189  	uint	smc_stmp;	/* SDMA Temp */
190  } smc_uart_t;
191  
192  /* SMC uart mode register (Internal memory map).
193  */
194  #define SMCMR_REN	((ushort)0x0001)
195  #define SMCMR_TEN	((ushort)0x0002)
196  #define SMCMR_DM	((ushort)0x000c)
197  #define SMCMR_SM_GCI	((ushort)0x0000)
198  #define SMCMR_SM_UART	((ushort)0x0020)
199  #define SMCMR_SM_TRANS	((ushort)0x0030)
200  #define SMCMR_SM_MASK	((ushort)0x0030)
201  #define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */
202  #define SMCMR_REVD	SMCMR_PM_EVEN
203  #define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */
204  #define SMCMR_BS	SMCMR_PEN
205  #define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */
206  #define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */
207  #define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)
208  
209  /* SMC Event and Mask register.
210  */
211  #define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
212  #define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
213  #define SMCM_TXE	((unsigned char)0x10)
214  #define SMCM_BSY	((unsigned char)0x04)
215  #define SMCM_TX		((unsigned char)0x02)
216  #define SMCM_RX		((unsigned char)0x01)
217  
218  /* SCCs.
219  */
220  #define SCC_GSMRH_IRP		((uint)0x00040000)
221  #define SCC_GSMRH_GDE		((uint)0x00010000)
222  #define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
223  #define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
224  #define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
225  #define SCC_GSMRH_REVD		((uint)0x00002000)
226  #define SCC_GSMRH_TRX		((uint)0x00001000)
227  #define SCC_GSMRH_TTX		((uint)0x00000800)
228  #define SCC_GSMRH_CDP		((uint)0x00000400)
229  #define SCC_GSMRH_CTSP		((uint)0x00000200)
230  #define SCC_GSMRH_CDS		((uint)0x00000100)
231  #define SCC_GSMRH_CTSS		((uint)0x00000080)
232  #define SCC_GSMRH_TFL		((uint)0x00000040)
233  #define SCC_GSMRH_RFW		((uint)0x00000020)
234  #define SCC_GSMRH_TXSY		((uint)0x00000010)
235  #define SCC_GSMRH_SYNL16	((uint)0x0000000c)
236  #define SCC_GSMRH_SYNL8		((uint)0x00000008)
237  #define SCC_GSMRH_SYNL4		((uint)0x00000004)
238  #define SCC_GSMRH_RTSM		((uint)0x00000002)
239  #define SCC_GSMRH_RSYN		((uint)0x00000001)
240  
241  #define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
242  #define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
243  #define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
244  #define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
245  #define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
246  #define SCC_GSMRL_TCI		((uint)0x10000000)
247  #define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
248  #define SCC_GSMRL_TSNC_4	((uint)0x08000000)
249  #define SCC_GSMRL_TSNC_14	((uint)0x04000000)
250  #define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
251  #define SCC_GSMRL_RINV		((uint)0x02000000)
252  #define SCC_GSMRL_TINV		((uint)0x01000000)
253  #define SCC_GSMRL_TPL_128	((uint)0x00c00000)
254  #define SCC_GSMRL_TPL_64	((uint)0x00a00000)
255  #define SCC_GSMRL_TPL_48	((uint)0x00800000)
256  #define SCC_GSMRL_TPL_32	((uint)0x00600000)
257  #define SCC_GSMRL_TPL_16	((uint)0x00400000)
258  #define SCC_GSMRL_TPL_8		((uint)0x00200000)
259  #define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
260  #define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
261  #define SCC_GSMRL_TPP_01	((uint)0x00100000)
262  #define SCC_GSMRL_TPP_10	((uint)0x00080000)
263  #define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
264  #define SCC_GSMRL_TEND		((uint)0x00040000)
265  #define SCC_GSMRL_TDCR_32	((uint)0x00030000)
266  #define SCC_GSMRL_TDCR_16	((uint)0x00020000)
267  #define SCC_GSMRL_TDCR_8	((uint)0x00010000)
268  #define SCC_GSMRL_TDCR_1	((uint)0x00000000)
269  #define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
270  #define SCC_GSMRL_RDCR_16	((uint)0x00008000)
271  #define SCC_GSMRL_RDCR_8	((uint)0x00004000)
272  #define SCC_GSMRL_RDCR_1	((uint)0x00000000)
273  #define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
274  #define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
275  #define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
276  #define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
277  #define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
278  #define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
279  #define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
280  #define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
281  #define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
282  #define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
283  #define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
284  #define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
285  #define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
286  #define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
287  #define SCC_GSMRL_ENR		((uint)0x00000020)
288  #define SCC_GSMRL_ENT		((uint)0x00000010)
289  #define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
290  #define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
291  #define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
292  #define SCC_GSMRL_MODE_V14	((uint)0x00000007)
293  #define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
294  #define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
295  #define SCC_GSMRL_MODE_UART	((uint)0x00000004)
296  #define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
297  #define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
298  #define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
299  
300  #define SCC_TODR_TOD		((ushort)0x8000)
301  
302  /* SCC Event and Mask register.
303  */
304  #define SCCM_TXE	((unsigned char)0x10)
305  #define SCCM_BSY	((unsigned char)0x04)
306  #define SCCM_TX		((unsigned char)0x02)
307  #define SCCM_RX		((unsigned char)0x01)
308  
309  typedef struct scc_param {
310  	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
311  	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
312  	u_char	scc_rfcr;	/* Rx function code */
313  	u_char	scc_tfcr;	/* Tx function code */
314  	ushort	scc_mrblr;	/* Max receive buffer length */
315  	uint	scc_rstate;	/* Internal */
316  	uint	scc_idp;	/* Internal */
317  	ushort	scc_rbptr;	/* Internal */
318  	ushort	scc_ibc;	/* Internal */
319  	uint	scc_rxtmp;	/* Internal */
320  	uint	scc_tstate;	/* Internal */
321  	uint	scc_tdp;	/* Internal */
322  	ushort	scc_tbptr;	/* Internal */
323  	ushort	scc_tbc;	/* Internal */
324  	uint	scc_txtmp;	/* Internal */
325  	uint	scc_rcrc;	/* Internal */
326  	uint	scc_tcrc;	/* Internal */
327  } sccp_t;
328  
329  /* Function code bits.
330  */
331  #define SCC_EB	((u_char) 0x10)	/* Set big endian byte order */
332  #define SCC_GBL	((u_char) 0x20) /* Snooping enabled */
333  
334  /* CPM Ethernet through SCC1.
335   */
336  typedef struct scc_enet {
337  	sccp_t	sen_genscc;
338  	uint	sen_cpres;	/* Preset CRC */
339  	uint	sen_cmask;	/* Constant mask for CRC */
340  	uint	sen_crcec;	/* CRC Error counter */
341  	uint	sen_alec;	/* alignment error counter */
342  	uint	sen_disfc;	/* discard frame counter */
343  	ushort	sen_pads;	/* Tx short frame pad character */
344  	ushort	sen_retlim;	/* Retry limit threshold */
345  	ushort	sen_retcnt;	/* Retry limit counter */
346  	ushort	sen_maxflr;	/* maximum frame length register */
347  	ushort	sen_minflr;	/* minimum frame length register */
348  	ushort	sen_maxd1;	/* maximum DMA1 length */
349  	ushort	sen_maxd2;	/* maximum DMA2 length */
350  	ushort	sen_maxd;	/* Rx max DMA */
351  	ushort	sen_dmacnt;	/* Rx DMA counter */
352  	ushort	sen_maxb;	/* Max BD byte count */
353  	ushort	sen_gaddr1;	/* Group address filter */
354  	ushort	sen_gaddr2;
355  	ushort	sen_gaddr3;
356  	ushort	sen_gaddr4;
357  	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
358  	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
359  	uint	sen_tbuf0rba;	/* Internal */
360  	uint	sen_tbuf0crc;	/* Internal */
361  	ushort	sen_tbuf0bcnt;	/* Internal */
362  	ushort	sen_paddrh;	/* physical address (MSB) */
363  	ushort	sen_paddrm;
364  	ushort	sen_paddrl;	/* physical address (LSB) */
365  	ushort	sen_pper;	/* persistence */
366  	ushort	sen_rfbdptr;	/* Rx first BD pointer */
367  	ushort	sen_tfbdptr;	/* Tx first BD pointer */
368  	ushort	sen_tlbdptr;	/* Tx last BD pointer */
369  	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
370  	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
371  	uint	sen_tbuf1rba;	/* Internal */
372  	uint	sen_tbuf1crc;	/* Internal */
373  	ushort	sen_tbuf1bcnt;	/* Internal */
374  	ushort	sen_txlen;	/* Tx Frame length counter */
375  	ushort	sen_iaddr1;	/* Individual address filter */
376  	ushort	sen_iaddr2;
377  	ushort	sen_iaddr3;
378  	ushort	sen_iaddr4;
379  	ushort	sen_boffcnt;	/* Backoff counter */
380  
381  	/* NOTE: Some versions of the manual have the following items
382  	 * incorrectly documented.  Below is the proper order.
383  	 */
384  	ushort	sen_taddrh;	/* temp address (MSB) */
385  	ushort	sen_taddrm;
386  	ushort	sen_taddrl;	/* temp address (LSB) */
387  } scc_enet_t;
388  
389  
390  /* SCC Event register as used by Ethernet.
391  */
392  #define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
393  #define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
394  #define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
395  #define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
396  #define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
397  #define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
398  
399  /* SCC Mode Register (PSMR) as used by Ethernet.
400  */
401  #define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
402  #define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
403  #define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
404  #define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
405  #define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
406  #define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
407  #define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
408  #define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
409  #define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
410  #define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
411  #define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
412  #define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
413  #define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
414  
415  /* SCC as UART
416  */
417  typedef struct scc_uart {
418  	sccp_t	scc_genscc;
419  	uint	scc_res1;	/* Reserved */
420  	uint	scc_res2;	/* Reserved */
421  	ushort	scc_maxidl;	/* Maximum idle chars */
422  	ushort	scc_idlc;	/* temp idle counter */
423  	ushort	scc_brkcr;	/* Break count register */
424  	ushort	scc_parec;	/* receive parity error counter */
425  	ushort	scc_frmec;	/* receive framing error counter */
426  	ushort	scc_nosec;	/* receive noise counter */
427  	ushort	scc_brkec;	/* receive break condition counter */
428  	ushort	scc_brkln;	/* last received break length */
429  	ushort	scc_uaddr1;	/* UART address character 1 */
430  	ushort	scc_uaddr2;	/* UART address character 2 */
431  	ushort	scc_rtemp;	/* Temp storage */
432  	ushort	scc_toseq;	/* Transmit out of sequence char */
433  	ushort	scc_char1;	/* control character 1 */
434  	ushort	scc_char2;	/* control character 2 */
435  	ushort	scc_char3;	/* control character 3 */
436  	ushort	scc_char4;	/* control character 4 */
437  	ushort	scc_char5;	/* control character 5 */
438  	ushort	scc_char6;	/* control character 6 */
439  	ushort	scc_char7;	/* control character 7 */
440  	ushort	scc_char8;	/* control character 8 */
441  	ushort	scc_rccm;	/* receive control character mask */
442  	ushort	scc_rccr;	/* receive control character register */
443  	ushort	scc_rlbc;	/* receive last break character */
444  } scc_uart_t;
445  
446  /* SCC Event and Mask registers when it is used as a UART.
447  */
448  #define UART_SCCM_GLR		((ushort)0x1000)
449  #define UART_SCCM_GLT		((ushort)0x0800)
450  #define UART_SCCM_AB		((ushort)0x0200)
451  #define UART_SCCM_IDL		((ushort)0x0100)
452  #define UART_SCCM_GRA		((ushort)0x0080)
453  #define UART_SCCM_BRKE		((ushort)0x0040)
454  #define UART_SCCM_BRKS		((ushort)0x0020)
455  #define UART_SCCM_CCR		((ushort)0x0008)
456  #define UART_SCCM_BSY		((ushort)0x0004)
457  #define UART_SCCM_TX		((ushort)0x0002)
458  #define UART_SCCM_RX		((ushort)0x0001)
459  
460  /* The SCC PSMR when used as a UART.
461  */
462  #define SCU_PSMR_FLC		((ushort)0x8000)
463  #define SCU_PSMR_SL		((ushort)0x4000)
464  #define SCU_PSMR_CL		((ushort)0x3000)
465  #define SCU_PSMR_UM		((ushort)0x0c00)
466  #define SCU_PSMR_FRZ		((ushort)0x0200)
467  #define SCU_PSMR_RZS		((ushort)0x0100)
468  #define SCU_PSMR_SYN		((ushort)0x0080)
469  #define SCU_PSMR_DRT		((ushort)0x0040)
470  #define SCU_PSMR_PEN		((ushort)0x0010)
471  #define SCU_PSMR_RPM		((ushort)0x000c)
472  #define SCU_PSMR_REVP		((ushort)0x0008)
473  #define SCU_PSMR_TPM		((ushort)0x0003)
474  #define SCU_PSMR_TEVP		((ushort)0x0002)
475  
476  /* CPM Transparent mode SCC.
477   */
478  typedef struct scc_trans {
479  	sccp_t	st_genscc;
480  	uint	st_cpres;	/* Preset CRC */
481  	uint	st_cmask;	/* Constant mask for CRC */
482  } scc_trans_t;
483  
484  /* How about some FCCs.....
485  */
486  #define FCC_GFMR_DIAG_NORM	((uint)0x00000000)
487  #define FCC_GFMR_DIAG_LE	((uint)0x40000000)
488  #define FCC_GFMR_DIAG_AE	((uint)0x80000000)
489  #define FCC_GFMR_DIAG_ALE	((uint)0xc0000000)
490  #define FCC_GFMR_TCI		((uint)0x20000000)
491  #define FCC_GFMR_TRX		((uint)0x10000000)
492  #define FCC_GFMR_TTX		((uint)0x08000000)
493  #define FCC_GFMR_CDP		((uint)0x04000000)
494  #define FCC_GFMR_CTSP		((uint)0x02000000)
495  #define FCC_GFMR_CDS		((uint)0x01000000)
496  #define FCC_GFMR_CTSS		((uint)0x00800000)
497  #define FCC_GFMR_SYNL_NONE	((uint)0x00000000)
498  #define FCC_GFMR_SYNL_AUTO	((uint)0x00004000)
499  #define FCC_GFMR_SYNL_8		((uint)0x00008000)
500  #define FCC_GFMR_SYNL_16	((uint)0x0000c000)
501  #define FCC_GFMR_RTSM		((uint)0x00002000)
502  #define FCC_GFMR_RENC_NRZ	((uint)0x00000000)
503  #define FCC_GFMR_RENC_NRZI	((uint)0x00000800)
504  #define FCC_GFMR_REVD		((uint)0x00000400)
505  #define FCC_GFMR_TENC_NRZ	((uint)0x00000000)
506  #define FCC_GFMR_TENC_NRZI	((uint)0x00000100)
507  #define FCC_GFMR_TCRC_16	((uint)0x00000000)
508  #define FCC_GFMR_TCRC_32	((uint)0x00000080)
509  #define FCC_GFMR_ENR		((uint)0x00000020)
510  #define FCC_GFMR_ENT		((uint)0x00000010)
511  #define FCC_GFMR_MODE_ENET	((uint)0x0000000c)
512  #define FCC_GFMR_MODE_ATM	((uint)0x0000000a)
513  #define FCC_GFMR_MODE_HDLC	((uint)0x00000000)
514  
515  /* Generic FCC parameter ram.
516  */
517  typedef struct fcc_param {
518  	ushort	fcc_riptr;	/* Rx Internal temp pointer */
519  	ushort	fcc_tiptr;	/* Tx Internal temp pointer */
520  	ushort	fcc_res1;
521  	ushort	fcc_mrblr;	/* Max receive buffer length, mod 32 bytes */
522  	uint	fcc_rstate;	/* Upper byte is Func code, must be set */
523  	uint	fcc_rbase;	/* Receive BD base */
524  	ushort	fcc_rbdstat;	/* RxBD status */
525  	ushort	fcc_rbdlen;	/* RxBD down counter */
526  	uint	fcc_rdptr;	/* RxBD internal data pointer */
527  	uint	fcc_tstate;	/* Upper byte is Func code, must be set */
528  	uint	fcc_tbase;	/* Transmit BD base */
529  	ushort	fcc_tbdstat;	/* TxBD status */
530  	ushort	fcc_tbdlen;	/* TxBD down counter */
531  	uint	fcc_tdptr;	/* TxBD internal data pointer */
532  	uint	fcc_rbptr;	/* Rx BD Internal buf pointer */
533  	uint	fcc_tbptr;	/* Tx BD Internal buf pointer */
534  	uint	fcc_rcrc;	/* Rx temp CRC */
535  	uint	fcc_res2;
536  	uint	fcc_tcrc;	/* Tx temp CRC */
537  } fccp_t;
538  
539  
540  /* Ethernet controller through FCC.
541  */
542  typedef struct fcc_enet {
543  	fccp_t	fen_genfcc;
544  	uint	fen_statbuf;	/* Internal status buffer */
545  	uint	fen_camptr;	/* CAM address */
546  	uint	fen_cmask;	/* Constant mask for CRC */
547  	uint	fen_cpres;	/* Preset CRC */
548  	uint	fen_crcec;	/* CRC Error counter */
549  	uint	fen_alec;	/* alignment error counter */
550  	uint	fen_disfc;	/* discard frame counter */
551  	ushort	fen_retlim;	/* Retry limit */
552  	ushort	fen_retcnt;	/* Retry counter */
553  	ushort	fen_pper;	/* Persistence */
554  	ushort	fen_boffcnt;	/* backoff counter */
555  	uint	fen_gaddrh;	/* Group address filter, high 32-bits */
556  	uint	fen_gaddrl;	/* Group address filter, low 32-bits */
557  	ushort	fen_tfcstat;	/* out of sequence TxBD */
558  	ushort	fen_tfclen;
559  	uint	fen_tfcptr;
560  	ushort	fen_mflr;	/* Maximum frame length (1518) */
561  	ushort	fen_paddrh;	/* MAC address */
562  	ushort	fen_paddrm;
563  	ushort	fen_paddrl;
564  	ushort	fen_ibdcount;	/* Internal BD counter */
565  	ushort	fen_ibdstart;	/* Internal BD start pointer */
566  	ushort	fen_ibdend;	/* Internal BD end pointer */
567  	ushort	fen_txlen;	/* Internal Tx frame length counter */
568  	uint	fen_ibdbase[8]; /* Internal use */
569  	uint	fen_iaddrh;	/* Individual address filter */
570  	uint	fen_iaddrl;
571  	ushort	fen_minflr;	/* Minimum frame length (64) */
572  	ushort	fen_taddrh;	/* Filter transfer MAC address */
573  	ushort	fen_taddrm;
574  	ushort	fen_taddrl;
575  	ushort	fen_padptr;	/* Pointer to pad byte buffer */
576  	ushort	fen_cftype;	/* control frame type */
577  	ushort	fen_cfrange;	/* control frame range */
578  	ushort	fen_maxb;	/* maximum BD count */
579  	ushort	fen_maxd1;	/* Max DMA1 length (1520) */
580  	ushort	fen_maxd2;	/* Max DMA2 length (1520) */
581  	ushort	fen_maxd;	/* internal max DMA count */
582  	ushort	fen_dmacnt;	/* internal DMA counter */
583  	uint	fen_octc;	/* Total octect counter */
584  	uint	fen_colc;	/* Total collision counter */
585  	uint	fen_broc;	/* Total broadcast packet counter */
586  	uint	fen_mulc;	/* Total multicast packet count */
587  	uint	fen_uspc;	/* Total packets < 64 bytes */
588  	uint	fen_frgc;	/* Total packets < 64 bytes with errors */
589  	uint	fen_ospc;	/* Total packets > 1518 */
590  	uint	fen_jbrc;	/* Total packets > 1518 with errors */
591  	uint	fen_p64c;	/* Total packets == 64 bytes */
592  	uint	fen_p65c;	/* Total packets 64 < bytes <= 127 */
593  	uint	fen_p128c;	/* Total packets 127 < bytes <= 255 */
594  	uint	fen_p256c;	/* Total packets 256 < bytes <= 511 */
595  	uint	fen_p512c;	/* Total packets 512 < bytes <= 1023 */
596  	uint	fen_p1024c;	/* Total packets 1024 < bytes <= 1518 */
597  	uint	fen_cambuf;	/* Internal CAM buffer pointer */
598  	ushort	fen_rfthr;	/* Received frames threshold */
599  	ushort	fen_rfcnt;	/* Received frames count */
600  } fcc_enet_t;
601  
602  /* FCC Event/Mask register as used by Ethernet.
603  */
604  #define FCC_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
605  #define FCC_ENET_RXC	((ushort)0x0040)	/* Control Frame Received */
606  #define FCC_ENET_TXC	((ushort)0x0020)	/* Out of seq. Tx sent */
607  #define FCC_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
608  #define FCC_ENET_RXF	((ushort)0x0008)	/* Full frame received */
609  #define FCC_ENET_BSY	((ushort)0x0004)	/* Busy.  Rx Frame dropped */
610  #define FCC_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
611  #define FCC_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
612  
613  /* FCC Mode Register (FPSMR) as used by Ethernet.
614  */
615  #define FCC_PSMR_HBC	((uint)0x80000000)	/* Enable heartbeat */
616  #define FCC_PSMR_FC	((uint)0x40000000)	/* Force Collision */
617  #define FCC_PSMR_SBT	((uint)0x20000000)	/* Stop backoff timer */
618  #define FCC_PSMR_LPB	((uint)0x10000000)	/* Local protect. 1 = FDX */
619  #define FCC_PSMR_LCW	((uint)0x08000000)	/* Late collision select */
620  #define FCC_PSMR_FDE	((uint)0x04000000)	/* Full Duplex Enable */
621  #define FCC_PSMR_MON	((uint)0x02000000)	/* RMON Enable */
622  #define FCC_PSMR_PRO	((uint)0x00400000)	/* Promiscuous Enable */
623  #define FCC_PSMR_FCE	((uint)0x00200000)	/* Flow Control Enable */
624  #define FCC_PSMR_RSH	((uint)0x00100000)	/* Receive Short Frames */
625  #define FCC_PSMR_CAM	((uint)0x00000400)	/* CAM enable */
626  #define FCC_PSMR_BRO	((uint)0x00000200)	/* Broadcast pkt discard */
627  #define FCC_PSMR_ENCRC	((uint)0x00000080)	/* Use 32-bit CRC */
628  
629  /* IIC parameter RAM.
630  */
631  typedef struct iic {
632  	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
633  	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
634  	u_char	iic_rfcr;	/* Rx function code */
635  	u_char	iic_tfcr;	/* Tx function code */
636  	ushort	iic_mrblr;	/* Max receive buffer length */
637  	uint	iic_rstate;	/* Internal */
638  	uint	iic_rdp;	/* Internal */
639  	ushort	iic_rbptr;	/* Internal */
640  	ushort	iic_rbc;	/* Internal */
641  	uint	iic_rxtmp;	/* Internal */
642  	uint	iic_tstate;	/* Internal */
643  	uint	iic_tdp;	/* Internal */
644  	ushort	iic_tbptr;	/* Internal */
645  	ushort	iic_tbc;	/* Internal */
646  	uint	iic_txtmp;	/* Internal */
647  } iic_t;
648  
649  /* IDMA parameter RAM
650  */
651  typedef struct idma {
652  	ushort ibase;		/* IDMA buffer descriptor table base address */
653  	ushort dcm;		/* DMA channel mode */
654  	ushort ibdptr;		/* IDMA current buffer descriptor pointer */
655  	ushort dpr_buf;		/* IDMA transfer buffer base address */
656  	ushort buf_inv;		/* internal buffer inventory */
657  	ushort ss_max;		/* steady-state maximum transfer size */
658  	ushort dpr_in_ptr;	/* write pointer inside the internal buffer */
659  	ushort sts;		/* source transfer size */
660  	ushort dpr_out_ptr;	/* read pointer inside the internal buffer */
661  	ushort seob;		/* source end of burst */
662  	ushort deob;		/* destination end of burst */
663  	ushort dts;		/* destination transfer size */
664  	ushort ret_add;		/* return address when working in ERM=1 mode */
665  	ushort res0;		/* reserved */
666  	uint   bd_cnt;		/* internal byte count */
667  	uint   s_ptr;		/* source internal data pointer */
668  	uint   d_ptr;		/* destination internal data pointer */
669  	uint   istate;		/* internal state */
670  	u_char res1[20];	/* pad to 64-byte length */
671  } idma_t;
672  
673  /* DMA channel mode bit fields
674  */
675  #define IDMA_DCM_FB		((ushort)0x8000) /* fly-by mode */
676  #define IDMA_DCM_LP		((ushort)0x4000) /* low priority */
677  #define IDMA_DCM_TC2		((ushort)0x0400) /* value driven on TC[2] */
678  #define IDMA_DCM_DMA_WRAP_MASK	((ushort)0x01c0) /* mask for DMA wrap */
679  #define IDMA_DCM_DMA_WRAP_64	((ushort)0x0000) /* 64-byte DMA xfer buffer */
680  #define IDMA_DCM_DMA_WRAP_128	((ushort)0x0040) /* 128-byte DMA xfer buffer */
681  #define IDMA_DCM_DMA_WRAP_256	((ushort)0x0080) /* 256-byte DMA xfer buffer */
682  #define IDMA_DCM_DMA_WRAP_512	((ushort)0x00c0) /* 512-byte DMA xfer buffer */
683  #define IDMA_DCM_DMA_WRAP_1024	((ushort)0x0100) /* 1024-byte DMA xfer buffer */
684  #define IDMA_DCM_DMA_WRAP_2048	((ushort)0x0140) /* 2048-byte DMA xfer buffer */
685  #define IDMA_DCM_SINC		((ushort)0x0020) /* source inc addr */
686  #define IDMA_DCM_DINC		((ushort)0x0010) /* destination inc addr */
687  #define IDMA_DCM_ERM		((ushort)0x0008) /* external request mode */
688  #define IDMA_DCM_DT		((ushort)0x0004) /* DONE treatment */
689  #define IDMA_DCM_SD_MASK	((ushort)0x0003) /* mask for SD bit field */
690  #define IDMA_DCM_SD_MEM2MEM	((ushort)0x0000) /* memory-to-memory xfer */
691  #define IDMA_DCM_SD_PER2MEM	((ushort)0x0002) /* peripheral-to-memory xfer */
692  #define IDMA_DCM_SD_MEM2PER	((ushort)0x0001) /* memory-to-peripheral xfer */
693  
694  /* IDMA Buffer Descriptors
695  */
696  typedef struct idma_bd {
697  	uint flags;
698  	uint len;	/* data length */
699  	uint src;	/* source data buffer pointer */
700  	uint dst;	/* destination data buffer pointer */
701  } idma_bd_t;
702  
703  /* IDMA buffer descriptor flag bit fields
704  */
705  #define IDMA_BD_V	((uint)0x80000000)	/* valid */
706  #define IDMA_BD_W	((uint)0x20000000)	/* wrap */
707  #define IDMA_BD_I	((uint)0x10000000)	/* interrupt */
708  #define IDMA_BD_L	((uint)0x08000000)	/* last */
709  #define IDMA_BD_CM	((uint)0x02000000)	/* continuous mode */
710  #define IDMA_BD_SDN	((uint)0x00400000)	/* source done */
711  #define IDMA_BD_DDN	((uint)0x00200000)	/* destination done */
712  #define IDMA_BD_DGBL	((uint)0x00100000)	/* destination global */
713  #define IDMA_BD_DBO_LE	((uint)0x00040000)	/* little-end dest byte order */
714  #define IDMA_BD_DBO_BE	((uint)0x00080000)	/* big-end dest byte order */
715  #define IDMA_BD_DDTB	((uint)0x00010000)	/* destination data bus */
716  #define IDMA_BD_SGBL	((uint)0x00002000)	/* source global */
717  #define IDMA_BD_SBO_LE	((uint)0x00000800)	/* little-end src byte order */
718  #define IDMA_BD_SBO_BE	((uint)0x00001000)	/* big-end src byte order */
719  #define IDMA_BD_SDTB	((uint)0x00000200)	/* source data bus */
720  
721  /* per-channel IDMA registers
722  */
723  typedef struct im_idma {
724  	u_char idsr;			/* IDMAn event status register */
725  	u_char res0[3];
726  	u_char idmr;			/* IDMAn event mask register */
727  	u_char res1[3];
728  } im_idma_t;
729  
730  /* IDMA event register bit fields
731  */
732  #define IDMA_EVENT_SC	((unsigned char)0x08)	/* stop completed */
733  #define IDMA_EVENT_OB	((unsigned char)0x04)	/* out of buffers */
734  #define IDMA_EVENT_EDN	((unsigned char)0x02)	/* external DONE asserted */
735  #define IDMA_EVENT_BC	((unsigned char)0x01)	/* buffer descriptor complete */
736  
737  /* RISC Controller Configuration Register (RCCR) bit fields
738  */
739  #define RCCR_TIME	((uint)0x80000000) /* timer enable */
740  #define RCCR_TIMEP_MASK	((uint)0x3f000000) /* mask for timer period bit field */
741  #define RCCR_DR0M	((uint)0x00800000) /* IDMA0 request mode */
742  #define RCCR_DR1M	((uint)0x00400000) /* IDMA1 request mode */
743  #define RCCR_DR2M	((uint)0x00000080) /* IDMA2 request mode */
744  #define RCCR_DR3M	((uint)0x00000040) /* IDMA3 request mode */
745  #define RCCR_DR0QP_MASK	((uint)0x00300000) /* mask for IDMA0 req priority */
746  #define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
747  #define RCCR_DR0QP_MED	((uint)0x00100000) /* IDMA0 has medium req priority */
748  #define RCCR_DR0QP_LOW	((uint)0x00200000) /* IDMA0 has low req priority */
749  #define RCCR_DR1QP_MASK	((uint)0x00030000) /* mask for IDMA1 req priority */
750  #define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
751  #define RCCR_DR1QP_MED	((uint)0x00010000) /* IDMA1 has medium req priority */
752  #define RCCR_DR1QP_LOW	((uint)0x00020000) /* IDMA1 has low req priority */
753  #define RCCR_DR2QP_MASK	((uint)0x00000030) /* mask for IDMA2 req priority */
754  #define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
755  #define RCCR_DR2QP_MED	((uint)0x00000010) /* IDMA2 has medium req priority */
756  #define RCCR_DR2QP_LOW	((uint)0x00000020) /* IDMA2 has low req priority */
757  #define RCCR_DR3QP_MASK	((uint)0x00000003) /* mask for IDMA3 req priority */
758  #define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
759  #define RCCR_DR3QP_MED	((uint)0x00000001) /* IDMA3 has medium req priority */
760  #define RCCR_DR3QP_LOW	((uint)0x00000002) /* IDMA3 has low req priority */
761  #define RCCR_EIE	((uint)0x00080000) /* external interrupt enable */
762  #define RCCR_SCD	((uint)0x00040000) /* scheduler configuration */
763  #define RCCR_ERAM_MASK	((uint)0x0000e000) /* mask for enable RAM microcode */
764  #define RCCR_ERAM_0KB	((uint)0x00000000) /* use 0KB of dpram for microcode */
765  #define RCCR_ERAM_2KB	((uint)0x00002000) /* use 2KB of dpram for microcode */
766  #define RCCR_ERAM_4KB	((uint)0x00004000) /* use 4KB of dpram for microcode */
767  #define RCCR_ERAM_6KB	((uint)0x00006000) /* use 6KB of dpram for microcode */
768  #define RCCR_ERAM_8KB	((uint)0x00008000) /* use 8KB of dpram for microcode */
769  #define RCCR_ERAM_10KB	((uint)0x0000a000) /* use 10KB of dpram for microcode */
770  #define RCCR_ERAM_12KB	((uint)0x0000c000) /* use 12KB of dpram for microcode */
771  #define RCCR_EDM0	((uint)0x00000800) /* DREQ0 edge detect mode */
772  #define RCCR_EDM1	((uint)0x00000400) /* DREQ1 edge detect mode */
773  #define RCCR_EDM2	((uint)0x00000200) /* DREQ2 edge detect mode */
774  #define RCCR_EDM3	((uint)0x00000100) /* DREQ3 edge detect mode */
775  #define RCCR_DEM01	((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
776  #define RCCR_DEM23	((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
777  
778  /*-----------------------------------------------------------------------
779   * CMXFCR - CMX FCC Clock Route Register
780   */
781  #define CMXFCR_FC1         0x40000000   /* FCC1 connection              */
782  #define CMXFCR_RF1CS_MSK   0x38000000   /* Receive FCC1 Clock Source Mask */
783  #define CMXFCR_TF1CS_MSK   0x07000000   /* Transmit FCC1 Clock Source Mask */
784  #define CMXFCR_FC2         0x00400000   /* FCC2 connection              */
785  #define CMXFCR_RF2CS_MSK   0x00380000   /* Receive FCC2 Clock Source Mask */
786  #define CMXFCR_TF2CS_MSK   0x00070000   /* Transmit FCC2 Clock Source Mask */
787  #define CMXFCR_FC3         0x00004000   /* FCC3 connection              */
788  #define CMXFCR_RF3CS_MSK   0x00003800   /* Receive FCC3 Clock Source Mask */
789  #define CMXFCR_TF3CS_MSK   0x00000700   /* Transmit FCC3 Clock Source Mask */
790  
791  #define CMXFCR_RF1CS_BRG5  0x00000000   /* Receive FCC1 Clock Source is BRG5 */
792  #define CMXFCR_RF1CS_BRG6  0x08000000   /* Receive FCC1 Clock Source is BRG6 */
793  #define CMXFCR_RF1CS_BRG7  0x10000000   /* Receive FCC1 Clock Source is BRG7 */
794  #define CMXFCR_RF1CS_BRG8  0x18000000   /* Receive FCC1 Clock Source is BRG8 */
795  #define CMXFCR_RF1CS_CLK9  0x20000000   /* Receive FCC1 Clock Source is CLK9 */
796  #define CMXFCR_RF1CS_CLK10 0x28000000   /* Receive FCC1 Clock Source is CLK10 */
797  #define CMXFCR_RF1CS_CLK11 0x30000000   /* Receive FCC1 Clock Source is CLK11 */
798  #define CMXFCR_RF1CS_CLK12 0x38000000   /* Receive FCC1 Clock Source is CLK12 */
799  
800  #define CMXFCR_TF1CS_BRG5  0x00000000   /* Transmit FCC1 Clock Source is BRG5 */
801  #define CMXFCR_TF1CS_BRG6  0x01000000   /* Transmit FCC1 Clock Source is BRG6 */
802  #define CMXFCR_TF1CS_BRG7  0x02000000   /* Transmit FCC1 Clock Source is BRG7 */
803  #define CMXFCR_TF1CS_BRG8  0x03000000   /* Transmit FCC1 Clock Source is BRG8 */
804  #define CMXFCR_TF1CS_CLK9  0x04000000   /* Transmit FCC1 Clock Source is CLK9 */
805  #define CMXFCR_TF1CS_CLK10 0x05000000   /* Transmit FCC1 Clock Source is CLK10 */
806  #define CMXFCR_TF1CS_CLK11 0x06000000   /* Transmit FCC1 Clock Source is CLK11 */
807  #define CMXFCR_TF1CS_CLK12 0x07000000   /* Transmit FCC1 Clock Source is CLK12 */
808  
809  #define CMXFCR_RF2CS_BRG5  0x00000000   /* Receive FCC2 Clock Source is BRG5 */
810  #define CMXFCR_RF2CS_BRG6  0x00080000   /* Receive FCC2 Clock Source is BRG6 */
811  #define CMXFCR_RF2CS_BRG7  0x00100000   /* Receive FCC2 Clock Source is BRG7 */
812  #define CMXFCR_RF2CS_BRG8  0x00180000   /* Receive FCC2 Clock Source is BRG8 */
813  #define CMXFCR_RF2CS_CLK13 0x00200000   /* Receive FCC2 Clock Source is CLK13 */
814  #define CMXFCR_RF2CS_CLK14 0x00280000   /* Receive FCC2 Clock Source is CLK14 */
815  #define CMXFCR_RF2CS_CLK15 0x00300000   /* Receive FCC2 Clock Source is CLK15 */
816  #define CMXFCR_RF2CS_CLK16 0x00380000   /* Receive FCC2 Clock Source is CLK16 */
817  
818  #define CMXFCR_TF2CS_BRG5  0x00000000   /* Transmit FCC2 Clock Source is BRG5 */
819  #define CMXFCR_TF2CS_BRG6  0x00010000   /* Transmit FCC2 Clock Source is BRG6 */
820  #define CMXFCR_TF2CS_BRG7  0x00020000   /* Transmit FCC2 Clock Source is BRG7 */
821  #define CMXFCR_TF2CS_BRG8  0x00030000   /* Transmit FCC2 Clock Source is BRG8 */
822  #define CMXFCR_TF2CS_CLK13 0x00040000   /* Transmit FCC2 Clock Source is CLK13 */
823  #define CMXFCR_TF2CS_CLK14 0x00050000   /* Transmit FCC2 Clock Source is CLK14 */
824  #define CMXFCR_TF2CS_CLK15 0x00060000   /* Transmit FCC2 Clock Source is CLK15 */
825  #define CMXFCR_TF2CS_CLK16 0x00070000   /* Transmit FCC2 Clock Source is CLK16 */
826  
827  #define CMXFCR_RF3CS_BRG5  0x00000000   /* Receive FCC3 Clock Source is BRG5 */
828  #define CMXFCR_RF3CS_BRG6  0x00000800   /* Receive FCC3 Clock Source is BRG6 */
829  #define CMXFCR_RF3CS_BRG7  0x00001000   /* Receive FCC3 Clock Source is BRG7 */
830  #define CMXFCR_RF3CS_BRG8  0x00001800   /* Receive FCC3 Clock Source is BRG8 */
831  #define CMXFCR_RF3CS_CLK13 0x00002000   /* Receive FCC3 Clock Source is CLK13 */
832  #define CMXFCR_RF3CS_CLK14 0x00002800   /* Receive FCC3 Clock Source is CLK14 */
833  #define CMXFCR_RF3CS_CLK15 0x00003000   /* Receive FCC3 Clock Source is CLK15 */
834  #define CMXFCR_RF3CS_CLK16 0x00003800   /* Receive FCC3 Clock Source is CLK16 */
835  
836  #define CMXFCR_TF3CS_BRG5  0x00000000   /* Transmit FCC3 Clock Source is BRG5 */
837  #define CMXFCR_TF3CS_BRG6  0x00000100   /* Transmit FCC3 Clock Source is BRG6 */
838  #define CMXFCR_TF3CS_BRG7  0x00000200   /* Transmit FCC3 Clock Source is BRG7 */
839  #define CMXFCR_TF3CS_BRG8  0x00000300   /* Transmit FCC3 Clock Source is BRG8 */
840  #define CMXFCR_TF3CS_CLK13 0x00000400   /* Transmit FCC3 Clock Source is CLK13 */
841  #define CMXFCR_TF3CS_CLK14 0x00000500   /* Transmit FCC3 Clock Source is CLK14 */
842  #define CMXFCR_TF3CS_CLK15 0x00000600   /* Transmit FCC3 Clock Source is CLK15 */
843  #define CMXFCR_TF3CS_CLK16 0x00000700   /* Transmit FCC3 Clock Source is CLK16 */
844  
845  /*-----------------------------------------------------------------------
846   * CMXSCR - CMX SCC Clock Route Register
847   */
848  #define CMXSCR_GR1         0x80000000   /* Grant Support of SCC1        */
849  #define CMXSCR_SC1         0x40000000   /* SCC1 connection              */
850  #define CMXSCR_RS1CS_MSK   0x38000000   /* Receive SCC1 Clock Source Mask */
851  #define CMXSCR_TS1CS_MSK   0x07000000   /* Transmit SCC1 Clock Source Mask */
852  #define CMXSCR_GR2         0x00800000   /* Grant Support of SCC2        */
853  #define CMXSCR_SC2         0x00400000   /* SCC2 connection              */
854  #define CMXSCR_RS2CS_MSK   0x00380000   /* Receive SCC2 Clock Source Mask */
855  #define CMXSCR_TS2CS_MSK   0x00070000   /* Transmit SCC2 Clock Source Mask */
856  #define CMXSCR_GR3         0x00008000   /* Grant Support of SCC3        */
857  #define CMXSCR_SC3         0x00004000   /* SCC3 connection              */
858  #define CMXSCR_RS3CS_MSK   0x00003800   /* Receive SCC3 Clock Source Mask */
859  #define CMXSCR_TS3CS_MSK   0x00000700   /* Transmit SCC3 Clock Source Mask */
860  #define CMXSCR_GR4         0x00000080   /* Grant Support of SCC4        */
861  #define CMXSCR_SC4         0x00000040   /* SCC4 connection              */
862  #define CMXSCR_RS4CS_MSK   0x00000038   /* Receive SCC4 Clock Source Mask */
863  #define CMXSCR_TS4CS_MSK   0x00000007   /* Transmit SCC4 Clock Source Mask */
864  
865  #define CMXSCR_RS1CS_BRG1  0x00000000   /* SCC1 Rx Clock Source is BRG1 */
866  #define CMXSCR_RS1CS_BRG2  0x08000000   /* SCC1 Rx Clock Source is BRG2 */
867  #define CMXSCR_RS1CS_BRG3  0x10000000   /* SCC1 Rx Clock Source is BRG3 */
868  #define CMXSCR_RS1CS_BRG4  0x18000000   /* SCC1 Rx Clock Source is BRG4 */
869  #define CMXSCR_RS1CS_CLK11 0x20000000   /* SCC1 Rx Clock Source is CLK11 */
870  #define CMXSCR_RS1CS_CLK12 0x28000000   /* SCC1 Rx Clock Source is CLK12 */
871  #define CMXSCR_RS1CS_CLK3  0x30000000   /* SCC1 Rx Clock Source is CLK3 */
872  #define CMXSCR_RS1CS_CLK4  0x38000000   /* SCC1 Rx Clock Source is CLK4 */
873  
874  #define CMXSCR_TS1CS_BRG1  0x00000000   /* SCC1 Tx Clock Source is BRG1 */
875  #define CMXSCR_TS1CS_BRG2  0x01000000   /* SCC1 Tx Clock Source is BRG2 */
876  #define CMXSCR_TS1CS_BRG3  0x02000000   /* SCC1 Tx Clock Source is BRG3 */
877  #define CMXSCR_TS1CS_BRG4  0x03000000   /* SCC1 Tx Clock Source is BRG4 */
878  #define CMXSCR_TS1CS_CLK11 0x04000000   /* SCC1 Tx Clock Source is CLK11 */
879  #define CMXSCR_TS1CS_CLK12 0x05000000   /* SCC1 Tx Clock Source is CLK12 */
880  #define CMXSCR_TS1CS_CLK3  0x06000000   /* SCC1 Tx Clock Source is CLK3 */
881  #define CMXSCR_TS1CS_CLK4  0x07000000   /* SCC1 Tx Clock Source is CLK4 */
882  
883  #define CMXSCR_RS2CS_BRG1  0x00000000   /* SCC2 Rx Clock Source is BRG1 */
884  #define CMXSCR_RS2CS_BRG2  0x00080000   /* SCC2 Rx Clock Source is BRG2 */
885  #define CMXSCR_RS2CS_BRG3  0x00100000   /* SCC2 Rx Clock Source is BRG3 */
886  #define CMXSCR_RS2CS_BRG4  0x00180000   /* SCC2 Rx Clock Source is BRG4 */
887  #define CMXSCR_RS2CS_CLK11 0x00200000   /* SCC2 Rx Clock Source is CLK11 */
888  #define CMXSCR_RS2CS_CLK12 0x00280000   /* SCC2 Rx Clock Source is CLK12 */
889  #define CMXSCR_RS2CS_CLK3  0x00300000   /* SCC2 Rx Clock Source is CLK3 */
890  #define CMXSCR_RS2CS_CLK4  0x00380000   /* SCC2 Rx Clock Source is CLK4 */
891  
892  #define CMXSCR_TS2CS_BRG1  0x00000000   /* SCC2 Tx Clock Source is BRG1 */
893  #define CMXSCR_TS2CS_BRG2  0x00010000   /* SCC2 Tx Clock Source is BRG2 */
894  #define CMXSCR_TS2CS_BRG3  0x00020000   /* SCC2 Tx Clock Source is BRG3 */
895  #define CMXSCR_TS2CS_BRG4  0x00030000   /* SCC2 Tx Clock Source is BRG4 */
896  #define CMXSCR_TS2CS_CLK11 0x00040000   /* SCC2 Tx Clock Source is CLK11 */
897  #define CMXSCR_TS2CS_CLK12 0x00050000   /* SCC2 Tx Clock Source is CLK12 */
898  #define CMXSCR_TS2CS_CLK3  0x00060000   /* SCC2 Tx Clock Source is CLK3 */
899  #define CMXSCR_TS2CS_CLK4  0x00070000   /* SCC2 Tx Clock Source is CLK4 */
900  
901  #define CMXSCR_RS3CS_BRG1  0x00000000   /* SCC3 Rx Clock Source is BRG1 */
902  #define CMXSCR_RS3CS_BRG2  0x00000800   /* SCC3 Rx Clock Source is BRG2 */
903  #define CMXSCR_RS3CS_BRG3  0x00001000   /* SCC3 Rx Clock Source is BRG3 */
904  #define CMXSCR_RS3CS_BRG4  0x00001800   /* SCC3 Rx Clock Source is BRG4 */
905  #define CMXSCR_RS3CS_CLK5  0x00002000   /* SCC3 Rx Clock Source is CLK5 */
906  #define CMXSCR_RS3CS_CLK6  0x00002800   /* SCC3 Rx Clock Source is CLK6 */
907  #define CMXSCR_RS3CS_CLK7  0x00003000   /* SCC3 Rx Clock Source is CLK7 */
908  #define CMXSCR_RS3CS_CLK8  0x00003800   /* SCC3 Rx Clock Source is CLK8 */
909  
910  #define CMXSCR_TS3CS_BRG1  0x00000000   /* SCC3 Tx Clock Source is BRG1 */
911  #define CMXSCR_TS3CS_BRG2  0x00000100   /* SCC3 Tx Clock Source is BRG2 */
912  #define CMXSCR_TS3CS_BRG3  0x00000200   /* SCC3 Tx Clock Source is BRG3 */
913  #define CMXSCR_TS3CS_BRG4  0x00000300   /* SCC3 Tx Clock Source is BRG4 */
914  #define CMXSCR_TS3CS_CLK5  0x00000400   /* SCC3 Tx Clock Source is CLK5 */
915  #define CMXSCR_TS3CS_CLK6  0x00000500   /* SCC3 Tx Clock Source is CLK6 */
916  #define CMXSCR_TS3CS_CLK7  0x00000600   /* SCC3 Tx Clock Source is CLK7 */
917  #define CMXSCR_TS3CS_CLK8  0x00000700   /* SCC3 Tx Clock Source is CLK8 */
918  
919  #define CMXSCR_RS4CS_BRG1  0x00000000   /* SCC4 Rx Clock Source is BRG1 */
920  #define CMXSCR_RS4CS_BRG2  0x00000008   /* SCC4 Rx Clock Source is BRG2 */
921  #define CMXSCR_RS4CS_BRG3  0x00000010   /* SCC4 Rx Clock Source is BRG3 */
922  #define CMXSCR_RS4CS_BRG4  0x00000018   /* SCC4 Rx Clock Source is BRG4 */
923  #define CMXSCR_RS4CS_CLK5  0x00000020   /* SCC4 Rx Clock Source is CLK5 */
924  #define CMXSCR_RS4CS_CLK6  0x00000028   /* SCC4 Rx Clock Source is CLK6 */
925  #define CMXSCR_RS4CS_CLK7  0x00000030   /* SCC4 Rx Clock Source is CLK7 */
926  #define CMXSCR_RS4CS_CLK8  0x00000038   /* SCC4 Rx Clock Source is CLK8 */
927  
928  #define CMXSCR_TS4CS_BRG1  0x00000000   /* SCC4 Tx Clock Source is BRG1 */
929  #define CMXSCR_TS4CS_BRG2  0x00000001   /* SCC4 Tx Clock Source is BRG2 */
930  #define CMXSCR_TS4CS_BRG3  0x00000002   /* SCC4 Tx Clock Source is BRG3 */
931  #define CMXSCR_TS4CS_BRG4  0x00000003   /* SCC4 Tx Clock Source is BRG4 */
932  #define CMXSCR_TS4CS_CLK5  0x00000004   /* SCC4 Tx Clock Source is CLK5 */
933  #define CMXSCR_TS4CS_CLK6  0x00000005   /* SCC4 Tx Clock Source is CLK6 */
934  #define CMXSCR_TS4CS_CLK7  0x00000006   /* SCC4 Tx Clock Source is CLK7 */
935  #define CMXSCR_TS4CS_CLK8  0x00000007   /* SCC4 Tx Clock Source is CLK8 */
936  
937  /*-----------------------------------------------------------------------
938   * SIUMCR - SIU Module Configuration Register				 4-31
939   */
940  #define SIUMCR_BBD	0x80000000	/* Bus Busy Disable		*/
941  #define SIUMCR_ESE	0x40000000	/* External Snoop Enable	*/
942  #define SIUMCR_PBSE	0x20000000	/* Parity Byte Select Enable	*/
943  #define SIUMCR_CDIS	0x10000000	/* Core Disable			*/
944  #define SIUMCR_DPPC00	0x00000000	/* Data Parity Pins Configuration*/
945  #define SIUMCR_DPPC01	0x04000000	/* - " -			*/
946  #define SIUMCR_DPPC10	0x08000000	/* - " -			*/
947  #define SIUMCR_DPPC11	0x0c000000	/* - " -			*/
948  #define SIUMCR_L2CPC00	0x00000000	/* L2 Cache Pins Configuration	*/
949  #define SIUMCR_L2CPC01	0x01000000	/* - " -			*/
950  #define SIUMCR_L2CPC10	0x02000000	/* - " -			*/
951  #define SIUMCR_L2CPC11	0x03000000	/* - " -			*/
952  #define SIUMCR_LBPC00	0x00000000	/* Local Bus Pins Configuration	*/
953  #define SIUMCR_LBPC01	0x00400000	/* - " -			*/
954  #define SIUMCR_LBPC10	0x00800000	/* - " -			*/
955  #define SIUMCR_LBPC11	0x00c00000	/* - " -			*/
956  #define SIUMCR_APPC00	0x00000000	/* Address Parity Pins Configuration*/
957  #define SIUMCR_APPC01	0x00100000	/* - " -			*/
958  #define SIUMCR_APPC10	0x00200000	/* - " -			*/
959  #define SIUMCR_APPC11	0x00300000	/* - " -			*/
960  #define SIUMCR_CS10PC00	0x00000000	/* CS10 Pin Configuration	*/
961  #define SIUMCR_CS10PC01	0x00040000	/* - " -			*/
962  #define SIUMCR_CS10PC10	0x00080000	/* - " -			*/
963  #define SIUMCR_CS10PC11	0x000c0000	/* - " -			*/
964  #define SIUMCR_BCTLC00	0x00000000	/* Buffer Control Configuration	*/
965  #define SIUMCR_BCTLC01	0x00010000	/* - " -			*/
966  #define SIUMCR_BCTLC10	0x00020000	/* - " -			*/
967  #define SIUMCR_BCTLC11	0x00030000	/* - " -			*/
968  #define SIUMCR_MMR00	0x00000000	/* Mask Masters Requests	*/
969  #define SIUMCR_MMR01	0x00004000	/* - " -			*/
970  #define SIUMCR_MMR10	0x00008000	/* - " -			*/
971  #define SIUMCR_MMR11	0x0000c000	/* - " -			*/
972  #define SIUMCR_LPBSE	0x00002000	/* LocalBus Parity Byte Select Enable*/
973  
974  /*-----------------------------------------------------------------------
975   * SCCR - System Clock Control Register					 9-8
976  */
977  #define SCCR_PCI_MODE	0x00000100	/* PCI Mode	*/
978  #define SCCR_PCI_MODCK	0x00000080	/* Value of PCI_MODCK pin	*/
979  #define SCCR_PCIDF_MSK	0x00000078	/* PCI division factor	*/
980  #define SCCR_PCIDF_SHIFT 3
981  
982  #ifndef CPM_IMMR_OFFSET
983  #define CPM_IMMR_OFFSET	0x101a8
984  #endif
985  
986  #define FCC_PSMR_RMII	((uint)0x00020000)	/* Use RMII interface */
987  
988  /* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
989   * in order to use clock-computing stuff below for the FCC x
990   */
991  
992  /* Automatically generates register configurations */
993  #define PC_CLK(x)	((uint)(1<<(x-1)))	/* FCC CLK I/O ports */
994  
995  #define CMXFCR_RF1CS(x)	((uint)((x-5)<<27))	/* FCC1 Receive Clock Source */
996  #define CMXFCR_TF1CS(x)	((uint)((x-5)<<24))	/* FCC1 Transmit Clock Source */
997  #define CMXFCR_RF2CS(x)	((uint)((x-9)<<19))	/* FCC2 Receive Clock Source */
998  #define CMXFCR_TF2CS(x) ((uint)((x-9)<<16))	/* FCC2 Transmit Clock Source */
999  #define CMXFCR_RF3CS(x)	((uint)((x-9)<<11))	/* FCC3 Receive Clock Source */
1000  #define CMXFCR_TF3CS(x) ((uint)((x-9)<<8))	/* FCC3 Transmit Clock Source */
1001  
1002  #define PC_F1RXCLK	PC_CLK(F1_RXCLK)
1003  #define PC_F1TXCLK	PC_CLK(F1_TXCLK)
1004  #define CMX1_CLK_ROUTE	(CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
1005  #define CMX1_CLK_MASK	((uint)0xff000000)
1006  
1007  #define PC_F2RXCLK	PC_CLK(F2_RXCLK)
1008  #define PC_F2TXCLK	PC_CLK(F2_TXCLK)
1009  #define CMX2_CLK_ROUTE	(CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
1010  #define CMX2_CLK_MASK	((uint)0x00ff0000)
1011  
1012  #define PC_F3RXCLK	PC_CLK(F3_RXCLK)
1013  #define PC_F3TXCLK	PC_CLK(F3_TXCLK)
1014  #define CMX3_CLK_ROUTE	(CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
1015  #define CMX3_CLK_MASK	((uint)0x0000ff00)
1016  
1017  #define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
1018  #define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
1019  
1020  #define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
1021  
1022  /* I/O Pin assignment for FCC1.  I don't yet know the best way to do this,
1023   * but there is little variation among the choices.
1024   */
1025  #define PA1_COL		0x00000001U
1026  #define PA1_CRS		0x00000002U
1027  #define PA1_TXER	0x00000004U
1028  #define PA1_TXEN	0x00000008U
1029  #define PA1_RXDV	0x00000010U
1030  #define PA1_RXER	0x00000020U
1031  #define PA1_TXDAT	0x00003c00U
1032  #define PA1_RXDAT	0x0003c000U
1033  #define PA1_PSORA0	(PA1_RXDAT | PA1_TXDAT)
1034  #define PA1_PSORA1	(PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
1035  		PA1_RXDV | PA1_RXER)
1036  #define PA1_DIRA0	(PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
1037  #define PA1_DIRA1	(PA1_TXDAT | PA1_TXEN | PA1_TXER)
1038  
1039  
1040  /* I/O Pin assignment for FCC2.  I don't yet know the best way to do this,
1041   * but there is little variation among the choices.
1042   */
1043  #define PB2_TXER	0x00000001U
1044  #define PB2_RXDV	0x00000002U
1045  #define PB2_TXEN	0x00000004U
1046  #define PB2_RXER	0x00000008U
1047  #define PB2_COL		0x00000010U
1048  #define PB2_CRS		0x00000020U
1049  #define PB2_TXDAT	0x000003c0U
1050  #define PB2_RXDAT	0x00003c00U
1051  #define PB2_PSORB0	(PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
1052  		PB2_RXER | PB2_RXDV | PB2_TXER)
1053  #define PB2_PSORB1	(PB2_TXEN)
1054  #define PB2_DIRB0	(PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
1055  #define PB2_DIRB1	(PB2_TXDAT | PB2_TXEN | PB2_TXER)
1056  
1057  
1058  /* I/O Pin assignment for FCC3.  I don't yet know the best way to do this,
1059   * but there is little variation among the choices.
1060   */
1061  #define PB3_RXDV	0x00004000U
1062  #define PB3_RXER	0x00008000U
1063  #define PB3_TXER	0x00010000U
1064  #define PB3_TXEN	0x00020000U
1065  #define PB3_COL		0x00040000U
1066  #define PB3_CRS		0x00080000U
1067  #define PB3_TXDAT	0x0f000000U
1068  #define PC3_TXDAT	0x00000010U
1069  #define PB3_RXDAT	0x00f00000U
1070  #define PB3_PSORB0	(PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
1071  		PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
1072  #define PB3_PSORB1	0
1073  #define PB3_DIRB0	(PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
1074  #define PB3_DIRB1	(PB3_TXDAT | PB3_TXEN | PB3_TXER)
1075  #define PC3_DIRC1	(PC3_TXDAT)
1076  
1077  /* Handy macro to specify mem for FCCs*/
1078  #define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
1079  #define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
1080  #define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
1081  #define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
1082  
1083  /* Pipeline Maximum Depth */
1084  #define MPC82XX_BCR_PLDP 0x00800000
1085  
1086  /* Clocks and GRG's */
1087  
1088  enum cpm_clk_dir {
1089  	CPM_CLK_RX,
1090  	CPM_CLK_TX,
1091  	CPM_CLK_RTX
1092  };
1093  
1094  enum cpm_clk_target {
1095  	CPM_CLK_SCC1,
1096  	CPM_CLK_SCC2,
1097  	CPM_CLK_SCC3,
1098  	CPM_CLK_SCC4,
1099  	CPM_CLK_FCC1,
1100  	CPM_CLK_FCC2,
1101  	CPM_CLK_FCC3,
1102  	CPM_CLK_SMC1,
1103  	CPM_CLK_SMC2,
1104  };
1105  
1106  enum cpm_clk {
1107  	CPM_CLK_NONE = 0,
1108  	CPM_BRG1,	/* Baud Rate Generator  1 */
1109  	CPM_BRG2,	/* Baud Rate Generator  2 */
1110  	CPM_BRG3,	/* Baud Rate Generator  3 */
1111  	CPM_BRG4,	/* Baud Rate Generator  4 */
1112  	CPM_BRG5,	/* Baud Rate Generator  5 */
1113  	CPM_BRG6,	/* Baud Rate Generator  6 */
1114  	CPM_BRG7,	/* Baud Rate Generator  7 */
1115  	CPM_BRG8,	/* Baud Rate Generator  8 */
1116  	CPM_CLK1,	/* Clock  1 */
1117  	CPM_CLK2,	/* Clock  2 */
1118  	CPM_CLK3,	/* Clock  3 */
1119  	CPM_CLK4,	/* Clock  4 */
1120  	CPM_CLK5,	/* Clock  5 */
1121  	CPM_CLK6,	/* Clock  6 */
1122  	CPM_CLK7,	/* Clock  7 */
1123  	CPM_CLK8,	/* Clock  8 */
1124  	CPM_CLK9,	/* Clock  9 */
1125  	CPM_CLK10,	/* Clock 10 */
1126  	CPM_CLK11,	/* Clock 11 */
1127  	CPM_CLK12,	/* Clock 12 */
1128  	CPM_CLK13,	/* Clock 13 */
1129  	CPM_CLK14,	/* Clock 14 */
1130  	CPM_CLK15,	/* Clock 15 */
1131  	CPM_CLK16,	/* Clock 16 */
1132  	CPM_CLK17,	/* Clock 17 */
1133  	CPM_CLK18,	/* Clock 18 */
1134  	CPM_CLK19,	/* Clock 19 */
1135  	CPM_CLK20,	/* Clock 20 */
1136  	CPM_CLK_DUMMY
1137  };
1138  
1139  int __init cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
1140  int __init cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);
1141  
1142  #define CPM_PIN_INPUT     0
1143  #define CPM_PIN_OUTPUT    1
1144  #define CPM_PIN_PRIMARY   0
1145  #define CPM_PIN_SECONDARY 2
1146  #define CPM_PIN_GPIO      4
1147  #define CPM_PIN_OPENDRAIN 8
1148  
1149  void __init cpm2_set_pin(int port, int pin, int flags);
1150  
1151  #endif /* __CPM2__ */
1152  #endif /* __KERNEL__ */
1153