1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016-2024, IBM Corporation. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qemu/datadir.h" 24 #include "qemu/log.h" 25 #include "qemu/units.h" 26 #include "qemu/cutils.h" 27 #include "qapi/error.h" 28 #include "system/qtest.h" 29 #include "system/system.h" 30 #include "system/numa.h" 31 #include "system/reset.h" 32 #include "system/runstate.h" 33 #include "system/cpus.h" 34 #include "system/device_tree.h" 35 #include "system/hw_accel.h" 36 #include "target/ppc/cpu.h" 37 #include "hw/ppc/fdt.h" 38 #include "hw/ppc/ppc.h" 39 #include "hw/ppc/pnv.h" 40 #include "hw/ppc/pnv_core.h" 41 #include "hw/loader.h" 42 #include "hw/nmi.h" 43 #include "qapi/visitor.h" 44 #include "hw/intc/intc.h" 45 #include "hw/ipmi/ipmi.h" 46 #include "target/ppc/mmu-hash64.h" 47 #include "hw/pci/msi.h" 48 #include "hw/pci-host/pnv_phb.h" 49 #include "hw/pci-host/pnv_phb3.h" 50 #include "hw/pci-host/pnv_phb4.h" 51 52 #include "hw/ppc/xics.h" 53 #include "hw/qdev-properties.h" 54 #include "hw/ppc/pnv_chip.h" 55 #include "hw/ppc/pnv_xscom.h" 56 #include "hw/ppc/pnv_pnor.h" 57 58 #include "hw/isa/isa.h" 59 #include "hw/char/serial-isa.h" 60 #include "hw/rtc/mc146818rtc.h" 61 62 #include <libfdt.h> 63 64 #define FDT_MAX_SIZE (1 * MiB) 65 66 #define FW_FILE_NAME "skiboot.lid" 67 #define FW_LOAD_ADDR 0x0 68 #define FW_MAX_SIZE (16 * MiB) 69 70 #define PNOR_FILE_NAME "pnv-pnor.bin" 71 72 #define KERNEL_LOAD_ADDR 0x20000000 73 #define KERNEL_MAX_SIZE (128 * MiB) 74 #define INITRD_LOAD_ADDR 0x28000000 75 #define INITRD_MAX_SIZE (128 * MiB) 76 77 static const char *pnv_chip_core_typename(const PnvChip *o) 78 { 79 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 80 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 81 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 82 const char *core_type = object_class_get_name(object_class_by_name(s)); 83 g_free(s); 84 return core_type; 85 } 86 87 /* 88 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 89 * 4 * 4 sockets * 12 cores * 8 threads = 1536 90 * Let's make it 2^11 91 */ 92 #define MAX_CPUS 2048 93 94 /* 95 * Memory nodes are created by hostboot, one for each range of memory 96 * that has a different "affinity". In practice, it means one range 97 * per chip. 98 */ 99 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 100 { 101 char *mem_name; 102 uint64_t mem_reg_property[2]; 103 int off; 104 105 mem_reg_property[0] = cpu_to_be64(start); 106 mem_reg_property[1] = cpu_to_be64(size); 107 108 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 109 off = fdt_add_subnode(fdt, 0, mem_name); 110 g_free(mem_name); 111 112 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 113 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 114 sizeof(mem_reg_property)))); 115 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 116 } 117 118 static int get_cpus_node(void *fdt) 119 { 120 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 121 122 if (cpus_offset < 0) { 123 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 124 if (cpus_offset) { 125 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 126 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 127 } 128 } 129 _FDT(cpus_offset); 130 return cpus_offset; 131 } 132 133 /* 134 * The PowerNV cores (and threads) need to use real HW ids and not an 135 * incremental index like it has been done on other platforms. This HW 136 * id is stored in the CPU PIR, it is used to create cpu nodes in the 137 * device tree, used in XSCOM to address cores and in interrupt 138 * servers. 139 */ 140 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 141 { 142 PowerPCCPU *cpu = pc->threads[0]; 143 CPUState *cs = CPU(cpu); 144 DeviceClass *dc = DEVICE_GET_CLASS(cs); 145 int smt_threads = CPU_CORE(pc)->nr_threads; 146 CPUPPCState *env = &cpu->env; 147 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 148 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 149 uint32_t *servers_prop; 150 int i; 151 uint32_t pir, tir; 152 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 153 0xffffffff, 0xffffffff}; 154 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 155 uint32_t cpufreq = 1000000000; 156 uint32_t page_sizes_prop[64]; 157 size_t page_sizes_prop_size; 158 int offset; 159 char *nodename; 160 int cpus_offset = get_cpus_node(fdt); 161 162 pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir); 163 164 /* Only one DT node per (big) core */ 165 g_assert(tir == 0); 166 167 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 168 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 169 _FDT(offset); 170 g_free(nodename); 171 172 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 173 174 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 175 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 176 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 177 178 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 179 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 180 env->dcache_line_size))); 181 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 182 env->dcache_line_size))); 183 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 184 env->icache_line_size))); 185 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 186 env->icache_line_size))); 187 188 if (pcc->l1_dcache_size) { 189 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 190 pcc->l1_dcache_size))); 191 } else { 192 warn_report("Unknown L1 dcache size for cpu"); 193 } 194 if (pcc->l1_icache_size) { 195 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 196 pcc->l1_icache_size))); 197 } else { 198 warn_report("Unknown L1 icache size for cpu"); 199 } 200 201 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 202 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 203 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 204 cpu->hash64_opts->slb_size))); 205 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 206 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 207 208 if (ppc_has_spr(cpu, SPR_PURR)) { 209 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 210 } 211 212 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 213 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 214 segs, sizeof(segs)))); 215 } 216 217 /* 218 * Advertise VMX/VSX (vector extensions) if available 219 * 0 / no property == no vector extensions 220 * 1 == VMX / Altivec available 221 * 2 == VSX available 222 */ 223 if (env->insns_flags & PPC_ALTIVEC) { 224 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 225 226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 227 } 228 229 /* 230 * Advertise DFP (Decimal Floating Point) if available 231 * 0 / no property == no DFP 232 * 1 == DFP available 233 */ 234 if (env->insns_flags2 & PPC2_DFP) { 235 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 236 } 237 238 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 239 sizeof(page_sizes_prop)); 240 if (page_sizes_prop_size) { 241 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 242 page_sizes_prop, page_sizes_prop_size))); 243 } 244 245 /* Build interrupt servers properties */ 246 if (pc->big_core) { 247 servers_prop = g_new(uint32_t, smt_threads * 2); 248 for (i = 0; i < smt_threads; i++) { 249 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); 250 servers_prop[i * 2] = cpu_to_be32(pir); 251 252 pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL); 253 servers_prop[i * 2 + 1] = cpu_to_be32(pir); 254 } 255 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 256 servers_prop, sizeof(*servers_prop) * smt_threads 257 * 2))); 258 } else { 259 servers_prop = g_new(uint32_t, smt_threads); 260 for (i = 0; i < smt_threads; i++) { 261 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); 262 servers_prop[i] = cpu_to_be32(pir); 263 } 264 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 265 servers_prop, sizeof(*servers_prop) * smt_threads))); 266 } 267 g_free(servers_prop); 268 269 return offset; 270 } 271 272 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 273 uint32_t nr_threads) 274 { 275 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 276 uint32_t pir; 277 uint64_t addr; 278 char *name; 279 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 280 uint32_t irange[2], i, rsize; 281 uint64_t *reg; 282 int offset; 283 284 pcc->get_pir_tir(chip, hwid, 0, &pir, NULL); 285 addr = PNV_ICP_BASE(chip) | (pir << 12); 286 287 irange[0] = cpu_to_be32(pir); 288 irange[1] = cpu_to_be32(nr_threads); 289 290 rsize = sizeof(uint64_t) * 2 * nr_threads; 291 reg = g_malloc(rsize); 292 for (i = 0; i < nr_threads; i++) { 293 /* We know P8 PIR is linear with thread id */ 294 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 295 reg[i * 2 + 1] = cpu_to_be64(0x1000); 296 } 297 298 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 299 offset = fdt_add_subnode(fdt, 0, name); 300 _FDT(offset); 301 g_free(name); 302 303 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 304 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 305 _FDT((fdt_setprop_string(fdt, offset, "device_type", 306 "PowerPC-External-Interrupt-Presentation"))); 307 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 308 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 309 irange, sizeof(irange)))); 310 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 311 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 312 g_free(reg); 313 } 314 315 /* 316 * Adds a PnvPHB to the chip on P8. 317 * Implemented here, like for defaults PHBs 318 */ 319 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 320 { 321 Pnv8Chip *chip8 = PNV8_CHIP(chip); 322 323 phb->chip = chip; 324 325 chip8->phbs[chip8->num_phbs] = phb; 326 chip8->num_phbs++; 327 return chip; 328 } 329 330 /* 331 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 332 * HTM is always enabled because TCG does implement HTM, it's just a 333 * degenerate implementation. 334 */ 335 static const uint8_t pa_features_207[] = { 24, 0, 336 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 337 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 338 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 339 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 340 341 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 342 { 343 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 344 int i; 345 346 pnv_dt_xscom(chip, fdt, 0, 347 cpu_to_be64(PNV_XSCOM_BASE(chip)), 348 cpu_to_be64(PNV_XSCOM_SIZE), 349 compat, sizeof(compat)); 350 351 for (i = 0; i < chip->nr_cores; i++) { 352 PnvCore *pnv_core = chip->cores[i]; 353 int offset; 354 355 offset = pnv_dt_core(chip, pnv_core, fdt); 356 357 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 358 pa_features_207, sizeof(pa_features_207)))); 359 360 /* Interrupt Control Presenters (ICP). One per core. */ 361 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 362 } 363 364 if (chip->ram_size) { 365 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 366 } 367 } 368 369 /* 370 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 371 */ 372 static const uint8_t pa_features_300[] = { 66, 0, 373 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 374 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 375 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 376 /* 6: DS207 */ 377 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 378 /* 16: Vector */ 379 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 380 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 381 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 382 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 383 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 384 /* 32: LE atomic, 34: EBB + ext EBB */ 385 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 386 /* 40: Radix MMU */ 387 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 388 /* 42: PM, 44: PC RA, 46: SC vec'd */ 389 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 390 /* 48: SIMD, 50: QP BFP, 52: String */ 391 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 392 /* 54: DecFP, 56: DecI, 58: SHA */ 393 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 394 /* 60: NM atomic, 62: RNG */ 395 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 396 }; 397 398 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 399 { 400 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 401 int i; 402 403 pnv_dt_xscom(chip, fdt, 0, 404 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 405 cpu_to_be64(PNV9_XSCOM_SIZE), 406 compat, sizeof(compat)); 407 408 for (i = 0; i < chip->nr_cores; i++) { 409 PnvCore *pnv_core = chip->cores[i]; 410 int offset; 411 412 offset = pnv_dt_core(chip, pnv_core, fdt); 413 414 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 415 pa_features_300, sizeof(pa_features_300)))); 416 417 if (pnv_core->big_core) { 418 i++; /* Big-core groups two QEMU cores */ 419 } 420 } 421 422 if (chip->ram_size) { 423 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 424 } 425 426 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 427 } 428 429 /* 430 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 431 * always disables copy/paste. 432 */ 433 static const uint8_t pa_features_31[] = { 74, 0, 434 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 435 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 436 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 437 /* 6: DS207 */ 438 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 439 /* 16: Vector */ 440 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 441 /* 18: Vec. Scalar, 20: Vec. XOR */ 442 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 443 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 444 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 445 /* 32: LE atomic, 34: EBB + ext EBB */ 446 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 447 /* 40: Radix MMU */ 448 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 449 /* 42: PM, 44: PC RA, 46: SC vec'd */ 450 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 451 /* 48: SIMD, 50: QP BFP, 52: String */ 452 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 453 /* 54: DecFP, 56: DecI, 58: SHA */ 454 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 455 /* 60: NM atomic, 62: RNG */ 456 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 457 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 458 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 459 /* 72: [P]HASHST/[P]HASHCHK */ 460 0x80, 0x00, /* 72 - 73 */ 461 }; 462 463 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 464 { 465 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 466 int i; 467 468 pnv_dt_xscom(chip, fdt, 0, 469 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 470 cpu_to_be64(PNV10_XSCOM_SIZE), 471 compat, sizeof(compat)); 472 473 for (i = 0; i < chip->nr_cores; i++) { 474 PnvCore *pnv_core = chip->cores[i]; 475 int offset; 476 477 offset = pnv_dt_core(chip, pnv_core, fdt); 478 479 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 480 pa_features_31, sizeof(pa_features_31)))); 481 482 if (pnv_core->big_core) { 483 i++; /* Big-core groups two QEMU cores */ 484 } 485 } 486 487 if (chip->ram_size) { 488 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 489 } 490 491 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 492 } 493 494 static void pnv_chip_power11_dt_populate(PnvChip *chip, void *fdt) 495 { 496 static const char compat[] = "ibm,power11-xscom\0ibm,xscom"; 497 int i; 498 499 pnv_dt_xscom(chip, fdt, 0, 500 cpu_to_be64(PNV11_XSCOM_BASE(chip)), 501 cpu_to_be64(PNV11_XSCOM_SIZE), 502 compat, sizeof(compat)); 503 504 for (i = 0; i < chip->nr_cores; i++) { 505 PnvCore *pnv_core = chip->cores[i]; 506 int offset; 507 508 offset = pnv_dt_core(chip, pnv_core, fdt); 509 510 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 511 pa_features_31, sizeof(pa_features_31)))); 512 513 if (pnv_core->big_core) { 514 i++; /* Big-core groups two QEMU cores */ 515 } 516 } 517 518 if (chip->ram_size) { 519 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 520 } 521 522 pnv_dt_lpc(chip, fdt, 0, PNV11_LPCM_BASE(chip), PNV11_LPCM_SIZE); 523 } 524 525 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 526 { 527 uint32_t io_base = d->ioport_id; 528 uint32_t io_regs[] = { 529 cpu_to_be32(1), 530 cpu_to_be32(io_base), 531 cpu_to_be32(2) 532 }; 533 char *name; 534 int node; 535 536 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 537 node = fdt_add_subnode(fdt, lpc_off, name); 538 _FDT(node); 539 g_free(name); 540 541 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 542 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 543 } 544 545 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 546 { 547 const char compatible[] = "ns16550\0pnpPNP,501"; 548 uint32_t io_base = d->ioport_id; 549 uint32_t io_regs[] = { 550 cpu_to_be32(1), 551 cpu_to_be32(io_base), 552 cpu_to_be32(8) 553 }; 554 uint32_t irq; 555 char *name; 556 int node; 557 558 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 559 560 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 561 node = fdt_add_subnode(fdt, lpc_off, name); 562 _FDT(node); 563 g_free(name); 564 565 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 566 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 567 sizeof(compatible)))); 568 569 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 570 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 571 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 572 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 573 fdt_get_phandle(fdt, lpc_off)))); 574 575 /* This is needed by Linux */ 576 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 577 } 578 579 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 580 { 581 const char compatible[] = "bt\0ipmi-bt"; 582 uint32_t io_base; 583 uint32_t io_regs[] = { 584 cpu_to_be32(1), 585 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 586 cpu_to_be32(3) 587 }; 588 uint32_t irq; 589 char *name; 590 int node; 591 592 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 593 io_regs[1] = cpu_to_be32(io_base); 594 595 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 596 597 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 598 node = fdt_add_subnode(fdt, lpc_off, name); 599 _FDT(node); 600 g_free(name); 601 602 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 603 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 604 sizeof(compatible)))); 605 606 /* Mark it as reserved to avoid Linux trying to claim it */ 607 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 608 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 609 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 610 fdt_get_phandle(fdt, lpc_off)))); 611 } 612 613 typedef struct ForeachPopulateArgs { 614 void *fdt; 615 int offset; 616 } ForeachPopulateArgs; 617 618 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 619 { 620 ForeachPopulateArgs *args = opaque; 621 ISADevice *d = ISA_DEVICE(dev); 622 623 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 624 pnv_dt_rtc(d, args->fdt, args->offset); 625 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 626 pnv_dt_serial(d, args->fdt, args->offset); 627 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 628 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 629 } else { 630 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 631 d->ioport_id); 632 } 633 634 return 0; 635 } 636 637 /* 638 * The default LPC bus of a multichip system is on chip 0. It's 639 * recognized by the firmware (skiboot) using a "primary" property. 640 */ 641 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 642 { 643 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 644 ForeachPopulateArgs args = { 645 .fdt = fdt, 646 .offset = isa_offset, 647 }; 648 uint32_t phandle; 649 650 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 651 652 phandle = qemu_fdt_alloc_phandle(fdt); 653 assert(phandle > 0); 654 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 655 656 /* 657 * ISA devices are not necessarily parented to the ISA bus so we 658 * can not use object_child_foreach() 659 */ 660 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 661 &args); 662 } 663 664 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 665 { 666 int off; 667 668 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 669 off = fdt_add_subnode(fdt, off, "power-mgt"); 670 671 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 672 } 673 674 static void *pnv_dt_create(MachineState *machine) 675 { 676 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 677 PnvMachineState *pnv = PNV_MACHINE(machine); 678 void *fdt; 679 char *buf; 680 int off; 681 int i; 682 683 fdt = g_malloc0(FDT_MAX_SIZE); 684 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 685 686 /* /qemu node */ 687 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 688 689 /* Root node */ 690 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 691 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 692 _FDT((fdt_setprop_string(fdt, 0, "model", 693 "IBM PowerNV (emulated by qemu)"))); 694 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 695 696 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 697 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 698 if (qemu_uuid_set) { 699 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 700 } 701 g_free(buf); 702 703 off = fdt_add_subnode(fdt, 0, "chosen"); 704 if (machine->kernel_cmdline) { 705 _FDT((fdt_setprop_string(fdt, off, "bootargs", 706 machine->kernel_cmdline))); 707 } 708 709 if (pnv->initrd_size) { 710 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 711 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 712 713 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 714 &start_prop, sizeof(start_prop)))); 715 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 716 &end_prop, sizeof(end_prop)))); 717 } 718 719 /* Populate device tree for each chip */ 720 for (i = 0; i < pnv->num_chips; i++) { 721 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 722 } 723 724 /* Populate ISA devices on chip 0 */ 725 pnv_dt_isa(pnv, fdt); 726 727 if (pnv->bmc) { 728 pnv_dt_bmc_sensors(pnv->bmc, fdt); 729 } 730 731 /* Create an extra node for power management on machines that support it */ 732 if (pmc->dt_power_mgt) { 733 pmc->dt_power_mgt(pnv, fdt); 734 } 735 736 return fdt; 737 } 738 739 static void pnv_powerdown_notify(Notifier *n, void *opaque) 740 { 741 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 742 743 if (pnv->bmc) { 744 pnv_bmc_powerdown(pnv->bmc); 745 } 746 } 747 748 static void pnv_reset(MachineState *machine, ResetType type) 749 { 750 PnvMachineState *pnv = PNV_MACHINE(machine); 751 IPMIBmc *bmc; 752 void *fdt; 753 754 qemu_devices_reset(type); 755 756 /* 757 * The machine should provide by default an internal BMC simulator. 758 * If not, try to use the BMC device that was provided on the command 759 * line. 760 */ 761 bmc = pnv_bmc_find(&error_fatal); 762 if (!pnv->bmc) { 763 if (!bmc) { 764 if (!qtest_enabled()) { 765 warn_report("machine has no BMC device. Use '-device " 766 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 767 "to define one"); 768 } 769 } else { 770 pnv_bmc_set_pnor(bmc, pnv->pnor); 771 pnv->bmc = bmc; 772 } 773 } 774 775 if (machine->fdt) { 776 fdt = machine->fdt; 777 } else { 778 fdt = pnv_dt_create(machine); 779 /* Pack resulting tree */ 780 _FDT((fdt_pack(fdt))); 781 } 782 783 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 784 785 /* Update machine->fdt with latest fdt */ 786 if (machine->fdt != fdt) { 787 /* 788 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 789 * the existing machine->fdt to avoid leaking it during 790 * a reset. 791 */ 792 g_free(machine->fdt); 793 machine->fdt = fdt; 794 } 795 } 796 797 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 798 { 799 Pnv8Chip *chip8 = PNV8_CHIP(chip); 800 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 801 802 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 803 804 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 805 } 806 807 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 808 { 809 Pnv8Chip *chip8 = PNV8_CHIP(chip); 810 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 811 812 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 813 814 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 815 } 816 817 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 818 { 819 Pnv9Chip *chip9 = PNV9_CHIP(chip); 820 qemu_irq irq; 821 822 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 823 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "LPCHC", 0, irq); 824 825 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ0); 826 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 0, irq); 827 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ1); 828 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 1, irq); 829 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ2); 830 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 2, irq); 831 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ3); 832 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 3, irq); 833 834 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 835 } 836 837 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 838 { 839 Pnv10Chip *chip10 = PNV10_CHIP(chip); 840 qemu_irq irq; 841 842 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 843 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "LPCHC", 0, irq); 844 845 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ0); 846 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 0, irq); 847 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ1); 848 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 1, irq); 849 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ2); 850 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 2, irq); 851 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ3); 852 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 3, irq); 853 854 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 855 } 856 857 static ISABus *pnv_chip_power11_isa_create(PnvChip *chip, Error **errp) 858 { 859 Pnv11Chip *chip11 = PNV11_CHIP(chip); 860 qemu_irq irq; 861 862 irq = qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPCHC); 863 qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "LPCHC", 0, irq); 864 865 irq = qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPC_SIRQ0); 866 qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "SERIRQ", 0, irq); 867 irq = qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPC_SIRQ1); 868 qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "SERIRQ", 1, irq); 869 irq = qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPC_SIRQ2); 870 qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "SERIRQ", 2, irq); 871 irq = qdev_get_gpio_in(DEVICE(&chip11->psi), PSIHB9_IRQ_LPC_SIRQ3); 872 qdev_connect_gpio_out_named(DEVICE(&chip11->lpc), "SERIRQ", 3, irq); 873 874 return pnv_lpc_isa_create(&chip11->lpc, false, errp); 875 } 876 877 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 878 { 879 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 880 } 881 882 static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf) 883 { 884 Pnv8Chip *chip8 = PNV8_CHIP(chip); 885 int i; 886 887 ics_pic_print_info(&chip8->psi.ics, buf); 888 889 for (i = 0; i < chip8->num_phbs; i++) { 890 PnvPHB *phb = chip8->phbs[i]; 891 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 892 893 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 894 ics_pic_print_info(&phb3->lsis, buf); 895 } 896 } 897 898 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 899 { 900 GString *buf = opaque; 901 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 902 903 if (!phb) { 904 return 0; 905 } 906 907 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); 908 909 return 0; 910 } 911 912 static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf) 913 { 914 Pnv9Chip *chip9 = PNV9_CHIP(chip); 915 916 pnv_xive_pic_print_info(&chip9->xive, buf); 917 pnv_psi_pic_print_info(&chip9->psi, buf); 918 object_child_foreach_recursive(OBJECT(chip), 919 pnv_chip_power9_pic_print_info_child, buf); 920 } 921 922 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 923 uint32_t core_id) 924 { 925 return PNV_XSCOM_EX_BASE(core_id); 926 } 927 928 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 929 uint32_t core_id) 930 { 931 return PNV9_XSCOM_EC_BASE(core_id); 932 } 933 934 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 935 uint32_t core_id) 936 { 937 return PNV10_XSCOM_EC_BASE(core_id); 938 } 939 940 static uint64_t pnv_chip_power11_xscom_core_base(PnvChip *chip, 941 uint32_t core_id) 942 { 943 return PNV11_XSCOM_EC_BASE(core_id); 944 } 945 946 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 947 { 948 PowerPCCPUClass *ppc_default = 949 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 950 PowerPCCPUClass *ppc = 951 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 952 953 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 954 } 955 956 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 957 { 958 ISADevice *dev = isa_new("isa-ipmi-bt"); 959 960 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 961 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 962 isa_realize_and_unref(dev, bus, &error_fatal); 963 } 964 965 static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf) 966 { 967 Pnv10Chip *chip10 = PNV10_CHIP(chip); 968 969 pnv_xive2_pic_print_info(&chip10->xive, buf); 970 pnv_psi_pic_print_info(&chip10->psi, buf); 971 object_child_foreach_recursive(OBJECT(chip), 972 pnv_chip_power9_pic_print_info_child, buf); 973 } 974 975 static void pnv_chip_power11_pic_print_info(PnvChip *chip, GString *buf) 976 { 977 Pnv11Chip *chip11 = PNV11_CHIP(chip); 978 979 pnv_xive2_pic_print_info(&chip11->xive, buf); 980 pnv_psi_pic_print_info(&chip11->psi, buf); 981 object_child_foreach_recursive(OBJECT(chip), 982 pnv_chip_power9_pic_print_info_child, buf); 983 } 984 985 /* Always give the first 1GB to chip 0 else we won't boot */ 986 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 987 { 988 MachineState *machine = MACHINE(pnv); 989 uint64_t ram_per_chip; 990 991 assert(machine->ram_size >= 1 * GiB); 992 993 ram_per_chip = machine->ram_size / pnv->num_chips; 994 if (ram_per_chip >= 1 * GiB) { 995 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 996 } 997 998 assert(pnv->num_chips > 1); 999 1000 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 1001 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 1002 } 1003 1004 static void pnv_init(MachineState *machine) 1005 { 1006 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 1007 PnvMachineState *pnv = PNV_MACHINE(machine); 1008 MachineClass *mc = MACHINE_GET_CLASS(machine); 1009 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 1010 int max_smt_threads = pmc->max_smt_threads; 1011 char *fw_filename; 1012 uint64_t chip_ram_start = 0; 1013 int i; 1014 char *chip_typename; 1015 DriveInfo *pnor; 1016 DeviceState *dev; 1017 1018 if (kvm_enabled()) { 1019 error_report("machine %s does not support the KVM accelerator", 1020 mc->name); 1021 exit(EXIT_FAILURE); 1022 } 1023 1024 /* allocate RAM */ 1025 if (machine->ram_size < mc->default_ram_size) { 1026 char *sz = size_to_str(mc->default_ram_size); 1027 error_report("Invalid RAM size, should be bigger than %s", sz); 1028 g_free(sz); 1029 exit(EXIT_FAILURE); 1030 } 1031 1032 /* checks for invalid option combinations */ 1033 if (machine->dtb && (strlen(machine->kernel_cmdline) != 0)) { 1034 error_report("-append and -dtb cannot be used together, as passed" 1035 " command line is ignored in case of custom dtb"); 1036 exit(EXIT_FAILURE); 1037 } 1038 1039 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 1040 1041 /* 1042 * Create our simple PNOR device 1043 */ 1044 dev = qdev_new(TYPE_PNV_PNOR); 1045 pnor = drive_get(IF_MTD, 0, 0); 1046 if (!pnor && defaults_enabled()) { 1047 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, PNOR_FILE_NAME); 1048 if (!fw_filename) { 1049 warn_report("Could not find PNOR '%s'", PNOR_FILE_NAME); 1050 } else { 1051 QemuOpts *opts; 1052 opts = drive_add(IF_MTD, -1, fw_filename, "format=raw,readonly=on"); 1053 pnor = drive_new(opts, IF_MTD, &error_fatal); 1054 g_free(fw_filename); 1055 } 1056 } 1057 if (pnor) { 1058 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 1059 } 1060 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1061 pnv->pnor = PNV_PNOR(dev); 1062 1063 /* load skiboot firmware */ 1064 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1065 if (!fw_filename) { 1066 error_report("Could not find OPAL firmware '%s'", bios_name); 1067 exit(1); 1068 } 1069 1070 load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE, 1071 &error_fatal); 1072 g_free(fw_filename); 1073 1074 /* load kernel */ 1075 if (machine->kernel_filename) { 1076 load_image_targphys(machine->kernel_filename, 1077 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE, &error_fatal); 1078 } 1079 1080 /* load initrd */ 1081 if (machine->initrd_filename) { 1082 pnv->initrd_base = INITRD_LOAD_ADDR; 1083 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 1084 pnv->initrd_base, 1085 INITRD_MAX_SIZE, &error_fatal); 1086 } 1087 1088 /* load dtb if passed */ 1089 if (machine->dtb) { 1090 int fdt_size; 1091 1092 warn_report("with manually passed dtb, some options like '-append'" 1093 " will get ignored and the dtb passed will be used as-is"); 1094 1095 /* read the file 'machine->dtb', and load it into 'fdt' buffer */ 1096 machine->fdt = load_device_tree(machine->dtb, &fdt_size); 1097 if (!machine->fdt) { 1098 error_report("Could not load dtb '%s'", machine->dtb); 1099 exit(1); 1100 } 1101 } 1102 1103 /* MSIs are supported on this platform */ 1104 msi_nonbroken = true; 1105 1106 /* 1107 * Check compatibility of the specified CPU with the machine 1108 * default. 1109 */ 1110 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 1111 error_report("invalid CPU model '%s' for %s machine", 1112 machine->cpu_type, mc->name); 1113 exit(1); 1114 } 1115 1116 /* Create the processor chips */ 1117 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 1118 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 1119 i, machine->cpu_type); 1120 if (!object_class_by_name(chip_typename)) { 1121 error_report("invalid chip model '%.*s' for %s machine", 1122 i, machine->cpu_type, mc->name); 1123 exit(1); 1124 } 1125 1126 /* Set lpar-per-core mode if lpar-per-thread is not supported */ 1127 if (!pmc->has_lpar_per_thread) { 1128 pnv->lpar_per_core = true; 1129 } 1130 1131 pnv->num_chips = 1132 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 1133 1134 if (pnv->big_core) { 1135 if (machine->smp.threads % 2 == 1) { 1136 error_report("Cannot support %d threads with big-core option " 1137 "because it must be an even number", 1138 machine->smp.threads); 1139 exit(1); 1140 } 1141 max_smt_threads *= 2; 1142 } 1143 1144 if (machine->smp.threads > max_smt_threads) { 1145 error_report("Cannot support more than %d threads/core " 1146 "on %s machine", max_smt_threads, mc->desc); 1147 if (pmc->max_smt_threads == 4) { 1148 error_report("(use big-core=on for 8 threads per core)"); 1149 } 1150 exit(1); 1151 } 1152 1153 if (pnv->big_core) { 1154 /* 1155 * powernv models PnvCore as a SMT4 core. Big-core requires 2xPnvCore 1156 * per core, so adjust topology here. pnv_dt_core() processor 1157 * device-tree and TCG SMT code make the 2 cores appear as one big core 1158 * from software point of view. pnv pervasive models and xscoms tend to 1159 * see the big core as 2 small core halves. 1160 */ 1161 machine->smp.cores *= 2; 1162 machine->smp.threads /= 2; 1163 } 1164 1165 if (!is_power_of_2(machine->smp.threads)) { 1166 error_report("Cannot support %d threads/core on a powernv " 1167 "machine because it must be a power of 2", 1168 machine->smp.threads); 1169 exit(1); 1170 } 1171 1172 /* 1173 * TODO: should we decide on how many chips we can create based 1174 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1175 */ 1176 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 1177 error_report("invalid number of chips: '%d'", pnv->num_chips); 1178 error_printf( 1179 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 1180 exit(1); 1181 } 1182 1183 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1184 for (i = 0; i < pnv->num_chips; i++) { 1185 char chip_name[32]; 1186 Object *chip = OBJECT(qdev_new(chip_typename)); 1187 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1188 1189 pnv->chips[i] = PNV_CHIP(chip); 1190 1191 /* Distribute RAM among the chips */ 1192 object_property_set_int(chip, "ram-start", chip_ram_start, 1193 &error_fatal); 1194 object_property_set_int(chip, "ram-size", chip_ram_size, 1195 &error_fatal); 1196 chip_ram_start += chip_ram_size; 1197 1198 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1199 object_property_add_child(OBJECT(pnv), chip_name, chip); 1200 object_property_set_int(chip, "chip-id", i, &error_fatal); 1201 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1202 &error_fatal); 1203 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1204 &error_fatal); 1205 object_property_set_bool(chip, "big-core", pnv->big_core, 1206 &error_fatal); 1207 object_property_set_bool(chip, "lpar-per-core", pnv->lpar_per_core, 1208 &error_fatal); 1209 /* 1210 * The POWER8 machine use the XICS interrupt interface. 1211 * Propagate the XICS fabric to the chip and its controllers. 1212 */ 1213 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1214 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1215 } 1216 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1217 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1218 &error_abort); 1219 } 1220 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1221 } 1222 g_free(chip_typename); 1223 1224 /* Instantiate ISA bus on chip 0 */ 1225 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1226 1227 /* Create serial port */ 1228 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1229 1230 /* Create an RTC ISA device too */ 1231 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1232 1233 /* 1234 * Create the machine BMC simulator and the IPMI BT device for 1235 * communication with the BMC 1236 */ 1237 if (defaults_enabled()) { 1238 pnv->bmc = pnv_bmc_create(pnv->pnor); 1239 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1240 } 1241 1242 /* 1243 * The PNOR is mapped on the LPC FW address space by the BMC. 1244 * Since we can not reach the remote BMC machine with LPC memops, 1245 * map it always for now. 1246 */ 1247 memory_region_add_subregion(pnv->chips[0]->fw_mr, pnv->pnor->lpc_address, 1248 &pnv->pnor->mmio); 1249 1250 /* 1251 * OpenPOWER systems use a IPMI SEL Event message to notify the 1252 * host to powerdown 1253 */ 1254 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1255 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1256 1257 /* 1258 * Create/Connect any machine-specific I2C devices 1259 */ 1260 if (pmc->i2c_init) { 1261 pmc->i2c_init(pnv); 1262 } 1263 } 1264 1265 /* 1266 * 0:21 Reserved - Read as zeros 1267 * 22:24 Chip ID 1268 * 25:28 Core number 1269 * 29:31 Thread ID 1270 */ 1271 static void pnv_get_pir_tir_p8(PnvChip *chip, 1272 uint32_t core_id, uint32_t thread_id, 1273 uint32_t *pir, uint32_t *tir) 1274 { 1275 if (pir) { 1276 *pir = (chip->chip_id << 7) | (core_id << 3) | thread_id; 1277 } 1278 if (tir) { 1279 *tir = thread_id; 1280 } 1281 } 1282 1283 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1284 Error **errp) 1285 { 1286 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1287 Error *local_err = NULL; 1288 Object *obj; 1289 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1290 1291 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1292 if (local_err) { 1293 error_propagate(errp, local_err); 1294 return; 1295 } 1296 1297 pnv_cpu->intc = obj; 1298 } 1299 1300 1301 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1302 { 1303 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1304 1305 icp_reset(ICP(pnv_cpu->intc)); 1306 } 1307 1308 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1309 { 1310 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1311 1312 icp_destroy(ICP(pnv_cpu->intc)); 1313 pnv_cpu->intc = NULL; 1314 } 1315 1316 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1317 GString *buf) 1318 { 1319 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1320 } 1321 1322 /* 1323 * 0:48 Reserved - Read as zeroes 1324 * 49:52 Node ID 1325 * 53:55 Chip ID 1326 * 56 Reserved - Read as zero 1327 * 57:61 Core number 1328 * 62:63 Thread ID 1329 * 1330 * We only care about the lower bits. uint32_t is fine for the moment. 1331 */ 1332 static void pnv_get_pir_tir_p9(PnvChip *chip, 1333 uint32_t core_id, uint32_t thread_id, 1334 uint32_t *pir, uint32_t *tir) 1335 { 1336 if (chip->big_core) { 1337 /* Big-core interleaves thread ID between small-cores */ 1338 thread_id <<= 1; 1339 thread_id |= core_id & 1; 1340 core_id >>= 1; 1341 1342 if (pir) { 1343 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; 1344 } 1345 } else { 1346 if (pir) { 1347 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1348 } 1349 } 1350 if (tir) { 1351 *tir = thread_id; 1352 } 1353 } 1354 1355 /* 1356 * 0:48 Reserved - Read as zeroes 1357 * 49:52 Node ID 1358 * 53:55 Chip ID 1359 * 56 Reserved - Read as zero 1360 * 57:59 Quad ID 1361 * 60 Core Chiplet Pair ID 1362 * 61:63 Thread/Core Chiplet ID t0-t2 1363 * 1364 * We only care about the lower bits. uint32_t is fine for the moment. 1365 */ 1366 static void pnv_get_pir_tir_p10(PnvChip *chip, 1367 uint32_t core_id, uint32_t thread_id, 1368 uint32_t *pir, uint32_t *tir) 1369 { 1370 if (chip->big_core) { 1371 /* Big-core interleaves thread ID between small-cores */ 1372 thread_id <<= 1; 1373 thread_id |= core_id & 1; 1374 core_id >>= 1; 1375 1376 if (pir) { 1377 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; 1378 } 1379 } else { 1380 if (pir) { 1381 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1382 } 1383 } 1384 if (tir) { 1385 *tir = thread_id; 1386 } 1387 } 1388 1389 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1390 Error **errp) 1391 { 1392 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1393 Error *local_err = NULL; 1394 Object *obj; 1395 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1396 1397 /* 1398 * The core creates its interrupt presenter but the XIVE interrupt 1399 * controller object is initialized afterwards. Hopefully, it's 1400 * only used at runtime. 1401 */ 1402 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1403 &local_err); 1404 if (local_err) { 1405 error_propagate(errp, local_err); 1406 return; 1407 } 1408 1409 pnv_cpu->intc = obj; 1410 } 1411 1412 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1413 { 1414 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1415 1416 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1417 } 1418 1419 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1420 { 1421 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1422 1423 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1424 pnv_cpu->intc = NULL; 1425 } 1426 1427 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1428 GString *buf) 1429 { 1430 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1431 } 1432 1433 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1434 Error **errp) 1435 { 1436 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1437 Error *local_err = NULL; 1438 Object *obj; 1439 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1440 1441 /* 1442 * The core creates its interrupt presenter but the XIVE2 interrupt 1443 * controller object is initialized afterwards. Hopefully, it's 1444 * only used at runtime. 1445 */ 1446 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1447 &local_err); 1448 if (local_err) { 1449 error_propagate(errp, local_err); 1450 return; 1451 } 1452 1453 pnv_cpu->intc = obj; 1454 } 1455 1456 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1457 { 1458 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1459 1460 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1461 } 1462 1463 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1464 { 1465 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1466 1467 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1468 pnv_cpu->intc = NULL; 1469 } 1470 1471 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1472 GString *buf) 1473 { 1474 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1475 } 1476 1477 static void *pnv_chip_power10_intc_get(PnvChip *chip) 1478 { 1479 return &PNV10_CHIP(chip)->xive; 1480 } 1481 1482 static void pnv_chip_power11_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1483 Error **errp) 1484 { 1485 Pnv11Chip *chip11 = PNV11_CHIP(chip); 1486 Error *local_err = NULL; 1487 Object *obj; 1488 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1489 1490 /* 1491 * The core creates its interrupt presenter but the XIVE2 interrupt 1492 * controller object is initialized afterwards. Hopefully, it's 1493 * only used at runtime. 1494 */ 1495 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip11->xive), 1496 &local_err); 1497 if (local_err) { 1498 error_propagate(errp, local_err); 1499 return; 1500 } 1501 1502 pnv_cpu->intc = obj; 1503 } 1504 1505 static void pnv_chip_power11_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1506 { 1507 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1508 1509 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1510 } 1511 1512 static void pnv_chip_power11_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1513 { 1514 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1515 1516 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1517 pnv_cpu->intc = NULL; 1518 } 1519 1520 static void pnv_chip_power11_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1521 GString *buf) 1522 { 1523 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1524 } 1525 1526 static void *pnv_chip_power11_intc_get(PnvChip *chip) 1527 { 1528 return &PNV11_CHIP(chip)->xive; 1529 } 1530 1531 /* 1532 * Allowed core identifiers on a POWER8 Processor Chip : 1533 * 1534 * <EX0 reserved> 1535 * EX1 - Venice only 1536 * EX2 - Venice only 1537 * EX3 - Venice only 1538 * EX4 1539 * EX5 1540 * EX6 1541 * <EX7,8 reserved> <reserved> 1542 * EX9 - Venice only 1543 * EX10 - Venice only 1544 * EX11 - Venice only 1545 * EX12 1546 * EX13 1547 * EX14 1548 * <EX15 reserved> 1549 */ 1550 #define POWER8E_CORE_MASK (0x7070ull) 1551 #define POWER8_CORE_MASK (0x7e7eull) 1552 1553 /* 1554 * POWER9 has 24 cores, ids starting at 0x0 1555 */ 1556 #define POWER9_CORE_MASK (0xffffffffffffffull) 1557 1558 1559 #define POWER10_CORE_MASK (0xffffffffffffffull) 1560 1561 #define POWER11_CORE_MASK (0xffffffffffffffull) 1562 1563 static void pnv_chip_power8_instance_init(Object *obj) 1564 { 1565 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1566 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1567 int i; 1568 1569 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1570 (Object **)&chip8->xics, 1571 object_property_allow_set_link, 1572 OBJ_PROP_LINK_STRONG); 1573 1574 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1575 1576 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1577 1578 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1579 1580 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1581 1582 if (defaults_enabled()) { 1583 chip8->num_phbs = pcc->num_phbs; 1584 1585 for (i = 0; i < chip8->num_phbs; i++) { 1586 Object *phb = object_new(TYPE_PNV_PHB); 1587 1588 /* 1589 * We need the chip to parent the PHB to allow the DT 1590 * to build correctly (via pnv_xscom_dt()). 1591 * 1592 * TODO: the PHB should be parented by a PEC device that, at 1593 * this moment, is not modelled powernv8/phb3. 1594 */ 1595 object_property_add_child(obj, "phb[*]", phb); 1596 chip8->phbs[i] = PNV_PHB(phb); 1597 } 1598 } 1599 1600 } 1601 1602 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1603 { 1604 PnvChip *chip = PNV_CHIP(chip8); 1605 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1606 int i, j; 1607 char *name; 1608 1609 name = g_strdup_printf("icp-%x", chip->chip_id); 1610 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1611 g_free(name); 1612 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1613 &chip8->icp_mmio); 1614 1615 /* Map the ICP registers for each thread */ 1616 for (i = 0; i < chip->nr_cores; i++) { 1617 PnvCore *pnv_core = chip->cores[i]; 1618 int core_hwid = CPU_CORE(pnv_core)->core_id; 1619 1620 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1621 uint32_t pir; 1622 PnvICPState *icp; 1623 1624 pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL); 1625 icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1626 1627 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1628 &icp->mmio); 1629 } 1630 } 1631 } 1632 1633 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1634 { 1635 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1636 PnvChip *chip = PNV_CHIP(dev); 1637 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1638 Pnv8Psi *psi8 = &chip8->psi; 1639 Error *local_err = NULL; 1640 int i; 1641 1642 assert(chip8->xics); 1643 1644 /* XSCOM bridge is first */ 1645 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1646 1647 pcc->parent_realize(dev, &local_err); 1648 if (local_err) { 1649 error_propagate(errp, local_err); 1650 return; 1651 } 1652 1653 /* Processor Service Interface (PSI) Host Bridge */ 1654 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1655 &error_fatal); 1656 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1657 OBJECT(chip8->xics), &error_abort); 1658 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1659 return; 1660 } 1661 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1662 &PNV_PSI(psi8)->xscom_regs); 1663 1664 /* Create LPC controller */ 1665 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1666 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1667 1668 chip->fw_mr = &chip8->lpc.isa_fw; 1669 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1670 (uint64_t) PNV_XSCOM_BASE(chip), 1671 PNV_XSCOM_LPC_BASE); 1672 1673 /* 1674 * Interrupt Management Area. This is the memory region holding 1675 * all the Interrupt Control Presenter (ICP) registers 1676 */ 1677 pnv_chip_icp_realize(chip8, &local_err); 1678 if (local_err) { 1679 error_propagate(errp, local_err); 1680 return; 1681 } 1682 1683 /* HOMER (must be created before OCC) */ 1684 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1685 &error_abort); 1686 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1687 return; 1688 } 1689 /* Homer Xscom region */ 1690 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1691 /* Homer RAM region */ 1692 memory_region_add_subregion(get_system_memory(), chip8->homer.base, 1693 &chip8->homer.mem); 1694 1695 /* Create the simplified OCC model */ 1696 object_property_set_link(OBJECT(&chip8->occ), "homer", 1697 OBJECT(&chip8->homer), &error_abort); 1698 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1699 return; 1700 } 1701 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1702 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1703 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1704 1705 /* OCC SRAM model */ 1706 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1707 &chip8->occ.sram_regs); 1708 1709 /* PHB controllers */ 1710 for (i = 0; i < chip8->num_phbs; i++) { 1711 PnvPHB *phb = chip8->phbs[i]; 1712 1713 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1714 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1715 &error_fatal); 1716 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1717 &error_fatal); 1718 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1719 return; 1720 } 1721 } 1722 } 1723 1724 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1725 { 1726 addr &= (PNV_XSCOM_SIZE - 1); 1727 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1728 } 1729 1730 static void pnv_chip_power8e_class_init(ObjectClass *klass, const void *data) 1731 { 1732 DeviceClass *dc = DEVICE_CLASS(klass); 1733 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1734 1735 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1736 k->cores_mask = POWER8E_CORE_MASK; 1737 k->num_phbs = 3; 1738 k->get_pir_tir = pnv_get_pir_tir_p8; 1739 k->intc_create = pnv_chip_power8_intc_create; 1740 k->intc_reset = pnv_chip_power8_intc_reset; 1741 k->intc_destroy = pnv_chip_power8_intc_destroy; 1742 k->intc_print_info = pnv_chip_power8_intc_print_info; 1743 k->isa_create = pnv_chip_power8_isa_create; 1744 k->dt_populate = pnv_chip_power8_dt_populate; 1745 k->pic_print_info = pnv_chip_power8_pic_print_info; 1746 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1747 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1748 dc->desc = "PowerNV Chip POWER8E"; 1749 1750 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1751 &k->parent_realize); 1752 } 1753 1754 static void pnv_chip_power8_class_init(ObjectClass *klass, const void *data) 1755 { 1756 DeviceClass *dc = DEVICE_CLASS(klass); 1757 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1758 1759 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1760 k->cores_mask = POWER8_CORE_MASK; 1761 k->num_phbs = 3; 1762 k->get_pir_tir = pnv_get_pir_tir_p8; 1763 k->intc_create = pnv_chip_power8_intc_create; 1764 k->intc_reset = pnv_chip_power8_intc_reset; 1765 k->intc_destroy = pnv_chip_power8_intc_destroy; 1766 k->intc_print_info = pnv_chip_power8_intc_print_info; 1767 k->isa_create = pnv_chip_power8_isa_create; 1768 k->dt_populate = pnv_chip_power8_dt_populate; 1769 k->pic_print_info = pnv_chip_power8_pic_print_info; 1770 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1771 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1772 dc->desc = "PowerNV Chip POWER8"; 1773 1774 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1775 &k->parent_realize); 1776 } 1777 1778 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, const void *data) 1779 { 1780 DeviceClass *dc = DEVICE_CLASS(klass); 1781 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1782 1783 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1784 k->cores_mask = POWER8_CORE_MASK; 1785 k->num_phbs = 4; 1786 k->get_pir_tir = pnv_get_pir_tir_p8; 1787 k->intc_create = pnv_chip_power8_intc_create; 1788 k->intc_reset = pnv_chip_power8_intc_reset; 1789 k->intc_destroy = pnv_chip_power8_intc_destroy; 1790 k->intc_print_info = pnv_chip_power8_intc_print_info; 1791 k->isa_create = pnv_chip_power8nvl_isa_create; 1792 k->dt_populate = pnv_chip_power8_dt_populate; 1793 k->pic_print_info = pnv_chip_power8_pic_print_info; 1794 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1795 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1796 dc->desc = "PowerNV Chip POWER8NVL"; 1797 1798 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1799 &k->parent_realize); 1800 } 1801 1802 static void pnv_chip_power9_instance_init(Object *obj) 1803 { 1804 PnvChip *chip = PNV_CHIP(obj); 1805 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1806 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1807 int i; 1808 1809 object_initialize_child(obj, "adu", &chip9->adu, TYPE_PNV_ADU); 1810 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1811 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1812 "xive-fabric"); 1813 1814 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1815 1816 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1817 1818 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1819 1820 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1821 1822 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1823 1824 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1825 1826 /* Number of PECs is the chip default */ 1827 chip->num_pecs = pcc->num_pecs; 1828 1829 for (i = 0; i < chip->num_pecs; i++) { 1830 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1831 TYPE_PNV_PHB4_PEC); 1832 } 1833 1834 for (i = 0; i < pcc->i2c_num_engines; i++) { 1835 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1836 } 1837 } 1838 1839 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1840 PnvCore *pnv_core, 1841 const char *type) 1842 { 1843 char eq_name[32]; 1844 int core_id = CPU_CORE(pnv_core)->core_id; 1845 1846 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1847 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1848 sizeof(*eq), type, 1849 &error_fatal, NULL); 1850 1851 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1852 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1853 } 1854 1855 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1856 { 1857 PnvChip *chip = PNV_CHIP(chip9); 1858 int i; 1859 1860 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1861 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1862 1863 for (i = 0; i < chip9->nr_quads; i++) { 1864 PnvQuad *eq = &chip9->quads[i]; 1865 1866 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1867 PNV_QUAD_TYPE_NAME("power9")); 1868 1869 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1870 &eq->xscom_regs); 1871 } 1872 } 1873 1874 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1875 { 1876 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1877 int i; 1878 1879 for (i = 0; i < chip->num_pecs; i++) { 1880 PnvPhb4PecState *pec = &chip9->pecs[i]; 1881 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1882 uint32_t pec_cplt_base; 1883 uint32_t pec_nest_base; 1884 uint32_t pec_pci_base; 1885 1886 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1887 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1888 &error_fatal); 1889 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1890 &error_fatal); 1891 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1892 return; 1893 } 1894 1895 pec_cplt_base = pecc->xscom_cplt_base(pec); 1896 pec_nest_base = pecc->xscom_nest_base(pec); 1897 pec_pci_base = pecc->xscom_pci_base(pec); 1898 1899 pnv_xscom_add_subregion(chip, pec_cplt_base, 1900 &pec->nest_pervasive.xscom_ctrl_regs_mr); 1901 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1902 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1903 } 1904 } 1905 1906 static uint64_t pnv_handle_sprd_load(CPUPPCState *env) 1907 { 1908 PowerPCCPU *cpu = env_archcpu(env); 1909 PnvCore *pc = pnv_cpu_state(cpu)->pnv_core; 1910 uint64_t sprc = env->spr[SPR_POWER_SPRC]; 1911 1912 if (pc->big_core) { 1913 pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1); 1914 } 1915 1916 switch (sprc & 0x3e0) { 1917 case 0: /* SCRATCH0-3 */ 1918 case 1: /* SCRATCH4-7 */ 1919 return pc->scratch[(sprc >> 3) & 0x7]; 1920 1921 case 0x1e0: /* core thread state */ 1922 if (env->excp_model == POWERPC_EXCP_POWER9) { 1923 /* 1924 * Only implement for POWER9 because skiboot uses it to check 1925 * big-core mode. Other bits are unimplemented so we would 1926 * prefer to get unimplemented message on POWER10 if it were 1927 * used anywhere. 1928 */ 1929 if (pc->big_core) { 1930 return PPC_BIT(63); 1931 } else { 1932 return 0; 1933 } 1934 } 1935 /* fallthru */ 1936 1937 default: 1938 qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x" 1939 TARGET_FMT_lx"\n", sprc); 1940 break; 1941 } 1942 return 0; 1943 } 1944 1945 static void pnv_handle_sprd_store(CPUPPCState *env, uint64_t val) 1946 { 1947 PowerPCCPU *cpu = env_archcpu(env); 1948 uint64_t sprc = env->spr[SPR_POWER_SPRC]; 1949 PnvCore *pc = pnv_cpu_state(cpu)->pnv_core; 1950 int nr; 1951 1952 if (pc->big_core) { 1953 pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1); 1954 } 1955 1956 switch (sprc & 0x3e0) { 1957 case 0: /* SCRATCH0-3 */ 1958 case 1: /* SCRATCH4-7 */ 1959 /* 1960 * Log stores to SCRATCH, because some firmware uses these for 1961 * debugging and logging, but they would normally be read by the BMC, 1962 * which is not implemented in QEMU yet. This gives a way to get at the 1963 * information. Could also dump these upon checkstop. 1964 */ 1965 nr = (sprc >> 3) & 0x7; 1966 pc->scratch[nr] = val; 1967 break; 1968 default: 1969 qemu_log_mask(LOG_UNIMP, "mtSPRD: Unimplemented SPRC:0x" 1970 TARGET_FMT_lx"\n", sprc); 1971 break; 1972 } 1973 } 1974 1975 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1976 { 1977 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1978 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1979 PnvChip *chip = PNV_CHIP(dev); 1980 Pnv9Psi *psi9 = &chip9->psi; 1981 PowerPCCPU *cpu; 1982 PowerPCCPUClass *cpu_class; 1983 Error *local_err = NULL; 1984 int i; 1985 1986 /* XSCOM bridge is first */ 1987 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1988 1989 pcc->parent_realize(dev, &local_err); 1990 if (local_err) { 1991 error_propagate(errp, local_err); 1992 return; 1993 } 1994 1995 /* ADU */ 1996 object_property_set_link(OBJECT(&chip9->adu), "lpc", OBJECT(&chip9->lpc), 1997 &error_abort); 1998 if (!qdev_realize(DEVICE(&chip9->adu), NULL, errp)) { 1999 return; 2000 } 2001 pnv_xscom_add_subregion(chip, PNV9_XSCOM_ADU_BASE, 2002 &chip9->adu.xscom_regs); 2003 2004 pnv_chip_quad_realize(chip9, &local_err); 2005 if (local_err) { 2006 error_propagate(errp, local_err); 2007 return; 2008 } 2009 2010 /* Set handlers for Special registers, such as SPRD */ 2011 cpu = chip->cores[0]->threads[0]; 2012 cpu_class = POWERPC_CPU_GET_CLASS(cpu); 2013 cpu_class->load_sprd = pnv_handle_sprd_load; 2014 cpu_class->store_sprd = pnv_handle_sprd_store; 2015 2016 /* XIVE interrupt controller (POWER9) */ 2017 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 2018 PNV9_XIVE_IC_BASE(chip), &error_fatal); 2019 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 2020 PNV9_XIVE_VC_BASE(chip), &error_fatal); 2021 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 2022 PNV9_XIVE_PC_BASE(chip), &error_fatal); 2023 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 2024 PNV9_XIVE_TM_BASE(chip), &error_fatal); 2025 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 2026 &error_abort); 2027 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 2028 return; 2029 } 2030 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 2031 &chip9->xive.xscom_regs); 2032 2033 /* Processor Service Interface (PSI) Host Bridge */ 2034 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 2035 &error_fatal); 2036 /* This is the only device with 4k ESB pages */ 2037 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 2038 &error_fatal); 2039 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 2040 return; 2041 } 2042 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 2043 &PNV_PSI(psi9)->xscom_regs); 2044 2045 /* LPC */ 2046 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 2047 return; 2048 } 2049 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 2050 &chip9->lpc.xscom_regs); 2051 2052 chip->fw_mr = &chip9->lpc.isa_fw; 2053 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 2054 (uint64_t) PNV9_LPCM_BASE(chip)); 2055 2056 /* ChipTOD */ 2057 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 2058 chip->chip_id == 0, &error_abort); 2059 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 2060 chip->chip_id == 1, &error_abort); 2061 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 2062 &error_abort); 2063 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 2064 return; 2065 } 2066 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 2067 &chip9->chiptod.xscom_regs); 2068 2069 /* SBE */ 2070 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 2071 return; 2072 } 2073 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 2074 &chip9->sbe.xscom_ctrl_regs); 2075 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 2076 &chip9->sbe.xscom_mbox_regs); 2077 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 2078 DEVICE(psi9), PSIHB9_IRQ_PSU)); 2079 2080 /* HOMER (must be created before OCC) */ 2081 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 2082 &error_abort); 2083 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 2084 return; 2085 } 2086 /* Homer Xscom region */ 2087 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 2088 /* Homer RAM region */ 2089 memory_region_add_subregion(get_system_memory(), chip9->homer.base, 2090 &chip9->homer.mem); 2091 2092 /* Create the simplified OCC model */ 2093 object_property_set_link(OBJECT(&chip9->occ), "homer", 2094 OBJECT(&chip9->homer), &error_abort); 2095 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 2096 return; 2097 } 2098 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 2099 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 2100 DEVICE(psi9), PSIHB9_IRQ_OCC)); 2101 2102 /* OCC SRAM model */ 2103 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 2104 &chip9->occ.sram_regs); 2105 2106 /* PEC PHBs */ 2107 pnv_chip_power9_pec_realize(chip, &local_err); 2108 if (local_err) { 2109 error_propagate(errp, local_err); 2110 return; 2111 } 2112 2113 /* 2114 * I2C 2115 */ 2116 for (i = 0; i < pcc->i2c_num_engines; i++) { 2117 Object *obj = OBJECT(&chip9->i2c[i]); 2118 2119 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2120 object_property_set_int(obj, "num-busses", 2121 pcc->i2c_ports_per_engine[i], 2122 &error_fatal); 2123 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2124 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2125 return; 2126 } 2127 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 2128 (chip9->i2c[i].engine - 1) * 2129 PNV9_XSCOM_I2CM_SIZE, 2130 &chip9->i2c[i].xscom_regs); 2131 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 2132 qdev_get_gpio_in(DEVICE(psi9), 2133 PSIHB9_IRQ_SBE_I2C)); 2134 } 2135 } 2136 2137 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 2138 { 2139 addr &= (PNV9_XSCOM_SIZE - 1); 2140 return addr >> 3; 2141 } 2142 2143 static void pnv_chip_power9_class_init(ObjectClass *klass, const void *data) 2144 { 2145 DeviceClass *dc = DEVICE_CLASS(klass); 2146 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2147 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 2148 2149 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 2150 k->cores_mask = POWER9_CORE_MASK; 2151 k->get_pir_tir = pnv_get_pir_tir_p9; 2152 k->intc_create = pnv_chip_power9_intc_create; 2153 k->intc_reset = pnv_chip_power9_intc_reset; 2154 k->intc_destroy = pnv_chip_power9_intc_destroy; 2155 k->intc_print_info = pnv_chip_power9_intc_print_info; 2156 k->isa_create = pnv_chip_power9_isa_create; 2157 k->dt_populate = pnv_chip_power9_dt_populate; 2158 k->pic_print_info = pnv_chip_power9_pic_print_info; 2159 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 2160 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 2161 dc->desc = "PowerNV Chip POWER9"; 2162 k->num_pecs = PNV9_CHIP_MAX_PEC; 2163 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 2164 k->i2c_ports_per_engine = i2c_ports_per_engine; 2165 2166 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 2167 &k->parent_realize); 2168 } 2169 2170 static void pnv_chip_power10_instance_init(Object *obj) 2171 { 2172 PnvChip *chip = PNV_CHIP(obj); 2173 Pnv10Chip *chip10 = PNV10_CHIP(obj); 2174 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 2175 int i; 2176 2177 object_initialize_child(obj, "adu", &chip10->adu, TYPE_PNV_ADU); 2178 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 2179 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 2180 "xive-fabric"); 2181 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 2182 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 2183 object_initialize_child(obj, "chiptod", &chip10->chiptod, 2184 TYPE_PNV10_CHIPTOD); 2185 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 2186 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 2187 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 2188 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 2189 TYPE_PNV_N1_CHIPLET); 2190 2191 chip->num_pecs = pcc->num_pecs; 2192 2193 for (i = 0; i < chip->num_pecs; i++) { 2194 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 2195 TYPE_PNV_PHB5_PEC); 2196 } 2197 2198 for (i = 0; i < pcc->i2c_num_engines; i++) { 2199 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 2200 } 2201 2202 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { 2203 object_initialize_child(obj, "pib_spic[*]", &chip10->pib_spic[i], 2204 TYPE_PNV_SPI); 2205 } 2206 } 2207 2208 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 2209 { 2210 PnvChip *chip = PNV_CHIP(chip10); 2211 int i; 2212 2213 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 2214 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 2215 2216 for (i = 0; i < chip10->nr_quads; i++) { 2217 PnvQuad *eq = &chip10->quads[i]; 2218 2219 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 2220 PNV_QUAD_TYPE_NAME("power10")); 2221 2222 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 2223 &eq->xscom_regs); 2224 2225 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 2226 &eq->xscom_qme_regs); 2227 } 2228 } 2229 2230 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 2231 { 2232 Pnv10Chip *chip10 = PNV10_CHIP(chip); 2233 int i; 2234 2235 for (i = 0; i < chip->num_pecs; i++) { 2236 PnvPhb4PecState *pec = &chip10->pecs[i]; 2237 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 2238 uint32_t pec_cplt_base; 2239 uint32_t pec_nest_base; 2240 uint32_t pec_pci_base; 2241 2242 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 2243 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 2244 &error_fatal); 2245 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 2246 &error_fatal); 2247 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 2248 return; 2249 } 2250 2251 pec_cplt_base = pecc->xscom_cplt_base(pec); 2252 pec_nest_base = pecc->xscom_nest_base(pec); 2253 pec_pci_base = pecc->xscom_pci_base(pec); 2254 2255 pnv_xscom_add_subregion(chip, pec_cplt_base, 2256 &pec->nest_pervasive.xscom_ctrl_regs_mr); 2257 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 2258 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 2259 } 2260 } 2261 2262 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 2263 { 2264 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 2265 PnvChip *chip = PNV_CHIP(dev); 2266 Pnv10Chip *chip10 = PNV10_CHIP(dev); 2267 PowerPCCPU *cpu; 2268 PowerPCCPUClass *cpu_class; 2269 Error *local_err = NULL; 2270 int i; 2271 2272 /* XSCOM bridge is first */ 2273 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 2274 2275 pcc->parent_realize(dev, &local_err); 2276 if (local_err) { 2277 error_propagate(errp, local_err); 2278 return; 2279 } 2280 2281 /* ADU */ 2282 object_property_set_link(OBJECT(&chip10->adu), "lpc", OBJECT(&chip10->lpc), 2283 &error_abort); 2284 if (!qdev_realize(DEVICE(&chip10->adu), NULL, errp)) { 2285 return; 2286 } 2287 pnv_xscom_add_subregion(chip, PNV10_XSCOM_ADU_BASE, 2288 &chip10->adu.xscom_regs); 2289 2290 pnv_chip_power10_quad_realize(chip10, &local_err); 2291 if (local_err) { 2292 error_propagate(errp, local_err); 2293 return; 2294 } 2295 2296 /* Set handlers for Special registers, such as SPRD */ 2297 cpu = chip->cores[0]->threads[0]; 2298 cpu_class = POWERPC_CPU_GET_CLASS(cpu); 2299 cpu_class->load_sprd = pnv_handle_sprd_load; 2300 cpu_class->store_sprd = pnv_handle_sprd_store; 2301 2302 /* XIVE2 interrupt controller (POWER10) */ 2303 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 2304 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 2305 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 2306 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 2307 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 2308 PNV10_XIVE2_END_BASE(chip), &error_fatal); 2309 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 2310 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 2311 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 2312 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 2313 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 2314 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 2315 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 2316 &error_abort); 2317 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 2318 return; 2319 } 2320 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 2321 &chip10->xive.xscom_regs); 2322 2323 /* Processor Service Interface (PSI) Host Bridge */ 2324 object_property_set_int(OBJECT(&chip10->psi), "bar", 2325 PNV10_PSIHB_BASE(chip), &error_fatal); 2326 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 2327 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 2328 &error_fatal); 2329 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 2330 return; 2331 } 2332 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 2333 &PNV_PSI(&chip10->psi)->xscom_regs); 2334 2335 /* LPC */ 2336 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 2337 return; 2338 } 2339 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 2340 &chip10->lpc.xscom_regs); 2341 2342 chip->fw_mr = &chip10->lpc.isa_fw; 2343 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 2344 (uint64_t) PNV10_LPCM_BASE(chip)); 2345 2346 /* ChipTOD */ 2347 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 2348 chip->chip_id == 0, &error_abort); 2349 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 2350 chip->chip_id == 1, &error_abort); 2351 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 2352 &error_abort); 2353 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 2354 return; 2355 } 2356 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 2357 &chip10->chiptod.xscom_regs); 2358 2359 /* HOMER (must be created before OCC) */ 2360 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 2361 &error_abort); 2362 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 2363 return; 2364 } 2365 /* Homer Xscom region */ 2366 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 2367 &chip10->homer.pba_regs); 2368 /* Homer RAM region */ 2369 memory_region_add_subregion(get_system_memory(), chip10->homer.base, 2370 &chip10->homer.mem); 2371 2372 /* Create the simplified OCC model */ 2373 object_property_set_link(OBJECT(&chip10->occ), "homer", 2374 OBJECT(&chip10->homer), &error_abort); 2375 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 2376 return; 2377 } 2378 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 2379 &chip10->occ.xscom_regs); 2380 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 2381 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 2382 2383 /* OCC SRAM model */ 2384 memory_region_add_subregion(get_system_memory(), 2385 PNV10_OCC_SENSOR_BASE(chip), 2386 &chip10->occ.sram_regs); 2387 2388 /* SBE */ 2389 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 2390 return; 2391 } 2392 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 2393 &chip10->sbe.xscom_ctrl_regs); 2394 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 2395 &chip10->sbe.xscom_mbox_regs); 2396 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 2397 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 2398 2399 /* N1 chiplet */ 2400 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2401 return; 2402 } 2403 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2404 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2405 2406 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2407 &chip10->n1_chiplet.xscom_pb_eq_mr); 2408 2409 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2410 &chip10->n1_chiplet.xscom_pb_es_mr); 2411 2412 /* PHBs */ 2413 pnv_chip_power10_phb_realize(chip, &local_err); 2414 if (local_err) { 2415 error_propagate(errp, local_err); 2416 return; 2417 } 2418 2419 2420 /* 2421 * I2C 2422 */ 2423 for (i = 0; i < pcc->i2c_num_engines; i++) { 2424 Object *obj = OBJECT(&chip10->i2c[i]); 2425 2426 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2427 object_property_set_int(obj, "num-busses", 2428 pcc->i2c_ports_per_engine[i], 2429 &error_fatal); 2430 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2431 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2432 return; 2433 } 2434 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2435 (chip10->i2c[i].engine - 1) * 2436 PNV10_XSCOM_I2CM_SIZE, 2437 &chip10->i2c[i].xscom_regs); 2438 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2439 qdev_get_gpio_in(DEVICE(&chip10->psi), 2440 PSIHB9_IRQ_SBE_I2C)); 2441 } 2442 /* PIB SPI Controller */ 2443 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { 2444 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "spic_num", 2445 i, &error_fatal); 2446 /* pib_spic[2] connected to 25csm04 which implements 1 byte transfer */ 2447 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "transfer_len", 2448 (i == 2) ? 1 : 4, &error_fatal); 2449 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "chip-id", 2450 chip->chip_id, &error_fatal); 2451 if (!sysbus_realize(SYS_BUS_DEVICE(OBJECT 2452 (&chip10->pib_spic[i])), errp)) { 2453 return; 2454 } 2455 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PIB_SPIC_BASE + 2456 i * PNV10_XSCOM_PIB_SPIC_SIZE, 2457 &chip10->pib_spic[i].xscom_spic_regs); 2458 } 2459 } 2460 2461 static void pnv_chip_power11_instance_init(Object *obj) 2462 { 2463 PnvChip *chip = PNV_CHIP(obj); 2464 Pnv11Chip *chip11 = PNV11_CHIP(obj); 2465 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 2466 int i; 2467 2468 object_initialize_child(obj, "adu", &chip11->adu, TYPE_PNV_ADU); 2469 2470 /* 2471 * Use Power10 device models for PSI/LPC/OCC/SBE/HOMER as corresponding 2472 * device models for Power11 are same 2473 */ 2474 object_initialize_child(obj, "psi", &chip11->psi, TYPE_PNV10_PSI); 2475 object_initialize_child(obj, "lpc", &chip11->lpc, TYPE_PNV10_LPC); 2476 object_initialize_child(obj, "occ", &chip11->occ, TYPE_PNV10_OCC); 2477 object_initialize_child(obj, "sbe", &chip11->sbe, TYPE_PNV10_SBE); 2478 object_initialize_child(obj, "homer", &chip11->homer, TYPE_PNV10_HOMER); 2479 2480 object_initialize_child(obj, "xive", &chip11->xive, TYPE_PNV_XIVE2); 2481 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip11->xive), 2482 "xive-fabric"); 2483 object_initialize_child(obj, "chiptod", &chip11->chiptod, 2484 TYPE_PNV11_CHIPTOD); 2485 object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet, 2486 TYPE_PNV_N1_CHIPLET); 2487 2488 chip->num_pecs = pcc->num_pecs; 2489 2490 for (i = 0; i < chip->num_pecs; i++) { 2491 object_initialize_child(obj, "pec[*]", &chip11->pecs[i], 2492 TYPE_PNV_PHB5_PEC); 2493 } 2494 2495 for (i = 0; i < pcc->i2c_num_engines; i++) { 2496 object_initialize_child(obj, "i2c[*]", &chip11->i2c[i], TYPE_PNV_I2C); 2497 } 2498 2499 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { 2500 object_initialize_child(obj, "pib_spic[*]", &chip11->pib_spic[i], 2501 TYPE_PNV_SPI); 2502 } 2503 } 2504 2505 static void pnv_chip_power11_quad_realize(Pnv11Chip *chip11, Error **errp) 2506 { 2507 PnvChip *chip = PNV_CHIP(chip11); 2508 int i; 2509 2510 chip11->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 2511 chip11->quads = g_new0(PnvQuad, chip11->nr_quads); 2512 2513 for (i = 0; i < chip11->nr_quads; i++) { 2514 PnvQuad *eq = &chip11->quads[i]; 2515 2516 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 2517 PNV_QUAD_TYPE_NAME("power11")); 2518 2519 pnv_xscom_add_subregion(chip, PNV11_XSCOM_EQ_BASE(eq->quad_id), 2520 &eq->xscom_regs); 2521 2522 pnv_xscom_add_subregion(chip, PNV11_XSCOM_QME_BASE(eq->quad_id), 2523 &eq->xscom_qme_regs); 2524 } 2525 } 2526 2527 static void pnv_chip_power11_phb_realize(PnvChip *chip, Error **errp) 2528 { 2529 Pnv11Chip *chip11 = PNV11_CHIP(chip); 2530 int i; 2531 2532 for (i = 0; i < chip->num_pecs; i++) { 2533 PnvPhb4PecState *pec = &chip11->pecs[i]; 2534 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 2535 uint32_t pec_cplt_base; 2536 uint32_t pec_nest_base; 2537 uint32_t pec_pci_base; 2538 2539 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 2540 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 2541 &error_fatal); 2542 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 2543 &error_fatal); 2544 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 2545 return; 2546 } 2547 2548 pec_cplt_base = pecc->xscom_cplt_base(pec); 2549 pec_nest_base = pecc->xscom_nest_base(pec); 2550 pec_pci_base = pecc->xscom_pci_base(pec); 2551 2552 pnv_xscom_add_subregion(chip, pec_cplt_base, 2553 &pec->nest_pervasive.xscom_ctrl_regs_mr); 2554 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 2555 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 2556 } 2557 } 2558 2559 static void pnv_chip_power11_realize(DeviceState *dev, Error **errp) 2560 { 2561 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 2562 PnvChip *chip = PNV_CHIP(dev); 2563 Pnv11Chip *chip11 = PNV11_CHIP(dev); 2564 PowerPCCPU *cpu; 2565 PowerPCCPUClass *cpu_class; 2566 Error *local_err = NULL; 2567 int i; 2568 2569 /* XSCOM bridge is first */ 2570 pnv_xscom_init(chip, PNV11_XSCOM_SIZE, PNV11_XSCOM_BASE(chip)); 2571 2572 pcc->parent_realize(dev, &local_err); 2573 if (local_err) { 2574 error_propagate(errp, local_err); 2575 return; 2576 } 2577 2578 /* Set handlers for Special registers, such as SPRD */ 2579 cpu = chip->cores[0]->threads[0]; 2580 cpu_class = POWERPC_CPU_GET_CLASS(cpu); 2581 cpu_class->load_sprd = pnv_handle_sprd_load; 2582 cpu_class->store_sprd = pnv_handle_sprd_store; 2583 2584 /* ADU */ 2585 object_property_set_link(OBJECT(&chip11->adu), "lpc", OBJECT(&chip11->lpc), 2586 &error_abort); 2587 if (!qdev_realize(DEVICE(&chip11->adu), NULL, errp)) { 2588 return; 2589 } 2590 pnv_xscom_add_subregion(chip, PNV11_XSCOM_ADU_BASE, 2591 &chip11->adu.xscom_regs); 2592 2593 pnv_chip_power11_quad_realize(chip11, &local_err); 2594 if (local_err) { 2595 error_propagate(errp, local_err); 2596 return; 2597 } 2598 2599 /* XIVE2 interrupt controller */ 2600 object_property_set_int(OBJECT(&chip11->xive), "ic-bar", 2601 PNV11_XIVE2_IC_BASE(chip), &error_fatal); 2602 object_property_set_int(OBJECT(&chip11->xive), "esb-bar", 2603 PNV11_XIVE2_ESB_BASE(chip), &error_fatal); 2604 object_property_set_int(OBJECT(&chip11->xive), "end-bar", 2605 PNV11_XIVE2_END_BASE(chip), &error_fatal); 2606 object_property_set_int(OBJECT(&chip11->xive), "nvpg-bar", 2607 PNV11_XIVE2_NVPG_BASE(chip), &error_fatal); 2608 object_property_set_int(OBJECT(&chip11->xive), "nvc-bar", 2609 PNV11_XIVE2_NVC_BASE(chip), &error_fatal); 2610 object_property_set_int(OBJECT(&chip11->xive), "tm-bar", 2611 PNV11_XIVE2_TM_BASE(chip), &error_fatal); 2612 object_property_set_link(OBJECT(&chip11->xive), "chip", OBJECT(chip), 2613 &error_abort); 2614 if (!sysbus_realize(SYS_BUS_DEVICE(&chip11->xive), errp)) { 2615 return; 2616 } 2617 pnv_xscom_add_subregion(chip, PNV11_XSCOM_XIVE2_BASE, 2618 &chip11->xive.xscom_regs); 2619 2620 /* Processor Service Interface (PSI) Host Bridge */ 2621 object_property_set_int(OBJECT(&chip11->psi), "bar", 2622 PNV11_PSIHB_BASE(chip), &error_fatal); 2623 /* PSI can be configured to use 64k ESB pages on Power11 */ 2624 object_property_set_int(OBJECT(&chip11->psi), "shift", XIVE_ESB_64K, 2625 &error_fatal); 2626 if (!qdev_realize(DEVICE(&chip11->psi), NULL, errp)) { 2627 return; 2628 } 2629 pnv_xscom_add_subregion(chip, PNV11_XSCOM_PSIHB_BASE, 2630 &PNV_PSI(&chip11->psi)->xscom_regs); 2631 2632 /* LPC */ 2633 if (!qdev_realize(DEVICE(&chip11->lpc), NULL, errp)) { 2634 return; 2635 } 2636 memory_region_add_subregion(get_system_memory(), PNV11_LPCM_BASE(chip), 2637 &chip11->lpc.xscom_regs); 2638 2639 chip->fw_mr = &chip11->lpc.isa_fw; 2640 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 2641 (uint64_t) PNV11_LPCM_BASE(chip)); 2642 2643 /* ChipTOD */ 2644 object_property_set_bool(OBJECT(&chip11->chiptod), "primary", 2645 chip->chip_id == 0, &error_abort); 2646 object_property_set_bool(OBJECT(&chip11->chiptod), "secondary", 2647 chip->chip_id == 1, &error_abort); 2648 object_property_set_link(OBJECT(&chip11->chiptod), "chip", OBJECT(chip), 2649 &error_abort); 2650 if (!qdev_realize(DEVICE(&chip11->chiptod), NULL, errp)) { 2651 return; 2652 } 2653 pnv_xscom_add_subregion(chip, PNV11_XSCOM_CHIPTOD_BASE, 2654 &chip11->chiptod.xscom_regs); 2655 2656 /* HOMER (must be created before OCC) */ 2657 object_property_set_link(OBJECT(&chip11->homer), "chip", OBJECT(chip), 2658 &error_abort); 2659 if (!qdev_realize(DEVICE(&chip11->homer), NULL, errp)) { 2660 return; 2661 } 2662 /* Homer Xscom region */ 2663 pnv_xscom_add_subregion(chip, PNV11_XSCOM_PBA_BASE, 2664 &chip11->homer.pba_regs); 2665 /* Homer RAM region */ 2666 memory_region_add_subregion(get_system_memory(), chip11->homer.base, 2667 &chip11->homer.mem); 2668 2669 /* Create the simplified OCC model */ 2670 object_property_set_link(OBJECT(&chip11->occ), "homer", 2671 OBJECT(&chip11->homer), &error_abort); 2672 if (!qdev_realize(DEVICE(&chip11->occ), NULL, errp)) { 2673 return; 2674 } 2675 pnv_xscom_add_subregion(chip, PNV11_XSCOM_OCC_BASE, 2676 &chip11->occ.xscom_regs); 2677 qdev_connect_gpio_out(DEVICE(&chip11->occ), 0, qdev_get_gpio_in( 2678 DEVICE(&chip11->psi), PSIHB9_IRQ_OCC)); 2679 2680 /* OCC SRAM model */ 2681 memory_region_add_subregion(get_system_memory(), 2682 PNV11_OCC_SENSOR_BASE(chip), 2683 &chip11->occ.sram_regs); 2684 2685 /* SBE */ 2686 if (!qdev_realize(DEVICE(&chip11->sbe), NULL, errp)) { 2687 return; 2688 } 2689 pnv_xscom_add_subregion(chip, PNV11_XSCOM_SBE_CTRL_BASE, 2690 &chip11->sbe.xscom_ctrl_regs); 2691 pnv_xscom_add_subregion(chip, PNV11_XSCOM_SBE_MBOX_BASE, 2692 &chip11->sbe.xscom_mbox_regs); 2693 qdev_connect_gpio_out(DEVICE(&chip11->sbe), 0, qdev_get_gpio_in( 2694 DEVICE(&chip11->psi), PSIHB9_IRQ_PSU)); 2695 2696 /* N1 chiplet */ 2697 if (!qdev_realize(DEVICE(&chip11->n1_chiplet), NULL, errp)) { 2698 return; 2699 } 2700 pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2701 &chip11->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2702 2703 pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_PB_SCOM_EQ_BASE, 2704 &chip11->n1_chiplet.xscom_pb_eq_mr); 2705 2706 pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_PB_SCOM_ES_BASE, 2707 &chip11->n1_chiplet.xscom_pb_es_mr); 2708 2709 /* PHBs */ 2710 pnv_chip_power11_phb_realize(chip, &local_err); 2711 if (local_err) { 2712 error_propagate(errp, local_err); 2713 return; 2714 } 2715 2716 /* 2717 * I2C 2718 */ 2719 for (i = 0; i < pcc->i2c_num_engines; i++) { 2720 Object *obj = OBJECT(&chip11->i2c[i]); 2721 2722 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2723 object_property_set_int(obj, "num-busses", 2724 pcc->i2c_ports_per_engine[i], 2725 &error_fatal); 2726 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2727 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2728 return; 2729 } 2730 pnv_xscom_add_subregion(chip, PNV11_XSCOM_I2CM_BASE + 2731 (chip11->i2c[i].engine - 1) * 2732 PNV11_XSCOM_I2CM_SIZE, 2733 &chip11->i2c[i].xscom_regs); 2734 qdev_connect_gpio_out(DEVICE(&chip11->i2c[i]), 0, 2735 qdev_get_gpio_in(DEVICE(&chip11->psi), 2736 PSIHB9_IRQ_SBE_I2C)); 2737 } 2738 /* PIB SPI Controller */ 2739 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { 2740 object_property_set_int(OBJECT(&chip11->pib_spic[i]), "spic_num", 2741 i, &error_fatal); 2742 /* pib_spic[2] connected to 25csm04 which implements 1 byte transfer */ 2743 object_property_set_int(OBJECT(&chip11->pib_spic[i]), "transfer_len", 2744 (i == 2) ? 1 : 4, &error_fatal); 2745 object_property_set_int(OBJECT(&chip11->pib_spic[i]), "chip-id", 2746 chip->chip_id, &error_fatal); 2747 if (!sysbus_realize(SYS_BUS_DEVICE(OBJECT 2748 (&chip11->pib_spic[i])), errp)) { 2749 return; 2750 } 2751 pnv_xscom_add_subregion(chip, PNV11_XSCOM_PIB_SPIC_BASE + 2752 i * PNV11_XSCOM_PIB_SPIC_SIZE, 2753 &chip11->pib_spic[i].xscom_spic_regs); 2754 } 2755 } 2756 2757 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2758 { 2759 int i; 2760 for (i = 0; i < pnv->num_chips; i++) { 2761 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2762 2763 /* 2764 * Add a PCA9552 I2C device for PCIe hotplug control 2765 * to engine 2, bus 1, address 0x63 2766 */ 2767 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2768 "pca9552", 0x63); 2769 2770 /* 2771 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2772 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2773 * after hypervisor code sets a SLOTx_EN pin high. 2774 */ 2775 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2776 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2777 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2778 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2779 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2780 2781 /* 2782 * Add a PCA9554 I2C device for cable card presence detection 2783 * to engine 2, bus 1, address 0x25 2784 */ 2785 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2786 } 2787 } 2788 2789 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2790 { 2791 addr &= (PNV10_XSCOM_SIZE - 1); 2792 return addr >> 3; 2793 } 2794 2795 static void pnv_chip_power10_class_init(ObjectClass *klass, const void *data) 2796 { 2797 DeviceClass *dc = DEVICE_CLASS(klass); 2798 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2799 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2800 2801 k->chip_cfam_id = 0x220da04980000000ull; /* P10 DD2.0 (with NX) */ 2802 k->cores_mask = POWER10_CORE_MASK; 2803 k->get_pir_tir = pnv_get_pir_tir_p10; 2804 k->intc_create = pnv_chip_power10_intc_create; 2805 k->intc_reset = pnv_chip_power10_intc_reset; 2806 k->intc_destroy = pnv_chip_power10_intc_destroy; 2807 k->intc_print_info = pnv_chip_power10_intc_print_info; 2808 k->intc_get = pnv_chip_power10_intc_get; 2809 k->isa_create = pnv_chip_power10_isa_create; 2810 k->dt_populate = pnv_chip_power10_dt_populate; 2811 k->pic_print_info = pnv_chip_power10_pic_print_info; 2812 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2813 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2814 dc->desc = "PowerNV Chip POWER10"; 2815 k->num_pecs = PNV10_CHIP_MAX_PEC; 2816 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2817 k->i2c_ports_per_engine = i2c_ports_per_engine; 2818 2819 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2820 &k->parent_realize); 2821 } 2822 2823 static uint32_t pnv_chip_power11_xscom_pcba(PnvChip *chip, uint64_t addr) 2824 { 2825 addr &= (PNV11_XSCOM_SIZE - 1); 2826 return addr >> 3; 2827 } 2828 2829 static void pnv_chip_power11_class_init(ObjectClass *klass, const void *data) 2830 { 2831 DeviceClass *dc = DEVICE_CLASS(klass); 2832 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2833 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2834 2835 k->chip_cfam_id = 0x220da04980000000ull; /* P11 DD2.0 (with NX) */ 2836 k->cores_mask = POWER11_CORE_MASK; 2837 k->get_pir_tir = pnv_get_pir_tir_p10; 2838 k->intc_create = pnv_chip_power11_intc_create; 2839 k->intc_reset = pnv_chip_power11_intc_reset; 2840 k->intc_destroy = pnv_chip_power11_intc_destroy; 2841 k->intc_print_info = pnv_chip_power11_intc_print_info; 2842 k->intc_get = pnv_chip_power11_intc_get; 2843 k->isa_create = pnv_chip_power11_isa_create; 2844 k->dt_populate = pnv_chip_power11_dt_populate; 2845 k->pic_print_info = pnv_chip_power11_pic_print_info; 2846 k->xscom_core_base = pnv_chip_power11_xscom_core_base; 2847 k->xscom_pcba = pnv_chip_power11_xscom_pcba; 2848 dc->desc = "PowerNV Chip Power11"; 2849 k->num_pecs = PNV10_CHIP_MAX_PEC; 2850 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2851 k->i2c_ports_per_engine = i2c_ports_per_engine; 2852 2853 device_class_set_parent_realize(dc, pnv_chip_power11_realize, 2854 &k->parent_realize); 2855 } 2856 2857 static void pnv_chip_core_sanitize(PnvMachineState *pnv, PnvChip *chip, 2858 Error **errp) 2859 { 2860 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2861 int cores_max; 2862 2863 /* 2864 * No custom mask for this chip, let's use the default one from * 2865 * the chip class 2866 */ 2867 if (!chip->cores_mask) { 2868 chip->cores_mask = pcc->cores_mask; 2869 } 2870 2871 /* filter alien core ids ! some are reserved */ 2872 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2873 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2874 chip->cores_mask); 2875 return; 2876 } 2877 chip->cores_mask &= pcc->cores_mask; 2878 2879 /* Ensure small-cores a paired up in big-core mode */ 2880 if (pnv->big_core) { 2881 uint64_t even_cores = chip->cores_mask & 0x5555555555555555ULL; 2882 uint64_t odd_cores = chip->cores_mask & 0xaaaaaaaaaaaaaaaaULL; 2883 2884 if (even_cores ^ (odd_cores >> 1)) { 2885 error_setg(errp, "warning: unpaired cores in big-core mode !"); 2886 return; 2887 } 2888 } 2889 2890 /* now that we have a sane layout, let check the number of cores */ 2891 cores_max = ctpop64(chip->cores_mask); 2892 if (chip->nr_cores > cores_max) { 2893 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2894 cores_max); 2895 return; 2896 } 2897 } 2898 2899 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2900 { 2901 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2902 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(pnv); 2903 Error *error = NULL; 2904 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2905 const char *typename = pnv_chip_core_typename(chip); 2906 int i, core_hwid; 2907 2908 if (!object_class_by_name(typename)) { 2909 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2910 return; 2911 } 2912 2913 /* Cores */ 2914 pnv_chip_core_sanitize(pnv, chip, &error); 2915 if (error) { 2916 error_propagate(errp, error); 2917 return; 2918 } 2919 2920 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2921 2922 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2923 && (i < chip->nr_cores); core_hwid++) { 2924 char core_name[32]; 2925 PnvCore *pnv_core; 2926 uint64_t xscom_core_base; 2927 2928 if (!(chip->cores_mask & (1ull << core_hwid))) { 2929 continue; 2930 } 2931 2932 pnv_core = PNV_CORE(object_new(typename)); 2933 2934 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2935 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2936 chip->cores[i] = pnv_core; 2937 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2938 chip->nr_threads, &error_fatal); 2939 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2940 core_hwid, &error_fatal); 2941 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2942 &error_fatal); 2943 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2944 &error_fatal); 2945 object_property_set_bool(OBJECT(pnv_core), "big-core", chip->big_core, 2946 &error_fatal); 2947 object_property_set_bool(OBJECT(pnv_core), "quirk-tb-big-core", 2948 pmc->quirk_tb_big_core, &error_fatal); 2949 object_property_set_bool(OBJECT(pnv_core), "lpar-per-core", 2950 chip->lpar_per_core, &error_fatal); 2951 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2952 &error_abort); 2953 2954 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2955 2956 /* Each core has an XSCOM MMIO region */ 2957 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2958 2959 pnv_xscom_add_subregion(chip, xscom_core_base, 2960 &pnv_core->xscom_regs); 2961 i++; 2962 } 2963 } 2964 2965 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2966 { 2967 PnvChip *chip = PNV_CHIP(dev); 2968 Error *error = NULL; 2969 2970 /* Cores */ 2971 pnv_chip_core_realize(chip, &error); 2972 if (error) { 2973 error_propagate(errp, error); 2974 return; 2975 } 2976 } 2977 2978 static const Property pnv_chip_properties[] = { 2979 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2980 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2981 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2982 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2983 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2984 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2985 DEFINE_PROP_BOOL("big-core", PnvChip, big_core, false), 2986 DEFINE_PROP_BOOL("lpar-per-core", PnvChip, lpar_per_core, false), 2987 }; 2988 2989 static void pnv_chip_class_init(ObjectClass *klass, const void *data) 2990 { 2991 DeviceClass *dc = DEVICE_CLASS(klass); 2992 2993 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2994 dc->realize = pnv_chip_realize; 2995 device_class_set_props(dc, pnv_chip_properties); 2996 dc->desc = "PowerNV Chip"; 2997 } 2998 2999 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 3000 { 3001 int i; 3002 3003 for (i = 0; i < chip->nr_cores; i++) { 3004 PnvCore *pc = chip->cores[i]; 3005 CPUCore *cc = CPU_CORE(pc); 3006 3007 if (cc->core_id == core_id) { 3008 return pc; 3009 } 3010 } 3011 return NULL; 3012 } 3013 3014 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 3015 { 3016 int i, j; 3017 3018 for (i = 0; i < chip->nr_cores; i++) { 3019 PnvCore *pc = chip->cores[i]; 3020 CPUCore *cc = CPU_CORE(pc); 3021 3022 for (j = 0; j < cc->nr_threads; j++) { 3023 if (ppc_cpu_pir(pc->threads[j]) == pir) { 3024 return pc->threads[j]; 3025 } 3026 } 3027 } 3028 return NULL; 3029 } 3030 3031 static void pnv_chip_foreach_cpu(PnvChip *chip, 3032 void (*fn)(PnvChip *chip, PowerPCCPU *cpu, void *opaque), 3033 void *opaque) 3034 { 3035 int i, j; 3036 3037 for (i = 0; i < chip->nr_cores; i++) { 3038 PnvCore *pc = chip->cores[i]; 3039 3040 for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) { 3041 fn(chip, pc->threads[j], opaque); 3042 } 3043 } 3044 } 3045 3046 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 3047 { 3048 PnvMachineState *pnv = PNV_MACHINE(xi); 3049 int i, j; 3050 3051 for (i = 0; i < pnv->num_chips; i++) { 3052 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 3053 3054 if (ics_valid_irq(&chip8->psi.ics, irq)) { 3055 return &chip8->psi.ics; 3056 } 3057 3058 for (j = 0; j < chip8->num_phbs; j++) { 3059 PnvPHB *phb = chip8->phbs[j]; 3060 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 3061 3062 if (ics_valid_irq(&phb3->lsis, irq)) { 3063 return &phb3->lsis; 3064 } 3065 3066 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 3067 return ICS(&phb3->msis); 3068 } 3069 } 3070 } 3071 return NULL; 3072 } 3073 3074 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 3075 { 3076 int i; 3077 3078 for (i = 0; i < pnv->num_chips; i++) { 3079 PnvChip *chip = pnv->chips[i]; 3080 if (chip->chip_id == chip_id) { 3081 return chip; 3082 } 3083 } 3084 return NULL; 3085 } 3086 3087 static void pnv_ics_resend(XICSFabric *xi) 3088 { 3089 PnvMachineState *pnv = PNV_MACHINE(xi); 3090 int i, j; 3091 3092 for (i = 0; i < pnv->num_chips; i++) { 3093 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 3094 3095 ics_resend(&chip8->psi.ics); 3096 3097 for (j = 0; j < chip8->num_phbs; j++) { 3098 PnvPHB *phb = chip8->phbs[j]; 3099 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 3100 3101 ics_resend(&phb3->lsis); 3102 ics_resend(ICS(&phb3->msis)); 3103 } 3104 } 3105 } 3106 3107 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 3108 { 3109 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 3110 3111 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 3112 } 3113 3114 static void pnv_pic_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 3115 void *opaque) 3116 { 3117 PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque); 3118 } 3119 3120 static void pnv_pic_print_info(InterruptStatsProvider *obj, GString *buf) 3121 { 3122 PnvMachineState *pnv = PNV_MACHINE(obj); 3123 int i; 3124 3125 for (i = 0; i < pnv->num_chips; i++) { 3126 PnvChip *chip = pnv->chips[i]; 3127 3128 /* First CPU presenters */ 3129 pnv_chip_foreach_cpu(chip, pnv_pic_intc_print_info, buf); 3130 3131 /* Then other devices, PHB, PSI, XIVE */ 3132 PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf); 3133 } 3134 } 3135 3136 static bool pnv_match_nvt(XiveFabric *xfb, uint8_t format, 3137 uint8_t nvt_blk, uint32_t nvt_idx, 3138 bool crowd, bool cam_ignore, uint8_t priority, 3139 uint32_t logic_serv, 3140 XiveTCTXMatch *match) 3141 { 3142 PnvMachineState *pnv = PNV_MACHINE(xfb); 3143 int i; 3144 3145 for (i = 0; i < pnv->num_chips; i++) { 3146 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 3147 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 3148 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 3149 3150 xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, 3151 cam_ignore, priority, logic_serv, match); 3152 } 3153 3154 return !!match->count; 3155 } 3156 3157 static bool pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 3158 uint8_t nvt_blk, uint32_t nvt_idx, 3159 bool crowd, bool cam_ignore, uint8_t priority, 3160 uint32_t logic_serv, 3161 XiveTCTXMatch *match) 3162 { 3163 PnvMachineState *pnv = PNV_MACHINE(xfb); 3164 int i; 3165 3166 for (i = 0; i < pnv->num_chips; i++) { 3167 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 3168 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 3169 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 3170 3171 xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, 3172 cam_ignore, priority, logic_serv, match); 3173 } 3174 3175 return !!match->count; 3176 } 3177 3178 static int pnv10_xive_broadcast(XiveFabric *xfb, 3179 uint8_t nvt_blk, uint32_t nvt_idx, 3180 bool crowd, bool cam_ignore, 3181 uint8_t priority) 3182 { 3183 PnvMachineState *pnv = PNV_MACHINE(xfb); 3184 int i; 3185 3186 for (i = 0; i < pnv->num_chips; i++) { 3187 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 3188 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 3189 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 3190 3191 xpc->broadcast(xptr, nvt_blk, nvt_idx, crowd, cam_ignore, priority); 3192 } 3193 return 0; 3194 } 3195 3196 static bool pnv11_xive_match_nvt(XiveFabric *xfb, uint8_t format, 3197 uint8_t nvt_blk, uint32_t nvt_idx, 3198 bool crowd, bool cam_ignore, uint8_t priority, 3199 uint32_t logic_serv, 3200 XiveTCTXMatch *match) 3201 { 3202 PnvMachineState *pnv = PNV_MACHINE(xfb); 3203 int i; 3204 3205 for (i = 0; i < pnv->num_chips; i++) { 3206 Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]); 3207 XivePresenter *xptr = XIVE_PRESENTER(&chip11->xive); 3208 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 3209 3210 xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, 3211 cam_ignore, priority, logic_serv, match); 3212 } 3213 3214 return !!match->count; 3215 } 3216 3217 static int pnv11_xive_broadcast(XiveFabric *xfb, 3218 uint8_t nvt_blk, uint32_t nvt_idx, 3219 bool crowd, bool cam_ignore, 3220 uint8_t priority) 3221 { 3222 PnvMachineState *pnv = PNV_MACHINE(xfb); 3223 int i; 3224 3225 for (i = 0; i < pnv->num_chips; i++) { 3226 Pnv11Chip *chip11 = PNV11_CHIP(pnv->chips[i]); 3227 XivePresenter *xptr = XIVE_PRESENTER(&chip11->xive); 3228 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 3229 3230 xpc->broadcast(xptr, nvt_blk, nvt_idx, crowd, cam_ignore, priority); 3231 } 3232 return 0; 3233 } 3234 3235 static bool pnv_machine_get_big_core(Object *obj, Error **errp) 3236 { 3237 PnvMachineState *pnv = PNV_MACHINE(obj); 3238 return pnv->big_core; 3239 } 3240 3241 static void pnv_machine_set_big_core(Object *obj, bool value, Error **errp) 3242 { 3243 PnvMachineState *pnv = PNV_MACHINE(obj); 3244 pnv->big_core = value; 3245 } 3246 3247 static bool pnv_machine_get_lpar_per_core(Object *obj, Error **errp) 3248 { 3249 PnvMachineState *pnv = PNV_MACHINE(obj); 3250 return pnv->lpar_per_core; 3251 } 3252 3253 static void pnv_machine_set_lpar_per_core(Object *obj, bool value, Error **errp) 3254 { 3255 PnvMachineState *pnv = PNV_MACHINE(obj); 3256 pnv->lpar_per_core = value; 3257 } 3258 3259 static bool pnv_machine_get_hb(Object *obj, Error **errp) 3260 { 3261 PnvMachineState *pnv = PNV_MACHINE(obj); 3262 3263 return !!pnv->fw_load_addr; 3264 } 3265 3266 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 3267 { 3268 PnvMachineState *pnv = PNV_MACHINE(obj); 3269 3270 if (value) { 3271 pnv->fw_load_addr = 0x8000000; 3272 } 3273 } 3274 3275 static void pnv_machine_power8_class_init(ObjectClass *oc, const void *data) 3276 { 3277 MachineClass *mc = MACHINE_CLASS(oc); 3278 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3279 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 3280 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 3281 3282 static GlobalProperty phb_compat[] = { 3283 { TYPE_PNV_PHB, "version", "3" }, 3284 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 3285 }; 3286 3287 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 3288 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 3289 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 3290 3291 xic->icp_get = pnv_icp_get; 3292 xic->ics_get = pnv_ics_get; 3293 xic->ics_resend = pnv_ics_resend; 3294 3295 pmc->compat = compat; 3296 pmc->compat_size = sizeof(compat); 3297 pmc->max_smt_threads = 8; 3298 /* POWER8 is always lpar-per-core mode */ 3299 pmc->has_lpar_per_thread = false; 3300 3301 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 3302 } 3303 3304 static void pnv_machine_power9_class_init(ObjectClass *oc, const void *data) 3305 { 3306 MachineClass *mc = MACHINE_CLASS(oc); 3307 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 3308 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 3309 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 3310 3311 static GlobalProperty phb_compat[] = { 3312 { TYPE_PNV_PHB, "version", "4" }, 3313 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 3314 }; 3315 3316 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 3317 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 3318 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 3319 3320 xfc->match_nvt = pnv_match_nvt; 3321 3322 pmc->compat = compat; 3323 pmc->compat_size = sizeof(compat); 3324 pmc->max_smt_threads = 4; 3325 pmc->has_lpar_per_thread = true; 3326 pmc->dt_power_mgt = pnv_dt_power_mgt; 3327 3328 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 3329 3330 object_class_property_add_bool(oc, "big-core", 3331 pnv_machine_get_big_core, 3332 pnv_machine_set_big_core); 3333 object_class_property_set_description(oc, "big-core", 3334 "Use big-core (aka fused-core) mode"); 3335 3336 object_class_property_add_bool(oc, "lpar-per-core", 3337 pnv_machine_get_lpar_per_core, 3338 pnv_machine_set_lpar_per_core); 3339 object_class_property_set_description(oc, "lpar-per-core", 3340 "Use 1 LPAR per core mode"); 3341 } 3342 3343 static void pnv_machine_p10_common_class_init(ObjectClass *oc, const void *data) 3344 { 3345 MachineClass *mc = MACHINE_CLASS(oc); 3346 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 3347 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 3348 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 3349 3350 static GlobalProperty phb_compat[] = { 3351 { TYPE_PNV_PHB, "version", "5" }, 3352 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 3353 }; 3354 3355 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 3356 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 3357 3358 mc->alias = "powernv"; 3359 3360 pmc->compat = compat; 3361 pmc->compat_size = sizeof(compat); 3362 pmc->max_smt_threads = 4; 3363 pmc->has_lpar_per_thread = true; 3364 pmc->quirk_tb_big_core = true; 3365 pmc->dt_power_mgt = pnv_dt_power_mgt; 3366 3367 xfc->match_nvt = pnv10_xive_match_nvt; 3368 xfc->broadcast = pnv10_xive_broadcast; 3369 3370 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 3371 } 3372 3373 static void pnv_machine_power10_class_init(ObjectClass *oc, const void *data) 3374 { 3375 MachineClass *mc = MACHINE_CLASS(oc); 3376 3377 pnv_machine_p10_common_class_init(oc, data); 3378 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 3379 3380 /* 3381 * This is the parent of POWER10 Rainier class, so properies go here 3382 * rather than common init (which would add them to both parent and 3383 * child which is invalid). 3384 */ 3385 object_class_property_add_bool(oc, "big-core", 3386 pnv_machine_get_big_core, 3387 pnv_machine_set_big_core); 3388 object_class_property_set_description(oc, "big-core", 3389 "Use big-core (aka fused-core) mode"); 3390 3391 object_class_property_add_bool(oc, "lpar-per-core", 3392 pnv_machine_get_lpar_per_core, 3393 pnv_machine_set_lpar_per_core); 3394 object_class_property_set_description(oc, "lpar-per-core", 3395 "Use 1 LPAR per core mode"); 3396 } 3397 3398 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, 3399 const void *data) 3400 { 3401 MachineClass *mc = MACHINE_CLASS(oc); 3402 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 3403 3404 pnv_machine_p10_common_class_init(oc, data); 3405 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 3406 pmc->i2c_init = pnv_rainier_i2c_init; 3407 } 3408 3409 static void pnv_machine_power11_class_init(ObjectClass *oc, const void *data) 3410 { 3411 MachineClass *mc = MACHINE_CLASS(oc); 3412 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 3413 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 3414 static const char compat[] = "qemu,powernv11\0ibm,powernv"; 3415 3416 static GlobalProperty phb_compat[] = { 3417 { TYPE_PNV_PHB, "version", "5" }, 3418 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 3419 }; 3420 3421 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 3422 3423 pmc->compat = compat; 3424 pmc->compat_size = sizeof(compat); 3425 pmc->max_smt_threads = 4; 3426 pmc->has_lpar_per_thread = true; 3427 pmc->quirk_tb_big_core = true; 3428 pmc->dt_power_mgt = pnv_dt_power_mgt; 3429 3430 xfc->match_nvt = pnv11_xive_match_nvt; 3431 xfc->broadcast = pnv11_xive_broadcast; 3432 3433 mc->desc = "IBM PowerNV (Non-Virtualized) Power11"; 3434 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11_v2.0"); 3435 3436 object_class_property_add_bool(oc, "big-core", 3437 pnv_machine_get_big_core, 3438 pnv_machine_set_big_core); 3439 object_class_property_set_description(oc, "big-core", 3440 "Use big-core (aka fused-core) mode"); 3441 3442 object_class_property_add_bool(oc, "lpar-per-core", 3443 pnv_machine_get_lpar_per_core, 3444 pnv_machine_set_lpar_per_core); 3445 object_class_property_set_description(oc, "lpar-per-core", 3446 "Use 1 LPAR per core mode"); 3447 } 3448 3449 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 3450 { 3451 CPUPPCState *env = cpu_env(cs); 3452 3453 cpu_synchronize_state(cs); 3454 ppc_cpu_do_system_reset(cs); 3455 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 3456 /* 3457 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 3458 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 3459 * (PPC_BIT(43)). 3460 */ 3461 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 3462 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 3463 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 3464 } 3465 } else { 3466 /* 3467 * For non-powersave system resets, SRR1[42:45] are defined to be 3468 * implementation-dependent. The POWER9 User Manual specifies that 3469 * an external (SCOM driven, which may come from a BMC nmi command or 3470 * another CPU requesting a NMI IPI) system reset exception should be 3471 * 0b0010 (PPC_BIT(44)). 3472 */ 3473 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 3474 } 3475 if (arg.host_int == 1) { 3476 cpu_resume(cs); 3477 } 3478 } 3479 3480 /* 3481 * Send a SRESET (NMI) interrupt to the CPU, and resume execution if it was 3482 * paused. 3483 */ 3484 void pnv_cpu_do_nmi_resume(CPUState *cs) 3485 { 3486 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(1)); 3487 } 3488 3489 static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque) 3490 { 3491 async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(0)); 3492 } 3493 3494 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 3495 { 3496 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 3497 int i; 3498 3499 for (i = 0; i < pnv->num_chips; i++) { 3500 pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL); 3501 } 3502 } 3503 3504 static void pnv_machine_class_init(ObjectClass *oc, const void *data) 3505 { 3506 MachineClass *mc = MACHINE_CLASS(oc); 3507 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3508 NMIClass *nc = NMI_CLASS(oc); 3509 3510 mc->desc = "IBM PowerNV (Non-Virtualized)"; 3511 mc->init = pnv_init; 3512 mc->reset = pnv_reset; 3513 mc->max_cpus = MAX_CPUS; 3514 /* Pnv provides a AHCI device for storage */ 3515 mc->block_default_type = IF_IDE; 3516 mc->no_parallel = 1; 3517 mc->default_boot_order = NULL; 3518 /* 3519 * RAM defaults to less than 2048 for 32-bit hosts, and large 3520 * enough to fit the maximum initrd size at it's load address 3521 */ 3522 mc->default_ram_size = 1 * GiB; 3523 mc->default_ram_id = "pnv.ram"; 3524 ispc->print_info = pnv_pic_print_info; 3525 nc->nmi_monitor_handler = pnv_nmi; 3526 3527 object_class_property_add_bool(oc, "hb-mode", 3528 pnv_machine_get_hb, pnv_machine_set_hb); 3529 object_class_property_set_description(oc, "hb-mode", 3530 "Use a hostboot like boot loader"); 3531 } 3532 3533 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 3534 { \ 3535 .name = type, \ 3536 .class_init = class_initfn, \ 3537 .parent = TYPE_PNV8_CHIP, \ 3538 } 3539 3540 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 3541 { \ 3542 .name = type, \ 3543 .class_init = class_initfn, \ 3544 .parent = TYPE_PNV9_CHIP, \ 3545 } 3546 3547 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 3548 { \ 3549 .name = type, \ 3550 .class_init = class_initfn, \ 3551 .parent = TYPE_PNV10_CHIP, \ 3552 } 3553 3554 #define DEFINE_PNV11_CHIP_TYPE(type, class_initfn) \ 3555 { \ 3556 .name = type, \ 3557 .class_init = class_initfn, \ 3558 .parent = TYPE_PNV11_CHIP, \ 3559 } 3560 3561 static const TypeInfo types[] = { 3562 { 3563 .name = MACHINE_TYPE_NAME("powernv11"), 3564 .parent = TYPE_PNV_MACHINE, 3565 .class_init = pnv_machine_power11_class_init, 3566 .interfaces = (InterfaceInfo[]) { 3567 { TYPE_XIVE_FABRIC }, 3568 { }, 3569 }, 3570 }, 3571 { 3572 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 3573 .parent = MACHINE_TYPE_NAME("powernv10"), 3574 .class_init = pnv_machine_p10_rainier_class_init, 3575 }, 3576 { 3577 .name = MACHINE_TYPE_NAME("powernv10"), 3578 .parent = TYPE_PNV_MACHINE, 3579 .class_init = pnv_machine_power10_class_init, 3580 .interfaces = (const InterfaceInfo[]) { 3581 { TYPE_XIVE_FABRIC }, 3582 { }, 3583 }, 3584 }, 3585 { 3586 .name = MACHINE_TYPE_NAME("powernv9"), 3587 .parent = TYPE_PNV_MACHINE, 3588 .class_init = pnv_machine_power9_class_init, 3589 .interfaces = (const InterfaceInfo[]) { 3590 { TYPE_XIVE_FABRIC }, 3591 { }, 3592 }, 3593 }, 3594 { 3595 .name = MACHINE_TYPE_NAME("powernv8"), 3596 .parent = TYPE_PNV_MACHINE, 3597 .class_init = pnv_machine_power8_class_init, 3598 .interfaces = (const InterfaceInfo[]) { 3599 { TYPE_XICS_FABRIC }, 3600 { }, 3601 }, 3602 }, 3603 { 3604 .name = TYPE_PNV_MACHINE, 3605 .parent = TYPE_MACHINE, 3606 .abstract = true, 3607 .instance_size = sizeof(PnvMachineState), 3608 .class_init = pnv_machine_class_init, 3609 .class_size = sizeof(PnvMachineClass), 3610 .interfaces = (const InterfaceInfo[]) { 3611 { TYPE_INTERRUPT_STATS_PROVIDER }, 3612 { TYPE_NMI }, 3613 { }, 3614 }, 3615 }, 3616 { 3617 .name = TYPE_PNV_CHIP, 3618 .parent = TYPE_SYS_BUS_DEVICE, 3619 .class_init = pnv_chip_class_init, 3620 .instance_size = sizeof(PnvChip), 3621 .class_size = sizeof(PnvChipClass), 3622 .abstract = true, 3623 }, 3624 3625 /* 3626 * P11 chip and variants 3627 */ 3628 { 3629 .name = TYPE_PNV11_CHIP, 3630 .parent = TYPE_PNV_CHIP, 3631 .instance_init = pnv_chip_power11_instance_init, 3632 .instance_size = sizeof(Pnv11Chip), 3633 }, 3634 DEFINE_PNV11_CHIP_TYPE(TYPE_PNV_CHIP_POWER11, pnv_chip_power11_class_init), 3635 3636 /* 3637 * P10 chip and variants 3638 */ 3639 { 3640 .name = TYPE_PNV10_CHIP, 3641 .parent = TYPE_PNV_CHIP, 3642 .instance_init = pnv_chip_power10_instance_init, 3643 .instance_size = sizeof(Pnv10Chip), 3644 }, 3645 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 3646 3647 /* 3648 * P9 chip and variants 3649 */ 3650 { 3651 .name = TYPE_PNV9_CHIP, 3652 .parent = TYPE_PNV_CHIP, 3653 .instance_init = pnv_chip_power9_instance_init, 3654 .instance_size = sizeof(Pnv9Chip), 3655 }, 3656 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 3657 3658 /* 3659 * P8 chip and variants 3660 */ 3661 { 3662 .name = TYPE_PNV8_CHIP, 3663 .parent = TYPE_PNV_CHIP, 3664 .instance_init = pnv_chip_power8_instance_init, 3665 .instance_size = sizeof(Pnv8Chip), 3666 }, 3667 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 3668 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 3669 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 3670 pnv_chip_power8nvl_class_init), 3671 }; 3672 3673 DEFINE_TYPES(types) 3674