1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * vme8349.c -- esd VME8349 board support
4 *
5 * Copyright (c) 2008-2009 esd gmbh.
6 *
7 * (C) Copyright 2006
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
11 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
12 */
13
14 #include <common.h>
15 #include <ioports.h>
16 #include <mpc83xx.h>
17 #include <asm/mpc8349_pci.h>
18 #if defined(CONFIG_OF_LIBFDT)
19 #include <linux/libfdt.h>
20 #endif
21 #include <asm/io.h>
22 #include <asm/mmu.h>
23 #include <spd.h>
24 #include <spd_sdram.h>
25 #include <i2c.h>
26 #include <netdev.h>
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 void ddr_enable_ecc(unsigned int dram_size);
31
dram_init(void)32 int dram_init(void)
33 {
34 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
35 u32 msize = 0;
36
37 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
38 return -ENXIO;
39
40 /* DDR SDRAM - Main memory */
41 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
42
43 msize = spd_sdram();
44
45 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
46 /*
47 * Initialize and enable DDR ECC.
48 */
49 ddr_enable_ecc(msize * 1024 * 1024);
50 #endif
51
52 /* Now check memory size (after ECC is initialized) */
53 msize = get_ram_size(0, msize);
54
55 /* return total bus SDRAM size(bytes) -- DDR */
56 gd->ram_size = msize * 1024 * 1024;
57
58 return 0;
59 }
60
checkboard(void)61 int checkboard(void)
62 {
63 #ifdef VME_CADDY2
64 puts("Board: esd VME-CADDY/2\n");
65 #else
66 puts("Board: esd VME-CPU/8349\n");
67 #endif
68
69 return 0;
70 }
71
72 #ifdef VME_CADDY2
board_eth_init(bd_t * bis)73 int board_eth_init(bd_t *bis)
74 {
75 return pci_eth_init(bis);
76 }
77 #endif
78
79 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)80 int ft_board_setup(void *blob, bd_t *bd)
81 {
82 ft_cpu_setup(blob, bd);
83
84 #ifdef CONFIG_PCI
85 ft_pci_setup(blob, bd);
86 #endif
87
88 return 0;
89 }
90 #endif
91
misc_init_r()92 int misc_init_r()
93 {
94 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
95
96 clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
97
98 return 0;
99 }
100
101 /*
102 * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
103 * and VME-CADDY/2) have different SDRAM configurations.
104 */
105 #ifdef VME_CADDY2
106 #define SMALL_RAM 0xff
107 #define LARGE_RAM 0x00
108 #else
109 #define SMALL_RAM 0x00
110 #define LARGE_RAM 0xff
111 #endif
112
113 #define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM))
114
115 static spd_eeprom_t default_spd_eeprom = {
116 SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */
117 SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */
118 SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */
119 SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */
120 SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */
121 SPD_VAL(0x00, 0x00), /* 05 */
122 SPD_VAL(0x40, 0x40), /* 06 */
123 SPD_VAL(0x00, 0x00), /* 07 */
124 SPD_VAL(0x05, 0x05), /* 08 */
125 SPD_VAL(0x30, 0x30), /* 09 */
126 SPD_VAL(0x45, 0x45), /* 10 */
127 SPD_VAL(0x02, 0x02), /* 11 ecc used */
128 SPD_VAL(0x82, 0x82), /* 12 */
129 SPD_VAL(0x10, 0x10), /* 13 */
130 SPD_VAL(0x08, 0x08), /* 14 */
131 SPD_VAL(0x00, 0x00), /* 15 */
132 SPD_VAL(0x0c, 0x0c), /* 16 */
133 SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */
134 SPD_VAL(0x38, 0x38), /* 18 */
135 SPD_VAL(0x00, 0x00), /* 19 */
136 SPD_VAL(0x02, 0x02), /* 20 */
137 SPD_VAL(0x00, 0x00), /* 21 */
138 SPD_VAL(0x03, 0x03), /* 22 */
139 SPD_VAL(0x3d, 0x3d), /* 23 */
140 SPD_VAL(0x45, 0x45), /* 24 */
141 SPD_VAL(0x50, 0x50), /* 25 */
142 SPD_VAL(0x45, 0x45), /* 26 */
143 SPD_VAL(0x3c, 0x3c), /* 27 */
144 SPD_VAL(0x28, 0x28), /* 28 */
145 SPD_VAL(0x3c, 0x3c), /* 29 */
146 SPD_VAL(0x2d, 0x2d), /* 30 */
147 SPD_VAL(0x20, 0x80), /* 31 */
148 SPD_VAL(0x20, 0x20), /* 32 */
149 SPD_VAL(0x27, 0x27), /* 33 */
150 SPD_VAL(0x10, 0x10), /* 34 */
151 SPD_VAL(0x17, 0x17), /* 35 */
152 SPD_VAL(0x3c, 0x3c), /* 36 */
153 SPD_VAL(0x1e, 0x1e), /* 37 */
154 SPD_VAL(0x1e, 0x1e), /* 38 */
155 SPD_VAL(0x00, 0x00), /* 39 */
156 SPD_VAL(0x00, 0x06), /* 40 */
157 SPD_VAL(0x37, 0x37), /* 41 */
158 SPD_VAL(0x4b, 0x7f), /* 42 */
159 SPD_VAL(0x80, 0x80), /* 43 */
160 SPD_VAL(0x18, 0x18), /* 44 */
161 SPD_VAL(0x22, 0x22), /* 45 */
162 SPD_VAL(0x00, 0x00), /* 46 */
163 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
164 SPD_VAL(0x10, 0x10), /* 62 */
165 SPD_VAL(0x7e, 0x1d), /* 63 */
166 { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
167 SPD_VAL(0x00, 0x00), /* 72 */
168 #ifdef VME_CADDY2
169 { "vme-caddy/2 ram " }
170 #else
171 { "vme-cpu/2 ram " }
172 #endif
173 };
174
vme8349_read_spd(uchar chip,uint addr,int alen,uchar * buffer,int len)175 int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
176 {
177 int old_bus = i2c_get_bus_num();
178 unsigned int l, sum;
179 int valid = 0;
180
181 i2c_set_bus_num(0);
182
183 if (i2c_read(chip, addr, alen, buffer, len) == 0)
184 if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
185 sum = 0;
186 for (l = 0; l < 63; l++)
187 sum = (sum + buffer[l]) & 0xff;
188 if (sum == buffer[63])
189 valid = 1;
190 else
191 printf("Invalid checksum in EEPROM %02x %02x\n",
192 sum, buffer[63]);
193 }
194
195 if (valid == 0) {
196 memcpy(buffer, (void *)&default_spd_eeprom, len);
197 sum = 0;
198 for (l = 0; l < 63; l++)
199 sum = (sum + buffer[l]) & 0xff;
200 if (sum != buffer[63])
201 printf("Invalid checksum in FLASH %02x %02x\n",
202 sum, buffer[63]);
203 buffer[63] = sum;
204 }
205
206 i2c_set_bus_num(old_bus);
207
208 return 0;
209 }
210