xref: /openbmc/linux/drivers/gpu/drm/radeon/sumo_dpm.c (revision 9e576111)
1 /*
2  * Copyright 2012 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include "radeon.h"
25 #include "radeon_asic.h"
26 #include "sumod.h"
27 #include "r600_dpm.h"
28 #include "cypress_dpm.h"
29 #include "sumo_dpm.h"
30 #include <linux/seq_file.h>
31 
32 #define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5
33 #define SUMO_MINIMUM_ENGINE_CLOCK 800
34 #define BOOST_DPM_LEVEL 7
35 
36 static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
37 {
38 	SUMO_UTC_DFLT_00,
39 	SUMO_UTC_DFLT_01,
40 	SUMO_UTC_DFLT_02,
41 	SUMO_UTC_DFLT_03,
42 	SUMO_UTC_DFLT_04,
43 	SUMO_UTC_DFLT_05,
44 	SUMO_UTC_DFLT_06,
45 	SUMO_UTC_DFLT_07,
46 	SUMO_UTC_DFLT_08,
47 	SUMO_UTC_DFLT_09,
48 	SUMO_UTC_DFLT_10,
49 	SUMO_UTC_DFLT_11,
50 	SUMO_UTC_DFLT_12,
51 	SUMO_UTC_DFLT_13,
52 	SUMO_UTC_DFLT_14,
53 };
54 
55 static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =
56 {
57 	SUMO_DTC_DFLT_00,
58 	SUMO_DTC_DFLT_01,
59 	SUMO_DTC_DFLT_02,
60 	SUMO_DTC_DFLT_03,
61 	SUMO_DTC_DFLT_04,
62 	SUMO_DTC_DFLT_05,
63 	SUMO_DTC_DFLT_06,
64 	SUMO_DTC_DFLT_07,
65 	SUMO_DTC_DFLT_08,
66 	SUMO_DTC_DFLT_09,
67 	SUMO_DTC_DFLT_10,
68 	SUMO_DTC_DFLT_11,
69 	SUMO_DTC_DFLT_12,
70 	SUMO_DTC_DFLT_13,
71 	SUMO_DTC_DFLT_14,
72 };
73 
sumo_get_ps(struct radeon_ps * rps)74 static struct sumo_ps *sumo_get_ps(struct radeon_ps *rps)
75 {
76 	struct sumo_ps *ps = rps->ps_priv;
77 
78 	return ps;
79 }
80 
sumo_get_pi(struct radeon_device * rdev)81 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev)
82 {
83 	struct sumo_power_info *pi = rdev->pm.dpm.priv;
84 
85 	return pi;
86 }
87 
sumo_gfx_clockgating_enable(struct radeon_device * rdev,bool enable)88 static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
89 {
90 	if (enable)
91 		WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
92 	else {
93 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
94 		WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
95 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
96 		RREG32(GB_ADDR_CONFIG);
97 	}
98 }
99 
100 #define CGCG_CGTT_LOCAL0_MASK 0xE5BFFFFF
101 #define CGCG_CGTT_LOCAL1_MASK 0xEFFF07FF
102 
sumo_mg_clockgating_enable(struct radeon_device * rdev,bool enable)103 static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable)
104 {
105 	u32 local0;
106 	u32 local1;
107 
108 	local0 = RREG32(CG_CGTT_LOCAL_0);
109 	local1 = RREG32(CG_CGTT_LOCAL_1);
110 
111 	if (enable) {
112 		WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
113 		WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
114 	} else {
115 		WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
116 		WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
117 	}
118 }
119 
sumo_program_git(struct radeon_device * rdev)120 static void sumo_program_git(struct radeon_device *rdev)
121 {
122 	u32 p, u;
123 	u32 xclk = radeon_get_xclk(rdev);
124 
125 	r600_calculate_u_and_p(SUMO_GICST_DFLT,
126 			       xclk, 16, &p, &u);
127 
128 	WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK);
129 }
130 
sumo_program_grsd(struct radeon_device * rdev)131 static void sumo_program_grsd(struct radeon_device *rdev)
132 {
133 	u32 p, u;
134 	u32 xclk = radeon_get_xclk(rdev);
135 	u32 grs = 256 * 25 / 100;
136 
137 	r600_calculate_u_and_p(1, xclk, 14, &p, &u);
138 
139 	WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u));
140 }
141 
sumo_gfx_clockgating_initialize(struct radeon_device * rdev)142 void sumo_gfx_clockgating_initialize(struct radeon_device *rdev)
143 {
144 	sumo_program_git(rdev);
145 	sumo_program_grsd(rdev);
146 }
147 
sumo_gfx_powergating_initialize(struct radeon_device * rdev)148 static void sumo_gfx_powergating_initialize(struct radeon_device *rdev)
149 {
150 	u32 rcu_pwr_gating_cntl;
151 	u32 p, u;
152 	u32 p_c, p_p, d_p;
153 	u32 r_t, i_t;
154 	u32 xclk = radeon_get_xclk(rdev);
155 
156 	if (rdev->family == CHIP_PALM) {
157 		p_c = 4;
158 		d_p = 10;
159 		r_t = 10;
160 		i_t = 4;
161 		p_p = 50 + 1000/200 + 6 * 32;
162 	} else {
163 		p_c = 16;
164 		d_p = 50;
165 		r_t = 50;
166 		i_t  = 50;
167 		p_p = 113;
168 	}
169 
170 	WREG32(CG_SCRATCH2, 0x01B60A17);
171 
172 	r600_calculate_u_and_p(SUMO_GFXPOWERGATINGT_DFLT,
173 			       xclk, 16, &p, &u);
174 
175 	WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u),
176 		 ~(PGP_MASK | PGU_MASK));
177 
178 	r600_calculate_u_and_p(SUMO_VOLTAGEDROPT_DFLT,
179 			       xclk, 16, &p, &u);
180 
181 	WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u),
182 		 ~(PGP_MASK | PGU_MASK));
183 
184 	if (rdev->family == CHIP_PALM) {
185 		WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210);
186 		WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010);
187 	} else {
188 		WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210);
189 		WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98);
190 	}
191 
192 	rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
193 	rcu_pwr_gating_cntl &=
194 		~(RSVD_MASK | PCV_MASK | PGS_MASK);
195 	rcu_pwr_gating_cntl |= PCV(p_c) | PGS(1) | PWR_GATING_EN;
196 	if (rdev->family == CHIP_PALM) {
197 		rcu_pwr_gating_cntl &= ~PCP_MASK;
198 		rcu_pwr_gating_cntl |= PCP(0x77);
199 	}
200 	WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
201 
202 	rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
203 	rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
204 	rcu_pwr_gating_cntl |= MPPU(p_p) | MPPD(50);
205 	WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
206 
207 	rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
208 	rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
209 	rcu_pwr_gating_cntl |= DPPU(d_p) | DPPD(50);
210 	WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
211 
212 	rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_4);
213 	rcu_pwr_gating_cntl &= ~(RT_MASK | IT_MASK);
214 	rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t);
215 	WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl);
216 
217 	if (rdev->family == CHIP_PALM)
218 		WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02);
219 
220 	sumo_smu_pg_init(rdev);
221 
222 	rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
223 	rcu_pwr_gating_cntl &=
224 		~(RSVD_MASK | PCV_MASK | PGS_MASK);
225 	rcu_pwr_gating_cntl |= PCV(p_c) | PGS(4) | PWR_GATING_EN;
226 	if (rdev->family == CHIP_PALM) {
227 		rcu_pwr_gating_cntl &= ~PCP_MASK;
228 		rcu_pwr_gating_cntl |= PCP(0x77);
229 	}
230 	WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
231 
232 	if (rdev->family == CHIP_PALM) {
233 		rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
234 		rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
235 		rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
236 		WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
237 
238 		rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
239 		rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
240 		rcu_pwr_gating_cntl |= DPPU(16) | DPPD(50);
241 		WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
242 	}
243 
244 	sumo_smu_pg_init(rdev);
245 
246 	rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
247 	rcu_pwr_gating_cntl &=
248 		~(RSVD_MASK | PCV_MASK | PGS_MASK);
249 	rcu_pwr_gating_cntl |= PGS(5) | PWR_GATING_EN;
250 
251 	if (rdev->family == CHIP_PALM) {
252 		rcu_pwr_gating_cntl |= PCV(4);
253 		rcu_pwr_gating_cntl &= ~PCP_MASK;
254 		rcu_pwr_gating_cntl |= PCP(0x77);
255 	} else
256 		rcu_pwr_gating_cntl |= PCV(11);
257 	WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
258 
259 	if (rdev->family == CHIP_PALM) {
260 		rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
261 		rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
262 		rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
263 		WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
264 
265 		rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
266 		rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
267 		rcu_pwr_gating_cntl |= DPPU(22) | DPPD(50);
268 		WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
269 	}
270 
271 	sumo_smu_pg_init(rdev);
272 }
273 
sumo_gfx_powergating_enable(struct radeon_device * rdev,bool enable)274 static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable)
275 {
276 	if (enable)
277 		WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
278 	else {
279 		WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN);
280 		RREG32(GB_ADDR_CONFIG);
281 	}
282 }
283 
sumo_enable_clock_power_gating(struct radeon_device * rdev)284 static int sumo_enable_clock_power_gating(struct radeon_device *rdev)
285 {
286 	struct sumo_power_info *pi = sumo_get_pi(rdev);
287 
288 	if (pi->enable_gfx_clock_gating)
289 		sumo_gfx_clockgating_initialize(rdev);
290 	if (pi->enable_gfx_power_gating)
291 		sumo_gfx_powergating_initialize(rdev);
292 	if (pi->enable_mg_clock_gating)
293 		sumo_mg_clockgating_enable(rdev, true);
294 	if (pi->enable_gfx_clock_gating)
295 		sumo_gfx_clockgating_enable(rdev, true);
296 	if (pi->enable_gfx_power_gating)
297 		sumo_gfx_powergating_enable(rdev, true);
298 
299 	return 0;
300 }
301 
sumo_disable_clock_power_gating(struct radeon_device * rdev)302 static void sumo_disable_clock_power_gating(struct radeon_device *rdev)
303 {
304 	struct sumo_power_info *pi = sumo_get_pi(rdev);
305 
306 	if (pi->enable_gfx_clock_gating)
307 		sumo_gfx_clockgating_enable(rdev, false);
308 	if (pi->enable_gfx_power_gating)
309 		sumo_gfx_powergating_enable(rdev, false);
310 	if (pi->enable_mg_clock_gating)
311 		sumo_mg_clockgating_enable(rdev, false);
312 }
313 
sumo_calculate_bsp(struct radeon_device * rdev,u32 high_clk)314 static void sumo_calculate_bsp(struct radeon_device *rdev,
315 			       u32 high_clk)
316 {
317 	struct sumo_power_info *pi = sumo_get_pi(rdev);
318 	u32 xclk = radeon_get_xclk(rdev);
319 
320 	pi->pasi = 65535 * 100 / high_clk;
321 	pi->asi = 65535 * 100 / high_clk;
322 
323 	r600_calculate_u_and_p(pi->asi,
324 			       xclk, 16, &pi->bsp, &pi->bsu);
325 
326 	r600_calculate_u_and_p(pi->pasi,
327 			       xclk, 16, &pi->pbsp, &pi->pbsu);
328 
329 	pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
330 	pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
331 }
332 
sumo_init_bsp(struct radeon_device * rdev)333 static void sumo_init_bsp(struct radeon_device *rdev)
334 {
335 	struct sumo_power_info *pi = sumo_get_pi(rdev);
336 
337 	WREG32(CG_BSP_0, pi->psp);
338 }
339 
340 
sumo_program_bsp(struct radeon_device * rdev,struct radeon_ps * rps)341 static void sumo_program_bsp(struct radeon_device *rdev,
342 			     struct radeon_ps *rps)
343 {
344 	struct sumo_power_info *pi = sumo_get_pi(rdev);
345 	struct sumo_ps *ps = sumo_get_ps(rps);
346 	u32 i;
347 	u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
348 
349 	if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
350 		highest_engine_clock = pi->boost_pl.sclk;
351 
352 	sumo_calculate_bsp(rdev, highest_engine_clock);
353 
354 	for (i = 0; i < ps->num_levels - 1; i++)
355 		WREG32(CG_BSP_0 + (i * 4), pi->dsp);
356 
357 	WREG32(CG_BSP_0 + (i * 4), pi->psp);
358 
359 	if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
360 		WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp);
361 }
362 
sumo_write_at(struct radeon_device * rdev,u32 index,u32 value)363 static void sumo_write_at(struct radeon_device *rdev,
364 			  u32 index, u32 value)
365 {
366 	if (index == 0)
367 		WREG32(CG_AT_0, value);
368 	else if (index == 1)
369 		WREG32(CG_AT_1, value);
370 	else if (index == 2)
371 		WREG32(CG_AT_2, value);
372 	else if (index == 3)
373 		WREG32(CG_AT_3, value);
374 	else if (index == 4)
375 		WREG32(CG_AT_4, value);
376 	else if (index == 5)
377 		WREG32(CG_AT_5, value);
378 	else if (index == 6)
379 		WREG32(CG_AT_6, value);
380 	else if (index == 7)
381 		WREG32(CG_AT_7, value);
382 }
383 
sumo_program_at(struct radeon_device * rdev,struct radeon_ps * rps)384 static void sumo_program_at(struct radeon_device *rdev,
385 			    struct radeon_ps *rps)
386 {
387 	struct sumo_power_info *pi = sumo_get_pi(rdev);
388 	struct sumo_ps *ps = sumo_get_ps(rps);
389 	u32 asi;
390 	u32 i;
391 	u32 m_a;
392 	u32 a_t;
393 	u32 r[SUMO_MAX_HARDWARE_POWERLEVELS];
394 	u32 l[SUMO_MAX_HARDWARE_POWERLEVELS];
395 
396 	r[0] = SUMO_R_DFLT0;
397 	r[1] = SUMO_R_DFLT1;
398 	r[2] = SUMO_R_DFLT2;
399 	r[3] = SUMO_R_DFLT3;
400 	r[4] = SUMO_R_DFLT4;
401 
402 	l[0] = SUMO_L_DFLT0;
403 	l[1] = SUMO_L_DFLT1;
404 	l[2] = SUMO_L_DFLT2;
405 	l[3] = SUMO_L_DFLT3;
406 	l[4] = SUMO_L_DFLT4;
407 
408 	for (i = 0; i < ps->num_levels; i++) {
409 		asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi;
410 
411 		m_a = asi * ps->levels[i].sclk / 100;
412 
413 		a_t = CG_R(m_a * r[i] / 100) | CG_L(m_a * l[i] / 100);
414 
415 		sumo_write_at(rdev, i, a_t);
416 	}
417 
418 	if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
419 		asi = pi->pasi;
420 
421 		m_a = asi * pi->boost_pl.sclk / 100;
422 
423 		a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) |
424 			CG_L(m_a * l[ps->num_levels - 1] / 100);
425 
426 		sumo_write_at(rdev, BOOST_DPM_LEVEL, a_t);
427 	}
428 }
429 
sumo_program_tp(struct radeon_device * rdev)430 static void sumo_program_tp(struct radeon_device *rdev)
431 {
432 	int i;
433 	enum r600_td td = R600_TD_DFLT;
434 
435 	for (i = 0; i < SUMO_PM_NUMBER_OF_TC; i++) {
436 		WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK);
437 		WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK);
438 	}
439 
440 	if (td == R600_TD_AUTO)
441 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
442 	else
443 		WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
444 
445 	if (td == R600_TD_UP)
446 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
447 
448 	if (td == R600_TD_DOWN)
449 		WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
450 }
451 
sumo_program_vc(struct radeon_device * rdev,u32 vrc)452 void sumo_program_vc(struct radeon_device *rdev, u32 vrc)
453 {
454 	WREG32(CG_FTV, vrc);
455 }
456 
sumo_clear_vc(struct radeon_device * rdev)457 void sumo_clear_vc(struct radeon_device *rdev)
458 {
459 	WREG32(CG_FTV, 0);
460 }
461 
sumo_program_sstp(struct radeon_device * rdev)462 void sumo_program_sstp(struct radeon_device *rdev)
463 {
464 	u32 p, u;
465 	u32 xclk = radeon_get_xclk(rdev);
466 
467 	r600_calculate_u_and_p(SUMO_SST_DFLT,
468 			       xclk, 16, &p, &u);
469 
470 	WREG32(CG_SSP, SSTU(u) | SST(p));
471 }
472 
sumo_set_divider_value(struct radeon_device * rdev,u32 index,u32 divider)473 static void sumo_set_divider_value(struct radeon_device *rdev,
474 				   u32 index, u32 divider)
475 {
476 	u32 reg_index = index / 4;
477 	u32 field_index = index % 4;
478 
479 	if (field_index == 0)
480 		WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
481 			 SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK);
482 	else if (field_index == 1)
483 		WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
484 			 SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK);
485 	else if (field_index == 2)
486 		WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
487 			 SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK);
488 	else if (field_index == 3)
489 		WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
490 			 SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK);
491 }
492 
sumo_set_ds_dividers(struct radeon_device * rdev,u32 index,u32 divider)493 static void sumo_set_ds_dividers(struct radeon_device *rdev,
494 				 u32 index, u32 divider)
495 {
496 	struct sumo_power_info *pi = sumo_get_pi(rdev);
497 
498 	if (pi->enable_sclk_ds) {
499 		u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6);
500 
501 		dpm_ctrl &= ~(0x7 << (index * 3));
502 		dpm_ctrl |= (divider << (index * 3));
503 		WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl);
504 	}
505 }
506 
sumo_set_ss_dividers(struct radeon_device * rdev,u32 index,u32 divider)507 static void sumo_set_ss_dividers(struct radeon_device *rdev,
508 				 u32 index, u32 divider)
509 {
510 	struct sumo_power_info *pi = sumo_get_pi(rdev);
511 
512 	if (pi->enable_sclk_ds) {
513 		u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11);
514 
515 		dpm_ctrl &= ~(0x7 << (index * 3));
516 		dpm_ctrl |= (divider << (index * 3));
517 		WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl);
518 	}
519 }
520 
sumo_set_vid(struct radeon_device * rdev,u32 index,u32 vid)521 static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
522 {
523 	u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL);
524 
525 	voltage_cntl &= ~(DPM_STATE0_LEVEL_MASK << (index * 2));
526 	voltage_cntl |= (vid << (DPM_STATE0_LEVEL_SHIFT + index * 2));
527 	WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl);
528 }
529 
sumo_set_allos_gnb_slow(struct radeon_device * rdev,u32 index,u32 gnb_slow)530 static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow)
531 {
532 	struct sumo_power_info *pi = sumo_get_pi(rdev);
533 	u32 temp = gnb_slow;
534 	u32 cg_sclk_dpm_ctrl_3;
535 
536 	if (pi->driver_nbps_policy_disable)
537 		temp = 1;
538 
539 	cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
540 	cg_sclk_dpm_ctrl_3 &= ~(GNB_SLOW_FSTATE_0_MASK << index);
541 	cg_sclk_dpm_ctrl_3 |= (temp << (GNB_SLOW_FSTATE_0_SHIFT + index));
542 
543 	WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
544 }
545 
sumo_program_power_level(struct radeon_device * rdev,struct sumo_pl * pl,u32 index)546 static void sumo_program_power_level(struct radeon_device *rdev,
547 				     struct sumo_pl *pl, u32 index)
548 {
549 	struct sumo_power_info *pi = sumo_get_pi(rdev);
550 	int ret;
551 	struct atom_clock_dividers dividers;
552 	u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS;
553 
554 	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
555 					     pl->sclk, false, &dividers);
556 	if (ret)
557 		return;
558 
559 	sumo_set_divider_value(rdev, index, dividers.post_div);
560 
561 	sumo_set_vid(rdev, index, pl->vddc_index);
562 
563 	if (pl->ss_divider_index == 0 || pl->ds_divider_index == 0) {
564 		if (ds_en)
565 			WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
566 	} else {
567 		sumo_set_ss_dividers(rdev, index, pl->ss_divider_index);
568 		sumo_set_ds_dividers(rdev, index, pl->ds_divider_index);
569 
570 		if (!ds_en)
571 			WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS);
572 	}
573 
574 	sumo_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow);
575 
576 	if (pi->enable_boost)
577 		sumo_set_tdp_limit(rdev, index, pl->sclk_dpm_tdp_limit);
578 }
579 
sumo_power_level_enable(struct radeon_device * rdev,u32 index,bool enable)580 static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable)
581 {
582 	u32 reg_index = index / 4;
583 	u32 field_index = index % 4;
584 
585 	if (field_index == 0)
586 		WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
587 			 enable ? SCLK_FSTATE_0_VLD : 0, ~SCLK_FSTATE_0_VLD);
588 	else if (field_index == 1)
589 		WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
590 			 enable ? SCLK_FSTATE_1_VLD : 0, ~SCLK_FSTATE_1_VLD);
591 	else if (field_index == 2)
592 		WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
593 			 enable ? SCLK_FSTATE_2_VLD : 0, ~SCLK_FSTATE_2_VLD);
594 	else if (field_index == 3)
595 		WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
596 			 enable ? SCLK_FSTATE_3_VLD : 0, ~SCLK_FSTATE_3_VLD);
597 }
598 
sumo_dpm_enabled(struct radeon_device * rdev)599 static bool sumo_dpm_enabled(struct radeon_device *rdev)
600 {
601 	if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE)
602 		return true;
603 	else
604 		return false;
605 }
606 
sumo_start_dpm(struct radeon_device * rdev)607 static void sumo_start_dpm(struct radeon_device *rdev)
608 {
609 	WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE);
610 }
611 
sumo_stop_dpm(struct radeon_device * rdev)612 static void sumo_stop_dpm(struct radeon_device *rdev)
613 {
614 	WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE);
615 }
616 
sumo_set_forced_mode(struct radeon_device * rdev,bool enable)617 static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable)
618 {
619 	if (enable)
620 		WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN);
621 	else
622 		WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN);
623 }
624 
sumo_set_forced_mode_enabled(struct radeon_device * rdev)625 static void sumo_set_forced_mode_enabled(struct radeon_device *rdev)
626 {
627 	int i;
628 
629 	sumo_set_forced_mode(rdev, true);
630 	for (i = 0; i < rdev->usec_timeout; i++) {
631 		if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT)
632 			break;
633 		udelay(1);
634 	}
635 }
636 
sumo_wait_for_level_0(struct radeon_device * rdev)637 static void sumo_wait_for_level_0(struct radeon_device *rdev)
638 {
639 	int i;
640 
641 	for (i = 0; i < rdev->usec_timeout; i++) {
642 		if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0)
643 			break;
644 		udelay(1);
645 	}
646 	for (i = 0; i < rdev->usec_timeout; i++) {
647 		if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0)
648 			break;
649 		udelay(1);
650 	}
651 }
652 
sumo_set_forced_mode_disabled(struct radeon_device * rdev)653 static void sumo_set_forced_mode_disabled(struct radeon_device *rdev)
654 {
655 	sumo_set_forced_mode(rdev, false);
656 }
657 
sumo_enable_power_level_0(struct radeon_device * rdev)658 static void sumo_enable_power_level_0(struct radeon_device *rdev)
659 {
660 	sumo_power_level_enable(rdev, 0, true);
661 }
662 
sumo_patch_boost_state(struct radeon_device * rdev,struct radeon_ps * rps)663 static void sumo_patch_boost_state(struct radeon_device *rdev,
664 				   struct radeon_ps *rps)
665 {
666 	struct sumo_power_info *pi = sumo_get_pi(rdev);
667 	struct sumo_ps *new_ps = sumo_get_ps(rps);
668 
669 	if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
670 		pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];
671 		pi->boost_pl.sclk = pi->sys_info.boost_sclk;
672 		pi->boost_pl.vddc_index = pi->sys_info.boost_vid_2bit;
673 		pi->boost_pl.sclk_dpm_tdp_limit = pi->sys_info.sclk_dpm_tdp_limit_boost;
674 	}
675 }
676 
sumo_pre_notify_alt_vddnb_change(struct radeon_device * rdev,struct radeon_ps * new_rps,struct radeon_ps * old_rps)677 static void sumo_pre_notify_alt_vddnb_change(struct radeon_device *rdev,
678 					     struct radeon_ps *new_rps,
679 					     struct radeon_ps *old_rps)
680 {
681 	struct sumo_ps *new_ps = sumo_get_ps(new_rps);
682 	struct sumo_ps *old_ps = sumo_get_ps(old_rps);
683 	u32 nbps1_old = 0;
684 	u32 nbps1_new = 0;
685 
686 	if (old_ps != NULL)
687 		nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
688 
689 	nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
690 
691 	if (nbps1_old == 1 && nbps1_new == 0)
692 		sumo_smu_notify_alt_vddnb_change(rdev, 0, 0);
693 }
694 
sumo_post_notify_alt_vddnb_change(struct radeon_device * rdev,struct radeon_ps * new_rps,struct radeon_ps * old_rps)695 static void sumo_post_notify_alt_vddnb_change(struct radeon_device *rdev,
696 					      struct radeon_ps *new_rps,
697 					      struct radeon_ps *old_rps)
698 {
699 	struct sumo_ps *new_ps = sumo_get_ps(new_rps);
700 	struct sumo_ps *old_ps = sumo_get_ps(old_rps);
701 	u32 nbps1_old = 0;
702 	u32 nbps1_new = 0;
703 
704 	if (old_ps != NULL)
705 		nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
706 
707 	nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
708 
709 	if (nbps1_old == 0 && nbps1_new == 1)
710 		sumo_smu_notify_alt_vddnb_change(rdev, 1, 1);
711 }
712 
sumo_enable_boost(struct radeon_device * rdev,struct radeon_ps * rps,bool enable)713 static void sumo_enable_boost(struct radeon_device *rdev,
714 			      struct radeon_ps *rps,
715 			      bool enable)
716 {
717 	struct sumo_ps *new_ps = sumo_get_ps(rps);
718 
719 	if (enable) {
720 		if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
721 			sumo_boost_state_enable(rdev, true);
722 	} else
723 		sumo_boost_state_enable(rdev, false);
724 }
725 
sumo_set_forced_level(struct radeon_device * rdev,u32 index)726 static void sumo_set_forced_level(struct radeon_device *rdev, u32 index)
727 {
728 	WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK);
729 }
730 
sumo_set_forced_level_0(struct radeon_device * rdev)731 static void sumo_set_forced_level_0(struct radeon_device *rdev)
732 {
733 	sumo_set_forced_level(rdev, 0);
734 }
735 
sumo_program_wl(struct radeon_device * rdev,struct radeon_ps * rps)736 static void sumo_program_wl(struct radeon_device *rdev,
737 			    struct radeon_ps *rps)
738 {
739 	struct sumo_ps *new_ps = sumo_get_ps(rps);
740 	u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
741 
742 	dpm_ctrl4 &= 0xFFFFFF00;
743 	dpm_ctrl4 |= (1 << (new_ps->num_levels - 1));
744 
745 	if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
746 		dpm_ctrl4 |= (1 << BOOST_DPM_LEVEL);
747 
748 	WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
749 }
750 
sumo_program_power_levels_0_to_n(struct radeon_device * rdev,struct radeon_ps * new_rps,struct radeon_ps * old_rps)751 static void sumo_program_power_levels_0_to_n(struct radeon_device *rdev,
752 					     struct radeon_ps *new_rps,
753 					     struct radeon_ps *old_rps)
754 {
755 	struct sumo_power_info *pi = sumo_get_pi(rdev);
756 	struct sumo_ps *new_ps = sumo_get_ps(new_rps);
757 	struct sumo_ps *old_ps = sumo_get_ps(old_rps);
758 	u32 i;
759 	u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;
760 
761 	for (i = 0; i < new_ps->num_levels; i++) {
762 		sumo_program_power_level(rdev, &new_ps->levels[i], i);
763 		sumo_power_level_enable(rdev, i, true);
764 	}
765 
766 	for (i = new_ps->num_levels; i < n_current_state_levels; i++)
767 		sumo_power_level_enable(rdev, i, false);
768 
769 	if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
770 		sumo_program_power_level(rdev, &pi->boost_pl, BOOST_DPM_LEVEL);
771 }
772 
sumo_enable_acpi_pm(struct radeon_device * rdev)773 static void sumo_enable_acpi_pm(struct radeon_device *rdev)
774 {
775 	WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
776 }
777 
sumo_program_power_level_enter_state(struct radeon_device * rdev)778 static void sumo_program_power_level_enter_state(struct radeon_device *rdev)
779 {
780 	WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK);
781 }
782 
sumo_program_acpi_power_level(struct radeon_device * rdev)783 static void sumo_program_acpi_power_level(struct radeon_device *rdev)
784 {
785 	struct sumo_power_info *pi = sumo_get_pi(rdev);
786 	struct atom_clock_dividers dividers;
787 	int ret;
788 
789 	ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
790 					     pi->acpi_pl.sclk,
791 					     false, &dividers);
792 	if (ret)
793 		return;
794 
795 	WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);
796 	WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN);
797 }
798 
sumo_program_bootup_state(struct radeon_device * rdev)799 static void sumo_program_bootup_state(struct radeon_device *rdev)
800 {
801 	struct sumo_power_info *pi = sumo_get_pi(rdev);
802 	u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
803 	u32 i;
804 
805 	sumo_program_power_level(rdev, &pi->boot_pl, 0);
806 
807 	dpm_ctrl4 &= 0xFFFFFF00;
808 	WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
809 
810 	for (i = 1; i < 8; i++)
811 		sumo_power_level_enable(rdev, i, false);
812 }
813 
sumo_setup_uvd_clocks(struct radeon_device * rdev,struct radeon_ps * new_rps,struct radeon_ps * old_rps)814 static void sumo_setup_uvd_clocks(struct radeon_device *rdev,
815 				  struct radeon_ps *new_rps,
816 				  struct radeon_ps *old_rps)
817 {
818 	struct sumo_power_info *pi = sumo_get_pi(rdev);
819 
820 	if (pi->enable_gfx_power_gating) {
821 		sumo_gfx_powergating_enable(rdev, false);
822 	}
823 
824 	radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
825 
826 	if (pi->enable_gfx_power_gating) {
827 		if (!pi->disable_gfx_power_gating_in_uvd ||
828 		    !r600_is_uvd_state(new_rps->class, new_rps->class2))
829 			sumo_gfx_powergating_enable(rdev, true);
830 	}
831 }
832 
sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device * rdev,struct radeon_ps * new_rps,struct radeon_ps * old_rps)833 static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
834 						    struct radeon_ps *new_rps,
835 						    struct radeon_ps *old_rps)
836 {
837 	struct sumo_ps *new_ps = sumo_get_ps(new_rps);
838 	struct sumo_ps *current_ps = sumo_get_ps(old_rps);
839 
840 	if ((new_rps->vclk == old_rps->vclk) &&
841 	    (new_rps->dclk == old_rps->dclk))
842 		return;
843 
844 	if (new_ps->levels[new_ps->num_levels - 1].sclk >=
845 	    current_ps->levels[current_ps->num_levels - 1].sclk)
846 		return;
847 
848 	sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
849 }
850 
sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device * rdev,struct radeon_ps * new_rps,struct radeon_ps * old_rps)851 static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
852 						   struct radeon_ps *new_rps,
853 						   struct radeon_ps *old_rps)
854 {
855 	struct sumo_ps *new_ps = sumo_get_ps(new_rps);
856 	struct sumo_ps *current_ps = sumo_get_ps(old_rps);
857 
858 	if ((new_rps->vclk == old_rps->vclk) &&
859 	    (new_rps->dclk == old_rps->dclk))
860 		return;
861 
862 	if (new_ps->levels[new_ps->num_levels - 1].sclk <
863 	    current_ps->levels[current_ps->num_levels - 1].sclk)
864 		return;
865 
866 	sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
867 }
868 
sumo_take_smu_control(struct radeon_device * rdev,bool enable)869 void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
870 {
871 /* This bit selects who handles display phy powergating.
872  * Clear the bit to let atom handle it.
873  * Set it to let the driver handle it.
874  * For now we just let atom handle it.
875  */
876 #if 0
877 	u32 v = RREG32(DOUT_SCRATCH3);
878 
879 	if (enable)
880 		v |= 0x4;
881 	else
882 		v &= 0xFFFFFFFB;
883 
884 	WREG32(DOUT_SCRATCH3, v);
885 #endif
886 }
887 
sumo_enable_sclk_ds(struct radeon_device * rdev,bool enable)888 static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable)
889 {
890 	if (enable) {
891 		u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL);
892 		u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2);
893 		u32 t = 1;
894 
895 		deep_sleep_cntl &= ~R_DIS;
896 		deep_sleep_cntl &= ~HS_MASK;
897 		deep_sleep_cntl |= HS(t > 4095 ? 4095 : t);
898 
899 		deep_sleep_cntl2 |= LB_UFP_EN;
900 		deep_sleep_cntl2 &= INOUT_C_MASK;
901 		deep_sleep_cntl2 |= INOUT_C(0xf);
902 
903 		WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2);
904 		WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl);
905 	} else
906 		WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
907 }
908 
sumo_program_bootup_at(struct radeon_device * rdev)909 static void sumo_program_bootup_at(struct radeon_device *rdev)
910 {
911 	WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK);
912 	WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK);
913 }
914 
sumo_reset_am(struct radeon_device * rdev)915 static void sumo_reset_am(struct radeon_device *rdev)
916 {
917 	WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET);
918 }
919 
sumo_start_am(struct radeon_device * rdev)920 static void sumo_start_am(struct radeon_device *rdev)
921 {
922 	WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET);
923 }
924 
sumo_program_ttp(struct radeon_device * rdev)925 static void sumo_program_ttp(struct radeon_device *rdev)
926 {
927 	u32 xclk = radeon_get_xclk(rdev);
928 	u32 p, u;
929 	u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);
930 
931 	r600_calculate_u_and_p(1000,
932 			       xclk, 16, &p, &u);
933 
934 	cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK | TT_TU_MASK);
935 	cg_sclk_dpm_ctrl_5 |= TT_TP(p) | TT_TU(u);
936 
937 	WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5);
938 }
939 
sumo_program_ttt(struct radeon_device * rdev)940 static void sumo_program_ttt(struct radeon_device *rdev)
941 {
942 	u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
943 	struct sumo_power_info *pi = sumo_get_pi(rdev);
944 
945 	cg_sclk_dpm_ctrl_3 &= ~(GNB_TT_MASK | GNB_THERMTHRO_MASK);
946 	cg_sclk_dpm_ctrl_3 |= GNB_TT(pi->thermal_auto_throttling + 49);
947 
948 	WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
949 }
950 
951 
sumo_enable_voltage_scaling(struct radeon_device * rdev,bool enable)952 static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable)
953 {
954 	if (enable) {
955 		WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN);
956 		WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN);
957 	} else {
958 		WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN);
959 		WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN);
960 	}
961 }
962 
sumo_override_cnb_thermal_events(struct radeon_device * rdev)963 static void sumo_override_cnb_thermal_events(struct radeon_device *rdev)
964 {
965 	WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK,
966 		 ~CNB_THERMTHRO_MASK_SCLK);
967 }
968 
sumo_program_dc_hto(struct radeon_device * rdev)969 static void sumo_program_dc_hto(struct radeon_device *rdev)
970 {
971 	u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);
972 	u32 p, u;
973 	u32 xclk = radeon_get_xclk(rdev);
974 
975 	r600_calculate_u_and_p(100000,
976 			       xclk, 14, &p, &u);
977 
978 	cg_sclk_dpm_ctrl_4 &= ~(DC_HDC_MASK | DC_HU_MASK);
979 	cg_sclk_dpm_ctrl_4 |= DC_HDC(p) | DC_HU(u);
980 
981 	WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4);
982 }
983 
sumo_force_nbp_state(struct radeon_device * rdev,struct radeon_ps * rps)984 static void sumo_force_nbp_state(struct radeon_device *rdev,
985 				 struct radeon_ps *rps)
986 {
987 	struct sumo_power_info *pi = sumo_get_pi(rdev);
988 	struct sumo_ps *new_ps = sumo_get_ps(rps);
989 
990 	if (!pi->driver_nbps_policy_disable) {
991 		if (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
992 			WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1);
993 		else
994 			WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1);
995 	}
996 }
997 
sumo_get_sleep_divider_from_id(u32 id)998 u32 sumo_get_sleep_divider_from_id(u32 id)
999 {
1000 	return 1 << id;
1001 }
1002 
sumo_get_sleep_divider_id_from_clock(struct radeon_device * rdev,u32 sclk,u32 min_sclk_in_sr)1003 u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1004 					 u32 sclk,
1005 					 u32 min_sclk_in_sr)
1006 {
1007 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1008 	u32 i;
1009 	u32 temp;
1010 	u32 min = (min_sclk_in_sr > SUMO_MINIMUM_ENGINE_CLOCK) ?
1011 		min_sclk_in_sr : SUMO_MINIMUM_ENGINE_CLOCK;
1012 
1013 	if (sclk < min)
1014 		return 0;
1015 
1016 	if (!pi->enable_sclk_ds)
1017 		return 0;
1018 
1019 	for (i = SUMO_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1020 		temp = sclk / sumo_get_sleep_divider_from_id(i);
1021 
1022 		if (temp >= min || i == 0)
1023 			break;
1024 	}
1025 	return i;
1026 }
1027 
sumo_get_valid_engine_clock(struct radeon_device * rdev,u32 lower_limit)1028 static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev,
1029 				       u32 lower_limit)
1030 {
1031 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1032 	u32 i;
1033 
1034 	for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) {
1035 		if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit)
1036 			return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency;
1037 	}
1038 
1039 	return pi->sys_info.sclk_voltage_mapping_table.entries[pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1].sclk_frequency;
1040 }
1041 
sumo_patch_thermal_state(struct radeon_device * rdev,struct sumo_ps * ps,struct sumo_ps * current_ps)1042 static void sumo_patch_thermal_state(struct radeon_device *rdev,
1043 				     struct sumo_ps *ps,
1044 				     struct sumo_ps *current_ps)
1045 {
1046 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1047 	u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1048 	u32 current_vddc;
1049 	u32 current_sclk;
1050 	u32 current_index = 0;
1051 
1052 	if (current_ps) {
1053 		current_vddc = current_ps->levels[current_index].vddc_index;
1054 		current_sclk = current_ps->levels[current_index].sclk;
1055 	} else {
1056 		current_vddc = pi->boot_pl.vddc_index;
1057 		current_sclk = pi->boot_pl.sclk;
1058 	}
1059 
1060 	ps->levels[0].vddc_index = current_vddc;
1061 
1062 	if (ps->levels[0].sclk > current_sclk)
1063 		ps->levels[0].sclk = current_sclk;
1064 
1065 	ps->levels[0].ss_divider_index =
1066 		sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);
1067 
1068 	ps->levels[0].ds_divider_index =
1069 		sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1070 
1071 	if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1)
1072 		ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1;
1073 
1074 	if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) {
1075 		if (ps->levels[0].ss_divider_index > 1)
1076 			ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1;
1077 	}
1078 
1079 	if (ps->levels[0].ss_divider_index == 0)
1080 		ps->levels[0].ds_divider_index = 0;
1081 
1082 	if (ps->levels[0].ds_divider_index == 0)
1083 		ps->levels[0].ss_divider_index = 0;
1084 }
1085 
sumo_apply_state_adjust_rules(struct radeon_device * rdev,struct radeon_ps * new_rps,struct radeon_ps * old_rps)1086 static void sumo_apply_state_adjust_rules(struct radeon_device *rdev,
1087 					  struct radeon_ps *new_rps,
1088 					  struct radeon_ps *old_rps)
1089 {
1090 	struct sumo_ps *ps = sumo_get_ps(new_rps);
1091 	struct sumo_ps *current_ps = sumo_get_ps(old_rps);
1092 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1093 	u32 min_voltage = 0; /* ??? */
1094 	u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */
1095 	u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1096 	u32 i;
1097 
1098 	if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1099 		return sumo_patch_thermal_state(rdev, ps, current_ps);
1100 
1101 	if (pi->enable_boost) {
1102 		if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE)
1103 			ps->flags |= SUMO_POWERSTATE_FLAGS_BOOST_STATE;
1104 	}
1105 
1106 	if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) ||
1107 	    (new_rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) ||
1108 	    (new_rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE))
1109 		ps->flags |= SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE;
1110 
1111 	for (i = 0; i < ps->num_levels; i++) {
1112 		if (ps->levels[i].vddc_index < min_voltage)
1113 			ps->levels[i].vddc_index = min_voltage;
1114 
1115 		if (ps->levels[i].sclk < min_sclk)
1116 			ps->levels[i].sclk =
1117 				sumo_get_valid_engine_clock(rdev, min_sclk);
1118 
1119 		ps->levels[i].ss_divider_index =
1120 			sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);
1121 
1122 		ps->levels[i].ds_divider_index =
1123 			sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1124 
1125 		if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1)
1126 			ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1;
1127 
1128 		if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) {
1129 			if (ps->levels[i].ss_divider_index > 1)
1130 				ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1;
1131 		}
1132 
1133 		if (ps->levels[i].ss_divider_index == 0)
1134 			ps->levels[i].ds_divider_index = 0;
1135 
1136 		if (ps->levels[i].ds_divider_index == 0)
1137 			ps->levels[i].ss_divider_index = 0;
1138 
1139 		if (ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
1140 			ps->levels[i].allow_gnb_slow = 1;
1141 		else if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) ||
1142 			 (new_rps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC))
1143 			ps->levels[i].allow_gnb_slow = 0;
1144 		else if (i == ps->num_levels - 1)
1145 			ps->levels[i].allow_gnb_slow = 0;
1146 		else
1147 			ps->levels[i].allow_gnb_slow = 1;
1148 	}
1149 }
1150 
sumo_cleanup_asic(struct radeon_device * rdev)1151 static void sumo_cleanup_asic(struct radeon_device *rdev)
1152 {
1153 	sumo_take_smu_control(rdev, false);
1154 }
1155 
sumo_set_thermal_temperature_range(struct radeon_device * rdev,int min_temp,int max_temp)1156 static int sumo_set_thermal_temperature_range(struct radeon_device *rdev,
1157 					      int min_temp, int max_temp)
1158 {
1159 	int low_temp = 0 * 1000;
1160 	int high_temp = 255 * 1000;
1161 
1162 	if (low_temp < min_temp)
1163 		low_temp = min_temp;
1164 	if (high_temp > max_temp)
1165 		high_temp = max_temp;
1166 	if (high_temp < low_temp) {
1167 		DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1168 		return -EINVAL;
1169 	}
1170 
1171 	WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);
1172 	WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);
1173 
1174 	rdev->pm.dpm.thermal.min_temp = low_temp;
1175 	rdev->pm.dpm.thermal.max_temp = high_temp;
1176 
1177 	return 0;
1178 }
1179 
sumo_update_current_ps(struct radeon_device * rdev,struct radeon_ps * rps)1180 static void sumo_update_current_ps(struct radeon_device *rdev,
1181 				   struct radeon_ps *rps)
1182 {
1183 	struct sumo_ps *new_ps = sumo_get_ps(rps);
1184 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1185 
1186 	pi->current_rps = *rps;
1187 	pi->current_ps = *new_ps;
1188 	pi->current_rps.ps_priv = &pi->current_ps;
1189 }
1190 
sumo_update_requested_ps(struct radeon_device * rdev,struct radeon_ps * rps)1191 static void sumo_update_requested_ps(struct radeon_device *rdev,
1192 				     struct radeon_ps *rps)
1193 {
1194 	struct sumo_ps *new_ps = sumo_get_ps(rps);
1195 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1196 
1197 	pi->requested_rps = *rps;
1198 	pi->requested_ps = *new_ps;
1199 	pi->requested_rps.ps_priv = &pi->requested_ps;
1200 }
1201 
sumo_dpm_enable(struct radeon_device * rdev)1202 int sumo_dpm_enable(struct radeon_device *rdev)
1203 {
1204 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1205 
1206 	if (sumo_dpm_enabled(rdev))
1207 		return -EINVAL;
1208 
1209 	sumo_program_bootup_state(rdev);
1210 	sumo_init_bsp(rdev);
1211 	sumo_reset_am(rdev);
1212 	sumo_program_tp(rdev);
1213 	sumo_program_bootup_at(rdev);
1214 	sumo_start_am(rdev);
1215 	if (pi->enable_auto_thermal_throttling) {
1216 		sumo_program_ttp(rdev);
1217 		sumo_program_ttt(rdev);
1218 	}
1219 	sumo_program_dc_hto(rdev);
1220 	sumo_program_power_level_enter_state(rdev);
1221 	sumo_enable_voltage_scaling(rdev, true);
1222 	sumo_program_sstp(rdev);
1223 	sumo_program_vc(rdev, SUMO_VRC_DFLT);
1224 	sumo_override_cnb_thermal_events(rdev);
1225 	sumo_start_dpm(rdev);
1226 	sumo_wait_for_level_0(rdev);
1227 	if (pi->enable_sclk_ds)
1228 		sumo_enable_sclk_ds(rdev, true);
1229 	if (pi->enable_boost)
1230 		sumo_enable_boost_timer(rdev);
1231 
1232 	sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1233 
1234 	return 0;
1235 }
1236 
sumo_dpm_late_enable(struct radeon_device * rdev)1237 int sumo_dpm_late_enable(struct radeon_device *rdev)
1238 {
1239 	int ret;
1240 
1241 	ret = sumo_enable_clock_power_gating(rdev);
1242 	if (ret)
1243 		return ret;
1244 
1245 	if (rdev->irq.installed &&
1246 	    r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1247 		ret = sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1248 		if (ret)
1249 			return ret;
1250 		rdev->irq.dpm_thermal = true;
1251 		radeon_irq_set(rdev);
1252 	}
1253 
1254 	return 0;
1255 }
1256 
sumo_dpm_disable(struct radeon_device * rdev)1257 void sumo_dpm_disable(struct radeon_device *rdev)
1258 {
1259 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1260 
1261 	if (!sumo_dpm_enabled(rdev))
1262 		return;
1263 	sumo_disable_clock_power_gating(rdev);
1264 	if (pi->enable_sclk_ds)
1265 		sumo_enable_sclk_ds(rdev, false);
1266 	sumo_clear_vc(rdev);
1267 	sumo_wait_for_level_0(rdev);
1268 	sumo_stop_dpm(rdev);
1269 	sumo_enable_voltage_scaling(rdev, false);
1270 
1271 	if (rdev->irq.installed &&
1272 	    r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1273 		rdev->irq.dpm_thermal = false;
1274 		radeon_irq_set(rdev);
1275 	}
1276 
1277 	sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1278 }
1279 
sumo_dpm_pre_set_power_state(struct radeon_device * rdev)1280 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev)
1281 {
1282 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1283 	struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1284 	struct radeon_ps *new_ps = &requested_ps;
1285 
1286 	sumo_update_requested_ps(rdev, new_ps);
1287 
1288 	if (pi->enable_dynamic_patch_ps)
1289 		sumo_apply_state_adjust_rules(rdev,
1290 					      &pi->requested_rps,
1291 					      &pi->current_rps);
1292 
1293 	return 0;
1294 }
1295 
sumo_dpm_set_power_state(struct radeon_device * rdev)1296 int sumo_dpm_set_power_state(struct radeon_device *rdev)
1297 {
1298 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1299 	struct radeon_ps *new_ps = &pi->requested_rps;
1300 	struct radeon_ps *old_ps = &pi->current_rps;
1301 
1302 	if (pi->enable_dpm)
1303 		sumo_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1304 	if (pi->enable_boost) {
1305 		sumo_enable_boost(rdev, new_ps, false);
1306 		sumo_patch_boost_state(rdev, new_ps);
1307 	}
1308 	if (pi->enable_dpm) {
1309 		sumo_pre_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1310 		sumo_enable_power_level_0(rdev);
1311 		sumo_set_forced_level_0(rdev);
1312 		sumo_set_forced_mode_enabled(rdev);
1313 		sumo_wait_for_level_0(rdev);
1314 		sumo_program_power_levels_0_to_n(rdev, new_ps, old_ps);
1315 		sumo_program_wl(rdev, new_ps);
1316 		sumo_program_bsp(rdev, new_ps);
1317 		sumo_program_at(rdev, new_ps);
1318 		sumo_force_nbp_state(rdev, new_ps);
1319 		sumo_set_forced_mode_disabled(rdev);
1320 		sumo_set_forced_mode_enabled(rdev);
1321 		sumo_set_forced_mode_disabled(rdev);
1322 		sumo_post_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1323 	}
1324 	if (pi->enable_boost)
1325 		sumo_enable_boost(rdev, new_ps, true);
1326 	if (pi->enable_dpm)
1327 		sumo_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1328 
1329 	return 0;
1330 }
1331 
sumo_dpm_post_set_power_state(struct radeon_device * rdev)1332 void sumo_dpm_post_set_power_state(struct radeon_device *rdev)
1333 {
1334 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1335 	struct radeon_ps *new_ps = &pi->requested_rps;
1336 
1337 	sumo_update_current_ps(rdev, new_ps);
1338 }
1339 
1340 #if 0
1341 void sumo_dpm_reset_asic(struct radeon_device *rdev)
1342 {
1343 	sumo_program_bootup_state(rdev);
1344 	sumo_enable_power_level_0(rdev);
1345 	sumo_set_forced_level_0(rdev);
1346 	sumo_set_forced_mode_enabled(rdev);
1347 	sumo_wait_for_level_0(rdev);
1348 	sumo_set_forced_mode_disabled(rdev);
1349 	sumo_set_forced_mode_enabled(rdev);
1350 	sumo_set_forced_mode_disabled(rdev);
1351 }
1352 #endif
1353 
sumo_dpm_setup_asic(struct radeon_device * rdev)1354 void sumo_dpm_setup_asic(struct radeon_device *rdev)
1355 {
1356 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1357 
1358 	sumo_initialize_m3_arb(rdev);
1359 	pi->fw_version = sumo_get_running_fw_version(rdev);
1360 	DRM_INFO("Found smc ucode version: 0x%08x\n", pi->fw_version);
1361 	sumo_program_acpi_power_level(rdev);
1362 	sumo_enable_acpi_pm(rdev);
1363 	sumo_take_smu_control(rdev, true);
1364 }
1365 
sumo_dpm_display_configuration_changed(struct radeon_device * rdev)1366 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev)
1367 {
1368 
1369 }
1370 
1371 union power_info {
1372 	struct _ATOM_POWERPLAY_INFO info;
1373 	struct _ATOM_POWERPLAY_INFO_V2 info_2;
1374 	struct _ATOM_POWERPLAY_INFO_V3 info_3;
1375 	struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1376 	struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1377 	struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1378 };
1379 
1380 union pplib_clock_info {
1381 	struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1382 	struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1383 	struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1384 	struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1385 };
1386 
1387 union pplib_power_state {
1388 	struct _ATOM_PPLIB_STATE v1;
1389 	struct _ATOM_PPLIB_STATE_V2 v2;
1390 };
1391 
sumo_patch_boot_state(struct radeon_device * rdev,struct sumo_ps * ps)1392 static void sumo_patch_boot_state(struct radeon_device *rdev,
1393 				  struct sumo_ps *ps)
1394 {
1395 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1396 
1397 	ps->num_levels = 1;
1398 	ps->flags = 0;
1399 	ps->levels[0] = pi->boot_pl;
1400 }
1401 
sumo_parse_pplib_non_clock_info(struct radeon_device * rdev,struct radeon_ps * rps,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info,u8 table_rev)1402 static void sumo_parse_pplib_non_clock_info(struct radeon_device *rdev,
1403 					    struct radeon_ps *rps,
1404 					    struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
1405 					    u8 table_rev)
1406 {
1407 	struct sumo_ps *ps = sumo_get_ps(rps);
1408 
1409 	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1410 	rps->class = le16_to_cpu(non_clock_info->usClassification);
1411 	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
1412 
1413 	if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
1414 		rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
1415 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
1416 	} else {
1417 		rps->vclk = 0;
1418 		rps->dclk = 0;
1419 	}
1420 
1421 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1422 		rdev->pm.dpm.boot_ps = rps;
1423 		sumo_patch_boot_state(rdev, ps);
1424 	}
1425 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
1426 		rdev->pm.dpm.uvd_ps = rps;
1427 }
1428 
sumo_parse_pplib_clock_info(struct radeon_device * rdev,struct radeon_ps * rps,int index,union pplib_clock_info * clock_info)1429 static void sumo_parse_pplib_clock_info(struct radeon_device *rdev,
1430 					struct radeon_ps *rps, int index,
1431 					union pplib_clock_info *clock_info)
1432 {
1433 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1434 	struct sumo_ps *ps = sumo_get_ps(rps);
1435 	struct sumo_pl *pl = &ps->levels[index];
1436 	u32 sclk;
1437 
1438 	sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
1439 	sclk |= clock_info->sumo.ucEngineClockHigh << 16;
1440 	pl->sclk = sclk;
1441 	pl->vddc_index = clock_info->sumo.vddcIndex;
1442 	pl->sclk_dpm_tdp_limit = clock_info->sumo.tdpLimit;
1443 
1444 	ps->num_levels = index + 1;
1445 
1446 	if (pi->enable_sclk_ds) {
1447 		pl->ds_divider_index = 5;
1448 		pl->ss_divider_index = 4;
1449 	}
1450 }
1451 
sumo_parse_power_table(struct radeon_device * rdev)1452 static int sumo_parse_power_table(struct radeon_device *rdev)
1453 {
1454 	struct radeon_mode_info *mode_info = &rdev->mode_info;
1455 	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1456 	union pplib_power_state *power_state;
1457 	int i, j, k, non_clock_array_index, clock_array_index;
1458 	union pplib_clock_info *clock_info;
1459 	struct _StateArray *state_array;
1460 	struct _ClockInfoArray *clock_info_array;
1461 	struct _NonClockInfoArray *non_clock_info_array;
1462 	union power_info *power_info;
1463 	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1464 	u16 data_offset;
1465 	u8 frev, crev;
1466 	u8 *power_state_offset;
1467 	struct sumo_ps *ps;
1468 
1469 	if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1470 				   &frev, &crev, &data_offset))
1471 		return -EINVAL;
1472 	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1473 
1474 	state_array = (struct _StateArray *)
1475 		(mode_info->atom_context->bios + data_offset +
1476 		 le16_to_cpu(power_info->pplib.usStateArrayOffset));
1477 	clock_info_array = (struct _ClockInfoArray *)
1478 		(mode_info->atom_context->bios + data_offset +
1479 		 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
1480 	non_clock_info_array = (struct _NonClockInfoArray *)
1481 		(mode_info->atom_context->bios + data_offset +
1482 		 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
1483 
1484 	rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
1485 				  sizeof(struct radeon_ps),
1486 				  GFP_KERNEL);
1487 	if (!rdev->pm.dpm.ps)
1488 		return -ENOMEM;
1489 	power_state_offset = (u8 *)state_array->states;
1490 	for (i = 0; i < state_array->ucNumEntries; i++) {
1491 		u8 *idx;
1492 		power_state = (union pplib_power_state *)power_state_offset;
1493 		non_clock_array_index = power_state->v2.nonClockInfoIndex;
1494 		non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1495 			&non_clock_info_array->nonClockInfo[non_clock_array_index];
1496 		if (!rdev->pm.power_state[i].clock_info) {
1497 			kfree(rdev->pm.dpm.ps);
1498 			return -EINVAL;
1499 		}
1500 		ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL);
1501 		if (ps == NULL) {
1502 			kfree(rdev->pm.dpm.ps);
1503 			return -ENOMEM;
1504 		}
1505 		rdev->pm.dpm.ps[i].ps_priv = ps;
1506 		k = 0;
1507 		idx = (u8 *)&power_state->v2.clockInfoIndex[0];
1508 		for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
1509 			clock_array_index = idx[j];
1510 			if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
1511 				break;
1512 
1513 			clock_info = (union pplib_clock_info *)
1514 				((u8 *)&clock_info_array->clockInfo[0] +
1515 				 (clock_array_index * clock_info_array->ucEntrySize));
1516 			sumo_parse_pplib_clock_info(rdev,
1517 						    &rdev->pm.dpm.ps[i], k,
1518 						    clock_info);
1519 			k++;
1520 		}
1521 		sumo_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1522 						non_clock_info,
1523 						non_clock_info_array->ucEntrySize);
1524 		power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
1525 	}
1526 	rdev->pm.dpm.num_ps = state_array->ucNumEntries;
1527 	return 0;
1528 }
1529 
sumo_convert_vid2_to_vid7(struct radeon_device * rdev,struct sumo_vid_mapping_table * vid_mapping_table,u32 vid_2bit)1530 u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
1531 			      struct sumo_vid_mapping_table *vid_mapping_table,
1532 			      u32 vid_2bit)
1533 {
1534 	u32 i;
1535 
1536 	for (i = 0; i < vid_mapping_table->num_entries; i++) {
1537 		if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
1538 			return vid_mapping_table->entries[i].vid_7bit;
1539 	}
1540 
1541 	return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
1542 }
1543 
1544 #if 0
1545 u32 sumo_convert_vid7_to_vid2(struct radeon_device *rdev,
1546 			      struct sumo_vid_mapping_table *vid_mapping_table,
1547 			      u32 vid_7bit)
1548 {
1549 	u32 i;
1550 
1551 	for (i = 0; i < vid_mapping_table->num_entries; i++) {
1552 		if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
1553 			return vid_mapping_table->entries[i].vid_2bit;
1554 	}
1555 
1556 	return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
1557 }
1558 #endif
1559 
sumo_convert_voltage_index_to_value(struct radeon_device * rdev,u32 vid_2bit)1560 static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev,
1561 					       u32 vid_2bit)
1562 {
1563 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1564 	u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);
1565 
1566 	if (vid_7bit > 0x7C)
1567 		return 0;
1568 
1569 	return (15500 - vid_7bit * 125 + 5) / 10;
1570 }
1571 
sumo_construct_display_voltage_mapping_table(struct radeon_device * rdev,struct sumo_disp_clock_voltage_mapping_table * disp_clk_voltage_mapping_table,ATOM_CLK_VOLT_CAPABILITY * table)1572 static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev,
1573 							 struct sumo_disp_clock_voltage_mapping_table *disp_clk_voltage_mapping_table,
1574 							 ATOM_CLK_VOLT_CAPABILITY *table)
1575 {
1576 	u32 i;
1577 
1578 	for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1579 		if (table[i].ulMaximumSupportedCLK == 0)
1580 			break;
1581 
1582 		disp_clk_voltage_mapping_table->display_clock_frequency[i] =
1583 			table[i].ulMaximumSupportedCLK;
1584 	}
1585 
1586 	disp_clk_voltage_mapping_table->num_max_voltage_levels = i;
1587 
1588 	if (disp_clk_voltage_mapping_table->num_max_voltage_levels == 0) {
1589 		disp_clk_voltage_mapping_table->display_clock_frequency[0] = 80000;
1590 		disp_clk_voltage_mapping_table->num_max_voltage_levels = 1;
1591 	}
1592 }
1593 
sumo_construct_sclk_voltage_mapping_table(struct radeon_device * rdev,struct sumo_sclk_voltage_mapping_table * sclk_voltage_mapping_table,ATOM_AVAILABLE_SCLK_LIST * table)1594 void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
1595 					       struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
1596 					       ATOM_AVAILABLE_SCLK_LIST *table)
1597 {
1598 	u32 i;
1599 	u32 n = 0;
1600 	u32 prev_sclk = 0;
1601 
1602 	for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1603 		if (table[i].ulSupportedSCLK > prev_sclk) {
1604 			sclk_voltage_mapping_table->entries[n].sclk_frequency =
1605 				table[i].ulSupportedSCLK;
1606 			sclk_voltage_mapping_table->entries[n].vid_2bit =
1607 				table[i].usVoltageIndex;
1608 			prev_sclk = table[i].ulSupportedSCLK;
1609 			n++;
1610 		}
1611 	}
1612 
1613 	sclk_voltage_mapping_table->num_max_dpm_entries = n;
1614 }
1615 
sumo_construct_vid_mapping_table(struct radeon_device * rdev,struct sumo_vid_mapping_table * vid_mapping_table,ATOM_AVAILABLE_SCLK_LIST * table)1616 void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
1617 				      struct sumo_vid_mapping_table *vid_mapping_table,
1618 				      ATOM_AVAILABLE_SCLK_LIST *table)
1619 {
1620 	u32 i, j;
1621 
1622 	for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1623 		if (table[i].ulSupportedSCLK != 0) {
1624 			if (table[i].usVoltageIndex >= SUMO_MAX_NUMBER_VOLTAGES)
1625 				continue;
1626 			vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
1627 				table[i].usVoltageID;
1628 			vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
1629 				table[i].usVoltageIndex;
1630 		}
1631 	}
1632 
1633 	for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1634 		if (vid_mapping_table->entries[i].vid_7bit == 0) {
1635 			for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
1636 				if (vid_mapping_table->entries[j].vid_7bit != 0) {
1637 					vid_mapping_table->entries[i] =
1638 						vid_mapping_table->entries[j];
1639 					vid_mapping_table->entries[j].vid_7bit = 0;
1640 					break;
1641 				}
1642 			}
1643 
1644 			if (j == SUMO_MAX_NUMBER_VOLTAGES)
1645 				break;
1646 		}
1647 	}
1648 
1649 	vid_mapping_table->num_entries = i;
1650 }
1651 
1652 union igp_info {
1653 	struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1654 	struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1655 	struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
1656 	struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1657 };
1658 
sumo_parse_sys_info_table(struct radeon_device * rdev)1659 static int sumo_parse_sys_info_table(struct radeon_device *rdev)
1660 {
1661 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1662 	struct radeon_mode_info *mode_info = &rdev->mode_info;
1663 	int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1664 	union igp_info *igp_info;
1665 	u8 frev, crev;
1666 	u16 data_offset;
1667 	int i;
1668 
1669 	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1670 				   &frev, &crev, &data_offset)) {
1671 		igp_info = (union igp_info *)(mode_info->atom_context->bios +
1672 					      data_offset);
1673 
1674 		if (crev != 6) {
1675 			DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1676 			return -EINVAL;
1677 		}
1678 		pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_6.ulBootUpEngineClock);
1679 		pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock);
1680 		pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_6.ulBootUpUMAClock);
1681 		pi->sys_info.bootup_nb_voltage_index =
1682 			le16_to_cpu(igp_info->info_6.usBootUpNBVoltage);
1683 		if (igp_info->info_6.ucHtcTmpLmt == 0)
1684 			pi->sys_info.htc_tmp_lmt = 203;
1685 		else
1686 			pi->sys_info.htc_tmp_lmt = igp_info->info_6.ucHtcTmpLmt;
1687 		if (igp_info->info_6.ucHtcHystLmt == 0)
1688 			pi->sys_info.htc_hyst_lmt = 5;
1689 		else
1690 			pi->sys_info.htc_hyst_lmt = igp_info->info_6.ucHtcHystLmt;
1691 		if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
1692 			DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
1693 		}
1694 		for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) {
1695 			pi->sys_info.csr_m3_arb_cntl_default[i] =
1696 				le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_DEFAULT[i]);
1697 			pi->sys_info.csr_m3_arb_cntl_uvd[i] =
1698 				le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_UVD[i]);
1699 			pi->sys_info.csr_m3_arb_cntl_fs3d[i] =
1700 				le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_FS3D[i]);
1701 		}
1702 		pi->sys_info.sclk_dpm_boost_margin =
1703 			le32_to_cpu(igp_info->info_6.SclkDpmBoostMargin);
1704 		pi->sys_info.sclk_dpm_throttle_margin =
1705 			le32_to_cpu(igp_info->info_6.SclkDpmThrottleMargin);
1706 		pi->sys_info.sclk_dpm_tdp_limit_pg =
1707 			le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitPG);
1708 		pi->sys_info.gnb_tdp_limit = le16_to_cpu(igp_info->info_6.GnbTdpLimit);
1709 		pi->sys_info.sclk_dpm_tdp_limit_boost =
1710 			le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitBoost);
1711 		pi->sys_info.boost_sclk = le32_to_cpu(igp_info->info_6.ulBoostEngineCLock);
1712 		pi->sys_info.boost_vid_2bit = igp_info->info_6.ulBoostVid_2bit;
1713 		if (igp_info->info_6.EnableBoost)
1714 			pi->sys_info.enable_boost = true;
1715 		else
1716 			pi->sys_info.enable_boost = false;
1717 		sumo_construct_display_voltage_mapping_table(rdev,
1718 							     &pi->sys_info.disp_clk_voltage_mapping_table,
1719 							     igp_info->info_6.sDISPCLK_Voltage);
1720 		sumo_construct_sclk_voltage_mapping_table(rdev,
1721 							  &pi->sys_info.sclk_voltage_mapping_table,
1722 							  igp_info->info_6.sAvail_SCLK);
1723 		sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,
1724 						 igp_info->info_6.sAvail_SCLK);
1725 
1726 	}
1727 	return 0;
1728 }
1729 
sumo_construct_boot_and_acpi_state(struct radeon_device * rdev)1730 static void sumo_construct_boot_and_acpi_state(struct radeon_device *rdev)
1731 {
1732 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1733 
1734 	pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1735 	pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1736 	pi->boot_pl.ds_divider_index = 0;
1737 	pi->boot_pl.ss_divider_index = 0;
1738 	pi->boot_pl.allow_gnb_slow = 1;
1739 	pi->acpi_pl = pi->boot_pl;
1740 	pi->current_ps.num_levels = 1;
1741 	pi->current_ps.levels[0] = pi->boot_pl;
1742 }
1743 
sumo_dpm_init(struct radeon_device * rdev)1744 int sumo_dpm_init(struct radeon_device *rdev)
1745 {
1746 	struct sumo_power_info *pi;
1747 	u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
1748 	int ret;
1749 
1750 	pi = kzalloc(sizeof(struct sumo_power_info), GFP_KERNEL);
1751 	if (pi == NULL)
1752 		return -ENOMEM;
1753 	rdev->pm.dpm.priv = pi;
1754 
1755 	pi->driver_nbps_policy_disable = false;
1756 	if ((rdev->family == CHIP_PALM) && (hw_rev < 3))
1757 		pi->disable_gfx_power_gating_in_uvd = true;
1758 	else
1759 		pi->disable_gfx_power_gating_in_uvd = false;
1760 	pi->enable_alt_vddnb = true;
1761 	pi->enable_sclk_ds = true;
1762 	pi->enable_dynamic_m3_arbiter = false;
1763 	pi->enable_dynamic_patch_ps = true;
1764 	/* Some PALM chips don't seem to properly ungate gfx when UVD is in use;
1765 	 * for now just disable gfx PG.
1766 	 */
1767 	if (rdev->family == CHIP_PALM)
1768 		pi->enable_gfx_power_gating = false;
1769 	else
1770 		pi->enable_gfx_power_gating = true;
1771 	pi->enable_gfx_clock_gating = true;
1772 	pi->enable_mg_clock_gating = true;
1773 	pi->enable_auto_thermal_throttling = true;
1774 
1775 	ret = sumo_parse_sys_info_table(rdev);
1776 	if (ret)
1777 		return ret;
1778 
1779 	sumo_construct_boot_and_acpi_state(rdev);
1780 
1781 	ret = r600_get_platform_caps(rdev);
1782 	if (ret)
1783 		return ret;
1784 
1785 	ret = sumo_parse_power_table(rdev);
1786 	if (ret)
1787 		return ret;
1788 
1789 	pi->pasi = CYPRESS_HASI_DFLT;
1790 	pi->asi = RV770_ASI_DFLT;
1791 	pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt;
1792 	pi->enable_boost = pi->sys_info.enable_boost;
1793 	pi->enable_dpm = true;
1794 
1795 	return 0;
1796 }
1797 
sumo_dpm_print_power_state(struct radeon_device * rdev,struct radeon_ps * rps)1798 void sumo_dpm_print_power_state(struct radeon_device *rdev,
1799 				struct radeon_ps *rps)
1800 {
1801 	int i;
1802 	struct sumo_ps *ps = sumo_get_ps(rps);
1803 
1804 	r600_dpm_print_class_info(rps->class, rps->class2);
1805 	r600_dpm_print_cap_info(rps->caps);
1806 	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1807 	for (i = 0; i < ps->num_levels; i++) {
1808 		struct sumo_pl *pl = &ps->levels[i];
1809 		printk("\t\tpower level %d    sclk: %u vddc: %u\n",
1810 		       i, pl->sclk,
1811 		       sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1812 	}
1813 	r600_dpm_print_ps_status(rdev, rps);
1814 }
1815 
sumo_dpm_debugfs_print_current_performance_level(struct radeon_device * rdev,struct seq_file * m)1816 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
1817 						      struct seq_file *m)
1818 {
1819 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1820 	struct radeon_ps *rps = &pi->current_rps;
1821 	struct sumo_ps *ps = sumo_get_ps(rps);
1822 	struct sumo_pl *pl;
1823 	u32 current_index =
1824 		(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
1825 		CURR_INDEX_SHIFT;
1826 
1827 	if (current_index == BOOST_DPM_LEVEL) {
1828 		pl = &pi->boost_pl;
1829 		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1830 		seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
1831 			   current_index, pl->sclk,
1832 			   sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1833 	} else if (current_index >= ps->num_levels) {
1834 		seq_printf(m, "invalid dpm profile %d\n", current_index);
1835 	} else {
1836 		pl = &ps->levels[current_index];
1837 		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1838 		seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
1839 			   current_index, pl->sclk,
1840 			   sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1841 	}
1842 }
1843 
sumo_dpm_get_current_sclk(struct radeon_device * rdev)1844 u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev)
1845 {
1846 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1847 	struct radeon_ps *rps = &pi->current_rps;
1848 	struct sumo_ps *ps = sumo_get_ps(rps);
1849 	struct sumo_pl *pl;
1850 	u32 current_index =
1851 		(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
1852 		CURR_INDEX_SHIFT;
1853 
1854 	if (current_index == BOOST_DPM_LEVEL) {
1855 		pl = &pi->boost_pl;
1856 		return pl->sclk;
1857 	} else if (current_index >= ps->num_levels) {
1858 		return 0;
1859 	} else {
1860 		pl = &ps->levels[current_index];
1861 		return pl->sclk;
1862 	}
1863 }
1864 
sumo_dpm_get_current_mclk(struct radeon_device * rdev)1865 u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev)
1866 {
1867 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1868 
1869 	return pi->sys_info.bootup_uma_clk;
1870 }
1871 
sumo_dpm_get_current_vddc(struct radeon_device * rdev)1872 u16 sumo_dpm_get_current_vddc(struct radeon_device *rdev)
1873 {
1874 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1875 	struct radeon_ps *rps = &pi->current_rps;
1876 	struct sumo_ps *ps = sumo_get_ps(rps);
1877 	struct sumo_pl *pl;
1878 	u32 current_index =
1879 		(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
1880 		CURR_INDEX_SHIFT;
1881 
1882 	if (current_index == BOOST_DPM_LEVEL) {
1883 		pl = &pi->boost_pl;
1884 	} else if (current_index >= ps->num_levels) {
1885 		return 0;
1886 	} else {
1887 		pl = &ps->levels[current_index];
1888 	}
1889 	return sumo_convert_voltage_index_to_value(rdev, pl->vddc_index);
1890 }
1891 
sumo_dpm_fini(struct radeon_device * rdev)1892 void sumo_dpm_fini(struct radeon_device *rdev)
1893 {
1894 	int i;
1895 
1896 	sumo_cleanup_asic(rdev); /* ??? */
1897 
1898 	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1899 		kfree(rdev->pm.dpm.ps[i].ps_priv);
1900 	}
1901 	kfree(rdev->pm.dpm.ps);
1902 	kfree(rdev->pm.dpm.priv);
1903 }
1904 
sumo_dpm_get_sclk(struct radeon_device * rdev,bool low)1905 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low)
1906 {
1907 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1908 	struct sumo_ps *requested_state = sumo_get_ps(&pi->requested_rps);
1909 
1910 	if (low)
1911 		return requested_state->levels[0].sclk;
1912 	else
1913 		return requested_state->levels[requested_state->num_levels - 1].sclk;
1914 }
1915 
sumo_dpm_get_mclk(struct radeon_device * rdev,bool low)1916 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low)
1917 {
1918 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1919 
1920 	return pi->sys_info.bootup_uma_clk;
1921 }
1922 
sumo_dpm_force_performance_level(struct radeon_device * rdev,enum radeon_dpm_forced_level level)1923 int sumo_dpm_force_performance_level(struct radeon_device *rdev,
1924 				     enum radeon_dpm_forced_level level)
1925 {
1926 	struct sumo_power_info *pi = sumo_get_pi(rdev);
1927 	struct radeon_ps *rps = &pi->current_rps;
1928 	struct sumo_ps *ps = sumo_get_ps(rps);
1929 	int i;
1930 
1931 	if (ps->num_levels <= 1)
1932 		return 0;
1933 
1934 	if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1935 		if (pi->enable_boost)
1936 			sumo_enable_boost(rdev, rps, false);
1937 		sumo_power_level_enable(rdev, ps->num_levels - 1, true);
1938 		sumo_set_forced_level(rdev, ps->num_levels - 1);
1939 		sumo_set_forced_mode_enabled(rdev);
1940 		for (i = 0; i < ps->num_levels - 1; i++) {
1941 			sumo_power_level_enable(rdev, i, false);
1942 		}
1943 		sumo_set_forced_mode(rdev, false);
1944 		sumo_set_forced_mode_enabled(rdev);
1945 		sumo_set_forced_mode(rdev, false);
1946 	} else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1947 		if (pi->enable_boost)
1948 			sumo_enable_boost(rdev, rps, false);
1949 		sumo_power_level_enable(rdev, 0, true);
1950 		sumo_set_forced_level(rdev, 0);
1951 		sumo_set_forced_mode_enabled(rdev);
1952 		for (i = 1; i < ps->num_levels; i++) {
1953 			sumo_power_level_enable(rdev, i, false);
1954 		}
1955 		sumo_set_forced_mode(rdev, false);
1956 		sumo_set_forced_mode_enabled(rdev);
1957 		sumo_set_forced_mode(rdev, false);
1958 	} else {
1959 		for (i = 0; i < ps->num_levels; i++) {
1960 			sumo_power_level_enable(rdev, i, true);
1961 		}
1962 		if (pi->enable_boost)
1963 			sumo_enable_boost(rdev, rps, true);
1964 	}
1965 
1966 	rdev->pm.dpm.forced_level = level;
1967 
1968 	return 0;
1969 }
1970