1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dcn32_clk_mgr_smu_msg.h"
27
28 #include "clk_mgr_internal.h"
29 #include "reg_helper.h"
30 #include "dalsmc.h"
31 #include "smu13_driver_if.h"
32
33 #define mmDAL_MSG_REG 0x1628A
34 #define mmDAL_ARG_REG 0x16273
35 #define mmDAL_RESP_REG 0x16274
36
37 #define REG(reg_name) \
38 mm ## reg_name
39
40 #include "logger_types.h"
41
42 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
43
44
45 /*
46 * Function to be used instead of REG_WAIT macro because the wait ends when
47 * the register is NOT EQUAL to zero, and because the translation in msg_if.h
48 * won't work with REG_WAIT.
49 */
dcn32_smu_wait_for_response(struct clk_mgr_internal * clk_mgr,unsigned int delay_us,unsigned int max_retries)50 static uint32_t dcn32_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
51 {
52 uint32_t reg = 0;
53
54 do {
55 reg = REG_READ(DAL_RESP_REG);
56 if (reg)
57 break;
58
59 if (delay_us >= 1000)
60 msleep(delay_us/1000);
61 else if (delay_us > 0)
62 udelay(delay_us);
63 } while (max_retries--);
64
65 return reg;
66 }
67
dcn32_smu_send_msg_with_param(struct clk_mgr_internal * clk_mgr,uint32_t msg_id,uint32_t param_in,uint32_t * param_out)68 static bool dcn32_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)
69 {
70 /* Wait for response register to be ready */
71 dcn32_smu_wait_for_response(clk_mgr, 10, 200000);
72
73 /* Clear response register */
74 REG_WRITE(DAL_RESP_REG, 0);
75
76 /* Set the parameter register for the SMU message */
77 REG_WRITE(DAL_ARG_REG, param_in);
78
79 /* Trigger the message transaction by writing the message ID */
80 REG_WRITE(DAL_MSG_REG, msg_id);
81
82 /* Wait for response */
83 if (dcn32_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) {
84 if (param_out)
85 *param_out = REG_READ(DAL_ARG_REG);
86
87 return true;
88 }
89
90 return false;
91 }
92
dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal * clk_mgr,bool enable)93 void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable)
94 {
95 smu_print("FCLK P-state support value is : %d\n", enable);
96
97 dcn32_smu_send_msg_with_param(clk_mgr,
98 DALSMC_MSG_SetFclkSwitchAllow, enable ? FCLK_PSTATE_SUPPORTED : FCLK_PSTATE_NOTSUPPORTED, NULL);
99 }
100
dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal * clk_mgr,unsigned int num_ways)101 void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways)
102 {
103 uint32_t param = (num_ways << 1) | (num_ways > 0);
104
105 dcn32_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetCabForUclkPstate, param, NULL);
106 smu_print("Numways for SubVP : %d\n", num_ways);
107 }
108
dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal * clk_mgr)109 void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
110 {
111 smu_print("SMU Transfer WM table DRAM 2 SMU\n");
112
113 dcn32_smu_send_msg_with_param(clk_mgr,
114 DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL);
115 }
116
dcn32_smu_set_pme_workaround(struct clk_mgr_internal * clk_mgr)117 void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)
118 {
119 smu_print("SMU Set PME workaround\n");
120
121 dcn32_smu_send_msg_with_param(clk_mgr,
122 DALSMC_MSG_BacoAudioD3PME, 0, NULL);
123 }
124
125 /* Returns the actual frequency that was set in MHz, 0 on failure */
dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal * clk_mgr,uint32_t clk,uint16_t freq_mhz)126 unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)
127 {
128 uint32_t response = 0;
129
130 /* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
131 uint32_t param = (clk << 16) | freq_mhz;
132
133 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);
134
135 dcn32_smu_send_msg_with_param(clk_mgr,
136 DALSMC_MSG_SetHardMinByFreq, param, &response);
137
138 smu_print("SMU Frequency set = %d KHz\n", response);
139
140 return response;
141 }
142
dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal * clk_mgr,bool enable)143 void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable)
144 {
145 smu_print("PMFW to wait for DMCUB ack for MCLK : %d\n", enable);
146
147 dcn32_smu_send_msg_with_param(clk_mgr, 0x14, enable ? 1 : 0, NULL);
148 }
149