1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 
27 #include "reg_helper.h"
28 
29 #include "core_types.h"
30 #include "link_encoder.h"
31 #include "dcn321_dio_link_encoder.h"
32 #include "dcn31/dcn31_dio_link_encoder.h"
33 #include "stream_encoder.h"
34 #include "dc_bios_types.h"
35 
36 #include "gpio_service_interface.h"
37 
38 #ifndef MIN
39 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
40 #endif
41 
42 #define CTX \
43 	enc10->base.ctx
44 #define DC_LOGGER \
45 	enc10->base.ctx->logger
46 
47 #define REG(reg)\
48 	(enc10->link_regs->reg)
49 
50 #undef FN
51 #define FN(reg_name, field_name) \
52 	enc10->link_shift->field_name, enc10->link_mask->field_name
53 
54 #define AUX_REG(reg)\
55 	(enc10->aux_regs->reg)
56 
57 #define AUX_REG_READ(reg_name) \
58 		dm_read_reg(CTX, AUX_REG(reg_name))
59 
60 #define AUX_REG_WRITE(reg_name, val) \
61 			dm_write_reg(CTX, AUX_REG(reg_name), val)
62 
63 static const struct link_encoder_funcs dcn321_link_enc_funcs = {
64 	.read_state = link_enc2_read_state,
65 	.validate_output_with_stream =
66 			dcn30_link_encoder_validate_output_with_stream,
67 	.hw_init = enc32_hw_init,
68 	.setup = dcn10_link_encoder_setup,
69 	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
70 	.enable_dp_output = dcn32_link_encoder_enable_dp_output,
71 	.enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
72 	.disable_output = dcn10_link_encoder_disable_output,
73 	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
74 	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
75 	.update_mst_stream_allocation_table =
76 		dcn10_link_encoder_update_mst_stream_allocation_table,
77 	.psr_program_dp_dphy_fast_training =
78 			dcn10_psr_program_dp_dphy_fast_training,
79 	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
80 	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
81 	.enable_hpd = dcn10_link_encoder_enable_hpd,
82 	.disable_hpd = dcn10_link_encoder_disable_hpd,
83 	.is_dig_enabled = dcn10_is_dig_enabled,
84 	.destroy = dcn10_link_encoder_destroy,
85 	.fec_set_enable = enc2_fec_set_enable,
86 	.fec_set_ready = enc2_fec_set_ready,
87 	.fec_is_active = enc2_fec_is_active,
88 	.get_dig_frontend = dcn10_get_dig_frontend,
89 	.get_dig_mode = dcn10_get_dig_mode,
90 	.is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
91 	.get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
92 	.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
93 };
94 
dcn321_link_encoder_construct(struct dcn20_link_encoder * enc20,const struct encoder_init_data * init_data,const struct encoder_feature_support * enc_features,const struct dcn10_link_enc_registers * link_regs,const struct dcn10_link_enc_aux_registers * aux_regs,const struct dcn10_link_enc_hpd_registers * hpd_regs,const struct dcn10_link_enc_shift * link_shift,const struct dcn10_link_enc_mask * link_mask)95 void dcn321_link_encoder_construct(
96 	struct dcn20_link_encoder *enc20,
97 	const struct encoder_init_data *init_data,
98 	const struct encoder_feature_support *enc_features,
99 	const struct dcn10_link_enc_registers *link_regs,
100 	const struct dcn10_link_enc_aux_registers *aux_regs,
101 	const struct dcn10_link_enc_hpd_registers *hpd_regs,
102 	const struct dcn10_link_enc_shift *link_shift,
103 	const struct dcn10_link_enc_mask *link_mask)
104 {
105 	struct bp_connector_speed_cap_info bp_cap_info = {0};
106 	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
107 	enum bp_result result = BP_RESULT_OK;
108 	struct dcn10_link_encoder *enc10 = &enc20->enc10;
109 
110 	enc10->base.funcs = &dcn321_link_enc_funcs;
111 	enc10->base.ctx = init_data->ctx;
112 	enc10->base.id = init_data->encoder;
113 
114 	enc10->base.hpd_source = init_data->hpd_source;
115 	enc10->base.connector = init_data->connector;
116 
117 	if (enc10->base.connector.id == CONNECTOR_ID_USBC)
118 		enc10->base.features.flags.bits.DP_IS_USB_C = 1;
119 
120 	enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
121 
122 	enc10->base.features = *enc_features;
123 
124 	enc10->base.transmitter = init_data->transmitter;
125 
126 	/* set the flag to indicate whether driver poll the I2C data pin
127 	 * while doing the DP sink detect
128 	 */
129 
130 /*	if (dal_adapter_service_is_feature_supported(as,
131 		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
132 		enc10->base.features.flags.bits.
133 			DP_SINK_DETECT_POLL_DATA_PIN = true;*/
134 
135 	enc10->base.output_signals =
136 		SIGNAL_TYPE_DVI_SINGLE_LINK |
137 		SIGNAL_TYPE_DVI_DUAL_LINK |
138 		SIGNAL_TYPE_LVDS |
139 		SIGNAL_TYPE_DISPLAY_PORT |
140 		SIGNAL_TYPE_DISPLAY_PORT_MST |
141 		SIGNAL_TYPE_EDP |
142 		SIGNAL_TYPE_HDMI_TYPE_A;
143 
144 	enc10->link_regs = link_regs;
145 	enc10->aux_regs = aux_regs;
146 	enc10->hpd_regs = hpd_regs;
147 	enc10->link_shift = link_shift;
148 	enc10->link_mask = link_mask;
149 
150 	switch (enc10->base.transmitter) {
151 	case TRANSMITTER_UNIPHY_A:
152 		enc10->base.preferred_engine = ENGINE_ID_DIGA;
153 	break;
154 	case TRANSMITTER_UNIPHY_B:
155 		enc10->base.preferred_engine = ENGINE_ID_DIGB;
156 	break;
157 	case TRANSMITTER_UNIPHY_C:
158 		enc10->base.preferred_engine = ENGINE_ID_DIGC;
159 	break;
160 	case TRANSMITTER_UNIPHY_D:
161 		enc10->base.preferred_engine = ENGINE_ID_DIGD;
162 	break;
163 	case TRANSMITTER_UNIPHY_E:
164 		enc10->base.preferred_engine = ENGINE_ID_DIGE;
165 	break;
166 	default:
167 		ASSERT_CRITICAL(false);
168 		enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
169 	}
170 
171 	/* default to one to mirror Windows behavior */
172 	enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
173 
174 	if (bp_funcs->get_connector_speed_cap_info)
175 		result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios,
176 						enc10->base.connector, &bp_cap_info);
177 
178 	/* Override features with DCE-specific values */
179 	if (result == BP_RESULT_OK) {
180 		enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
181 				bp_cap_info.DP_HBR2_EN;
182 		enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
183 				bp_cap_info.DP_HBR3_EN;
184 		enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
185 		enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;
186 		enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
187 		enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
188 		enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
189 	} else {
190 		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
191 				__func__,
192 				result);
193 	}
194 	if (enc10->base.ctx->dc->debug.hdmi20_disable) {
195 		enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
196 	}
197 }
198