1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27
28 #include "dm_services.h"
29 #include "dc.h"
30
31 #include "dcn31/dcn31_init.h"
32 #include "dcn314/dcn314_init.h"
33
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn314_resource.h"
37
38 #include "dcn20/dcn20_resource.h"
39 #include "dcn30/dcn30_resource.h"
40 #include "dcn31/dcn31_resource.h"
41
42 #include "dcn10/dcn10_ipp.h"
43 #include "dcn30/dcn30_hubbub.h"
44 #include "dcn31/dcn31_hubbub.h"
45 #include "dcn30/dcn30_mpc.h"
46 #include "dcn31/dcn31_hubp.h"
47 #include "irq/dcn31/irq_service_dcn31.h"
48 #include "irq/dcn314/irq_service_dcn314.h"
49 #include "dcn30/dcn30_dpp.h"
50 #include "dcn314/dcn314_optc.h"
51 #include "dcn20/dcn20_hwseq.h"
52 #include "dcn30/dcn30_hwseq.h"
53 #include "dce110/dce110_hw_sequencer.h"
54 #include "dcn30/dcn30_opp.h"
55 #include "dcn20/dcn20_dsc.h"
56 #include "dcn30/dcn30_vpg.h"
57 #include "dcn30/dcn30_afmt.h"
58 #include "dcn31/dcn31_dio_link_encoder.h"
59 #include "dcn314/dcn314_dio_stream_encoder.h"
60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
61 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
62 #include "dcn31/dcn31_apg.h"
63 #include "dcn31/dcn31_vpg.h"
64 #include "dcn31/dcn31_afmt.h"
65 #include "dce/dce_clock_source.h"
66 #include "dce/dce_audio.h"
67 #include "dce/dce_hwseq.h"
68 #include "clk_mgr.h"
69 #include "virtual/virtual_stream_encoder.h"
70 #include "dce110/dce110_resource.h"
71 #include "dml/display_mode_vba.h"
72 #include "dml/dcn31/dcn31_fpu.h"
73 #include "dml/dcn314/dcn314_fpu.h"
74 #include "dcn314/dcn314_dccg.h"
75 #include "dcn10/dcn10_resource.h"
76 #include "dcn31/dcn31_panel_cntl.h"
77 #include "dcn314/dcn314_hwseq.h"
78
79 #include "dcn30/dcn30_dwb.h"
80 #include "dcn30/dcn30_mmhubbub.h"
81
82 #include "dcn/dcn_3_1_4_offset.h"
83 #include "dcn/dcn_3_1_4_sh_mask.h"
84 #include "dpcs/dpcs_3_1_4_offset.h"
85 #include "dpcs/dpcs_3_1_4_sh_mask.h"
86
87 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
89
90 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
91 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
92
93 #include "reg_helper.h"
94 #include "dce/dmub_abm.h"
95 #include "dce/dmub_psr.h"
96 #include "dce/dmub_replay.h"
97 #include "dce/dce_aux.h"
98 #include "dce/dce_i2c.h"
99 #include "dml/dcn314/display_mode_vba_314.h"
100 #include "vm_helper.h"
101 #include "dcn20/dcn20_vmid.h"
102
103 #include "link_enc_cfg.h"
104
105 #define DCN_BASE__INST0_SEG1 0x000000C0
106 #define DCN_BASE__INST0_SEG2 0x000034C0
107 #define DCN_BASE__INST0_SEG3 0x00009000
108
109 #define NBIO_BASE__INST0_SEG1 0x00000014
110
111 #define MAX_INSTANCE 7
112 #define MAX_SEGMENT 8
113
114 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a
115 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1
116 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b
117 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1
118 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e
119 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1
120
121 #define DC_LOGGER_INIT(logger)
122
123 enum dcn31_clk_src_array_id {
124 DCN31_CLK_SRC_PLL0,
125 DCN31_CLK_SRC_PLL1,
126 DCN31_CLK_SRC_PLL2,
127 DCN31_CLK_SRC_PLL3,
128 DCN31_CLK_SRC_PLL4,
129 DCN30_CLK_SRC_TOTAL
130 };
131
132 /* begin *********************
133 * macros to expend register list macro defined in HW object header file
134 */
135
136 /* DCN */
137 /* TODO awful hack. fixup dcn20_dwb.h */
138 #undef BASE_INNER
139 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
140
141 #define BASE(seg) BASE_INNER(seg)
142
143 #define SR(reg_name)\
144 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
145 reg ## reg_name
146
147 #define SRI(reg_name, block, id)\
148 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
149 reg ## block ## id ## _ ## reg_name
150
151 #define SRI2(reg_name, block, id)\
152 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
153 reg ## reg_name
154
155 #define SRIR(var_name, reg_name, block, id)\
156 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
157 reg ## block ## id ## _ ## reg_name
158
159 #define SRII(reg_name, block, id)\
160 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
161 reg ## block ## id ## _ ## reg_name
162
163 #define SRII_MPC_RMU(reg_name, block, id)\
164 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
165 reg ## block ## id ## _ ## reg_name
166
167 #define SRII_DWB(reg_name, temp_name, block, id)\
168 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
169 reg ## block ## id ## _ ## temp_name
170
171 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
172 .field_name = reg_name ## __ ## field_name ## post_fix
173
174 #define DCCG_SRII(reg_name, block, id)\
175 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
176 reg ## block ## id ## _ ## reg_name
177
178 #define VUPDATE_SRII(reg_name, block, id)\
179 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
180 reg ## reg_name ## _ ## block ## id
181
182 /* NBIO */
183 #define NBIO_BASE_INNER(seg) \
184 NBIO_BASE__INST0_SEG ## seg
185
186 #define NBIO_BASE(seg) \
187 NBIO_BASE_INNER(seg)
188
189 #define NBIO_SR(reg_name)\
190 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
191 regBIF_BX2_ ## reg_name
192
193 /* MMHUB */
194 #define MMHUB_BASE_INNER(seg) \
195 MMHUB_BASE__INST0_SEG ## seg
196
197 #define MMHUB_BASE(seg) \
198 MMHUB_BASE_INNER(seg)
199
200 #define MMHUB_SR(reg_name)\
201 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \
202 reg ## reg_name
203
204 /* CLOCK */
205 #define CLK_BASE_INNER(seg) \
206 CLK_BASE__INST0_SEG ## seg
207
208 #define CLK_BASE(seg) \
209 CLK_BASE_INNER(seg)
210
211 #define CLK_SRI(reg_name, block, inst)\
212 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
213 reg ## block ## _ ## inst ## _ ## reg_name
214
215
216 static const struct bios_registers bios_regs = {
217 NBIO_SR(BIOS_SCRATCH_3),
218 NBIO_SR(BIOS_SCRATCH_6)
219 };
220
221 #define clk_src_regs(index, pllid)\
222 [index] = {\
223 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
224 }
225
226 static const struct dce110_clk_src_regs clk_src_regs[] = {
227 clk_src_regs(0, A),
228 clk_src_regs(1, B),
229 clk_src_regs(2, C),
230 clk_src_regs(3, D),
231 clk_src_regs(4, E)
232 };
233
234 static const struct dce110_clk_src_shift cs_shift = {
235 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
236 };
237
238 static const struct dce110_clk_src_mask cs_mask = {
239 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
240 };
241
242 #define abm_regs(id)\
243 [id] = {\
244 ABM_DCN302_REG_LIST(id)\
245 }
246
247 static const struct dce_abm_registers abm_regs[] = {
248 abm_regs(0),
249 abm_regs(1),
250 abm_regs(2),
251 abm_regs(3),
252 };
253
254 static const struct dce_abm_shift abm_shift = {
255 ABM_MASK_SH_LIST_DCN30(__SHIFT)
256 };
257
258 static const struct dce_abm_mask abm_mask = {
259 ABM_MASK_SH_LIST_DCN30(_MASK)
260 };
261
262 #define audio_regs(id)\
263 [id] = {\
264 AUD_COMMON_REG_LIST(id)\
265 }
266
267 static const struct dce_audio_registers audio_regs[] = {
268 audio_regs(0),
269 audio_regs(1),
270 audio_regs(2),
271 audio_regs(3),
272 audio_regs(4),
273 audio_regs(5),
274 audio_regs(6)
275 };
276
277 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
278 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
279 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
280 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
281
282 static const struct dce_audio_shift audio_shift = {
283 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
284 };
285
286 static const struct dce_audio_mask audio_mask = {
287 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
288 };
289
290 #define vpg_regs(id)\
291 [id] = {\
292 VPG_DCN31_REG_LIST(id)\
293 }
294
295 static const struct dcn31_vpg_registers vpg_regs[] = {
296 vpg_regs(0),
297 vpg_regs(1),
298 vpg_regs(2),
299 vpg_regs(3),
300 vpg_regs(4),
301 vpg_regs(5),
302 vpg_regs(6),
303 vpg_regs(7),
304 vpg_regs(8),
305 vpg_regs(9),
306 };
307
308 static const struct dcn31_vpg_shift vpg_shift = {
309 DCN31_VPG_MASK_SH_LIST(__SHIFT)
310 };
311
312 static const struct dcn31_vpg_mask vpg_mask = {
313 DCN31_VPG_MASK_SH_LIST(_MASK)
314 };
315
316 #define afmt_regs(id)\
317 [id] = {\
318 AFMT_DCN31_REG_LIST(id)\
319 }
320
321 static const struct dcn31_afmt_registers afmt_regs[] = {
322 afmt_regs(0),
323 afmt_regs(1),
324 afmt_regs(2),
325 afmt_regs(3),
326 afmt_regs(4),
327 afmt_regs(5)
328 };
329
330 static const struct dcn31_afmt_shift afmt_shift = {
331 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
332 };
333
334 static const struct dcn31_afmt_mask afmt_mask = {
335 DCN31_AFMT_MASK_SH_LIST(_MASK)
336 };
337
338 #define apg_regs(id)\
339 [id] = {\
340 APG_DCN31_REG_LIST(id)\
341 }
342
343 static const struct dcn31_apg_registers apg_regs[] = {
344 apg_regs(0),
345 apg_regs(1),
346 apg_regs(2),
347 apg_regs(3)
348 };
349
350 static const struct dcn31_apg_shift apg_shift = {
351 DCN31_APG_MASK_SH_LIST(__SHIFT)
352 };
353
354 static const struct dcn31_apg_mask apg_mask = {
355 DCN31_APG_MASK_SH_LIST(_MASK)
356 };
357
358 #define stream_enc_regs(id)\
359 [id] = {\
360 SE_DCN314_REG_LIST(id)\
361 }
362
363 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
364 stream_enc_regs(0),
365 stream_enc_regs(1),
366 stream_enc_regs(2),
367 stream_enc_regs(3),
368 stream_enc_regs(4)
369 };
370
371 static const struct dcn10_stream_encoder_shift se_shift = {
372 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT)
373 };
374
375 static const struct dcn10_stream_encoder_mask se_mask = {
376 SE_COMMON_MASK_SH_LIST_DCN314(_MASK)
377 };
378
379
380 #define aux_regs(id)\
381 [id] = {\
382 DCN2_AUX_REG_LIST(id)\
383 }
384
385 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
386 aux_regs(0),
387 aux_regs(1),
388 aux_regs(2),
389 aux_regs(3),
390 aux_regs(4)
391 };
392
393 #define hpd_regs(id)\
394 [id] = {\
395 HPD_REG_LIST(id)\
396 }
397
398 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
399 hpd_regs(0),
400 hpd_regs(1),
401 hpd_regs(2),
402 hpd_regs(3),
403 hpd_regs(4)
404 };
405
406 #define link_regs(id, phyid)\
407 [id] = {\
408 LE_DCN31_REG_LIST(id), \
409 UNIPHY_DCN2_REG_LIST(phyid), \
410 }
411
412 static const struct dce110_aux_registers_shift aux_shift = {
413 DCN_AUX_MASK_SH_LIST(__SHIFT)
414 };
415
416 static const struct dce110_aux_registers_mask aux_mask = {
417 DCN_AUX_MASK_SH_LIST(_MASK)
418 };
419
420 static const struct dcn10_link_enc_registers link_enc_regs[] = {
421 link_regs(0, A),
422 link_regs(1, B),
423 link_regs(2, C),
424 link_regs(3, D),
425 link_regs(4, E)
426 };
427
428 static const struct dcn10_link_enc_shift le_shift = {
429 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT),
430 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
431 };
432
433 static const struct dcn10_link_enc_mask le_mask = {
434 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK),
435 DPCS_DCN31_MASK_SH_LIST(_MASK)
436 };
437
438 #define hpo_dp_stream_encoder_reg_list(id)\
439 [id] = {\
440 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
441 }
442
443 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
444 hpo_dp_stream_encoder_reg_list(0),
445 hpo_dp_stream_encoder_reg_list(1),
446 hpo_dp_stream_encoder_reg_list(2),
447 hpo_dp_stream_encoder_reg_list(3)
448 };
449
450 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
451 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
452 };
453
454 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
455 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
456 };
457
458
459 #define hpo_dp_link_encoder_reg_list(id)\
460 [id] = {\
461 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
462 DCN3_1_RDPCSTX_REG_LIST(0),\
463 DCN3_1_RDPCSTX_REG_LIST(1),\
464 DCN3_1_RDPCSTX_REG_LIST(2),\
465 }
466
467 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
468 hpo_dp_link_encoder_reg_list(0),
469 hpo_dp_link_encoder_reg_list(1),
470 };
471
472 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
473 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
474 };
475
476 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
477 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
478 };
479
480 #define dpp_regs(id)\
481 [id] = {\
482 DPP_REG_LIST_DCN30(id),\
483 }
484
485 static const struct dcn3_dpp_registers dpp_regs[] = {
486 dpp_regs(0),
487 dpp_regs(1),
488 dpp_regs(2),
489 dpp_regs(3)
490 };
491
492 static const struct dcn3_dpp_shift tf_shift = {
493 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
494 };
495
496 static const struct dcn3_dpp_mask tf_mask = {
497 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
498 };
499
500 #define opp_regs(id)\
501 [id] = {\
502 OPP_REG_LIST_DCN30(id),\
503 }
504
505 static const struct dcn20_opp_registers opp_regs[] = {
506 opp_regs(0),
507 opp_regs(1),
508 opp_regs(2),
509 opp_regs(3)
510 };
511
512 static const struct dcn20_opp_shift opp_shift = {
513 OPP_MASK_SH_LIST_DCN20(__SHIFT)
514 };
515
516 static const struct dcn20_opp_mask opp_mask = {
517 OPP_MASK_SH_LIST_DCN20(_MASK)
518 };
519
520 #define aux_engine_regs(id)\
521 [id] = {\
522 AUX_COMMON_REG_LIST0(id), \
523 .AUXN_IMPCAL = 0, \
524 .AUXP_IMPCAL = 0, \
525 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
526 }
527
528 static const struct dce110_aux_registers aux_engine_regs[] = {
529 aux_engine_regs(0),
530 aux_engine_regs(1),
531 aux_engine_regs(2),
532 aux_engine_regs(3),
533 aux_engine_regs(4)
534 };
535
536 #define dwbc_regs_dcn3(id)\
537 [id] = {\
538 DWBC_COMMON_REG_LIST_DCN30(id),\
539 }
540
541 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
542 dwbc_regs_dcn3(0),
543 };
544
545 static const struct dcn30_dwbc_shift dwbc30_shift = {
546 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
547 };
548
549 static const struct dcn30_dwbc_mask dwbc30_mask = {
550 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
551 };
552
553 #define mcif_wb_regs_dcn3(id)\
554 [id] = {\
555 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
556 }
557
558 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
559 mcif_wb_regs_dcn3(0)
560 };
561
562 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
563 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
564 };
565
566 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
567 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
568 };
569
570 #define dsc_regsDCN314(id)\
571 [id] = {\
572 DSC_REG_LIST_DCN20(id)\
573 }
574
575 static const struct dcn20_dsc_registers dsc_regs[] = {
576 dsc_regsDCN314(0),
577 dsc_regsDCN314(1),
578 dsc_regsDCN314(2),
579 dsc_regsDCN314(3)
580 };
581
582 static const struct dcn20_dsc_shift dsc_shift = {
583 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
584 };
585
586 static const struct dcn20_dsc_mask dsc_mask = {
587 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
588 };
589
590 static const struct dcn30_mpc_registers mpc_regs = {
591 MPC_REG_LIST_DCN3_0(0),
592 MPC_REG_LIST_DCN3_0(1),
593 MPC_REG_LIST_DCN3_0(2),
594 MPC_REG_LIST_DCN3_0(3),
595 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
596 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
597 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
598 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
599 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
600 MPC_RMU_REG_LIST_DCN3AG(0),
601 MPC_RMU_REG_LIST_DCN3AG(1),
602 //MPC_RMU_REG_LIST_DCN3AG(2),
603 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
604 };
605
606 static const struct dcn30_mpc_shift mpc_shift = {
607 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
608 };
609
610 static const struct dcn30_mpc_mask mpc_mask = {
611 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
612 };
613
614 #define optc_regs(id)\
615 [id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)}
616
617 static const struct dcn_optc_registers optc_regs[] = {
618 optc_regs(0),
619 optc_regs(1),
620 optc_regs(2),
621 optc_regs(3)
622 };
623
624 static const struct dcn_optc_shift optc_shift = {
625 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT)
626 };
627
628 static const struct dcn_optc_mask optc_mask = {
629 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK)
630 };
631
632 #define hubp_regs(id)\
633 [id] = {\
634 HUBP_REG_LIST_DCN30(id)\
635 }
636
637 static const struct dcn_hubp2_registers hubp_regs[] = {
638 hubp_regs(0),
639 hubp_regs(1),
640 hubp_regs(2),
641 hubp_regs(3)
642 };
643
644
645 static const struct dcn_hubp2_shift hubp_shift = {
646 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
647 };
648
649 static const struct dcn_hubp2_mask hubp_mask = {
650 HUBP_MASK_SH_LIST_DCN31(_MASK)
651 };
652 static const struct dcn_hubbub_registers hubbub_reg = {
653 HUBBUB_REG_LIST_DCN31(0)
654 };
655
656 static const struct dcn_hubbub_shift hubbub_shift = {
657 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
658 };
659
660 static const struct dcn_hubbub_mask hubbub_mask = {
661 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
662 };
663
664 static const struct dccg_registers dccg_regs = {
665 DCCG_REG_LIST_DCN314()
666 };
667
668 static const struct dccg_shift dccg_shift = {
669 DCCG_MASK_SH_LIST_DCN314(__SHIFT)
670 };
671
672 static const struct dccg_mask dccg_mask = {
673 DCCG_MASK_SH_LIST_DCN314(_MASK)
674 };
675
676
677 #define SRII2(reg_name_pre, reg_name_post, id)\
678 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
679 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
680 reg ## reg_name_pre ## id ## _ ## reg_name_post
681
682
683 #define HWSEQ_DCN31_REG_LIST()\
684 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
685 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
686 SR(DIO_MEM_PWR_CTRL), \
687 SR(ODM_MEM_PWR_CTRL3), \
688 SR(DMU_MEM_PWR_CNTL), \
689 SR(MMHUBBUB_MEM_PWR_CNTL), \
690 SR(DCCG_GATE_DISABLE_CNTL), \
691 SR(DCCG_GATE_DISABLE_CNTL2), \
692 SR(DCFCLK_CNTL),\
693 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
694 SRII(PIXEL_RATE_CNTL, OTG, 0), \
695 SRII(PIXEL_RATE_CNTL, OTG, 1),\
696 SRII(PIXEL_RATE_CNTL, OTG, 2),\
697 SRII(PIXEL_RATE_CNTL, OTG, 3),\
698 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
699 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
700 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
701 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
702 SR(MICROSECOND_TIME_BASE_DIV), \
703 SR(MILLISECOND_TIME_BASE_DIV), \
704 SR(DISPCLK_FREQ_CHANGE_CNTL), \
705 SR(RBBMIF_TIMEOUT_DIS), \
706 SR(RBBMIF_TIMEOUT_DIS_2), \
707 SR(DCHUBBUB_CRC_CTRL), \
708 SR(DPP_TOP0_DPP_CRC_CTRL), \
709 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
710 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
711 SR(MPC_CRC_CTRL), \
712 SR(MPC_CRC_RESULT_GB), \
713 SR(MPC_CRC_RESULT_C), \
714 SR(MPC_CRC_RESULT_AR), \
715 SR(DOMAIN0_PG_CONFIG), \
716 SR(DOMAIN1_PG_CONFIG), \
717 SR(DOMAIN2_PG_CONFIG), \
718 SR(DOMAIN3_PG_CONFIG), \
719 SR(DOMAIN16_PG_CONFIG), \
720 SR(DOMAIN17_PG_CONFIG), \
721 SR(DOMAIN18_PG_CONFIG), \
722 SR(DOMAIN19_PG_CONFIG), \
723 SR(DOMAIN0_PG_STATUS), \
724 SR(DOMAIN1_PG_STATUS), \
725 SR(DOMAIN2_PG_STATUS), \
726 SR(DOMAIN3_PG_STATUS), \
727 SR(DOMAIN16_PG_STATUS), \
728 SR(DOMAIN17_PG_STATUS), \
729 SR(DOMAIN18_PG_STATUS), \
730 SR(DOMAIN19_PG_STATUS), \
731 SR(D1VGA_CONTROL), \
732 SR(D2VGA_CONTROL), \
733 SR(D3VGA_CONTROL), \
734 SR(D4VGA_CONTROL), \
735 SR(D5VGA_CONTROL), \
736 SR(D6VGA_CONTROL), \
737 SR(DC_IP_REQUEST_CNTL), \
738 SR(AZALIA_AUDIO_DTO), \
739 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
740 SR(HPO_TOP_HW_CONTROL)
741
742 static const struct dce_hwseq_registers hwseq_reg = {
743 HWSEQ_DCN31_REG_LIST()
744 };
745
746 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
747 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
748 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
749 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
750 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
751 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
752 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
753 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
754 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
755 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
756 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
757 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
758 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
759 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
760 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
761 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
762 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
763 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
764 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
765 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
766 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
767 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
768 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
769 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
770 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
771 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
772 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
773 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
774 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
775 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
776 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
777 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
778 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
779 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
780 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
781 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
782 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
783
784 static const struct dce_hwseq_shift hwseq_shift = {
785 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
786 };
787
788 static const struct dce_hwseq_mask hwseq_mask = {
789 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
790 };
791 #define vmid_regs(id)\
792 [id] = {\
793 DCN20_VMID_REG_LIST(id)\
794 }
795
796 static const struct dcn_vmid_registers vmid_regs[] = {
797 vmid_regs(0),
798 vmid_regs(1),
799 vmid_regs(2),
800 vmid_regs(3),
801 vmid_regs(4),
802 vmid_regs(5),
803 vmid_regs(6),
804 vmid_regs(7),
805 vmid_regs(8),
806 vmid_regs(9),
807 vmid_regs(10),
808 vmid_regs(11),
809 vmid_regs(12),
810 vmid_regs(13),
811 vmid_regs(14),
812 vmid_regs(15)
813 };
814
815 static const struct dcn20_vmid_shift vmid_shifts = {
816 DCN20_VMID_MASK_SH_LIST(__SHIFT)
817 };
818
819 static const struct dcn20_vmid_mask vmid_masks = {
820 DCN20_VMID_MASK_SH_LIST(_MASK)
821 };
822
823 static const struct resource_caps res_cap_dcn314 = {
824 .num_timing_generator = 4,
825 .num_opp = 4,
826 .num_video_plane = 4,
827 .num_audio = 5,
828 .num_stream_encoder = 5,
829 .num_dig_link_enc = 5,
830 .num_hpo_dp_stream_encoder = 4,
831 .num_hpo_dp_link_encoder = 2,
832 .num_pll = 5,
833 .num_dwb = 1,
834 .num_ddc = 5,
835 .num_vmid = 16,
836 .num_mpc_3dlut = 2,
837 .num_dsc = 4,
838 };
839
840 static const struct dc_plane_cap plane_cap = {
841 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
842 .per_pixel_alpha = true,
843
844 .pixel_format_support = {
845 .argb8888 = true,
846 .nv12 = true,
847 .fp16 = true,
848 .p010 = true,
849 .ayuv = false,
850 },
851
852 .max_upscale_factor = {
853 .argb8888 = 16000,
854 .nv12 = 16000,
855 .fp16 = 16000
856 },
857
858 // 6:1 downscaling ratio: 1000/6 = 166.666
859 // 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 playback: 1000/4 = 250
860 .max_downscale_factor = {
861 .argb8888 = 250,
862 .nv12 = 167,
863 .fp16 = 167
864 },
865 64,
866 64
867 };
868
869 static const struct dc_debug_options debug_defaults_drv = {
870 .disable_z10 = false,
871 .enable_z9_disable_interface = true,
872 .minimum_z8_residency_time = 2100,
873 .psr_skip_crtc_disable = true,
874 .replay_skip_crtc_disabled = true,
875 .disable_dmcu = true,
876 .force_abm_enable = false,
877 .timing_trace = false,
878 .clock_trace = true,
879 .disable_dpp_power_gate = false,
880 .disable_hubp_power_gate = false,
881 .disable_pplib_clock_request = false,
882 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
883 .force_single_disp_pipe_split = false,
884 .disable_dcc = DCC_ENABLE,
885 .vsr_support = true,
886 .performance_trace = false,
887 .max_downscale_src_width = 4096,/*upto true 4k*/
888 .disable_pplib_wm_range = false,
889 .scl_reset_length10 = true,
890 .sanity_checks = true,
891 .underflow_assert_delay_us = 0xFFFFFFFF,
892 .dwb_fi_phase = -1, // -1 = disable,
893 .dmub_command_table = true,
894 .pstate_enabled = true,
895 .use_max_lb = true,
896 .enable_mem_low_power = {
897 .bits = {
898 .vga = true,
899 .i2c = true,
900 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
901 .dscl = true,
902 .cm = true,
903 .mpc = true,
904 .optc = true,
905 .vpg = true,
906 .afmt = true,
907 }
908 },
909
910 .root_clock_optimization = {
911 .bits = {
912 .dpp = true,
913 .dsc = true,
914 .hdmistream = true,
915 .hdmichar = true,
916 .dpstream = true,
917 .symclk32_se = true,
918 .symclk32_le = true,
919 .symclk_fe = true,
920 .physymclk = true,
921 .dpiasymclk = true,
922 }
923 },
924
925 .seamless_boot_odm_combine = true
926 };
927
928 static const struct dc_debug_options debug_defaults_diags = {
929 .disable_dmcu = true,
930 .force_abm_enable = false,
931 .timing_trace = true,
932 .clock_trace = true,
933 .disable_dpp_power_gate = true,
934 .disable_hubp_power_gate = true,
935 .disable_clock_gate = true,
936 .disable_pplib_clock_request = true,
937 .disable_pplib_wm_range = true,
938 .disable_stutter = false,
939 .scl_reset_length10 = true,
940 .dwb_fi_phase = -1, // -1 = disable
941 .dmub_command_table = true,
942 .enable_tri_buf = true,
943 .use_max_lb = true
944 };
945
946 static const struct dc_panel_config panel_config_defaults = {
947 .psr = {
948 .disable_psr = false,
949 .disallow_psrsu = false,
950 .disallow_replay = false,
951 },
952 .ilr = {
953 .optimize_edp_link_rate = true,
954 },
955 };
956
dcn31_dpp_destroy(struct dpp ** dpp)957 static void dcn31_dpp_destroy(struct dpp **dpp)
958 {
959 kfree(TO_DCN20_DPP(*dpp));
960 *dpp = NULL;
961 }
962
dcn31_dpp_create(struct dc_context * ctx,uint32_t inst)963 static struct dpp *dcn31_dpp_create(
964 struct dc_context *ctx,
965 uint32_t inst)
966 {
967 struct dcn3_dpp *dpp =
968 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
969
970 if (!dpp)
971 return NULL;
972
973 if (dpp3_construct(dpp, ctx, inst,
974 &dpp_regs[inst], &tf_shift, &tf_mask))
975 return &dpp->base;
976
977 BREAK_TO_DEBUGGER();
978 kfree(dpp);
979 return NULL;
980 }
981
dcn31_opp_create(struct dc_context * ctx,uint32_t inst)982 static struct output_pixel_processor *dcn31_opp_create(
983 struct dc_context *ctx, uint32_t inst)
984 {
985 struct dcn20_opp *opp =
986 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
987
988 if (!opp) {
989 BREAK_TO_DEBUGGER();
990 return NULL;
991 }
992
993 dcn20_opp_construct(opp, ctx, inst,
994 &opp_regs[inst], &opp_shift, &opp_mask);
995 return &opp->base;
996 }
997
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)998 static struct dce_aux *dcn31_aux_engine_create(
999 struct dc_context *ctx,
1000 uint32_t inst)
1001 {
1002 struct aux_engine_dce110 *aux_engine =
1003 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1004
1005 if (!aux_engine)
1006 return NULL;
1007
1008 dce110_aux_engine_construct(aux_engine, ctx, inst,
1009 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1010 &aux_engine_regs[inst],
1011 &aux_mask,
1012 &aux_shift,
1013 ctx->dc->caps.extended_aux_timeout_support);
1014
1015 return &aux_engine->base;
1016 }
1017 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1018
1019 static const struct dce_i2c_registers i2c_hw_regs[] = {
1020 i2c_inst_regs(1),
1021 i2c_inst_regs(2),
1022 i2c_inst_regs(3),
1023 i2c_inst_regs(4),
1024 i2c_inst_regs(5),
1025 };
1026
1027 static const struct dce_i2c_shift i2c_shifts = {
1028 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1029 };
1030
1031 static const struct dce_i2c_mask i2c_masks = {
1032 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1033 };
1034
1035 /* ========================================================== */
1036
1037 /*
1038 * DPIA index | Preferred Encoder | Host Router
1039 * 0 | C | 0
1040 * 1 | First Available | 0
1041 * 2 | D | 1
1042 * 3 | First Available | 1
1043 */
1044 /* ========================================================== */
1045 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
1046 ENGINE_ID_DIGC,
1047 ENGINE_ID_DIGC,
1048 ENGINE_ID_DIGD,
1049 ENGINE_ID_DIGD
1050 };
1051
dcn314_get_preferred_eng_id_dpia(unsigned int dpia_index)1052 static enum engine_id dcn314_get_preferred_eng_id_dpia(unsigned int dpia_index)
1053 {
1054 return dpia_to_preferred_enc_id_table[dpia_index];
1055 }
1056
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)1057 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1058 struct dc_context *ctx,
1059 uint32_t inst)
1060 {
1061 struct dce_i2c_hw *dce_i2c_hw =
1062 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1063
1064 if (!dce_i2c_hw)
1065 return NULL;
1066
1067 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1068 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1069
1070 return dce_i2c_hw;
1071 }
dcn31_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1072 static struct mpc *dcn31_mpc_create(
1073 struct dc_context *ctx,
1074 int num_mpcc,
1075 int num_rmu)
1076 {
1077 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1078 GFP_KERNEL);
1079
1080 if (!mpc30)
1081 return NULL;
1082
1083 dcn30_mpc_construct(mpc30, ctx,
1084 &mpc_regs,
1085 &mpc_shift,
1086 &mpc_mask,
1087 num_mpcc,
1088 num_rmu);
1089
1090 return &mpc30->base;
1091 }
1092
dcn31_hubbub_create(struct dc_context * ctx)1093 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1094 {
1095 int i;
1096
1097 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1098 GFP_KERNEL);
1099
1100 if (!hubbub3)
1101 return NULL;
1102
1103 hubbub31_construct(hubbub3, ctx,
1104 &hubbub_reg,
1105 &hubbub_shift,
1106 &hubbub_mask,
1107 dcn3_14_ip.det_buffer_size_kbytes,
1108 dcn3_14_ip.pixel_chunk_size_kbytes,
1109 dcn3_14_ip.config_return_buffer_size_in_kbytes);
1110
1111
1112 for (i = 0; i < res_cap_dcn314.num_vmid; i++) {
1113 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1114
1115 vmid->ctx = ctx;
1116
1117 vmid->regs = &vmid_regs[i];
1118 vmid->shifts = &vmid_shifts;
1119 vmid->masks = &vmid_masks;
1120 }
1121
1122 return &hubbub3->base;
1123 }
1124
dcn31_timing_generator_create(struct dc_context * ctx,uint32_t instance)1125 static struct timing_generator *dcn31_timing_generator_create(
1126 struct dc_context *ctx,
1127 uint32_t instance)
1128 {
1129 struct optc *tgn10 =
1130 kzalloc(sizeof(struct optc), GFP_KERNEL);
1131
1132 if (!tgn10)
1133 return NULL;
1134
1135 tgn10->base.inst = instance;
1136 tgn10->base.ctx = ctx;
1137
1138 tgn10->tg_regs = &optc_regs[instance];
1139 tgn10->tg_shift = &optc_shift;
1140 tgn10->tg_mask = &optc_mask;
1141
1142 dcn314_timing_generator_init(tgn10);
1143
1144 return &tgn10->base;
1145 }
1146
1147 static const struct encoder_feature_support link_enc_feature = {
1148 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1149 .max_hdmi_pixel_clock = 600000,
1150 .hdmi_ycbcr420_supported = true,
1151 .dp_ycbcr420_supported = true,
1152 .fec_supported = true,
1153 .flags.bits.IS_HBR2_CAPABLE = true,
1154 .flags.bits.IS_HBR3_CAPABLE = true,
1155 .flags.bits.IS_TPS3_CAPABLE = true,
1156 .flags.bits.IS_TPS4_CAPABLE = true
1157 };
1158
dcn31_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1159 static struct link_encoder *dcn31_link_encoder_create(
1160 struct dc_context *ctx,
1161 const struct encoder_init_data *enc_init_data)
1162 {
1163 struct dcn20_link_encoder *enc20 =
1164 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1165
1166 if (!enc20)
1167 return NULL;
1168
1169 dcn31_link_encoder_construct(enc20,
1170 enc_init_data,
1171 &link_enc_feature,
1172 &link_enc_regs[enc_init_data->transmitter],
1173 &link_enc_aux_regs[enc_init_data->channel - 1],
1174 &link_enc_hpd_regs[enc_init_data->hpd_source],
1175 &le_shift,
1176 &le_mask);
1177
1178 return &enc20->enc10.base;
1179 }
1180
1181 /* Create a minimal link encoder object not associated with a particular
1182 * physical connector.
1183 * resource_funcs.link_enc_create_minimal
1184 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1185 static struct link_encoder *dcn31_link_enc_create_minimal(
1186 struct dc_context *ctx, enum engine_id eng_id)
1187 {
1188 struct dcn20_link_encoder *enc20;
1189
1190 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1191 return NULL;
1192
1193 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1194 if (!enc20)
1195 return NULL;
1196
1197 dcn31_link_encoder_construct_minimal(
1198 enc20,
1199 ctx,
1200 &link_enc_feature,
1201 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1202 eng_id);
1203
1204 return &enc20->enc10.base;
1205 }
1206
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1207 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1208 {
1209 struct dcn31_panel_cntl *panel_cntl =
1210 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1211
1212 if (!panel_cntl)
1213 return NULL;
1214
1215 dcn31_panel_cntl_construct(panel_cntl, init_data);
1216
1217 return &panel_cntl->base;
1218 }
1219
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1220 static void read_dce_straps(
1221 struct dc_context *ctx,
1222 struct resource_straps *straps)
1223 {
1224 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1225 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1226
1227 }
1228
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1229 static struct audio *dcn31_create_audio(
1230 struct dc_context *ctx, unsigned int inst)
1231 {
1232 return dce_audio_create(ctx, inst,
1233 &audio_regs[inst], &audio_shift, &audio_mask);
1234 }
1235
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1236 static struct vpg *dcn31_vpg_create(
1237 struct dc_context *ctx,
1238 uint32_t inst)
1239 {
1240 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1241
1242 if (!vpg31)
1243 return NULL;
1244
1245 vpg31_construct(vpg31, ctx, inst,
1246 &vpg_regs[inst],
1247 &vpg_shift,
1248 &vpg_mask);
1249
1250 return &vpg31->base;
1251 }
1252
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1253 static struct afmt *dcn31_afmt_create(
1254 struct dc_context *ctx,
1255 uint32_t inst)
1256 {
1257 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1258
1259 if (!afmt31)
1260 return NULL;
1261
1262 afmt31_construct(afmt31, ctx, inst,
1263 &afmt_regs[inst],
1264 &afmt_shift,
1265 &afmt_mask);
1266
1267 // Light sleep by default, no need to power down here
1268
1269 return &afmt31->base;
1270 }
1271
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1272 static struct apg *dcn31_apg_create(
1273 struct dc_context *ctx,
1274 uint32_t inst)
1275 {
1276 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1277
1278 if (!apg31)
1279 return NULL;
1280
1281 apg31_construct(apg31, ctx, inst,
1282 &apg_regs[inst],
1283 &apg_shift,
1284 &apg_mask);
1285
1286 return &apg31->base;
1287 }
1288
dcn314_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1289 static struct stream_encoder *dcn314_stream_encoder_create(
1290 enum engine_id eng_id,
1291 struct dc_context *ctx)
1292 {
1293 struct dcn10_stream_encoder *enc1;
1294 struct vpg *vpg;
1295 struct afmt *afmt;
1296 int vpg_inst;
1297 int afmt_inst;
1298
1299 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1300 if (eng_id < ENGINE_ID_DIGF) {
1301 vpg_inst = eng_id;
1302 afmt_inst = eng_id;
1303 } else
1304 return NULL;
1305
1306 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1307 vpg = dcn31_vpg_create(ctx, vpg_inst);
1308 afmt = dcn31_afmt_create(ctx, afmt_inst);
1309
1310 if (!enc1 || !vpg || !afmt) {
1311 kfree(enc1);
1312 kfree(vpg);
1313 kfree(afmt);
1314 return NULL;
1315 }
1316
1317 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1318 eng_id, vpg, afmt,
1319 &stream_enc_regs[eng_id],
1320 &se_shift, &se_mask);
1321
1322 return &enc1->base;
1323 }
1324
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1325 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1326 enum engine_id eng_id,
1327 struct dc_context *ctx)
1328 {
1329 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1330 struct vpg *vpg;
1331 struct apg *apg;
1332 uint32_t hpo_dp_inst;
1333 uint32_t vpg_inst;
1334 uint32_t apg_inst;
1335
1336 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1337 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1338
1339 /* Mapping of VPG register blocks to HPO DP block instance:
1340 * VPG[6] -> HPO_DP[0]
1341 * VPG[7] -> HPO_DP[1]
1342 * VPG[8] -> HPO_DP[2]
1343 * VPG[9] -> HPO_DP[3]
1344 */
1345 //Uses offset index 5-8, but actually maps to vpg_inst 6-9
1346 vpg_inst = hpo_dp_inst + 5;
1347
1348 /* Mapping of APG register blocks to HPO DP block instance:
1349 * APG[0] -> HPO_DP[0]
1350 * APG[1] -> HPO_DP[1]
1351 * APG[2] -> HPO_DP[2]
1352 * APG[3] -> HPO_DP[3]
1353 */
1354 apg_inst = hpo_dp_inst;
1355
1356 /* allocate HPO stream encoder and create VPG sub-block */
1357 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1358 vpg = dcn31_vpg_create(ctx, vpg_inst);
1359 apg = dcn31_apg_create(ctx, apg_inst);
1360
1361 if (!hpo_dp_enc31 || !vpg || !apg) {
1362 kfree(hpo_dp_enc31);
1363 kfree(vpg);
1364 kfree(apg);
1365 return NULL;
1366 }
1367
1368 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1369 hpo_dp_inst, eng_id, vpg, apg,
1370 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1371 &hpo_dp_se_shift, &hpo_dp_se_mask);
1372
1373 return &hpo_dp_enc31->base;
1374 }
1375
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1376 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1377 uint8_t inst,
1378 struct dc_context *ctx)
1379 {
1380 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1381
1382 /* allocate HPO link encoder */
1383 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1384
1385 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1386 &hpo_dp_link_enc_regs[inst],
1387 &hpo_dp_le_shift, &hpo_dp_le_mask);
1388
1389 return &hpo_dp_enc31->base;
1390 }
1391
dcn314_hwseq_create(struct dc_context * ctx)1392 static struct dce_hwseq *dcn314_hwseq_create(
1393 struct dc_context *ctx)
1394 {
1395 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1396
1397 if (hws) {
1398 hws->ctx = ctx;
1399 hws->regs = &hwseq_reg;
1400 hws->shifts = &hwseq_shift;
1401 hws->masks = &hwseq_mask;
1402 }
1403 return hws;
1404 }
1405 static const struct resource_create_funcs res_create_funcs = {
1406 .read_dce_straps = read_dce_straps,
1407 .create_audio = dcn31_create_audio,
1408 .create_stream_encoder = dcn314_stream_encoder_create,
1409 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1410 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1411 .create_hwseq = dcn314_hwseq_create,
1412 };
1413
dcn314_resource_destruct(struct dcn314_resource_pool * pool)1414 static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)
1415 {
1416 unsigned int i;
1417
1418 for (i = 0; i < pool->base.stream_enc_count; i++) {
1419 if (pool->base.stream_enc[i] != NULL) {
1420 if (pool->base.stream_enc[i]->vpg != NULL) {
1421 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1422 pool->base.stream_enc[i]->vpg = NULL;
1423 }
1424 if (pool->base.stream_enc[i]->afmt != NULL) {
1425 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1426 pool->base.stream_enc[i]->afmt = NULL;
1427 }
1428 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1429 pool->base.stream_enc[i] = NULL;
1430 }
1431 }
1432
1433 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1434 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1435 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1436 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1437 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1438 }
1439 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1440 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1441 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1442 }
1443 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1444 pool->base.hpo_dp_stream_enc[i] = NULL;
1445 }
1446 }
1447
1448 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1449 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1450 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1451 pool->base.hpo_dp_link_enc[i] = NULL;
1452 }
1453 }
1454
1455 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1456 if (pool->base.dscs[i] != NULL)
1457 dcn20_dsc_destroy(&pool->base.dscs[i]);
1458 }
1459
1460 if (pool->base.mpc != NULL) {
1461 kfree(TO_DCN20_MPC(pool->base.mpc));
1462 pool->base.mpc = NULL;
1463 }
1464 if (pool->base.hubbub != NULL) {
1465 kfree(pool->base.hubbub);
1466 pool->base.hubbub = NULL;
1467 }
1468 for (i = 0; i < pool->base.pipe_count; i++) {
1469 if (pool->base.dpps[i] != NULL)
1470 dcn31_dpp_destroy(&pool->base.dpps[i]);
1471
1472 if (pool->base.ipps[i] != NULL)
1473 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1474
1475 if (pool->base.hubps[i] != NULL) {
1476 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1477 pool->base.hubps[i] = NULL;
1478 }
1479
1480 if (pool->base.irqs != NULL)
1481 dal_irq_service_destroy(&pool->base.irqs);
1482 }
1483
1484 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1485 if (pool->base.engines[i] != NULL)
1486 dce110_engine_destroy(&pool->base.engines[i]);
1487 if (pool->base.hw_i2cs[i] != NULL) {
1488 kfree(pool->base.hw_i2cs[i]);
1489 pool->base.hw_i2cs[i] = NULL;
1490 }
1491 if (pool->base.sw_i2cs[i] != NULL) {
1492 kfree(pool->base.sw_i2cs[i]);
1493 pool->base.sw_i2cs[i] = NULL;
1494 }
1495 }
1496
1497 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1498 if (pool->base.opps[i] != NULL)
1499 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1500 }
1501
1502 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1503 if (pool->base.timing_generators[i] != NULL) {
1504 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1505 pool->base.timing_generators[i] = NULL;
1506 }
1507 }
1508
1509 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1510 if (pool->base.dwbc[i] != NULL) {
1511 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1512 pool->base.dwbc[i] = NULL;
1513 }
1514 if (pool->base.mcif_wb[i] != NULL) {
1515 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1516 pool->base.mcif_wb[i] = NULL;
1517 }
1518 }
1519
1520 for (i = 0; i < pool->base.audio_count; i++) {
1521 if (pool->base.audios[i])
1522 dce_aud_destroy(&pool->base.audios[i]);
1523 }
1524
1525 for (i = 0; i < pool->base.clk_src_count; i++) {
1526 if (pool->base.clock_sources[i] != NULL) {
1527 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1528 pool->base.clock_sources[i] = NULL;
1529 }
1530 }
1531
1532 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1533 if (pool->base.mpc_lut[i] != NULL) {
1534 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1535 pool->base.mpc_lut[i] = NULL;
1536 }
1537 if (pool->base.mpc_shaper[i] != NULL) {
1538 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1539 pool->base.mpc_shaper[i] = NULL;
1540 }
1541 }
1542
1543 if (pool->base.dp_clock_source != NULL) {
1544 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1545 pool->base.dp_clock_source = NULL;
1546 }
1547
1548 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1549 if (pool->base.multiple_abms[i] != NULL)
1550 dce_abm_destroy(&pool->base.multiple_abms[i]);
1551 }
1552
1553 if (pool->base.psr != NULL)
1554 dmub_psr_destroy(&pool->base.psr);
1555
1556 if (pool->base.replay != NULL)
1557 dmub_replay_destroy(&pool->base.replay);
1558
1559 if (pool->base.dccg != NULL)
1560 dcn_dccg_destroy(&pool->base.dccg);
1561 }
1562
dcn31_hubp_create(struct dc_context * ctx,uint32_t inst)1563 static struct hubp *dcn31_hubp_create(
1564 struct dc_context *ctx,
1565 uint32_t inst)
1566 {
1567 struct dcn20_hubp *hubp2 =
1568 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1569
1570 if (!hubp2)
1571 return NULL;
1572
1573 if (hubp31_construct(hubp2, ctx, inst,
1574 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1575 return &hubp2->base;
1576
1577 BREAK_TO_DEBUGGER();
1578 kfree(hubp2);
1579 return NULL;
1580 }
1581
dcn31_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1582 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1583 {
1584 int i;
1585 uint32_t pipe_count = pool->res_cap->num_dwb;
1586
1587 for (i = 0; i < pipe_count; i++) {
1588 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1589 GFP_KERNEL);
1590
1591 if (!dwbc30) {
1592 dm_error("DC: failed to create dwbc30!\n");
1593 return false;
1594 }
1595
1596 dcn30_dwbc_construct(dwbc30, ctx,
1597 &dwbc30_regs[i],
1598 &dwbc30_shift,
1599 &dwbc30_mask,
1600 i);
1601
1602 pool->dwbc[i] = &dwbc30->base;
1603 }
1604 return true;
1605 }
1606
dcn31_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1607 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1608 {
1609 int i;
1610 uint32_t pipe_count = pool->res_cap->num_dwb;
1611
1612 for (i = 0; i < pipe_count; i++) {
1613 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1614 GFP_KERNEL);
1615
1616 if (!mcif_wb30) {
1617 dm_error("DC: failed to create mcif_wb30!\n");
1618 return false;
1619 }
1620
1621 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1622 &mcif_wb30_regs[i],
1623 &mcif_wb30_shift,
1624 &mcif_wb30_mask,
1625 i);
1626
1627 pool->mcif_wb[i] = &mcif_wb30->base;
1628 }
1629 return true;
1630 }
1631
dcn314_dsc_create(struct dc_context * ctx,uint32_t inst)1632 static struct display_stream_compressor *dcn314_dsc_create(
1633 struct dc_context *ctx, uint32_t inst)
1634 {
1635 struct dcn20_dsc *dsc =
1636 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1637
1638 if (!dsc) {
1639 BREAK_TO_DEBUGGER();
1640 return NULL;
1641 }
1642
1643 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1644 return &dsc->base;
1645 }
1646
dcn314_destroy_resource_pool(struct resource_pool ** pool)1647 static void dcn314_destroy_resource_pool(struct resource_pool **pool)
1648 {
1649 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool);
1650
1651 dcn314_resource_destruct(dcn314_pool);
1652 kfree(dcn314_pool);
1653 *pool = NULL;
1654 }
1655
dcn31_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1656 static struct clock_source *dcn31_clock_source_create(
1657 struct dc_context *ctx,
1658 struct dc_bios *bios,
1659 enum clock_source_id id,
1660 const struct dce110_clk_src_regs *regs,
1661 bool dp_clk_src)
1662 {
1663 struct dce110_clk_src *clk_src =
1664 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1665
1666 if (!clk_src)
1667 return NULL;
1668
1669 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1670 regs, &cs_shift, &cs_mask)) {
1671 clk_src->base.dp_clk_src = dp_clk_src;
1672 return &clk_src->base;
1673 }
1674
1675 BREAK_TO_DEBUGGER();
1676 kfree(clk_src);
1677 return NULL;
1678 }
1679
dcn314_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1680 static int dcn314_populate_dml_pipes_from_context(
1681 struct dc *dc, struct dc_state *context,
1682 display_e2e_pipe_params_st *pipes,
1683 bool fast_validate)
1684 {
1685 int pipe_cnt;
1686
1687 DC_FP_START();
1688 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate);
1689 DC_FP_END();
1690
1691 return pipe_cnt;
1692 }
1693
1694 static struct dc_cap_funcs cap_funcs = {
1695 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1696 };
1697
dcn314_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1698 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1699 {
1700 DC_FP_START();
1701 dcn314_update_bw_bounding_box_fpu(dc, bw_params);
1702 DC_FP_END();
1703 }
1704
dcn314_get_panel_config_defaults(struct dc_panel_config * panel_config)1705 static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_config)
1706 {
1707 *panel_config = panel_config_defaults;
1708 }
1709
filter_modes_for_single_channel_workaround(struct dc * dc,struct dc_state * context)1710 static bool filter_modes_for_single_channel_workaround(struct dc *dc,
1711 struct dc_state *context)
1712 {
1713 // Filter 2K@240Hz+8K@24fps above combination timing if memory only has single dimm LPDDR
1714 if (dc->clk_mgr->bw_params->vram_type == 34 &&
1715 dc->clk_mgr->bw_params->num_channels < 2 &&
1716 context->stream_count > 1) {
1717 int total_phy_pix_clk = 0;
1718
1719 for (int i = 0; i < context->stream_count; i++)
1720 if (context->res_ctx.pipe_ctx[i].stream)
1721 total_phy_pix_clk += context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;
1722
1723 if (total_phy_pix_clk >= (1148928+826260)) //2K@240Hz+8K@24fps
1724 return true;
1725 }
1726 return false;
1727 }
1728
dcn314_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1729 bool dcn314_validate_bandwidth(struct dc *dc,
1730 struct dc_state *context,
1731 bool fast_validate)
1732 {
1733 bool out = false;
1734
1735 BW_VAL_TRACE_SETUP();
1736
1737 int vlevel = 0;
1738 int pipe_cnt = 0;
1739 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1740 DC_LOGGER_INIT(dc->ctx->logger);
1741
1742 BW_VAL_TRACE_COUNT();
1743
1744 if (filter_modes_for_single_channel_workaround(dc, context))
1745 goto validate_fail;
1746
1747 DC_FP_START();
1748 // do not support self refresh only
1749 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false);
1750 DC_FP_END();
1751
1752 // Disable fast_validate to set min dcfclk in calculate_wm_and_dlg
1753 if (pipe_cnt == 0)
1754 fast_validate = false;
1755
1756 if (!out)
1757 goto validate_fail;
1758
1759 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1760
1761 if (fast_validate) {
1762 BW_VAL_TRACE_SKIP(fast);
1763 goto validate_out;
1764 }
1765 if (dc->res_pool->funcs->calculate_wm_and_dlg)
1766 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1767
1768 BW_VAL_TRACE_END_WATERMARKS();
1769
1770 goto validate_out;
1771
1772 validate_fail:
1773 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1774 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1775
1776 BW_VAL_TRACE_SKIP(fail);
1777 out = false;
1778
1779 validate_out:
1780 kfree(pipes);
1781
1782 BW_VAL_TRACE_FINISH();
1783
1784 return out;
1785 }
1786
1787 static struct resource_funcs dcn314_res_pool_funcs = {
1788 .destroy = dcn314_destroy_resource_pool,
1789 .link_enc_create = dcn31_link_encoder_create,
1790 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1791 .link_encs_assign = link_enc_cfg_link_encs_assign,
1792 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1793 .panel_cntl_create = dcn31_panel_cntl_create,
1794 .validate_bandwidth = dcn314_validate_bandwidth,
1795 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1796 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1797 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context,
1798 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1799 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1800 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1801 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1802 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1803 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1804 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1805 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1806 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1807 .update_bw_bounding_box = dcn314_update_bw_bounding_box,
1808 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1809 .get_panel_config_defaults = dcn314_get_panel_config_defaults,
1810 .get_preferred_eng_id_dpia = dcn314_get_preferred_eng_id_dpia,
1811 };
1812
dcn30_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1813 static struct clock_source *dcn30_clock_source_create(
1814 struct dc_context *ctx,
1815 struct dc_bios *bios,
1816 enum clock_source_id id,
1817 const struct dce110_clk_src_regs *regs,
1818 bool dp_clk_src)
1819 {
1820 struct dce110_clk_src *clk_src =
1821 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1822
1823 if (!clk_src)
1824 return NULL;
1825
1826 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1827 regs, &cs_shift, &cs_mask)) {
1828 clk_src->base.dp_clk_src = dp_clk_src;
1829 return &clk_src->base;
1830 }
1831
1832 BREAK_TO_DEBUGGER();
1833 kfree(clk_src);
1834 return NULL;
1835 }
1836
dcn314_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn314_resource_pool * pool)1837 static bool dcn314_resource_construct(
1838 uint8_t num_virtual_links,
1839 struct dc *dc,
1840 struct dcn314_resource_pool *pool)
1841 {
1842 int i;
1843 struct dc_context *ctx = dc->ctx;
1844 struct irq_service_init_data init_data;
1845
1846 ctx->dc_bios->regs = &bios_regs;
1847
1848 pool->base.res_cap = &res_cap_dcn314;
1849 pool->base.funcs = &dcn314_res_pool_funcs;
1850
1851 /*************************************************
1852 * Resource + asic cap harcoding *
1853 *************************************************/
1854 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1855 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1856 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1857 dc->caps.max_downscale_ratio = 400;
1858 dc->caps.i2c_speed_in_khz = 100;
1859 dc->caps.i2c_speed_in_khz_hdcp = 100;
1860 dc->caps.max_cursor_size = 256;
1861 dc->caps.min_horizontal_blanking_period = 80;
1862 dc->caps.dmdata_alloc_size = 2048;
1863 dc->caps.max_slave_planes = 2;
1864 dc->caps.max_slave_yuv_planes = 2;
1865 dc->caps.max_slave_rgb_planes = 2;
1866 dc->caps.post_blend_color_processing = true;
1867 dc->caps.force_dp_tps4_for_cp2520 = true;
1868 if (dc->config.forceHBR2CP2520)
1869 dc->caps.force_dp_tps4_for_cp2520 = false;
1870 dc->caps.dp_hpo = true;
1871 dc->caps.dp_hdmi21_pcon_support = true;
1872 dc->caps.edp_dsc_support = true;
1873 dc->caps.extended_aux_timeout_support = true;
1874 dc->caps.dmcub_support = true;
1875 dc->caps.is_apu = true;
1876 dc->caps.seamless_odm = true;
1877
1878 dc->caps.zstate_support = true;
1879
1880 /* Color pipeline capabilities */
1881 dc->caps.color.dpp.dcn_arch = 1;
1882 dc->caps.color.dpp.input_lut_shared = 0;
1883 dc->caps.color.dpp.icsc = 1;
1884 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1885 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1886 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1887 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1888 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1889 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1890 dc->caps.color.dpp.post_csc = 1;
1891 dc->caps.color.dpp.gamma_corr = 1;
1892 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1893
1894 dc->caps.color.dpp.hw_3d_lut = 1;
1895 dc->caps.color.dpp.ogam_ram = 1;
1896 // no OGAM ROM on DCN301
1897 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1898 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1899 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1900 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1901 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1902 dc->caps.color.dpp.ocsc = 0;
1903
1904 dc->caps.color.mpc.gamut_remap = 1;
1905 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1906 dc->caps.color.mpc.ogam_ram = 1;
1907 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1908 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1909 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1910 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1911 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1912 dc->caps.color.mpc.ocsc = 1;
1913
1914 /* Use pipe context based otg sync logic */
1915 dc->config.use_pipe_ctx_sync_logic = true;
1916
1917 /* read VBIOS LTTPR caps */
1918 {
1919 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1920 enum bp_result bp_query_result;
1921 uint8_t is_vbios_lttpr_enable = 0;
1922
1923 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1924 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1925 }
1926
1927 /* interop bit is implicit */
1928 {
1929 dc->caps.vbios_lttpr_aware = true;
1930 }
1931 }
1932
1933 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1934 dc->debug = debug_defaults_drv;
1935 else
1936 dc->debug = debug_defaults_diags;
1937
1938 /* Disable pipe power gating */
1939 dc->debug.disable_dpp_power_gate = true;
1940 dc->debug.disable_hubp_power_gate = true;
1941
1942 /* Disable root clock optimization */
1943 dc->debug.root_clock_optimization.u32All = 0;
1944
1945 // Init the vm_helper
1946 if (dc->vm_helper)
1947 vm_helper_init(dc->vm_helper, 16);
1948
1949 /*************************************************
1950 * Create resources *
1951 *************************************************/
1952
1953 /* Clock Sources for Pixel Clock*/
1954 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1955 dcn30_clock_source_create(ctx, ctx->dc_bios,
1956 CLOCK_SOURCE_COMBO_PHY_PLL0,
1957 &clk_src_regs[0], false);
1958 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1959 dcn30_clock_source_create(ctx, ctx->dc_bios,
1960 CLOCK_SOURCE_COMBO_PHY_PLL1,
1961 &clk_src_regs[1], false);
1962 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1963 dcn30_clock_source_create(ctx, ctx->dc_bios,
1964 CLOCK_SOURCE_COMBO_PHY_PLL2,
1965 &clk_src_regs[2], false);
1966 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1967 dcn30_clock_source_create(ctx, ctx->dc_bios,
1968 CLOCK_SOURCE_COMBO_PHY_PLL3,
1969 &clk_src_regs[3], false);
1970 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1971 dcn30_clock_source_create(ctx, ctx->dc_bios,
1972 CLOCK_SOURCE_COMBO_PHY_PLL4,
1973 &clk_src_regs[4], false);
1974
1975 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1976
1977 /* todo: not reuse phy_pll registers */
1978 pool->base.dp_clock_source =
1979 dcn31_clock_source_create(ctx, ctx->dc_bios,
1980 CLOCK_SOURCE_ID_DP_DTO,
1981 &clk_src_regs[0], true);
1982
1983 for (i = 0; i < pool->base.clk_src_count; i++) {
1984 if (pool->base.clock_sources[i] == NULL) {
1985 dm_error("DC: failed to create clock sources!\n");
1986 BREAK_TO_DEBUGGER();
1987 goto create_fail;
1988 }
1989 }
1990
1991 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1992 if (pool->base.dccg == NULL) {
1993 dm_error("DC: failed to create dccg!\n");
1994 BREAK_TO_DEBUGGER();
1995 goto create_fail;
1996 }
1997
1998 init_data.ctx = dc->ctx;
1999 pool->base.irqs = dal_irq_service_dcn314_create(&init_data);
2000 if (!pool->base.irqs)
2001 goto create_fail;
2002
2003 /* HUBBUB */
2004 pool->base.hubbub = dcn31_hubbub_create(ctx);
2005 if (pool->base.hubbub == NULL) {
2006 BREAK_TO_DEBUGGER();
2007 dm_error("DC: failed to create hubbub!\n");
2008 goto create_fail;
2009 }
2010
2011 /* HUBPs, DPPs, OPPs and TGs */
2012 for (i = 0; i < pool->base.pipe_count; i++) {
2013 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2014 if (pool->base.hubps[i] == NULL) {
2015 BREAK_TO_DEBUGGER();
2016 dm_error(
2017 "DC: failed to create hubps!\n");
2018 goto create_fail;
2019 }
2020
2021 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2022 if (pool->base.dpps[i] == NULL) {
2023 BREAK_TO_DEBUGGER();
2024 dm_error(
2025 "DC: failed to create dpps!\n");
2026 goto create_fail;
2027 }
2028 }
2029
2030 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2031 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2032 if (pool->base.opps[i] == NULL) {
2033 BREAK_TO_DEBUGGER();
2034 dm_error(
2035 "DC: failed to create output pixel processor!\n");
2036 goto create_fail;
2037 }
2038 }
2039
2040 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2041 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2042 ctx, i);
2043 if (pool->base.timing_generators[i] == NULL) {
2044 BREAK_TO_DEBUGGER();
2045 dm_error("DC: failed to create tg!\n");
2046 goto create_fail;
2047 }
2048 }
2049 pool->base.timing_generator_count = i;
2050
2051 /* PSR */
2052 pool->base.psr = dmub_psr_create(ctx);
2053 if (pool->base.psr == NULL) {
2054 dm_error("DC: failed to create psr obj!\n");
2055 BREAK_TO_DEBUGGER();
2056 goto create_fail;
2057 }
2058
2059 /* Replay */
2060 pool->base.replay = dmub_replay_create(ctx);
2061 if (pool->base.replay == NULL) {
2062 dm_error("DC: failed to create replay obj!\n");
2063 BREAK_TO_DEBUGGER();
2064 goto create_fail;
2065 }
2066
2067 /* ABM */
2068 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2069 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2070 &abm_regs[i],
2071 &abm_shift,
2072 &abm_mask);
2073 if (pool->base.multiple_abms[i] == NULL) {
2074 dm_error("DC: failed to create abm for pipe %d!\n", i);
2075 BREAK_TO_DEBUGGER();
2076 goto create_fail;
2077 }
2078 }
2079
2080 /* MPC and DSC */
2081 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2082 if (pool->base.mpc == NULL) {
2083 BREAK_TO_DEBUGGER();
2084 dm_error("DC: failed to create mpc!\n");
2085 goto create_fail;
2086 }
2087
2088 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2089 pool->base.dscs[i] = dcn314_dsc_create(ctx, i);
2090 if (pool->base.dscs[i] == NULL) {
2091 BREAK_TO_DEBUGGER();
2092 dm_error("DC: failed to create display stream compressor %d!\n", i);
2093 goto create_fail;
2094 }
2095 }
2096
2097 /* DWB and MMHUBBUB */
2098 if (!dcn31_dwbc_create(ctx, &pool->base)) {
2099 BREAK_TO_DEBUGGER();
2100 dm_error("DC: failed to create dwbc!\n");
2101 goto create_fail;
2102 }
2103
2104 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2105 BREAK_TO_DEBUGGER();
2106 dm_error("DC: failed to create mcif_wb!\n");
2107 goto create_fail;
2108 }
2109
2110 /* AUX and I2C */
2111 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2112 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2113 if (pool->base.engines[i] == NULL) {
2114 BREAK_TO_DEBUGGER();
2115 dm_error(
2116 "DC:failed to create aux engine!!\n");
2117 goto create_fail;
2118 }
2119 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2120 if (pool->base.hw_i2cs[i] == NULL) {
2121 BREAK_TO_DEBUGGER();
2122 dm_error(
2123 "DC:failed to create hw i2c!!\n");
2124 goto create_fail;
2125 }
2126 pool->base.sw_i2cs[i] = NULL;
2127 }
2128
2129 /* DCN314 has 4 DPIA */
2130 pool->base.usb4_dpia_count = 4;
2131
2132 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2133 if (!resource_construct(num_virtual_links, dc, &pool->base,
2134 &res_create_funcs))
2135 goto create_fail;
2136
2137 /* HW Sequencer and Plane caps */
2138 dcn314_hw_sequencer_construct(dc);
2139
2140 dc->caps.max_planes = pool->base.pipe_count;
2141
2142 for (i = 0; i < dc->caps.max_planes; ++i)
2143 dc->caps.planes[i] = plane_cap;
2144
2145 dc->cap_funcs = cap_funcs;
2146
2147 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp;
2148
2149 return true;
2150
2151 create_fail:
2152
2153 dcn314_resource_destruct(pool);
2154
2155 return false;
2156 }
2157
dcn314_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2158 struct resource_pool *dcn314_create_resource_pool(
2159 const struct dc_init_data *init_data,
2160 struct dc *dc)
2161 {
2162 struct dcn314_resource_pool *pool =
2163 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL);
2164
2165 if (!pool)
2166 return NULL;
2167
2168 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool))
2169 return &pool->base;
2170
2171 BREAK_TO_DEBUGGER();
2172 kfree(pool);
2173 return NULL;
2174 }
2175