1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27
28
29 #include "dcn314_clk_mgr.h"
30
31 #include "dccg.h"
32 #include "clk_mgr_internal.h"
33
34 // For dce12_get_dp_ref_freq_khz
35 #include "dce100/dce_clk_mgr.h"
36
37 // For dcn20_update_clocks_update_dpp_dto
38 #include "dcn20/dcn20_clk_mgr.h"
39
40
41
42 #include "reg_helper.h"
43 #include "core_types.h"
44 #include "dm_helpers.h"
45
46 /* TODO: remove this include once we ported over remaining clk mgr functions*/
47 #include "dcn30/dcn30_clk_mgr.h"
48 #include "dcn31/dcn31_clk_mgr.h"
49
50 #include "dc_dmub_srv.h"
51 #include "link.h"
52 #include "dcn314_smu.h"
53
54
55 #include "logger_types.h"
56 #undef DC_LOGGER
57 #define DC_LOGGER \
58 clk_mgr->base.base.ctx->logger
59
60
61 #define MAX_INSTANCE 7
62 #define MAX_SEGMENT 8
63
64 struct IP_BASE_INSTANCE {
65 unsigned int segment[MAX_SEGMENT];
66 };
67
68 struct IP_BASE {
69 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
70 };
71
72 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0, 0, 0 } },
73 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0, 0, 0 } },
74 { { 0x00017000, 0x02402000, 0, 0, 0, 0, 0, 0 } },
75 { { 0x00017200, 0x02402400, 0, 0, 0, 0, 0, 0 } },
76 { { 0x0001B000, 0x0242D800, 0, 0, 0, 0, 0, 0 } },
77 { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0, 0, 0 } },
78 { { 0x0001B400, 0x0242E000, 0, 0, 0, 0, 0, 0 } } } };
79
80 #define regCLK1_CLK_PLL_REQ 0x0237
81 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0
82
83 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
84 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
85 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
86 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
87 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
88 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
89
90 #define REG(reg_name) \
91 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
92
93 #define TO_CLK_MGR_DCN314(clk_mgr)\
94 container_of(clk_mgr, struct clk_mgr_dcn314, base)
95
dcn314_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context)96 static int dcn314_get_active_display_cnt_wa(
97 struct dc *dc,
98 struct dc_state *context)
99 {
100 int i, display_count;
101 bool tmds_present = false;
102
103 display_count = 0;
104 for (i = 0; i < context->stream_count; i++) {
105 const struct dc_stream_state *stream = context->streams[i];
106
107 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
108 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
109 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
110 tmds_present = true;
111
112 /* Checking stream / link detection ensuring that PHY is active*/
113 if (dc_is_dp_signal(stream->signal) && !stream->dpms_off)
114 display_count++;
115
116 }
117
118 for (i = 0; i < dc->link_count; i++) {
119 const struct dc_link *link = dc->links[i];
120
121 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
122 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
123 link->link_enc->funcs->is_dig_enabled(link->link_enc))
124 display_count++;
125 }
126
127 /* WA for hang on HDMI after display off back on*/
128 if (display_count == 0 && tmds_present)
129 display_count = 1;
130
131 return display_count;
132 }
133
dcn314_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower,bool disable)134 static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,
135 bool safe_to_lower, bool disable)
136 {
137 struct dc *dc = clk_mgr_base->ctx->dc;
138 int i;
139
140 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
141 struct pipe_ctx *pipe = safe_to_lower
142 ? &context->res_ctx.pipe_ctx[i]
143 : &dc->current_state->res_ctx.pipe_ctx[i];
144
145 if (pipe->top_pipe || pipe->prev_odm_pipe)
146 continue;
147 if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
148 if (disable) {
149 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)
150 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
151
152 reset_sync_context_for_pipe(dc, context, i);
153 } else {
154 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
155 }
156 }
157 }
158 }
159
dcn314_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)160 void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,
161 struct dc_state *context,
162 bool safe_to_lower)
163 {
164 union dmub_rb_cmd cmd;
165 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
166 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
167 struct dc *dc = clk_mgr_base->ctx->dc;
168 int display_count;
169 bool update_dppclk = false;
170 bool update_dispclk = false;
171 bool dpp_clock_lowered = false;
172
173 if (dc->work_arounds.skip_clock_update)
174 return;
175
176 /*
177 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
178 * also if safe to lower is false, we just go in the higher state
179 */
180 if (safe_to_lower) {
181 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW &&
182 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
183 dcn314_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);
184 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);
185 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
186 }
187
188 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
189 dcn314_smu_set_dtbclk(clk_mgr, false);
190 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
191 }
192 /* check that we're not already in lower */
193 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
194 display_count = dcn314_get_active_display_cnt_wa(dc, context);
195 /* if we can go lower, go lower */
196 if (display_count == 0) {
197 union display_idle_optimization_u idle_info = { 0 };
198 idle_info.idle_info.df_request_disabled = 1;
199 idle_info.idle_info.phy_ref_clk_off = 1;
200 idle_info.idle_info.s0i2_rdy = 1;
201 dcn314_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
202 /* update power state */
203 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
204 }
205 }
206 } else {
207 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
208 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
209 dcn314_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);
210 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);
211 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
212 }
213
214 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
215 dcn314_smu_set_dtbclk(clk_mgr, true);
216 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
217 }
218
219 /* check that we're not already in D0 */
220 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
221 union display_idle_optimization_u idle_info = { 0 };
222
223 dcn314_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
224 /* update power state */
225 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
226 }
227 }
228
229 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
230 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
231 dcn314_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
232 }
233
234 if (should_set_clock(safe_to_lower,
235 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
236 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
237 dcn314_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
238 }
239
240 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
241 if (new_clocks->dppclk_khz < 100000)
242 new_clocks->dppclk_khz = 100000;
243
244 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
245 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
246 dpp_clock_lowered = true;
247 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
248 update_dppclk = true;
249 }
250
251 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
252 dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
253
254 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
255 dcn314_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
256 dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
257
258 update_dispclk = true;
259 }
260
261 if (dpp_clock_lowered) {
262 // increase per DPP DTO before lowering global dppclk
263 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
264 dcn314_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
265 } else {
266 // increase global DPPCLK before lowering per DPP DTO
267 if (update_dppclk || update_dispclk)
268 dcn314_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
269 // always update dtos unless clock is lowered and not safe to lower
270 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
271 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
272 }
273
274 // notify DMCUB of latest clocks
275 memset(&cmd, 0, sizeof(cmd));
276 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
277 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
278 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
279 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
280 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
281 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
282 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
283
284 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
285 }
286
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)287 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
288 {
289 /* get FbMult value */
290 struct fixed31_32 pll_req;
291 unsigned int fbmult_frac_val = 0;
292 unsigned int fbmult_int_val = 0;
293
294 /*
295 * Register value of fbmult is in 8.16 format, we are converting to 314.32
296 * to leverage the fix point operations available in driver
297 */
298
299 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
300 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
301
302 pll_req = dc_fixpt_from_int(fbmult_int_val);
303
304 /*
305 * since fractional part is only 16 bit in register definition but is 32 bit
306 * in our fix point definiton, need to shift left by 16 to obtain correct value
307 */
308 pll_req.value |= fbmult_frac_val << 16;
309
310 /* multiply by REFCLK period */
311 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
312
313 /* integer part is now VCO frequency in kHz */
314 return dc_fixpt_floor(pll_req);
315 }
316
dcn314_enable_pme_wa(struct clk_mgr * clk_mgr_base)317 static void dcn314_enable_pme_wa(struct clk_mgr *clk_mgr_base)
318 {
319 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
320
321 dcn314_smu_enable_pme_wa(clk_mgr);
322 }
323
dcn314_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)324 bool dcn314_are_clock_states_equal(struct dc_clocks *a,
325 struct dc_clocks *b)
326 {
327 if (a->dispclk_khz != b->dispclk_khz)
328 return false;
329 else if (a->dppclk_khz != b->dppclk_khz)
330 return false;
331 else if (a->dcfclk_khz != b->dcfclk_khz)
332 return false;
333 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
334 return false;
335 else if (a->zstate_support != b->zstate_support)
336 return false;
337 else if (a->dtbclk_en != b->dtbclk_en)
338 return false;
339
340 return true;
341 }
342
dcn314_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)343 static void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
344 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
345 {
346 return;
347 }
348
349 static struct clk_bw_params dcn314_bw_params = {
350 .vram_type = Ddr4MemType,
351 .num_channels = 1,
352 .clk_table = {
353 .num_entries = 4,
354 },
355
356 };
357
358 static struct wm_table ddr5_wm_table = {
359 .entries = {
360 {
361 .wm_inst = WM_A,
362 .wm_type = WM_TYPE_PSTATE_CHG,
363 .pstate_latency_us = 11.72,
364 .sr_exit_time_us = 12.5,
365 .sr_enter_plus_exit_time_us = 14.5,
366 .valid = true,
367 },
368 {
369 .wm_inst = WM_B,
370 .wm_type = WM_TYPE_PSTATE_CHG,
371 .pstate_latency_us = 11.72,
372 .sr_exit_time_us = 12.5,
373 .sr_enter_plus_exit_time_us = 14.5,
374 .valid = true,
375 },
376 {
377 .wm_inst = WM_C,
378 .wm_type = WM_TYPE_PSTATE_CHG,
379 .pstate_latency_us = 11.72,
380 .sr_exit_time_us = 12.5,
381 .sr_enter_plus_exit_time_us = 14.5,
382 .valid = true,
383 },
384 {
385 .wm_inst = WM_D,
386 .wm_type = WM_TYPE_PSTATE_CHG,
387 .pstate_latency_us = 11.72,
388 .sr_exit_time_us = 12.5,
389 .sr_enter_plus_exit_time_us = 14.5,
390 .valid = true,
391 },
392 }
393 };
394
395 static struct wm_table lpddr5_wm_table = {
396 .entries = {
397 {
398 .wm_inst = WM_A,
399 .wm_type = WM_TYPE_PSTATE_CHG,
400 .pstate_latency_us = 11.65333,
401 .sr_exit_time_us = 30.0,
402 .sr_enter_plus_exit_time_us = 32.0,
403 .valid = true,
404 },
405 {
406 .wm_inst = WM_B,
407 .wm_type = WM_TYPE_PSTATE_CHG,
408 .pstate_latency_us = 11.65333,
409 .sr_exit_time_us = 30.0,
410 .sr_enter_plus_exit_time_us = 32.0,
411 .valid = true,
412 },
413 {
414 .wm_inst = WM_C,
415 .wm_type = WM_TYPE_PSTATE_CHG,
416 .pstate_latency_us = 11.65333,
417 .sr_exit_time_us = 30.0,
418 .sr_enter_plus_exit_time_us = 32.0,
419 .valid = true,
420 },
421 {
422 .wm_inst = WM_D,
423 .wm_type = WM_TYPE_PSTATE_CHG,
424 .pstate_latency_us = 11.65333,
425 .sr_exit_time_us = 30.0,
426 .sr_enter_plus_exit_time_us = 32.0,
427 .valid = true,
428 },
429 }
430 };
431
432 static DpmClocks314_t dummy_clocks;
433
434 static struct dcn314_watermarks dummy_wms = { 0 };
435
dcn314_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn314_watermarks * table)436 static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn314_watermarks *table)
437 {
438 int i, num_valid_sets;
439
440 num_valid_sets = 0;
441
442 for (i = 0; i < WM_SET_COUNT; i++) {
443 /* skip empty entries, the smu array has no holes*/
444 if (!bw_params->wm_table.entries[i].valid)
445 continue;
446
447 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
448 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
449 /* We will not select WM based on fclk, so leave it as unconstrained */
450 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
451 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
452
453 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
454 if (i == 0)
455 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
456 else {
457 /* add 1 to make it non-overlapping with next lvl */
458 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
459 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
460 }
461 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
462 bw_params->clk_table.entries[i].dcfclk_mhz;
463
464 } else {
465 /* unconstrained for memory retraining */
466 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
467 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
468
469 /* Modify previous watermark range to cover up to max */
470 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
471 }
472 num_valid_sets++;
473 }
474
475 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
476
477 /* modify the min and max to make sure we cover the whole range*/
478 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
479 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
480 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
481 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
482
483 /* This is for writeback only, does not matter currently as no writeback support*/
484 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
485 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
486 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
487 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
488 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
489 }
490
dcn314_notify_wm_ranges(struct clk_mgr * clk_mgr_base)491 static void dcn314_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
492 {
493 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
494 struct clk_mgr_dcn314 *clk_mgr_dcn314 = TO_CLK_MGR_DCN314(clk_mgr);
495 struct dcn314_watermarks *table = clk_mgr_dcn314->smu_wm_set.wm_set;
496
497 if (!clk_mgr->smu_ver)
498 return;
499
500 if (!table || clk_mgr_dcn314->smu_wm_set.mc_address.quad_part == 0)
501 return;
502
503 memset(table, 0, sizeof(*table));
504
505 dcn314_build_watermark_ranges(clk_mgr_base->bw_params, table);
506
507 dcn314_smu_set_dram_addr_high(clk_mgr,
508 clk_mgr_dcn314->smu_wm_set.mc_address.high_part);
509 dcn314_smu_set_dram_addr_low(clk_mgr,
510 clk_mgr_dcn314->smu_wm_set.mc_address.low_part);
511 dcn314_smu_transfer_wm_table_dram_2_smu(clk_mgr);
512 }
513
dcn314_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn314_smu_dpm_clks * smu_dpm_clks)514 static void dcn314_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
515 struct dcn314_smu_dpm_clks *smu_dpm_clks)
516 {
517 DpmClocks314_t *table = smu_dpm_clks->dpm_clks;
518
519 if (!clk_mgr->smu_ver)
520 return;
521
522 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
523 return;
524
525 memset(table, 0, sizeof(*table));
526
527 dcn314_smu_set_dram_addr_high(clk_mgr,
528 smu_dpm_clks->mc_address.high_part);
529 dcn314_smu_set_dram_addr_low(clk_mgr,
530 smu_dpm_clks->mc_address.low_part);
531 dcn314_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
532 }
533
is_valid_clock_value(uint32_t clock_value)534 static inline bool is_valid_clock_value(uint32_t clock_value)
535 {
536 return clock_value > 1 && clock_value < 100000;
537 }
538
convert_wck_ratio(uint8_t wck_ratio)539 static unsigned int convert_wck_ratio(uint8_t wck_ratio)
540 {
541 switch (wck_ratio) {
542 case WCK_RATIO_1_2:
543 return 2;
544
545 case WCK_RATIO_1_4:
546 return 4;
547
548 default:
549 break;
550 }
551 return 1;
552 }
553
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)554 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
555 {
556 uint32_t max = 0;
557 int i;
558
559 for (i = 0; i < num_clocks; ++i) {
560 if (clocks[i] > max)
561 max = clocks[i];
562 }
563
564 return max;
565 }
566
dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,const DpmClocks314_t * clock_table)567 static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
568 struct integrated_info *bios_info,
569 const DpmClocks314_t *clock_table)
570 {
571 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
572 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
573 uint32_t max_pstate = 0, max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0;
574 int i;
575
576 /* Find highest valid fclk pstate */
577 for (i = 0; i < clock_table->NumDfPstatesEnabled; i++) {
578 if (is_valid_clock_value(clock_table->DfPstateTable[i].FClk) &&
579 clock_table->DfPstateTable[i].FClk > max_fclk) {
580 max_fclk = clock_table->DfPstateTable[i].FClk;
581 max_pstate = i;
582 }
583 }
584
585 /* We expect the table to contain at least one valid fclk entry. */
586 ASSERT(is_valid_clock_value(max_fclk));
587
588 /* Dispclk and dppclk can be max at any voltage, same number of levels for both */
589 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
590 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
591 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
592 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
593 } else {
594 /* Invalid number of entries in the table from PMFW. */
595 ASSERT(0);
596 }
597
598 /* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */
599 for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) {
600 uint32_t min_fclk = clock_table->DfPstateTable[0].FClk;
601 int j;
602
603 for (j = 1; j < clock_table->NumDfPstatesEnabled; j++) {
604 if (is_valid_clock_value(clock_table->DfPstateTable[j].FClk) &&
605 clock_table->DfPstateTable[j].FClk < min_fclk &&
606 clock_table->DfPstateTable[j].Voltage <= clock_table->SocVoltage[i]) {
607 min_fclk = clock_table->DfPstateTable[j].FClk;
608 min_pstate = j;
609 }
610 }
611
612 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
613 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
614 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
615 break;
616
617 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
618 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
619 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
620
621 /* Now update clocks we do read */
622 bw_params->clk_table.entries[i].fclk_mhz = min_fclk;
623 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[min_pstate].MemClk;
624 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[min_pstate].Voltage;
625 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
626 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
627 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
628 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
629 bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
630 clock_table->DfPstateTable[min_pstate].WckRatio);
631 }
632
633 /* Make sure to include at least one entry at highest pstate */
634 if (max_pstate != min_pstate || i == 0) {
635 if (i > MAX_NUM_DPM_LVL - 1)
636 i = MAX_NUM_DPM_LVL - 1;
637
638 bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
639 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk;
640 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[max_pstate].Voltage;
641 bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS);
642 bw_params->clk_table.entries[i].socclk_mhz = find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
643 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
644 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
645 bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
646 clock_table->DfPstateTable[max_pstate].WckRatio);
647 i++;
648 }
649 bw_params->clk_table.num_entries = i--;
650
651 /* Make sure all highest clocks are included*/
652 bw_params->clk_table.entries[i].socclk_mhz = find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
653 bw_params->clk_table.entries[i].dispclk_mhz = find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS);
654 bw_params->clk_table.entries[i].dppclk_mhz = find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS);
655 ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS));
656 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
657 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
658 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
659
660 /*
661 * Set any 0 clocks to max default setting. Not an issue for
662 * power since we aren't doing switching in such case anyway
663 */
664 for (i = 0; i < bw_params->clk_table.num_entries; i++) {
665 if (!bw_params->clk_table.entries[i].fclk_mhz) {
666 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
667 bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
668 bw_params->clk_table.entries[i].voltage = def_max.voltage;
669 }
670 if (!bw_params->clk_table.entries[i].dcfclk_mhz)
671 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
672 if (!bw_params->clk_table.entries[i].socclk_mhz)
673 bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
674 if (!bw_params->clk_table.entries[i].dispclk_mhz)
675 bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
676 if (!bw_params->clk_table.entries[i].dppclk_mhz)
677 bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
678 if (!bw_params->clk_table.entries[i].phyclk_mhz)
679 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
680 if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
681 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
682 if (!bw_params->clk_table.entries[i].dtbclk_mhz)
683 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
684 }
685 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
686 bw_params->vram_type = bios_info->memory_type;
687
688 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
689 bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
690
691 for (i = 0; i < WM_SET_COUNT; i++) {
692 bw_params->wm_table.entries[i].wm_inst = i;
693
694 if (i >= bw_params->clk_table.num_entries) {
695 bw_params->wm_table.entries[i].valid = false;
696 continue;
697 }
698
699 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
700 bw_params->wm_table.entries[i].valid = true;
701 }
702 }
703
704 static struct clk_mgr_funcs dcn314_funcs = {
705 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
706 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
707 .update_clocks = dcn314_update_clocks,
708 .init_clocks = dcn31_init_clocks,
709 .enable_pme_wa = dcn314_enable_pme_wa,
710 .are_clock_states_equal = dcn314_are_clock_states_equal,
711 .notify_wm_ranges = dcn314_notify_wm_ranges
712 };
713 extern struct clk_mgr_funcs dcn3_fpga_funcs;
714
dcn314_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn314 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)715 void dcn314_clk_mgr_construct(
716 struct dc_context *ctx,
717 struct clk_mgr_dcn314 *clk_mgr,
718 struct pp_smu_funcs *pp_smu,
719 struct dccg *dccg)
720 {
721 struct dcn314_smu_dpm_clks smu_dpm_clks = { 0 };
722 struct clk_log_info log_info = {0};
723
724 clk_mgr->base.base.ctx = ctx;
725 clk_mgr->base.base.funcs = &dcn314_funcs;
726
727 clk_mgr->base.pp_smu = pp_smu;
728
729 clk_mgr->base.dccg = dccg;
730 clk_mgr->base.dfs_bypass_disp_clk = 0;
731
732 clk_mgr->base.dprefclk_ss_percentage = 0;
733 clk_mgr->base.dprefclk_ss_divider = 1000;
734 clk_mgr->base.ss_on_dprefclk = false;
735 clk_mgr->base.dfs_ref_freq_khz = 48000;
736
737 clk_mgr->smu_wm_set.wm_set = (struct dcn314_watermarks *)dm_helpers_allocate_gpu_mem(
738 clk_mgr->base.base.ctx,
739 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
740 sizeof(struct dcn314_watermarks),
741 &clk_mgr->smu_wm_set.mc_address.quad_part);
742
743 if (!clk_mgr->smu_wm_set.wm_set) {
744 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
745 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
746 }
747 ASSERT(clk_mgr->smu_wm_set.wm_set);
748
749 smu_dpm_clks.dpm_clks = (DpmClocks314_t *)dm_helpers_allocate_gpu_mem(
750 clk_mgr->base.base.ctx,
751 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
752 sizeof(DpmClocks314_t),
753 &smu_dpm_clks.mc_address.quad_part);
754
755 if (smu_dpm_clks.dpm_clks == NULL) {
756 smu_dpm_clks.dpm_clks = &dummy_clocks;
757 smu_dpm_clks.mc_address.quad_part = 0;
758 }
759
760 ASSERT(smu_dpm_clks.dpm_clks);
761
762 clk_mgr->base.smu_ver = dcn314_smu_get_smu_version(&clk_mgr->base);
763
764 if (clk_mgr->base.smu_ver)
765 clk_mgr->base.smu_present = true;
766
767 /* TODO: Check we get what we expect during bringup */
768 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
769
770 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType)
771 dcn314_bw_params.wm_table = lpddr5_wm_table;
772 else
773 dcn314_bw_params.wm_table = ddr5_wm_table;
774
775 /* Saved clocks configured at boot for debug purposes */
776 dcn314_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
777 &clk_mgr->base.base, &log_info);
778
779 clk_mgr->base.base.dprefclk_khz = 600000;
780 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
781 dce_clock_read_ss_info(&clk_mgr->base);
782 /*if bios enabled SS, driver needs to adjust dtb clock, only enable with correct bios*/
783
784 clk_mgr->base.base.bw_params = &dcn314_bw_params;
785
786 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
787 int i;
788
789 dcn314_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
790 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
791 "NumDispClkLevelsEnabled: %d\n"
792 "NumSocClkLevelsEnabled: %d\n"
793 "VcnClkLevelsEnabled: %d\n"
794 "NumDfPst atesEnabled: %d\n"
795 "MinGfxClk: %d\n"
796 "MaxGfxClk: %d\n",
797 smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
798 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
799 smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
800 smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
801 smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
802 smu_dpm_clks.dpm_clks->MinGfxClk,
803 smu_dpm_clks.dpm_clks->MaxGfxClk);
804 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
805 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
806 i,
807 smu_dpm_clks.dpm_clks->DcfClocks[i]);
808 }
809 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
810 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
811 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
812 }
813 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
814 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
815 i, smu_dpm_clks.dpm_clks->SocClocks[i]);
816 }
817 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++)
818 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
819 i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
820
821 for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {
822 DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"
823 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"
824 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",
825 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
826 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
827 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
828 }
829
830 if (ctx->dc_bios && ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
831 dcn314_clk_mgr_helper_populate_bw_params(
832 &clk_mgr->base,
833 ctx->dc_bios->integrated_info,
834 smu_dpm_clks.dpm_clks);
835 }
836 }
837
838 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
839 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
840 smu_dpm_clks.dpm_clks);
841 }
842
dcn314_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)843 void dcn314_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
844 {
845 struct clk_mgr_dcn314 *clk_mgr = TO_CLK_MGR_DCN314(clk_mgr_int);
846
847 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
848 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
849 clk_mgr->smu_wm_set.wm_set);
850 }
851