1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include <linux/delay.h>
27 #include "dcn30_clk_mgr_smu_msg.h"
28 
29 #include "clk_mgr_internal.h"
30 #include "reg_helper.h"
31 #include "dm_helpers.h"
32 
33 #include "dalsmc.h"
34 #include "dcn30_smu11_driver_if.h"
35 
36 #define mmDAL_MSG_REG  0x1628A
37 #define mmDAL_ARG_REG  0x16273
38 #define mmDAL_RESP_REG 0x16274
39 
40 #define REG(reg_name) \
41 	mm ## reg_name
42 
43 #include "logger_types.h"
44 #undef DC_LOGGER
45 #define DC_LOGGER \
46 	CTX->logger
47 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
48 
49 
50 /*
51  * Function to be used instead of REG_WAIT macro because the wait ends when
52  * the register is NOT EQUAL to zero, and because the translation in msg_if.h
53  * won't work with REG_WAIT.
54  */
dcn30_smu_wait_for_response(struct clk_mgr_internal * clk_mgr,unsigned int delay_us,unsigned int max_retries)55 static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
56 {
57 	uint32_t reg = 0;
58 
59 	do {
60 		reg = REG_READ(DAL_RESP_REG);
61 		if (reg)
62 			break;
63 
64 		if (delay_us >= 1000)
65 			msleep(delay_us/1000);
66 		else if (delay_us > 0)
67 			udelay(delay_us);
68 	} while (max_retries--);
69 
70 	/* handle DALSMC_Result_CmdRejectedBusy? */
71 
72 	/* Log? */
73 
74 	return reg;
75 }
76 
dcn30_smu_send_msg_with_param(struct clk_mgr_internal * clk_mgr,uint32_t msg_id,uint32_t param_in,uint32_t * param_out)77 static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)
78 {
79 	uint32_t result;
80 	/* Wait for response register to be ready */
81 	dcn30_smu_wait_for_response(clk_mgr, 10, 200000);
82 
83 	/* Clear response register */
84 	REG_WRITE(DAL_RESP_REG, 0);
85 
86 	/* Set the parameter register for the SMU message */
87 	REG_WRITE(DAL_ARG_REG, param_in);
88 
89 	/* Trigger the message transaction by writing the message ID */
90 	REG_WRITE(DAL_MSG_REG, msg_id);
91 
92 	result = dcn30_smu_wait_for_response(clk_mgr, 10, 200000);
93 
94 	if (IS_SMU_TIMEOUT(result)) {
95 		dm_helpers_smu_timeout(CTX, msg_id, param_in, 10 * 200000);
96 	}
97 
98 	/* Wait for response */
99 	if (result == DALSMC_Result_OK) {
100 		if (param_out)
101 			*param_out = REG_READ(DAL_ARG_REG);
102 
103 		return true;
104 	}
105 
106 	return false;
107 }
108 
109 /* Test message should return input + 1 */
dcn30_smu_test_message(struct clk_mgr_internal * clk_mgr,uint32_t input)110 bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input)
111 {
112 	uint32_t response = 0;
113 
114 	smu_print("SMU Test message: %d\n", input);
115 
116 	if (dcn30_smu_send_msg_with_param(clk_mgr,
117 			DALSMC_MSG_TestMessage, input, &response))
118 		if (response == input + 1)
119 			return true;
120 
121 	return false;
122 }
123 
dcn30_smu_get_smu_version(struct clk_mgr_internal * clk_mgr,unsigned int * version)124 bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version)
125 {
126 	smu_print("SMU Get SMU version\n");
127 
128 	if (dcn30_smu_send_msg_with_param(clk_mgr,
129 			DALSMC_MSG_GetSmuVersion, 0, version)) {
130 
131 		smu_print("SMU version: %d\n", *version);
132 
133 		return true;
134 	}
135 
136 	return false;
137 }
138 
139 /* Message output should match SMU11_DRIVER_IF_VERSION in smu11_driver_if.h */
dcn30_smu_check_driver_if_version(struct clk_mgr_internal * clk_mgr)140 bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr)
141 {
142 	uint32_t response = 0;
143 
144 	smu_print("SMU Check driver if version\n");
145 
146 	if (dcn30_smu_send_msg_with_param(clk_mgr,
147 			DALSMC_MSG_GetDriverIfVersion, 0, &response)) {
148 
149 		smu_print("SMU driver if version: %d\n", response);
150 
151 		if (response == SMU11_DRIVER_IF_VERSION)
152 			return true;
153 	}
154 
155 	return false;
156 }
157 
158 /* Message output should match DALSMC_VERSION in dalsmc.h */
dcn30_smu_check_msg_header_version(struct clk_mgr_internal * clk_mgr)159 bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr)
160 {
161 	uint32_t response = 0;
162 
163 	smu_print("SMU Check msg header version\n");
164 
165 	if (dcn30_smu_send_msg_with_param(clk_mgr,
166 			DALSMC_MSG_GetMsgHeaderVersion, 0, &response)) {
167 
168 		smu_print("SMU msg header version: %d\n", response);
169 
170 		if (response == DALSMC_VERSION)
171 			return true;
172 	}
173 
174 	return false;
175 }
176 
dcn30_smu_set_dram_addr_high(struct clk_mgr_internal * clk_mgr,uint32_t addr_high)177 void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
178 {
179 	smu_print("SMU Set DRAM addr high: %d\n", addr_high);
180 
181 	dcn30_smu_send_msg_with_param(clk_mgr,
182 			DALSMC_MSG_SetDalDramAddrHigh, addr_high, NULL);
183 }
184 
dcn30_smu_set_dram_addr_low(struct clk_mgr_internal * clk_mgr,uint32_t addr_low)185 void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
186 {
187 	smu_print("SMU Set DRAM addr low: %d\n", addr_low);
188 
189 	dcn30_smu_send_msg_with_param(clk_mgr,
190 			DALSMC_MSG_SetDalDramAddrLow, addr_low, NULL);
191 }
192 
dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal * clk_mgr)193 void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
194 {
195 	smu_print("SMU Transfer WM table SMU 2 DRAM\n");
196 
197 	dcn30_smu_send_msg_with_param(clk_mgr,
198 			DALSMC_MSG_TransferTableSmu2Dram, TABLE_WATERMARKS, NULL);
199 }
200 
dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal * clk_mgr)201 void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
202 {
203 	smu_print("SMU Transfer WM table DRAM 2 SMU\n");
204 
205 	dcn30_smu_send_msg_with_param(clk_mgr,
206 			DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL);
207 }
208 
209 /* Returns the actual frequency that was set in MHz, 0 on failure */
dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal * clk_mgr,uint32_t clk,uint16_t freq_mhz)210 unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)
211 {
212 	uint32_t response = 0;
213 
214 	/* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
215 	uint32_t param = (clk << 16) | freq_mhz;
216 
217 	smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);
218 
219 	dcn30_smu_send_msg_with_param(clk_mgr,
220 			DALSMC_MSG_SetHardMinByFreq, param, &response);
221 
222 	smu_print("SMU Frequency set = %d MHz\n", response);
223 
224 	return response;
225 }
226 
227 /* Returns the actual frequency that was set in MHz, 0 on failure */
dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal * clk_mgr,uint32_t clk,uint16_t freq_mhz)228 unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)
229 {
230 	uint32_t response = 0;
231 
232 	/* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
233 	uint32_t param = (clk << 16) | freq_mhz;
234 
235 	smu_print("SMU Set hard max by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);
236 
237 	dcn30_smu_send_msg_with_param(clk_mgr,
238 			DALSMC_MSG_SetHardMaxByFreq, param, &response);
239 
240 	smu_print("SMU Frequency set = %d MHz\n", response);
241 
242 	return response;
243 }
244 
245 /*
246  * Frequency in MHz returned in lower 16 bits for valid DPM level
247  *
248  * Call with dpm_level = 0xFF to query features, return value will be:
249  *     Bits 7:0 - number of DPM levels
250  *     Bit   28 - 1 = auto DPM on
251  *     Bit   29 - 1 = sweep DPM on
252  *     Bit   30 - 1 = forced DPM on
253  *     Bit   31 - 0 = discrete, 1 = fine-grained
254  *
255  * With fine-grained DPM, only min and max frequencies will be reported
256  *
257  * Returns 0 on failure
258  */
dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal * clk_mgr,uint32_t clk,uint8_t dpm_level)259 unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level)
260 {
261 	uint32_t response = 0;
262 
263 	/* bits 23:16 for clock type, lower 8 bits for DPM level */
264 	uint32_t param = (clk << 16) | dpm_level;
265 
266 	smu_print("SMU Get dpm freq by index: clk = %d, dpm_level = %d\n", clk, dpm_level);
267 
268 	dcn30_smu_send_msg_with_param(clk_mgr,
269 			DALSMC_MSG_GetDpmFreqByIndex, param, &response);
270 
271 	smu_print("SMU dpm freq: %d MHz\n", response);
272 
273 	return response;
274 }
275 
276 /* Returns the max DPM frequency in DC mode in MHz, 0 on failure */
dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal * clk_mgr,uint32_t clk)277 unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk)
278 {
279 	uint32_t response = 0;
280 
281 	/* bits 23:16 for clock type */
282 	uint32_t param = clk << 16;
283 
284 	smu_print("SMU Get DC mode max DPM freq: clk = %d\n", clk);
285 
286 	dcn30_smu_send_msg_with_param(clk_mgr,
287 			DALSMC_MSG_GetDcModeMaxDpmFreq, param, &response);
288 
289 	smu_print("SMU DC mode max DMP freq: %d MHz\n", response);
290 
291 	return response;
292 }
293 
dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal * clk_mgr,uint32_t freq_mhz)294 void dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz)
295 {
296 	smu_print("SMU Set min deep sleep dcef clk: freq_mhz = %d MHz\n", freq_mhz);
297 
298 	dcn30_smu_send_msg_with_param(clk_mgr,
299 			DALSMC_MSG_SetMinDeepSleepDcefclk, freq_mhz, NULL);
300 }
301 
dcn30_smu_set_num_of_displays(struct clk_mgr_internal * clk_mgr,uint32_t num_displays)302 void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays)
303 {
304 	smu_print("SMU Set num of displays: num_displays = %d\n", num_displays);
305 
306 	dcn30_smu_send_msg_with_param(clk_mgr,
307 			DALSMC_MSG_NumOfDisplays, num_displays, NULL);
308 }
309 
dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal * clk_mgr,bool enable,uint8_t cache_timer_delay,uint8_t cache_timer_scale)310 void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale)
311 {
312 	/* bits 8:7 for cache timer scale, bits 6:1 for cache timer delay, bit 0 = 1 for enable, = 0 for disable */
313 	uint32_t param = (cache_timer_scale << 7) | (cache_timer_delay << 1) | (enable ? 1 : 0);
314 
315 	smu_print("SMU Set display refresh from mall: enable = %d, cache_timer_delay = %d, cache_timer_scale = %d\n",
316 		enable, cache_timer_delay, cache_timer_scale);
317 
318 	dcn30_smu_send_msg_with_param(clk_mgr,
319 			DALSMC_MSG_SetDisplayRefreshFromMall, param, NULL);
320 }
321 
dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal * clk_mgr,bool enable)322 void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable)
323 {
324 	smu_print("SMU Set external client df cstate allow: enable = %d\n", enable);
325 
326 	dcn30_smu_send_msg_with_param(clk_mgr,
327 			DALSMC_MSG_SetExternalClientDfCstateAllow, enable ? 1 : 0, NULL);
328 }
329 
dcn30_smu_set_pme_workaround(struct clk_mgr_internal * clk_mgr)330 void dcn30_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)
331 {
332 	smu_print("SMU Set PME workaround\n");
333 
334 	dcn30_smu_send_msg_with_param(clk_mgr,
335 	DALSMC_MSG_BacoAudioD3PME, 0, NULL);
336 }
337