1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27
28 #include "core_types.h"
29 #include "link_encoder.h"
30 #include "dcn30_dio_link_encoder.h"
31 #include "stream_encoder.h"
32 #include "dc_bios_types.h"
33 /* #include "dcn3ag/dcn3ag_phy_fw.h" */
34
35 #include "gpio_service_interface.h"
36
37 #define CTX \
38 enc10->base.ctx
39 #define DC_LOGGER \
40 enc10->base.ctx->logger
41
42 #define REG(reg)\
43 (enc10->link_regs->reg)
44
45 #undef FN
46 #define FN(reg_name, field_name) \
47 enc10->link_shift->field_name, enc10->link_mask->field_name
48
49 #define IND_REG(index) \
50 (enc10->link_regs->index)
51
52
dcn30_link_encoder_validate_output_with_stream(struct link_encoder * enc,const struct dc_stream_state * stream)53 bool dcn30_link_encoder_validate_output_with_stream(
54 struct link_encoder *enc,
55 const struct dc_stream_state *stream)
56 {
57 return dcn10_link_encoder_validate_output_with_stream(enc, stream);
58 }
59
60 static const struct link_encoder_funcs dcn30_link_enc_funcs = {
61 .read_state = link_enc2_read_state,
62 .validate_output_with_stream =
63 dcn30_link_encoder_validate_output_with_stream,
64 .hw_init = enc3_hw_init,
65 .setup = dcn10_link_encoder_setup,
66 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
67 .enable_dp_output = dcn20_link_encoder_enable_dp_output,
68 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
69 .disable_output = dcn10_link_encoder_disable_output,
70 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
71 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
72 .update_mst_stream_allocation_table =
73 dcn10_link_encoder_update_mst_stream_allocation_table,
74 .psr_program_dp_dphy_fast_training =
75 dcn10_psr_program_dp_dphy_fast_training,
76 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
77 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
78 .enable_hpd = dcn10_link_encoder_enable_hpd,
79 .disable_hpd = dcn10_link_encoder_disable_hpd,
80 .is_dig_enabled = dcn10_is_dig_enabled,
81 .destroy = dcn10_link_encoder_destroy,
82 .fec_set_enable = enc2_fec_set_enable,
83 .fec_set_ready = enc2_fec_set_ready,
84 .fec_is_active = enc2_fec_is_active,
85 .get_dig_frontend = dcn10_get_dig_frontend,
86 .get_dig_mode = dcn10_get_dig_mode,
87 .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
88 .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
89 };
90
dcn30_link_encoder_construct(struct dcn20_link_encoder * enc20,const struct encoder_init_data * init_data,const struct encoder_feature_support * enc_features,const struct dcn10_link_enc_registers * link_regs,const struct dcn10_link_enc_aux_registers * aux_regs,const struct dcn10_link_enc_hpd_registers * hpd_regs,const struct dcn10_link_enc_shift * link_shift,const struct dcn10_link_enc_mask * link_mask)91 void dcn30_link_encoder_construct(
92 struct dcn20_link_encoder *enc20,
93 const struct encoder_init_data *init_data,
94 const struct encoder_feature_support *enc_features,
95 const struct dcn10_link_enc_registers *link_regs,
96 const struct dcn10_link_enc_aux_registers *aux_regs,
97 const struct dcn10_link_enc_hpd_registers *hpd_regs,
98 const struct dcn10_link_enc_shift *link_shift,
99 const struct dcn10_link_enc_mask *link_mask)
100 {
101 struct bp_encoder_cap_info bp_cap_info = {0};
102 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
103 enum bp_result result = BP_RESULT_OK;
104 struct dcn10_link_encoder *enc10 = &enc20->enc10;
105
106 enc10->base.funcs = &dcn30_link_enc_funcs;
107 enc10->base.ctx = init_data->ctx;
108 enc10->base.id = init_data->encoder;
109
110 enc10->base.hpd_source = init_data->hpd_source;
111 enc10->base.connector = init_data->connector;
112
113 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
114
115 enc10->base.features = *enc_features;
116
117 enc10->base.transmitter = init_data->transmitter;
118
119 /* set the flag to indicate whether driver poll the I2C data pin
120 * while doing the DP sink detect
121 */
122
123 /* if (dal_adapter_service_is_feature_supported(as,
124 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
125 enc10->base.features.flags.bits.
126 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
127
128 enc10->base.output_signals =
129 SIGNAL_TYPE_DVI_SINGLE_LINK |
130 SIGNAL_TYPE_DVI_DUAL_LINK |
131 SIGNAL_TYPE_LVDS |
132 SIGNAL_TYPE_DISPLAY_PORT |
133 SIGNAL_TYPE_DISPLAY_PORT_MST |
134 SIGNAL_TYPE_EDP |
135 SIGNAL_TYPE_HDMI_TYPE_A;
136
137 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
138 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
139 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
140 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
141 * Prefer DIG assignment is decided by board design.
142 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
143 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
144 * By this, adding DIGG should not hurt DCE 8.0.
145 * This will let DCE 8.1 share DCE 8.0 as much as possible
146 */
147
148 enc10->link_regs = link_regs;
149 enc10->aux_regs = aux_regs;
150 enc10->hpd_regs = hpd_regs;
151 enc10->link_shift = link_shift;
152 enc10->link_mask = link_mask;
153
154 switch (enc10->base.transmitter) {
155 case TRANSMITTER_UNIPHY_A:
156 enc10->base.preferred_engine = ENGINE_ID_DIGA;
157 break;
158 case TRANSMITTER_UNIPHY_B:
159 enc10->base.preferred_engine = ENGINE_ID_DIGB;
160 break;
161 case TRANSMITTER_UNIPHY_C:
162 enc10->base.preferred_engine = ENGINE_ID_DIGC;
163 break;
164 case TRANSMITTER_UNIPHY_D:
165 enc10->base.preferred_engine = ENGINE_ID_DIGD;
166 break;
167 case TRANSMITTER_UNIPHY_E:
168 enc10->base.preferred_engine = ENGINE_ID_DIGE;
169 break;
170 case TRANSMITTER_UNIPHY_F:
171 enc10->base.preferred_engine = ENGINE_ID_DIGF;
172 break;
173 case TRANSMITTER_UNIPHY_G:
174 enc10->base.preferred_engine = ENGINE_ID_DIGG;
175 break;
176 default:
177 ASSERT_CRITICAL(false);
178 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
179 }
180
181 /* default to one to mirror Windows behavior */
182 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
183
184 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
185 enc10->base.id, &bp_cap_info);
186
187 /* Override features with DCE-specific values */
188 if (result == BP_RESULT_OK) {
189 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
190 bp_cap_info.DP_HBR2_EN;
191 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
192 bp_cap_info.DP_HBR3_EN;
193 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
194 enc10->base.features.flags.bits.IS_DP2_CAPABLE = bp_cap_info.IS_DP2_CAPABLE;
195 enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
196 enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
197 enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
198 enc10->base.features.flags.bits.DP_IS_USB_C =
199 bp_cap_info.DP_IS_USB_C;
200 } else {
201 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
202 __func__,
203 result);
204 }
205 if (enc10->base.ctx->dc->debug.hdmi20_disable) {
206 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
207 }
208 }
209
210 #define AUX_REG(reg)\
211 (enc10->aux_regs->reg)
212
213 #define AUX_REG_READ(reg_name) \
214 dm_read_reg(CTX, AUX_REG(reg_name))
215
216 #define AUX_REG_WRITE(reg_name, val) \
217 dm_write_reg(CTX, AUX_REG(reg_name), val)
enc3_hw_init(struct link_encoder * enc)218 void enc3_hw_init(struct link_encoder *enc)
219 {
220 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
221
222 /*
223 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
224 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
225 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
226 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
227 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
228 05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
229 06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
230 07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
231 */
232
233 /*
234 AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
235 AUX_RX_START_WINDOW = 1 [6:4]
236 AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
237 AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1
238 AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
239 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0
240 AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1
241 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1
242 AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3
243 AUX_RX_DETECTION_THRESHOLD [30:28] = 1
244 */
245 AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
246
247 AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
248
249 //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
250 // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
251 // 27MHz -> 0xd
252 // 100MHz -> 0x32
253 // 48MHz -> 0x18
254
255 // Set TMDS_CTL0 to 1. This is a legacy setting.
256 REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
257
258 dcn10_aux_initialize(enc10);
259 }
260