1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dccg.h"
27 #include "clk_mgr_internal.h"
28
29 #include "dce100/dce_clk_mgr.h"
30 #include "dcn20_clk_mgr.h"
31 #include "reg_helper.h"
32 #include "core_types.h"
33 #include "dm_helpers.h"
34
35 #include "navi10_ip_offset.h"
36 #include "dcn/dcn_2_0_0_offset.h"
37 #include "dcn/dcn_2_0_0_sh_mask.h"
38 #include "clk/clk_11_0_0_offset.h"
39 #include "clk/clk_11_0_0_sh_mask.h"
40
41
42 #undef FN
43 #define FN(reg_name, field_name) \
44 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
45
46 #define REG(reg) \
47 (clk_mgr->regs->reg)
48
49 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
50
51 #define BASE(seg) BASE_INNER(seg)
52
53 #define SR(reg_name)\
54 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
55 mm ## reg_name
56
57 #define CLK_BASE_INNER(seg) \
58 CLK_BASE__INST0_SEG ## seg
59
60
61 static const struct clk_mgr_registers clk_mgr_regs = {
62 CLK_REG_LIST_NV10()
63 };
64
65 static const struct clk_mgr_shift clk_mgr_shift = {
66 CLK_MASK_SH_LIST_NV10(__SHIFT)
67 };
68
69 static const struct clk_mgr_mask clk_mgr_mask = {
70 CLK_MASK_SH_LIST_NV10(_MASK)
71 };
72
dentist_get_did_from_divider(int divider)73 uint32_t dentist_get_did_from_divider(int divider)
74 {
75 uint32_t divider_id;
76
77 /* we want to floor here to get higher clock than required rather than lower */
78 if (divider < DENTIST_DIVIDER_RANGE_2_START) {
79 if (divider < DENTIST_DIVIDER_RANGE_1_START)
80 divider_id = DENTIST_BASE_DID_1;
81 else
82 divider_id = DENTIST_BASE_DID_1
83 + (divider - DENTIST_DIVIDER_RANGE_1_START)
84 / DENTIST_DIVIDER_RANGE_1_STEP;
85 } else if (divider < DENTIST_DIVIDER_RANGE_3_START) {
86 divider_id = DENTIST_BASE_DID_2
87 + (divider - DENTIST_DIVIDER_RANGE_2_START)
88 / DENTIST_DIVIDER_RANGE_2_STEP;
89 } else if (divider < DENTIST_DIVIDER_RANGE_4_START) {
90 divider_id = DENTIST_BASE_DID_3
91 + (divider - DENTIST_DIVIDER_RANGE_3_START)
92 / DENTIST_DIVIDER_RANGE_3_STEP;
93 } else {
94 divider_id = DENTIST_BASE_DID_4
95 + (divider - DENTIST_DIVIDER_RANGE_4_START)
96 / DENTIST_DIVIDER_RANGE_4_STEP;
97 if (divider_id > DENTIST_MAX_DID)
98 divider_id = DENTIST_MAX_DID;
99 }
100
101 return divider_id;
102 }
103
dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower)104 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
105 struct dc_state *context, bool safe_to_lower)
106 {
107 int i;
108
109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
110 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
111 int dpp_inst, dppclk_khz, prev_dppclk_khz;
112
113 /* Loop index will match dpp->inst if resource exists,
114 * and we want to avoid dependency on dpp object
115 */
116 dpp_inst = i;
117 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
118
119 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
120
121 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
122 clk_mgr->dccg->funcs->update_dpp_dto(
123 clk_mgr->dccg, dpp_inst, dppclk_khz);
124 }
125 }
126
dcn20_update_clocks_update_dentist(struct clk_mgr_internal * clk_mgr,struct dc_state * context)127 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct dc_state *context)
128 {
129 int dpp_divider = 0;
130 int disp_divider = 0;
131 uint32_t dppclk_wdivider = 0;
132 uint32_t dispclk_wdivider = 0;
133 uint32_t current_dispclk_wdivider;
134 uint32_t i;
135
136 if (clk_mgr->base.clks.dppclk_khz == 0 || clk_mgr->base.clks.dispclk_khz == 0)
137 return;
138
139 dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
140 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
141 disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
142 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
143
144 dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
145 dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
146
147 REG_GET(DENTIST_DISPCLK_CNTL,
148 DENTIST_DISPCLK_WDIVIDER, ¤t_dispclk_wdivider);
149
150 /* When changing divider to or from 127, some extra programming is required to prevent corruption */
151 if (current_dispclk_wdivider == 127 && dispclk_wdivider != 127) {
152 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
153 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
154 uint32_t fifo_level;
155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
156 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
157 int32_t N;
158 int32_t j;
159
160 if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))
161 continue;
162 /* Virtual encoders don't have this function */
163 if (!stream_enc->funcs->get_fifo_cal_average_level)
164 continue;
165 fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
166 stream_enc);
167 N = fifo_level / 4;
168 dccg->funcs->set_fifo_errdet_ovr_en(
169 dccg,
170 true);
171 for (j = 0; j < N - 4; j++)
172 dccg->funcs->otg_drop_pixel(
173 dccg,
174 pipe_ctx->stream_res.tg->inst);
175 dccg->funcs->set_fifo_errdet_ovr_en(
176 dccg,
177 false);
178 }
179 } else if (dispclk_wdivider == 127 && current_dispclk_wdivider != 127) {
180 REG_UPDATE(DENTIST_DISPCLK_CNTL,
181 DENTIST_DISPCLK_WDIVIDER, 126);
182 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
183 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
184 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
185 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
186 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
187 uint32_t fifo_level;
188 int32_t N;
189 int32_t j;
190
191 if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))
192 continue;
193 /* Virtual encoders don't have this function */
194 if (!stream_enc->funcs->get_fifo_cal_average_level)
195 continue;
196 fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
197 stream_enc);
198 N = fifo_level / 4;
199 dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);
200 for (j = 0; j < 12 - N; j++)
201 dccg->funcs->otg_add_pixel(dccg,
202 pipe_ctx->stream_res.tg->inst);
203 dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);
204 }
205 }
206
207 REG_UPDATE(DENTIST_DISPCLK_CNTL,
208 DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
209 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
210 REG_UPDATE(DENTIST_DISPCLK_CNTL,
211 DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
212 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
213 }
214
215
dcn2_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)216 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
217 struct dc_state *context,
218 bool safe_to_lower)
219 {
220 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
221 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
222 struct dc *dc = clk_mgr_base->ctx->dc;
223 struct pp_smu_funcs_nv *pp_smu = NULL;
224 int display_count;
225 bool update_dppclk = false;
226 bool update_dispclk = false;
227 bool enter_display_off = false;
228 bool dpp_clock_lowered = false;
229 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
230 bool force_reset = false;
231 bool p_state_change_support;
232 int total_plane_count;
233
234 if (dc->work_arounds.skip_clock_update)
235 return;
236
237 if (clk_mgr_base->clks.dispclk_khz == 0 ||
238 dc->debug.force_clock_mode & 0x1) {
239 //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3.
240 force_reset = true;
241
242 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
243
244 //force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level.
245 }
246 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
247 if (dc->res_pool->pp_smu)
248 pp_smu = &dc->res_pool->pp_smu->nv_funcs;
249
250 if (display_count == 0)
251 enter_display_off = true;
252
253 if (enter_display_off == safe_to_lower) {
254 if (pp_smu && pp_smu->set_display_count)
255 pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
256 }
257
258 if (dc->debug.force_min_dcfclk_mhz > 0)
259 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
260 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
261
262 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
263 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
264 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq)
265 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
266 }
267
268 if (should_set_clock(safe_to_lower,
269 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
270 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
271 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk)
272 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
273 }
274
275 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) {
276 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
277 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq)
278 pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.socclk_khz));
279 }
280
281 total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
282 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
283 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
284 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
285 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
286 if (pp_smu && pp_smu->set_pstate_handshake_support)
287 pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
288 }
289
290 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
291 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
292 if (pp_smu && pp_smu->set_hard_min_uclk_by_freq)
293 pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
294 }
295
296 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
297 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
298 dpp_clock_lowered = true;
299 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
300
301 update_dppclk = true;
302 }
303
304 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
305 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
306
307 update_dispclk = true;
308 }
309
310 if (update_dppclk || update_dispclk) {
311 new_clocks->disp_dpp_voltage_level_khz = new_clocks->dppclk_khz;
312
313 if (update_dispclk)
314 new_clocks->disp_dpp_voltage_level_khz = new_clocks->dispclk_khz > new_clocks->dppclk_khz ? new_clocks->dispclk_khz : new_clocks->dppclk_khz;
315
316 clk_mgr_base->clks.disp_dpp_voltage_level_khz = new_clocks->disp_dpp_voltage_level_khz;
317 if (pp_smu && pp_smu->set_voltage_by_freq)
318 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.disp_dpp_voltage_level_khz));
319 }
320
321 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
322 if (dpp_clock_lowered) {
323 // if clock is being lowered, increase DTO before lowering refclk
324 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
325 dcn20_update_clocks_update_dentist(clk_mgr, context);
326 } else {
327 // if clock is being raised, increase refclk before lowering DTO
328 if (update_dppclk || update_dispclk)
329 dcn20_update_clocks_update_dentist(clk_mgr, context);
330 // always update dtos unless clock is lowered and not safe to lower
331 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
332 }
333 }
334
335 if (update_dispclk &&
336 dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
337 /*update dmcu for wait_loop count*/
338 dmcu->funcs->set_psr_wait_loop(dmcu,
339 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
340 }
341 }
342
dcn2_update_clocks_fpga(struct clk_mgr * clk_mgr,struct dc_state * context,bool safe_to_lower)343 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
344 struct dc_state *context,
345 bool safe_to_lower)
346 {
347 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
348
349 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
350 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
351 int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
352
353 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
354 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
355 }
356
357 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
358 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
359 }
360
361 if (should_set_clock(safe_to_lower,
362 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
363 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
364 }
365
366 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
367 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
368 }
369
370 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
371 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
372 }
373
374 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
375 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
376 }
377
378 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
379 clk_mgr->clks.fclk_khz = fclk_adj;
380 }
381
382 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
383 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
384 }
385
386 /* Both fclk and ref_dppclk run on the same scemi clock.
387 * So take the higher value since the DPP DTO is typically programmed
388 * such that max dppclk is 1:1 with ref_dppclk.
389 */
390 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
391 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
392 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
393 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
394
395 // Both fclk and ref_dppclk run on the same scemi clock.
396 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
397
398 /* TODO: set dtbclk in correct place */
399 clk_mgr->clks.dtbclk_en = false;
400 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
401 }
402
dcn2_init_clocks(struct clk_mgr * clk_mgr)403 void dcn2_init_clocks(struct clk_mgr *clk_mgr)
404 {
405 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
406 // Assumption is that boot state always supports pstate
407 clk_mgr->clks.p_state_change_support = true;
408 clk_mgr->clks.prev_p_state_change_support = true;
409 }
410
dcn2_enable_pme_wa(struct clk_mgr * clk_mgr_base)411 static void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
412 {
413 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
414 struct pp_smu_funcs_nv *pp_smu = NULL;
415
416 if (clk_mgr->pp_smu) {
417 pp_smu = &clk_mgr->pp_smu->nv_funcs;
418
419 if (pp_smu->set_pme_wa_enable)
420 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
421 }
422 }
423
424
dcn2_read_clocks_from_hw_dentist(struct clk_mgr * clk_mgr_base)425 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base)
426 {
427 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
428 uint32_t dispclk_wdivider;
429 uint32_t dppclk_wdivider;
430 int disp_divider;
431 int dpp_divider;
432
433 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
434 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, &dppclk_wdivider);
435
436 disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
437 dpp_divider = dentist_get_divider_from_did(dppclk_wdivider);
438
439 if (disp_divider && dpp_divider) {
440 /* Calculate the current DFS clock, in kHz.*/
441 clk_mgr_base->clks.dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
442 * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
443
444 clk_mgr_base->clks.dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
445 * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
446 }
447 }
448
dcn2_get_clock(struct clk_mgr * clk_mgr,struct dc_state * context,enum dc_clock_type clock_type,struct dc_clock_config * clock_cfg)449 void dcn2_get_clock(struct clk_mgr *clk_mgr,
450 struct dc_state *context,
451 enum dc_clock_type clock_type,
452 struct dc_clock_config *clock_cfg)
453 {
454
455 if (clock_type == DC_CLOCK_TYPE_DISPCLK) {
456 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
457 clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz;
458 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz;
459 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;
460 }
461 if (clock_type == DC_CLOCK_TYPE_DPPCLK) {
462 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
463 clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz;
464 clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz;
465 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;
466 }
467 }
468
dcn2_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)469 static bool dcn2_are_clock_states_equal(struct dc_clocks *a,
470 struct dc_clocks *b)
471 {
472 if (a->dispclk_khz != b->dispclk_khz)
473 return false;
474 else if (a->dppclk_khz != b->dppclk_khz)
475 return false;
476 else if (a->disp_dpp_voltage_level_khz != b->disp_dpp_voltage_level_khz)
477 return false;
478 else if (a->dcfclk_khz != b->dcfclk_khz)
479 return false;
480 else if (a->socclk_khz != b->socclk_khz)
481 return false;
482 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
483 return false;
484 else if (a->dramclk_khz != b->dramclk_khz)
485 return false;
486 else if (a->p_state_change_support != b->p_state_change_support)
487 return false;
488
489 return true;
490 }
491
492 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
dcn2_notify_link_rate_change(struct clk_mgr * clk_mgr_base,struct dc_link * link)493 static void dcn2_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
494 {
495 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
496 unsigned int i, max_phyclk_req = 0;
497 struct pp_smu_funcs_nv *pp_smu = NULL;
498
499 if (!clk_mgr->pp_smu || !clk_mgr->pp_smu->nv_funcs.set_voltage_by_freq)
500 return;
501
502 pp_smu = &clk_mgr->pp_smu->nv_funcs;
503
504 clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
505
506 for (i = 0; i < MAX_PIPES * 2; i++) {
507 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
508 max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
509 }
510
511 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
512 clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
513 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));
514 }
515 }
516
517 static struct clk_mgr_funcs dcn2_funcs = {
518 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
519 .update_clocks = dcn2_update_clocks,
520 .init_clocks = dcn2_init_clocks,
521 .enable_pme_wa = dcn2_enable_pme_wa,
522 .get_clock = dcn2_get_clock,
523 .are_clock_states_equal = dcn2_are_clock_states_equal,
524 .notify_link_rate_change = dcn2_notify_link_rate_change,
525 };
526
527
dcn20_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)528 void dcn20_clk_mgr_construct(
529 struct dc_context *ctx,
530 struct clk_mgr_internal *clk_mgr,
531 struct pp_smu_funcs *pp_smu,
532 struct dccg *dccg)
533 {
534 int dprefclk_did;
535 int target_div;
536 uint32_t pll_req_reg;
537 struct fixed31_32 pll_req;
538
539 clk_mgr->base.ctx = ctx;
540 clk_mgr->pp_smu = pp_smu;
541 clk_mgr->base.funcs = &dcn2_funcs;
542 clk_mgr->regs = &clk_mgr_regs;
543 clk_mgr->clk_mgr_shift = &clk_mgr_shift;
544 clk_mgr->clk_mgr_mask = &clk_mgr_mask;
545
546 clk_mgr->dccg = dccg;
547 clk_mgr->dfs_bypass_disp_clk = 0;
548
549 clk_mgr->dprefclk_ss_percentage = 0;
550 clk_mgr->dprefclk_ss_divider = 1000;
551 clk_mgr->ss_on_dprefclk = false;
552
553 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
554
555 /* DFS Slice 2 should be used for DPREFCLK */
556 dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL);
557 /* Convert DPREFCLK DFS Slice DID to actual divider */
558 target_div = dentist_get_divider_from_did(dprefclk_did);
559 /* get FbMult value */
560 pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ);
561
562 /* set up a fixed-point number
563 * this works because the int part is on the right edge of the register
564 * and the frac part is on the left edge
565 */
566
567 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
568 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
569
570 /* multiply by REFCLK period */
571 pll_req = dc_fixpt_mul_int(pll_req, 100000);
572
573 /* integer part is now VCO frequency in kHz */
574 clk_mgr->base.dentist_vco_freq_khz = dc_fixpt_floor(pll_req);
575
576 /* in case we don't get a value from the register, use default */
577 if (clk_mgr->base.dentist_vco_freq_khz == 0)
578 clk_mgr->base.dentist_vco_freq_khz = 3850000;
579
580 /* Calculate the DPREFCLK in kHz.*/
581 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
582 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
583 //Integrated_info table does not exist on dGPU projects so should not be referenced
584 //anywhere in code for dGPUs.
585 //Also there is no plan for now that DFS BYPASS will be used on NV10/12/14.
586 clk_mgr->dfs_bypass_enabled = false;
587
588 dce_clock_read_ss_info(clk_mgr);
589 }
590