1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dm_services.h"
27 
28 /* include DCE8 register header files */
29 #include "dce/dce_8_0_d.h"
30 #include "dce/dce_8_0_sh_mask.h"
31 
32 #include "dc_types.h"
33 
34 #include "include/grph_object_id.h"
35 #include "include/logger_interface.h"
36 #include "../dce110/dce110_timing_generator.h"
37 #include "dce80_timing_generator.h"
38 
39 #include "timing_generator.h"
40 
41 enum black_color_format {
42 	BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,	/* used as index in array */
43 	BLACK_COLOR_FORMAT_RGB_LIMITED,
44 	BLACK_COLOR_FORMAT_YUV_TV,
45 	BLACK_COLOR_FORMAT_YUV_CV,
46 	BLACK_COLOR_FORMAT_YUV_SUPER_AA,
47 
48 	BLACK_COLOR_FORMAT_COUNT
49 };
50 
51 static const struct dce110_timing_generator_offsets reg_offsets[] = {
52 {
53 	.crtc = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
54 	.dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
55 },
56 {
57 	.crtc = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
58 	.dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
59 },
60 {
61 	.crtc = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
62 	.dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
63 },
64 {
65 	.crtc = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
66 	.dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
67 },
68 {
69 	.crtc = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
70 	.dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
71 },
72 {
73 	.crtc = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
74 	.dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
75 }
76 };
77 
78 #define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
79 
80 #define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
81 #define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
82 
83 #define CRTC_REG(reg) (reg + tg110->offsets.crtc)
84 #define DCP_REG(reg) (reg + tg110->offsets.dcp)
85 #define DMIF_REG(reg) (reg + tg110->offsets.dmif)
86 
program_pix_dur(struct timing_generator * tg,uint32_t pix_clk_100hz)87 static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz)
88 {
89 	uint64_t pix_dur;
90 	uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
91 					+ DCE110TG_FROM_TG(tg)->offsets.dmif;
92 	uint32_t value = dm_read_reg(tg->ctx, addr);
93 
94 	if (pix_clk_100hz == 0)
95 		return;
96 
97 	pix_dur = div_u64(10000000000ull, pix_clk_100hz);
98 
99 	set_reg_field_value(
100 		value,
101 		pix_dur,
102 		DPG_PIPE_ARBITRATION_CONTROL1,
103 		PIXEL_DURATION);
104 
105 	dm_write_reg(tg->ctx, addr, value);
106 }
107 
program_timing(struct timing_generator * tg,const struct dc_crtc_timing * timing,int vready_offset,int vstartup_start,int vupdate_offset,int vupdate_width,const enum signal_type signal,bool use_vbios)108 static void program_timing(struct timing_generator *tg,
109 	const struct dc_crtc_timing *timing,
110 	int vready_offset,
111 	int vstartup_start,
112 	int vupdate_offset,
113 	int vupdate_width,
114 	const enum signal_type signal,
115 	bool use_vbios)
116 {
117 	if (!use_vbios)
118 		program_pix_dur(tg, timing->pix_clk_100hz);
119 
120 	dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios);
121 }
122 
dce80_timing_generator_enable_advanced_request(struct timing_generator * tg,bool enable,const struct dc_crtc_timing * timing)123 static void dce80_timing_generator_enable_advanced_request(
124 	struct timing_generator *tg,
125 	bool enable,
126 	const struct dc_crtc_timing *timing)
127 {
128 	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
129 	uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
130 	uint32_t value = dm_read_reg(tg->ctx, addr);
131 
132 	if (enable) {
133 		set_reg_field_value(
134 			value,
135 			0,
136 			CRTC_START_LINE_CONTROL,
137 			CRTC_LEGACY_REQUESTOR_EN);
138 	} else {
139 		set_reg_field_value(
140 			value,
141 			1,
142 			CRTC_START_LINE_CONTROL,
143 			CRTC_LEGACY_REQUESTOR_EN);
144 	}
145 
146 	if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
147 		set_reg_field_value(
148 			value,
149 			3,
150 			CRTC_START_LINE_CONTROL,
151 			CRTC_ADVANCED_START_LINE_POSITION);
152 		set_reg_field_value(
153 			value,
154 			0,
155 			CRTC_START_LINE_CONTROL,
156 			CRTC_PREFETCH_EN);
157 	} else {
158 		set_reg_field_value(
159 			value,
160 			4,
161 			CRTC_START_LINE_CONTROL,
162 			CRTC_ADVANCED_START_LINE_POSITION);
163 		set_reg_field_value(
164 			value,
165 			1,
166 			CRTC_START_LINE_CONTROL,
167 			CRTC_PREFETCH_EN);
168 	}
169 
170 	set_reg_field_value(
171 		value,
172 		1,
173 		CRTC_START_LINE_CONTROL,
174 		CRTC_PROGRESSIVE_START_LINE_EARLY);
175 
176 	set_reg_field_value(
177 		value,
178 		1,
179 		CRTC_START_LINE_CONTROL,
180 		CRTC_INTERLACE_START_LINE_EARLY);
181 
182 	dm_write_reg(tg->ctx, addr, value);
183 }
184 
185 static const struct timing_generator_funcs dce80_tg_funcs = {
186 		.validate_timing = dce110_tg_validate_timing,
187 		.program_timing = program_timing,
188 		.enable_crtc = dce110_timing_generator_enable_crtc,
189 		.disable_crtc = dce110_timing_generator_disable_crtc,
190 		.is_counter_moving = dce110_timing_generator_is_counter_moving,
191 		.get_position = dce110_timing_generator_get_position,
192 		.get_frame_count = dce110_timing_generator_get_vblank_counter,
193 		.get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos,
194 		.set_early_control = dce110_timing_generator_set_early_control,
195 		.wait_for_state = dce110_tg_wait_for_state,
196 		.set_blank = dce110_tg_set_blank,
197 		.is_blanked = dce110_tg_is_blanked,
198 		.set_colors = dce110_tg_set_colors,
199 		.set_overscan_blank_color =
200 				dce110_timing_generator_set_overscan_color_black,
201 		.set_blank_color = dce110_timing_generator_program_blank_color,
202 		.disable_vga = dce110_timing_generator_disable_vga,
203 		.did_triggered_reset_occur =
204 				dce110_timing_generator_did_triggered_reset_occur,
205 		.setup_global_swap_lock =
206 				dce110_timing_generator_setup_global_swap_lock,
207 		.enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
208 		.disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
209 		.tear_down_global_swap_lock =
210 				dce110_timing_generator_tear_down_global_swap_lock,
211 		.set_drr = dce110_timing_generator_set_drr,
212 		.get_last_used_drr_vtotal = NULL,
213 		.set_static_screen_control =
214 			dce110_timing_generator_set_static_screen_control,
215 		.set_test_pattern = dce110_timing_generator_set_test_pattern,
216 		.arm_vert_intr = dce110_arm_vert_intr,
217 
218 		/* DCE8.0 overrides */
219 		.enable_advanced_request =
220 				dce80_timing_generator_enable_advanced_request,
221 		.configure_crc = dce110_configure_crc,
222 		.get_crc = dce110_get_crc,
223 };
224 
dce80_timing_generator_construct(struct dce110_timing_generator * tg110,struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)225 void dce80_timing_generator_construct(
226 	struct dce110_timing_generator *tg110,
227 	struct dc_context *ctx,
228 	uint32_t instance,
229 	const struct dce110_timing_generator_offsets *offsets)
230 {
231 	tg110->controller_id = CONTROLLER_ID_D0 + instance;
232 	tg110->base.inst = instance;
233 	tg110->offsets = *offsets;
234 	tg110->derived_offsets = reg_offsets[instance];
235 
236 	tg110->base.funcs = &dce80_tg_funcs;
237 
238 	tg110->base.ctx = ctx;
239 	tg110->base.bp = ctx->dc_bios;
240 
241 	tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
242 	tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
243 
244 	tg110->min_h_blank = 56;
245 	tg110->min_h_front_porch = 4;
246 	tg110->min_h_back_porch = 4;
247 }
248 
249