1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 */
24
25 #include "dm_services.h"
26
27 #include "dc.h"
28
29 #include "core_status.h"
30 #include "core_types.h"
31 #include "hw_sequencer.h"
32 #include "dce/dce_hwseq.h"
33
34 #include "resource.h"
35
36 #include "gpio_service_interface.h"
37 #include "clk_mgr.h"
38 #include "clock_source.h"
39 #include "dc_bios_types.h"
40
41 #include "bios_parser_interface.h"
42 #include "bios/bios_parser_helper.h"
43 #include "include/irq_service_interface.h"
44 #include "transform.h"
45 #include "dmcu.h"
46 #include "dpp.h"
47 #include "timing_generator.h"
48 #include "abm.h"
49 #include "virtual/virtual_link_encoder.h"
50 #include "hubp.h"
51
52 #include "link_hwss.h"
53 #include "link_encoder.h"
54 #include "link_enc_cfg.h"
55
56 #include "link.h"
57 #include "dm_helpers.h"
58 #include "mem_input.h"
59
60 #include "dc_dmub_srv.h"
61
62 #include "dsc.h"
63
64 #include "vm_helper.h"
65
66 #include "dce/dce_i2c.h"
67
68 #include "dmub/dmub_srv.h"
69
70 #include "dce/dmub_psr.h"
71
72 #include "dce/dmub_hw_lock_mgr.h"
73
74 #include "dc_trace.h"
75
76 #include "hw_sequencer_private.h"
77
78 #include "dce/dmub_outbox.h"
79
80 #define CTX \
81 dc->ctx
82
83 #define DC_LOGGER \
84 dc->ctx->logger
85
86 static const char DC_BUILD_ID[] = "production-build";
87
88 /**
89 * DOC: Overview
90 *
91 * DC is the OS-agnostic component of the amdgpu DC driver.
92 *
93 * DC maintains and validates a set of structs representing the state of the
94 * driver and writes that state to AMD hardware
95 *
96 * Main DC HW structs:
97 *
98 * struct dc - The central struct. One per driver. Created on driver load,
99 * destroyed on driver unload.
100 *
101 * struct dc_context - One per driver.
102 * Used as a backpointer by most other structs in dc.
103 *
104 * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
105 * plugpoints). Created on driver load, destroyed on driver unload.
106 *
107 * struct dc_sink - One per display. Created on boot or hotplug.
108 * Destroyed on shutdown or hotunplug. A dc_link can have a local sink
109 * (the display directly attached). It may also have one or more remote
110 * sinks (in the Multi-Stream Transport case)
111 *
112 * struct resource_pool - One per driver. Represents the hw blocks not in the
113 * main pipeline. Not directly accessible by dm.
114 *
115 * Main dc state structs:
116 *
117 * These structs can be created and destroyed as needed. There is a full set of
118 * these structs in dc->current_state representing the currently programmed state.
119 *
120 * struct dc_state - The global DC state to track global state information,
121 * such as bandwidth values.
122 *
123 * struct dc_stream_state - Represents the hw configuration for the pipeline from
124 * a framebuffer to a display. Maps one-to-one with dc_sink.
125 *
126 * struct dc_plane_state - Represents a framebuffer. Each stream has at least one,
127 * and may have more in the Multi-Plane Overlay case.
128 *
129 * struct resource_context - Represents the programmable state of everything in
130 * the resource_pool. Not directly accessible by dm.
131 *
132 * struct pipe_ctx - A member of struct resource_context. Represents the
133 * internal hardware pipeline components. Each dc_plane_state has either
134 * one or two (in the pipe-split case).
135 */
136
137 /* Private functions */
138
elevate_update_type(enum surface_update_type * original,enum surface_update_type new)139 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
140 {
141 if (new > *original)
142 *original = new;
143 }
144
destroy_links(struct dc * dc)145 static void destroy_links(struct dc *dc)
146 {
147 uint32_t i;
148
149 for (i = 0; i < dc->link_count; i++) {
150 if (NULL != dc->links[i])
151 dc->link_srv->destroy_link(&dc->links[i]);
152 }
153 }
154
get_num_of_internal_disp(struct dc_link ** links,uint32_t num_links)155 static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links)
156 {
157 int i;
158 uint32_t count = 0;
159
160 for (i = 0; i < num_links; i++) {
161 if (links[i]->connector_signal == SIGNAL_TYPE_EDP ||
162 links[i]->is_internal_display)
163 count++;
164 }
165
166 return count;
167 }
168
get_seamless_boot_stream_count(struct dc_state * ctx)169 static int get_seamless_boot_stream_count(struct dc_state *ctx)
170 {
171 uint8_t i;
172 uint8_t seamless_boot_stream_count = 0;
173
174 for (i = 0; i < ctx->stream_count; i++)
175 if (ctx->streams[i]->apply_seamless_boot_optimization)
176 seamless_boot_stream_count++;
177
178 return seamless_boot_stream_count;
179 }
180
create_links(struct dc * dc,uint32_t num_virtual_links)181 static bool create_links(
182 struct dc *dc,
183 uint32_t num_virtual_links)
184 {
185 int i;
186 int connectors_num;
187 struct dc_bios *bios = dc->ctx->dc_bios;
188
189 dc->link_count = 0;
190
191 connectors_num = bios->funcs->get_connectors_number(bios);
192
193 DC_LOG_DC("BIOS object table - number of connectors: %d", connectors_num);
194
195 if (connectors_num > ENUM_ID_COUNT) {
196 dm_error(
197 "DC: Number of connectors %d exceeds maximum of %d!\n",
198 connectors_num,
199 ENUM_ID_COUNT);
200 return false;
201 }
202
203 dm_output_to_console(
204 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
205 __func__,
206 connectors_num,
207 num_virtual_links);
208
209 for (i = 0; i < connectors_num; i++) {
210 struct link_init_data link_init_params = {0};
211 struct dc_link *link;
212
213 DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);
214
215 link_init_params.ctx = dc->ctx;
216 /* next BIOS object table connector */
217 link_init_params.connector_index = i;
218 link_init_params.link_index = dc->link_count;
219 link_init_params.dc = dc;
220 link = dc->link_srv->create_link(&link_init_params);
221
222 if (link) {
223 dc->links[dc->link_count] = link;
224 link->dc = dc;
225 ++dc->link_count;
226 }
227 }
228
229 DC_LOG_DC("BIOS object table - end");
230
231 /* Create a link for each usb4 dpia port */
232 for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) {
233 struct link_init_data link_init_params = {0};
234 struct dc_link *link;
235
236 link_init_params.ctx = dc->ctx;
237 link_init_params.connector_index = i;
238 link_init_params.link_index = dc->link_count;
239 link_init_params.dc = dc;
240 link_init_params.is_dpia_link = true;
241
242 link = dc->link_srv->create_link(&link_init_params);
243 if (link) {
244 dc->links[dc->link_count] = link;
245 link->dc = dc;
246 ++dc->link_count;
247 }
248 }
249
250 for (i = 0; i < num_virtual_links; i++) {
251 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
252 struct encoder_init_data enc_init = {0};
253
254 if (link == NULL) {
255 BREAK_TO_DEBUGGER();
256 goto failed_alloc;
257 }
258
259 link->link_index = dc->link_count;
260 dc->links[dc->link_count] = link;
261 dc->link_count++;
262
263 link->ctx = dc->ctx;
264 link->dc = dc;
265 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
266 link->link_id.type = OBJECT_TYPE_CONNECTOR;
267 link->link_id.id = CONNECTOR_ID_VIRTUAL;
268 link->link_id.enum_id = ENUM_ID_1;
269 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
270 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
271
272 if (!link->link_enc) {
273 BREAK_TO_DEBUGGER();
274 goto failed_alloc;
275 }
276
277 link->link_status.dpcd_caps = &link->dpcd_caps;
278
279 enc_init.ctx = dc->ctx;
280 enc_init.channel = CHANNEL_ID_UNKNOWN;
281 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
282 enc_init.transmitter = TRANSMITTER_UNKNOWN;
283 enc_init.connector = link->link_id;
284 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
285 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
286 enc_init.encoder.enum_id = ENUM_ID_1;
287 virtual_link_encoder_construct(link->link_enc, &enc_init);
288 }
289
290 dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count);
291
292 return true;
293
294 failed_alloc:
295 return false;
296 }
297
298 /* Create additional DIG link encoder objects if fewer than the platform
299 * supports were created during link construction. This can happen if the
300 * number of physical connectors is less than the number of DIGs.
301 */
create_link_encoders(struct dc * dc)302 static bool create_link_encoders(struct dc *dc)
303 {
304 bool res = true;
305 unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;
306 unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;
307 int i;
308
309 /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG
310 * link encoders and physical display endpoints and does not require
311 * additional link encoder objects.
312 */
313 if (num_usb4_dpia == 0)
314 return res;
315
316 /* Create as many link encoder objects as the platform supports. DPIA
317 * endpoints can be programmably mapped to any DIG.
318 */
319 if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) {
320 for (i = 0; i < num_dig_link_enc; i++) {
321 struct link_encoder *link_enc = dc->res_pool->link_encoders[i];
322
323 if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) {
324 link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx,
325 (enum engine_id)(ENGINE_ID_DIGA + i));
326 if (link_enc) {
327 dc->res_pool->link_encoders[i] = link_enc;
328 dc->res_pool->dig_link_enc_count++;
329 } else {
330 res = false;
331 }
332 }
333 }
334 }
335
336 return res;
337 }
338
339 /* Destroy any additional DIG link encoder objects created by
340 * create_link_encoders().
341 * NB: Must only be called after destroy_links().
342 */
destroy_link_encoders(struct dc * dc)343 static void destroy_link_encoders(struct dc *dc)
344 {
345 unsigned int num_usb4_dpia;
346 unsigned int num_dig_link_enc;
347 int i;
348
349 if (!dc->res_pool)
350 return;
351
352 num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;
353 num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;
354
355 /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG
356 * link encoders and physical display endpoints and does not require
357 * additional link encoder objects.
358 */
359 if (num_usb4_dpia == 0)
360 return;
361
362 for (i = 0; i < num_dig_link_enc; i++) {
363 struct link_encoder *link_enc = dc->res_pool->link_encoders[i];
364
365 if (link_enc) {
366 link_enc->funcs->destroy(&link_enc);
367 dc->res_pool->link_encoders[i] = NULL;
368 dc->res_pool->dig_link_enc_count--;
369 }
370 }
371 }
372
dc_perf_trace_create(void)373 static struct dc_perf_trace *dc_perf_trace_create(void)
374 {
375 return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
376 }
377
dc_perf_trace_destroy(struct dc_perf_trace ** perf_trace)378 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
379 {
380 kfree(*perf_trace);
381 *perf_trace = NULL;
382 }
383
384 /**
385 * dc_stream_adjust_vmin_vmax - look up pipe context & update parts of DRR
386 * @dc: dc reference
387 * @stream: Initial dc stream state
388 * @adjust: Updated parameters for vertical_total_min and vertical_total_max
389 *
390 * Looks up the pipe context of dc_stream_state and updates the
391 * vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
392 * Rate, which is a power-saving feature that targets reducing panel
393 * refresh rate while the screen is static
394 *
395 * Return: %true if the pipe context is found and adjusted;
396 * %false if the pipe context is not found.
397 */
dc_stream_adjust_vmin_vmax(struct dc * dc,struct dc_stream_state * stream,struct dc_crtc_timing_adjust * adjust)398 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
399 struct dc_stream_state *stream,
400 struct dc_crtc_timing_adjust *adjust)
401 {
402 int i;
403
404 /*
405 * Don't adjust DRR while there's bandwidth optimizations pending to
406 * avoid conflicting with firmware updates.
407 */
408 if (dc->ctx->dce_version > DCE_VERSION_MAX)
409 if (dc->optimized_required || dc->wm_optimized_required)
410 return false;
411
412 stream->adjust.v_total_max = adjust->v_total_max;
413 stream->adjust.v_total_mid = adjust->v_total_mid;
414 stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
415 stream->adjust.v_total_min = adjust->v_total_min;
416
417 for (i = 0; i < MAX_PIPES; i++) {
418 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
419
420 if (pipe->stream == stream && pipe->stream_res.tg) {
421 dc->hwss.set_drr(&pipe,
422 1,
423 *adjust);
424
425 return true;
426 }
427 }
428 return false;
429 }
430
431 /**
432 * dc_stream_get_last_used_drr_vtotal - Looks up the pipe context of
433 * dc_stream_state and gets the last VTOTAL used by DRR (Dynamic Refresh Rate)
434 *
435 * @dc: [in] dc reference
436 * @stream: [in] Initial dc stream state
437 * @refresh_rate: [in] new refresh_rate
438 *
439 * Return: %true if the pipe context is found and there is an associated
440 * timing_generator for the DC;
441 * %false if the pipe context is not found or there is no
442 * timing_generator for the DC.
443 */
dc_stream_get_last_used_drr_vtotal(struct dc * dc,struct dc_stream_state * stream,uint32_t * refresh_rate)444 bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
445 struct dc_stream_state *stream,
446 uint32_t *refresh_rate)
447 {
448 bool status = false;
449
450 int i = 0;
451
452 for (i = 0; i < MAX_PIPES; i++) {
453 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
454
455 if (pipe->stream == stream && pipe->stream_res.tg) {
456 /* Only execute if a function pointer has been defined for
457 * the DC version in question
458 */
459 if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) {
460 pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate);
461
462 status = true;
463
464 break;
465 }
466 }
467 }
468
469 return status;
470 }
471
dc_stream_get_crtc_position(struct dc * dc,struct dc_stream_state ** streams,int num_streams,unsigned int * v_pos,unsigned int * nom_v_pos)472 bool dc_stream_get_crtc_position(struct dc *dc,
473 struct dc_stream_state **streams, int num_streams,
474 unsigned int *v_pos, unsigned int *nom_v_pos)
475 {
476 /* TODO: Support multiple streams */
477 const struct dc_stream_state *stream = streams[0];
478 int i;
479 bool ret = false;
480 struct crtc_position position;
481
482 for (i = 0; i < MAX_PIPES; i++) {
483 struct pipe_ctx *pipe =
484 &dc->current_state->res_ctx.pipe_ctx[i];
485
486 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
487 dc->hwss.get_position(&pipe, 1, &position);
488
489 *v_pos = position.vertical_count;
490 *nom_v_pos = position.nominal_vcount;
491 ret = true;
492 }
493 }
494 return ret;
495 }
496
497 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
498 static inline void
dc_stream_forward_dmub_crc_window(struct dc_dmub_srv * dmub_srv,struct rect * rect,struct otg_phy_mux * mux_mapping,bool is_stop)499 dc_stream_forward_dmub_crc_window(struct dc_dmub_srv *dmub_srv,
500 struct rect *rect, struct otg_phy_mux *mux_mapping, bool is_stop)
501 {
502 union dmub_rb_cmd cmd = {0};
503
504 cmd.secure_display.roi_info.phy_id = mux_mapping->phy_output_num;
505 cmd.secure_display.roi_info.otg_id = mux_mapping->otg_output_num;
506
507 if (is_stop) {
508 cmd.secure_display.header.type = DMUB_CMD__SECURE_DISPLAY;
509 cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE;
510 } else {
511 cmd.secure_display.header.type = DMUB_CMD__SECURE_DISPLAY;
512 cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY;
513 cmd.secure_display.roi_info.x_start = rect->x;
514 cmd.secure_display.roi_info.y_start = rect->y;
515 cmd.secure_display.roi_info.x_end = rect->x + rect->width;
516 cmd.secure_display.roi_info.y_end = rect->y + rect->height;
517 }
518
519 dm_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
520 }
521
522 static inline void
dc_stream_forward_dmcu_crc_window(struct dmcu * dmcu,struct rect * rect,struct otg_phy_mux * mux_mapping,bool is_stop)523 dc_stream_forward_dmcu_crc_window(struct dmcu *dmcu,
524 struct rect *rect, struct otg_phy_mux *mux_mapping, bool is_stop)
525 {
526 if (is_stop)
527 dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping);
528 else
529 dmcu->funcs->forward_crc_window(dmcu, rect, mux_mapping);
530 }
531
532 bool
dc_stream_forward_crc_window(struct dc_stream_state * stream,struct rect * rect,bool is_stop)533 dc_stream_forward_crc_window(struct dc_stream_state *stream,
534 struct rect *rect, bool is_stop)
535 {
536 struct dmcu *dmcu;
537 struct dc_dmub_srv *dmub_srv;
538 struct otg_phy_mux mux_mapping;
539 struct pipe_ctx *pipe;
540 int i;
541 struct dc *dc = stream->ctx->dc;
542
543 for (i = 0; i < MAX_PIPES; i++) {
544 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
545 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
546 break;
547 }
548
549 /* Stream not found */
550 if (i == MAX_PIPES)
551 return false;
552
553 mux_mapping.phy_output_num = stream->link->link_enc_hw_inst;
554 mux_mapping.otg_output_num = pipe->stream_res.tg->inst;
555
556 dmcu = dc->res_pool->dmcu;
557 dmub_srv = dc->ctx->dmub_srv;
558
559 /* forward to dmub */
560 if (dmub_srv)
561 dc_stream_forward_dmub_crc_window(dmub_srv, rect, &mux_mapping, is_stop);
562 /* forward to dmcu */
563 else if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
564 dc_stream_forward_dmcu_crc_window(dmcu, rect, &mux_mapping, is_stop);
565 else
566 return false;
567
568 return true;
569 }
570 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
571
572 /**
573 * dc_stream_configure_crc() - Configure CRC capture for the given stream.
574 * @dc: DC Object
575 * @stream: The stream to configure CRC on.
576 * @enable: Enable CRC if true, disable otherwise.
577 * @crc_window: CRC window (x/y start/end) information
578 * @continuous: Capture CRC on every frame if true. Otherwise, only capture
579 * once.
580 *
581 * By default, only CRC0 is configured, and the entire frame is used to
582 * calculate the CRC.
583 *
584 * Return: %false if the stream is not found or CRC capture is not supported;
585 * %true if the stream has been configured.
586 */
dc_stream_configure_crc(struct dc * dc,struct dc_stream_state * stream,struct crc_params * crc_window,bool enable,bool continuous)587 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
588 struct crc_params *crc_window, bool enable, bool continuous)
589 {
590 struct pipe_ctx *pipe;
591 struct crc_params param;
592 struct timing_generator *tg;
593
594 pipe = resource_get_otg_master_for_stream(
595 &dc->current_state->res_ctx, stream);
596
597 /* Stream not found */
598 if (pipe == NULL)
599 return false;
600
601 /* By default, capture the full frame */
602 param.windowa_x_start = 0;
603 param.windowa_y_start = 0;
604 param.windowa_x_end = pipe->stream->timing.h_addressable;
605 param.windowa_y_end = pipe->stream->timing.v_addressable;
606 param.windowb_x_start = 0;
607 param.windowb_y_start = 0;
608 param.windowb_x_end = pipe->stream->timing.h_addressable;
609 param.windowb_y_end = pipe->stream->timing.v_addressable;
610
611 if (crc_window) {
612 param.windowa_x_start = crc_window->windowa_x_start;
613 param.windowa_y_start = crc_window->windowa_y_start;
614 param.windowa_x_end = crc_window->windowa_x_end;
615 param.windowa_y_end = crc_window->windowa_y_end;
616 param.windowb_x_start = crc_window->windowb_x_start;
617 param.windowb_y_start = crc_window->windowb_y_start;
618 param.windowb_x_end = crc_window->windowb_x_end;
619 param.windowb_y_end = crc_window->windowb_y_end;
620 }
621
622 param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
623 param.odm_mode = pipe->next_odm_pipe ? 1:0;
624
625 /* Default to the union of both windows */
626 param.selection = UNION_WINDOW_A_B;
627 param.continuous_mode = continuous;
628 param.enable = enable;
629
630 tg = pipe->stream_res.tg;
631
632 /* Only call if supported */
633 if (tg->funcs->configure_crc)
634 return tg->funcs->configure_crc(tg, ¶m);
635 DC_LOG_WARNING("CRC capture not supported.");
636 return false;
637 }
638
639 /**
640 * dc_stream_get_crc() - Get CRC values for the given stream.
641 *
642 * @dc: DC object.
643 * @stream: The DC stream state of the stream to get CRCs from.
644 * @r_cr: CRC value for the red component.
645 * @g_y: CRC value for the green component.
646 * @b_cb: CRC value for the blue component.
647 *
648 * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
649 *
650 * Return:
651 * %false if stream is not found, or if CRCs are not enabled.
652 */
dc_stream_get_crc(struct dc * dc,struct dc_stream_state * stream,uint32_t * r_cr,uint32_t * g_y,uint32_t * b_cb)653 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
654 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
655 {
656 int i;
657 struct pipe_ctx *pipe;
658 struct timing_generator *tg;
659
660 for (i = 0; i < MAX_PIPES; i++) {
661 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
662 if (pipe->stream == stream)
663 break;
664 }
665 /* Stream not found */
666 if (i == MAX_PIPES)
667 return false;
668
669 tg = pipe->stream_res.tg;
670
671 if (tg->funcs->get_crc)
672 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
673 DC_LOG_WARNING("CRC capture not supported.");
674 return false;
675 }
676
dc_stream_set_dyn_expansion(struct dc * dc,struct dc_stream_state * stream,enum dc_dynamic_expansion option)677 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
678 enum dc_dynamic_expansion option)
679 {
680 /* OPP FMT dyn expansion updates*/
681 int i;
682 struct pipe_ctx *pipe_ctx;
683
684 for (i = 0; i < MAX_PIPES; i++) {
685 if (dc->current_state->res_ctx.pipe_ctx[i].stream
686 == stream) {
687 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
688 pipe_ctx->stream_res.opp->dyn_expansion = option;
689 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
690 pipe_ctx->stream_res.opp,
691 COLOR_SPACE_YCBCR601,
692 stream->timing.display_color_depth,
693 stream->signal);
694 }
695 }
696 }
697
dc_stream_set_dither_option(struct dc_stream_state * stream,enum dc_dither_option option)698 void dc_stream_set_dither_option(struct dc_stream_state *stream,
699 enum dc_dither_option option)
700 {
701 struct bit_depth_reduction_params params;
702 struct dc_link *link = stream->link;
703 struct pipe_ctx *pipes = NULL;
704 int i;
705
706 for (i = 0; i < MAX_PIPES; i++) {
707 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
708 stream) {
709 pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
710 break;
711 }
712 }
713
714 if (!pipes)
715 return;
716 if (option > DITHER_OPTION_MAX)
717 return;
718
719 stream->dither_option = option;
720
721 memset(¶ms, 0, sizeof(params));
722 resource_build_bit_depth_reduction_params(stream, ¶ms);
723 stream->bit_depth_params = params;
724
725 if (pipes->plane_res.xfm &&
726 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
727 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
728 pipes->plane_res.xfm,
729 pipes->plane_res.scl_data.lb_params.depth,
730 &stream->bit_depth_params);
731 }
732
733 pipes->stream_res.opp->funcs->
734 opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms);
735 }
736
dc_stream_set_gamut_remap(struct dc * dc,const struct dc_stream_state * stream)737 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
738 {
739 int i;
740 bool ret = false;
741 struct pipe_ctx *pipes;
742
743 for (i = 0; i < MAX_PIPES; i++) {
744 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
745 pipes = &dc->current_state->res_ctx.pipe_ctx[i];
746 dc->hwss.program_gamut_remap(pipes);
747 ret = true;
748 }
749 }
750
751 return ret;
752 }
753
dc_stream_program_csc_matrix(struct dc * dc,struct dc_stream_state * stream)754 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
755 {
756 int i;
757 bool ret = false;
758 struct pipe_ctx *pipes;
759
760 for (i = 0; i < MAX_PIPES; i++) {
761 if (dc->current_state->res_ctx.pipe_ctx[i].stream
762 == stream) {
763
764 pipes = &dc->current_state->res_ctx.pipe_ctx[i];
765 dc->hwss.program_output_csc(dc,
766 pipes,
767 stream->output_color_space,
768 stream->csc_color_matrix.matrix,
769 pipes->stream_res.opp->inst);
770 ret = true;
771 }
772 }
773
774 return ret;
775 }
776
dc_stream_set_static_screen_params(struct dc * dc,struct dc_stream_state ** streams,int num_streams,const struct dc_static_screen_params * params)777 void dc_stream_set_static_screen_params(struct dc *dc,
778 struct dc_stream_state **streams,
779 int num_streams,
780 const struct dc_static_screen_params *params)
781 {
782 int i, j;
783 struct pipe_ctx *pipes_affected[MAX_PIPES];
784 int num_pipes_affected = 0;
785
786 for (i = 0; i < num_streams; i++) {
787 struct dc_stream_state *stream = streams[i];
788
789 for (j = 0; j < MAX_PIPES; j++) {
790 if (dc->current_state->res_ctx.pipe_ctx[j].stream
791 == stream) {
792 pipes_affected[num_pipes_affected++] =
793 &dc->current_state->res_ctx.pipe_ctx[j];
794 }
795 }
796 }
797
798 dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
799 }
800
dc_destruct(struct dc * dc)801 static void dc_destruct(struct dc *dc)
802 {
803 // reset link encoder assignment table on destruct
804 if (dc->res_pool && dc->res_pool->funcs->link_encs_assign)
805 link_enc_cfg_init(dc, dc->current_state);
806
807 if (dc->current_state) {
808 dc_release_state(dc->current_state);
809 dc->current_state = NULL;
810 }
811
812 destroy_links(dc);
813
814 destroy_link_encoders(dc);
815
816 if (dc->clk_mgr) {
817 dc_destroy_clk_mgr(dc->clk_mgr);
818 dc->clk_mgr = NULL;
819 }
820
821 dc_destroy_resource_pool(dc);
822
823 if (dc->link_srv)
824 link_destroy_link_service(&dc->link_srv);
825
826 if (dc->ctx->gpio_service)
827 dal_gpio_service_destroy(&dc->ctx->gpio_service);
828
829 if (dc->ctx->created_bios)
830 dal_bios_parser_destroy(&dc->ctx->dc_bios);
831
832 dc_perf_trace_destroy(&dc->ctx->perf_trace);
833
834 kfree(dc->ctx);
835 dc->ctx = NULL;
836
837 kfree(dc->bw_vbios);
838 dc->bw_vbios = NULL;
839
840 kfree(dc->bw_dceip);
841 dc->bw_dceip = NULL;
842
843 kfree(dc->dcn_soc);
844 dc->dcn_soc = NULL;
845
846 kfree(dc->dcn_ip);
847 dc->dcn_ip = NULL;
848
849 kfree(dc->vm_helper);
850 dc->vm_helper = NULL;
851
852 }
853
dc_construct_ctx(struct dc * dc,const struct dc_init_data * init_params)854 static bool dc_construct_ctx(struct dc *dc,
855 const struct dc_init_data *init_params)
856 {
857 struct dc_context *dc_ctx;
858
859 dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
860 if (!dc_ctx)
861 return false;
862
863 dc_ctx->cgs_device = init_params->cgs_device;
864 dc_ctx->driver_context = init_params->driver;
865 dc_ctx->dc = dc;
866 dc_ctx->asic_id = init_params->asic_id;
867 dc_ctx->dc_sink_id_count = 0;
868 dc_ctx->dc_stream_id_count = 0;
869 dc_ctx->dce_environment = init_params->dce_environment;
870 dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets;
871 dc_ctx->nbio_reg_offsets = init_params->nbio_reg_offsets;
872
873 /* Create logger */
874
875 dc_ctx->dce_version = resource_parse_asic_id(init_params->asic_id);
876
877 dc_ctx->perf_trace = dc_perf_trace_create();
878 if (!dc_ctx->perf_trace) {
879 kfree(dc_ctx);
880 ASSERT_CRITICAL(false);
881 return false;
882 }
883
884 dc->ctx = dc_ctx;
885
886 dc->link_srv = link_create_link_service();
887 if (!dc->link_srv)
888 return false;
889
890 return true;
891 }
892
dc_construct(struct dc * dc,const struct dc_init_data * init_params)893 static bool dc_construct(struct dc *dc,
894 const struct dc_init_data *init_params)
895 {
896 struct dc_context *dc_ctx;
897 struct bw_calcs_dceip *dc_dceip;
898 struct bw_calcs_vbios *dc_vbios;
899 struct dcn_soc_bounding_box *dcn_soc;
900 struct dcn_ip_params *dcn_ip;
901
902 dc->config = init_params->flags;
903
904 // Allocate memory for the vm_helper
905 dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
906 if (!dc->vm_helper) {
907 dm_error("%s: failed to create dc->vm_helper\n", __func__);
908 goto fail;
909 }
910
911 memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
912
913 dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
914 if (!dc_dceip) {
915 dm_error("%s: failed to create dceip\n", __func__);
916 goto fail;
917 }
918
919 dc->bw_dceip = dc_dceip;
920
921 dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
922 if (!dc_vbios) {
923 dm_error("%s: failed to create vbios\n", __func__);
924 goto fail;
925 }
926
927 dc->bw_vbios = dc_vbios;
928 dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
929 if (!dcn_soc) {
930 dm_error("%s: failed to create dcn_soc\n", __func__);
931 goto fail;
932 }
933
934 dc->dcn_soc = dcn_soc;
935
936 dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
937 if (!dcn_ip) {
938 dm_error("%s: failed to create dcn_ip\n", __func__);
939 goto fail;
940 }
941
942 dc->dcn_ip = dcn_ip;
943
944 if (!dc_construct_ctx(dc, init_params)) {
945 dm_error("%s: failed to create ctx\n", __func__);
946 goto fail;
947 }
948
949 dc_ctx = dc->ctx;
950
951 /* Resource should construct all asic specific resources.
952 * This should be the only place where we need to parse the asic id
953 */
954 if (init_params->vbios_override)
955 dc_ctx->dc_bios = init_params->vbios_override;
956 else {
957 /* Create BIOS parser */
958 struct bp_init_data bp_init_data;
959
960 bp_init_data.ctx = dc_ctx;
961 bp_init_data.bios = init_params->asic_id.atombios_base_address;
962
963 dc_ctx->dc_bios = dal_bios_parser_create(
964 &bp_init_data, dc_ctx->dce_version);
965
966 if (!dc_ctx->dc_bios) {
967 ASSERT_CRITICAL(false);
968 goto fail;
969 }
970
971 dc_ctx->created_bios = true;
972 }
973
974 dc->vendor_signature = init_params->vendor_signature;
975
976 /* Create GPIO service */
977 dc_ctx->gpio_service = dal_gpio_service_create(
978 dc_ctx->dce_version,
979 dc_ctx->dce_environment,
980 dc_ctx);
981
982 if (!dc_ctx->gpio_service) {
983 ASSERT_CRITICAL(false);
984 goto fail;
985 }
986
987 dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
988 if (!dc->res_pool)
989 goto fail;
990
991 /* set i2c speed if not done by the respective dcnxxx__resource.c */
992 if (dc->caps.i2c_speed_in_khz_hdcp == 0)
993 dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz;
994 if (dc->caps.max_optimizable_video_width == 0)
995 dc->caps.max_optimizable_video_width = 5120;
996 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
997 if (!dc->clk_mgr)
998 goto fail;
999 #ifdef CONFIG_DRM_AMD_DC_FP
1000 dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
1001
1002 if (dc->res_pool->funcs->update_bw_bounding_box) {
1003 DC_FP_START();
1004 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
1005 DC_FP_END();
1006 }
1007 #endif
1008
1009 /* Creation of current_state must occur after dc->dml
1010 * is initialized in dc_create_resource_pool because
1011 * on creation it copies the contents of dc->dml
1012 */
1013
1014 dc->current_state = dc_create_state(dc);
1015
1016 if (!dc->current_state) {
1017 dm_error("%s: failed to create validate ctx\n", __func__);
1018 goto fail;
1019 }
1020
1021 if (!create_links(dc, init_params->num_virtual_links))
1022 goto fail;
1023
1024 /* Create additional DIG link encoder objects if fewer than the platform
1025 * supports were created during link construction.
1026 */
1027 if (!create_link_encoders(dc))
1028 goto fail;
1029
1030 dc_resource_state_construct(dc, dc->current_state);
1031
1032 return true;
1033
1034 fail:
1035 return false;
1036 }
1037
disable_all_writeback_pipes_for_stream(const struct dc * dc,struct dc_stream_state * stream,struct dc_state * context)1038 static void disable_all_writeback_pipes_for_stream(
1039 const struct dc *dc,
1040 struct dc_stream_state *stream,
1041 struct dc_state *context)
1042 {
1043 int i;
1044
1045 for (i = 0; i < stream->num_wb_info; i++)
1046 stream->writeback_info[i].wb_enabled = false;
1047 }
1048
apply_ctx_interdependent_lock(struct dc * dc,struct dc_state * context,struct dc_stream_state * stream,bool lock)1049 static void apply_ctx_interdependent_lock(struct dc *dc,
1050 struct dc_state *context,
1051 struct dc_stream_state *stream,
1052 bool lock)
1053 {
1054 int i;
1055
1056 /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
1057 if (dc->hwss.interdependent_update_lock)
1058 dc->hwss.interdependent_update_lock(dc, context, lock);
1059 else {
1060 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1061 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1062 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1063
1064 // Copied conditions that were previously in dce110_apply_ctx_for_surface
1065 if (stream == pipe_ctx->stream) {
1066 if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) &&
1067 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
1068 dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
1069 }
1070 }
1071 }
1072 }
1073
dc_update_viusal_confirm_color(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)1074 static void dc_update_viusal_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1075 {
1076 if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
1077 memset(&pipe_ctx->visual_confirm_color, 0, sizeof(struct tg_color));
1078
1079 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
1080 get_hdr_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1081 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1082 get_surface_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1083 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
1084 get_surface_tile_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1085 else {
1086 if (dc->ctx->dce_version < DCN_VERSION_2_0)
1087 color_space_to_black_color(
1088 dc, pipe_ctx->stream->output_color_space, &(pipe_ctx->visual_confirm_color));
1089 }
1090 if (dc->ctx->dce_version >= DCN_VERSION_2_0) {
1091 if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
1092 get_mpctree_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1093 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)
1094 get_subvp_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));
1095 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH)
1096 get_mclk_switch_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));
1097 }
1098 }
1099 }
1100
disable_dangling_plane(struct dc * dc,struct dc_state * context)1101 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
1102 {
1103 int i, j;
1104 struct dc_state *dangling_context = dc_create_state(dc);
1105 struct dc_state *current_ctx;
1106 struct pipe_ctx *pipe;
1107 struct timing_generator *tg;
1108
1109 if (dangling_context == NULL)
1110 return;
1111
1112 dc_resource_state_copy_construct(dc->current_state, dangling_context);
1113
1114 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1115 struct dc_stream_state *old_stream =
1116 dc->current_state->res_ctx.pipe_ctx[i].stream;
1117 bool should_disable = true;
1118 bool pipe_split_change = false;
1119
1120 if ((context->res_ctx.pipe_ctx[i].top_pipe) &&
1121 (dc->current_state->res_ctx.pipe_ctx[i].top_pipe))
1122 pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe->pipe_idx !=
1123 dc->current_state->res_ctx.pipe_ctx[i].top_pipe->pipe_idx;
1124 else
1125 pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe !=
1126 dc->current_state->res_ctx.pipe_ctx[i].top_pipe;
1127
1128 for (j = 0; j < context->stream_count; j++) {
1129 if (old_stream == context->streams[j]) {
1130 should_disable = false;
1131 break;
1132 }
1133 }
1134 if (!should_disable && pipe_split_change &&
1135 dc->current_state->stream_count != context->stream_count)
1136 should_disable = true;
1137
1138 if (old_stream && !dc->current_state->res_ctx.pipe_ctx[i].top_pipe &&
1139 !dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe) {
1140 struct pipe_ctx *old_pipe, *new_pipe;
1141
1142 old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1143 new_pipe = &context->res_ctx.pipe_ctx[i];
1144
1145 if (old_pipe->plane_state && !new_pipe->plane_state)
1146 should_disable = true;
1147 }
1148
1149 if (should_disable && old_stream) {
1150 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1151 tg = pipe->stream_res.tg;
1152 /* When disabling plane for a phantom pipe, we must turn on the
1153 * phantom OTG so the disable programming gets the double buffer
1154 * update. Otherwise the pipe will be left in a partially disabled
1155 * state that can result in underflow or hang when enabling it
1156 * again for different use.
1157 */
1158 if (old_stream->mall_stream_config.type == SUBVP_PHANTOM) {
1159 if (tg->funcs->enable_crtc) {
1160 int main_pipe_width, main_pipe_height;
1161
1162 main_pipe_width = old_stream->mall_stream_config.paired_stream->dst.width;
1163 main_pipe_height = old_stream->mall_stream_config.paired_stream->dst.height;
1164 if (dc->hwss.blank_phantom)
1165 dc->hwss.blank_phantom(dc, tg, main_pipe_width, main_pipe_height);
1166 tg->funcs->enable_crtc(tg);
1167 }
1168 }
1169 dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
1170 disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
1171
1172 if (pipe->stream && pipe->plane_state)
1173 dc_update_viusal_confirm_color(dc, context, pipe);
1174
1175 if (dc->hwss.apply_ctx_for_surface) {
1176 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
1177 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
1178 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
1179 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
1180 }
1181 if (dc->hwss.program_front_end_for_ctx) {
1182 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
1183 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
1184 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
1185 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
1186 }
1187 /* We need to put the phantom OTG back into it's default (disabled) state or we
1188 * can get corruption when transition from one SubVP config to a different one.
1189 * The OTG is set to disable on falling edge of VUPDATE so the plane disable
1190 * will still get it's double buffer update.
1191 */
1192 if (old_stream->mall_stream_config.type == SUBVP_PHANTOM) {
1193 if (tg->funcs->disable_phantom_crtc)
1194 tg->funcs->disable_phantom_crtc(tg);
1195 }
1196 }
1197 }
1198
1199 current_ctx = dc->current_state;
1200 dc->current_state = dangling_context;
1201 dc_release_state(current_ctx);
1202 }
1203
disable_vbios_mode_if_required(struct dc * dc,struct dc_state * context)1204 static void disable_vbios_mode_if_required(
1205 struct dc *dc,
1206 struct dc_state *context)
1207 {
1208 unsigned int i, j;
1209
1210 /* check if timing_changed, disable stream*/
1211 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1212 struct dc_stream_state *stream = NULL;
1213 struct dc_link *link = NULL;
1214 struct pipe_ctx *pipe = NULL;
1215
1216 pipe = &context->res_ctx.pipe_ctx[i];
1217 stream = pipe->stream;
1218 if (stream == NULL)
1219 continue;
1220
1221 if (stream->apply_seamless_boot_optimization)
1222 continue;
1223
1224 // only looking for first odm pipe
1225 if (pipe->prev_odm_pipe)
1226 continue;
1227
1228 if (stream->link->local_sink &&
1229 stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1230 link = stream->link;
1231 }
1232
1233 if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
1234 unsigned int enc_inst, tg_inst = 0;
1235 unsigned int pix_clk_100hz;
1236
1237 enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1238 if (enc_inst != ENGINE_ID_UNKNOWN) {
1239 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
1240 if (dc->res_pool->stream_enc[j]->id == enc_inst) {
1241 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
1242 dc->res_pool->stream_enc[j]);
1243 break;
1244 }
1245 }
1246
1247 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1248 dc->res_pool->dp_clock_source,
1249 tg_inst, &pix_clk_100hz);
1250
1251 if (link->link_status.link_active) {
1252 uint32_t requested_pix_clk_100hz =
1253 pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
1254
1255 if (pix_clk_100hz != requested_pix_clk_100hz) {
1256 dc->link_srv->set_dpms_off(pipe);
1257 pipe->stream->dpms_off = false;
1258 }
1259 }
1260 }
1261 }
1262 }
1263 }
1264
wait_for_no_pipes_pending(struct dc * dc,struct dc_state * context)1265 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
1266 {
1267 int i;
1268 PERF_TRACE();
1269 for (i = 0; i < MAX_PIPES; i++) {
1270 int count = 0;
1271 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1272
1273 if (!pipe->plane_state || pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)
1274 continue;
1275
1276 /* Timeout 100 ms */
1277 while (count < 100000) {
1278 /* Must set to false to start with, due to OR in update function */
1279 pipe->plane_state->status.is_flip_pending = false;
1280 dc->hwss.update_pending_status(pipe);
1281 if (!pipe->plane_state->status.is_flip_pending)
1282 break;
1283 udelay(1);
1284 count++;
1285 }
1286 ASSERT(!pipe->plane_state->status.is_flip_pending);
1287 }
1288 PERF_TRACE();
1289 }
1290
1291 /* Public functions */
1292
dc_create(const struct dc_init_data * init_params)1293 struct dc *dc_create(const struct dc_init_data *init_params)
1294 {
1295 struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
1296 unsigned int full_pipe_count;
1297
1298 if (!dc)
1299 return NULL;
1300
1301 if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
1302 dc->caps.linear_pitch_alignment = 64;
1303 if (!dc_construct_ctx(dc, init_params))
1304 goto destruct_dc;
1305 } else {
1306 if (!dc_construct(dc, init_params))
1307 goto destruct_dc;
1308
1309 full_pipe_count = dc->res_pool->pipe_count;
1310 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
1311 full_pipe_count--;
1312 dc->caps.max_streams = min(
1313 full_pipe_count,
1314 dc->res_pool->stream_enc_count);
1315
1316 dc->caps.max_links = dc->link_count;
1317 dc->caps.max_audios = dc->res_pool->audio_count;
1318 dc->caps.linear_pitch_alignment = 64;
1319
1320 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
1321
1322 dc->caps.max_otg_num = dc->res_pool->res_cap->num_timing_generator;
1323
1324 if (dc->res_pool->dmcu != NULL)
1325 dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
1326 }
1327
1328 dc->dcn_reg_offsets = init_params->dcn_reg_offsets;
1329 dc->nbio_reg_offsets = init_params->nbio_reg_offsets;
1330
1331 /* Populate versioning information */
1332 dc->versions.dc_ver = DC_VER;
1333
1334 dc->build_id = DC_BUILD_ID;
1335
1336 DC_LOG_DC("Display Core initialized\n");
1337
1338
1339
1340 return dc;
1341
1342 destruct_dc:
1343 dc_destruct(dc);
1344 kfree(dc);
1345 return NULL;
1346 }
1347
detect_edp_presence(struct dc * dc)1348 static void detect_edp_presence(struct dc *dc)
1349 {
1350 struct dc_link *edp_links[MAX_NUM_EDP];
1351 struct dc_link *edp_link = NULL;
1352 enum dc_connection_type type;
1353 int i;
1354 int edp_num;
1355
1356 dc_get_edp_links(dc, edp_links, &edp_num);
1357 if (!edp_num)
1358 return;
1359
1360 for (i = 0; i < edp_num; i++) {
1361 edp_link = edp_links[i];
1362 if (dc->config.edp_not_connected) {
1363 edp_link->edp_sink_present = false;
1364 } else {
1365 dc_link_detect_connection_type(edp_link, &type);
1366 edp_link->edp_sink_present = (type != dc_connection_none);
1367 }
1368 }
1369 }
1370
dc_hardware_init(struct dc * dc)1371 void dc_hardware_init(struct dc *dc)
1372 {
1373
1374 detect_edp_presence(dc);
1375 if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
1376 dc->hwss.init_hw(dc);
1377 }
1378
dc_init_callbacks(struct dc * dc,const struct dc_callback_init * init_params)1379 void dc_init_callbacks(struct dc *dc,
1380 const struct dc_callback_init *init_params)
1381 {
1382 dc->ctx->cp_psp = init_params->cp_psp;
1383 }
1384
dc_deinit_callbacks(struct dc * dc)1385 void dc_deinit_callbacks(struct dc *dc)
1386 {
1387 memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
1388 }
1389
dc_destroy(struct dc ** dc)1390 void dc_destroy(struct dc **dc)
1391 {
1392 dc_destruct(*dc);
1393 kfree(*dc);
1394 *dc = NULL;
1395 }
1396
enable_timing_multisync(struct dc * dc,struct dc_state * ctx)1397 static void enable_timing_multisync(
1398 struct dc *dc,
1399 struct dc_state *ctx)
1400 {
1401 int i, multisync_count = 0;
1402 int pipe_count = dc->res_pool->pipe_count;
1403 struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
1404
1405 for (i = 0; i < pipe_count; i++) {
1406 if (!ctx->res_ctx.pipe_ctx[i].stream ||
1407 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
1408 continue;
1409 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
1410 continue;
1411 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
1412 multisync_count++;
1413 }
1414
1415 if (multisync_count > 0) {
1416 dc->hwss.enable_per_frame_crtc_position_reset(
1417 dc, multisync_count, multisync_pipes);
1418 }
1419 }
1420
program_timing_sync(struct dc * dc,struct dc_state * ctx)1421 static void program_timing_sync(
1422 struct dc *dc,
1423 struct dc_state *ctx)
1424 {
1425 int i, j, k;
1426 int group_index = 0;
1427 int num_group = 0;
1428 int pipe_count = dc->res_pool->pipe_count;
1429 struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
1430
1431 for (i = 0; i < pipe_count; i++) {
1432 if (!ctx->res_ctx.pipe_ctx[i].stream
1433 || ctx->res_ctx.pipe_ctx[i].top_pipe
1434 || ctx->res_ctx.pipe_ctx[i].prev_odm_pipe)
1435 continue;
1436
1437 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
1438 }
1439
1440 for (i = 0; i < pipe_count; i++) {
1441 int group_size = 1;
1442 enum timing_synchronization_type sync_type = NOT_SYNCHRONIZABLE;
1443 struct pipe_ctx *pipe_set[MAX_PIPES];
1444
1445 if (!unsynced_pipes[i])
1446 continue;
1447
1448 pipe_set[0] = unsynced_pipes[i];
1449 unsynced_pipes[i] = NULL;
1450
1451 /* Add tg to the set, search rest of the tg's for ones with
1452 * same timing, add all tgs with same timing to the group
1453 */
1454 for (j = i + 1; j < pipe_count; j++) {
1455 if (!unsynced_pipes[j])
1456 continue;
1457 if (sync_type != TIMING_SYNCHRONIZABLE &&
1458 dc->hwss.enable_vblanks_synchronization &&
1459 unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks &&
1460 resource_are_vblanks_synchronizable(
1461 unsynced_pipes[j]->stream,
1462 pipe_set[0]->stream)) {
1463 sync_type = VBLANK_SYNCHRONIZABLE;
1464 pipe_set[group_size] = unsynced_pipes[j];
1465 unsynced_pipes[j] = NULL;
1466 group_size++;
1467 } else
1468 if (sync_type != VBLANK_SYNCHRONIZABLE &&
1469 resource_are_streams_timing_synchronizable(
1470 unsynced_pipes[j]->stream,
1471 pipe_set[0]->stream)) {
1472 sync_type = TIMING_SYNCHRONIZABLE;
1473 pipe_set[group_size] = unsynced_pipes[j];
1474 unsynced_pipes[j] = NULL;
1475 group_size++;
1476 }
1477 }
1478
1479 /* set first unblanked pipe as master */
1480 for (j = 0; j < group_size; j++) {
1481 bool is_blanked;
1482
1483 if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1484 is_blanked =
1485 pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1486 else
1487 is_blanked =
1488 pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1489 if (!is_blanked) {
1490 if (j == 0)
1491 break;
1492
1493 swap(pipe_set[0], pipe_set[j]);
1494 break;
1495 }
1496 }
1497
1498 for (k = 0; k < group_size; k++) {
1499 struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
1500
1501 status->timing_sync_info.group_id = num_group;
1502 status->timing_sync_info.group_size = group_size;
1503 if (k == 0)
1504 status->timing_sync_info.master = true;
1505 else
1506 status->timing_sync_info.master = false;
1507
1508 }
1509
1510 /* remove any other pipes that are already been synced */
1511 if (dc->config.use_pipe_ctx_sync_logic) {
1512 /* check pipe's syncd to decide which pipe to be removed */
1513 for (j = 1; j < group_size; j++) {
1514 if (pipe_set[j]->pipe_idx_syncd == pipe_set[0]->pipe_idx_syncd) {
1515 group_size--;
1516 pipe_set[j] = pipe_set[group_size];
1517 j--;
1518 } else
1519 /* link slave pipe's syncd with master pipe */
1520 pipe_set[j]->pipe_idx_syncd = pipe_set[0]->pipe_idx_syncd;
1521 }
1522 } else {
1523 for (j = j + 1; j < group_size; j++) {
1524 bool is_blanked;
1525
1526 if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1527 is_blanked =
1528 pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1529 else
1530 is_blanked =
1531 pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1532 if (!is_blanked) {
1533 group_size--;
1534 pipe_set[j] = pipe_set[group_size];
1535 j--;
1536 }
1537 }
1538 }
1539
1540 if (group_size > 1) {
1541 if (sync_type == TIMING_SYNCHRONIZABLE) {
1542 dc->hwss.enable_timing_synchronization(
1543 dc, group_index, group_size, pipe_set);
1544 } else
1545 if (sync_type == VBLANK_SYNCHRONIZABLE) {
1546 dc->hwss.enable_vblanks_synchronization(
1547 dc, group_index, group_size, pipe_set);
1548 }
1549 group_index++;
1550 }
1551 num_group++;
1552 }
1553 }
1554
streams_changed(struct dc * dc,struct dc_stream_state * streams[],uint8_t stream_count)1555 static bool streams_changed(struct dc *dc,
1556 struct dc_stream_state *streams[],
1557 uint8_t stream_count)
1558 {
1559 uint8_t i;
1560
1561 if (stream_count != dc->current_state->stream_count)
1562 return true;
1563
1564 for (i = 0; i < dc->current_state->stream_count; i++) {
1565 if (dc->current_state->streams[i] != streams[i])
1566 return true;
1567 if (!streams[i]->link->link_state_valid)
1568 return true;
1569 }
1570
1571 return false;
1572 }
1573
dc_validate_boot_timing(const struct dc * dc,const struct dc_sink * sink,struct dc_crtc_timing * crtc_timing)1574 bool dc_validate_boot_timing(const struct dc *dc,
1575 const struct dc_sink *sink,
1576 struct dc_crtc_timing *crtc_timing)
1577 {
1578 struct timing_generator *tg;
1579 struct stream_encoder *se = NULL;
1580
1581 struct dc_crtc_timing hw_crtc_timing = {0};
1582
1583 struct dc_link *link = sink->link;
1584 unsigned int i, enc_inst, tg_inst = 0;
1585
1586 /* Support seamless boot on EDP displays only */
1587 if (sink->sink_signal != SIGNAL_TYPE_EDP) {
1588 return false;
1589 }
1590
1591 if (dc->debug.force_odm_combine)
1592 return false;
1593
1594 /* Check for enabled DIG to identify enabled display */
1595 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1596 return false;
1597
1598 enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1599
1600 if (enc_inst == ENGINE_ID_UNKNOWN)
1601 return false;
1602
1603 for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1604 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1605
1606 se = dc->res_pool->stream_enc[i];
1607
1608 tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1609 dc->res_pool->stream_enc[i]);
1610 break;
1611 }
1612 }
1613
1614 // tg_inst not found
1615 if (i == dc->res_pool->stream_enc_count)
1616 return false;
1617
1618 if (tg_inst >= dc->res_pool->timing_generator_count)
1619 return false;
1620
1621 if (tg_inst != link->link_enc->preferred_engine)
1622 return false;
1623
1624 tg = dc->res_pool->timing_generators[tg_inst];
1625
1626 if (!tg->funcs->get_hw_timing)
1627 return false;
1628
1629 if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1630 return false;
1631
1632 if (crtc_timing->h_total != hw_crtc_timing.h_total)
1633 return false;
1634
1635 if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1636 return false;
1637
1638 if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1639 return false;
1640
1641 if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1642 return false;
1643
1644 if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1645 return false;
1646
1647 if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1648 return false;
1649
1650 if (crtc_timing->v_total != hw_crtc_timing.v_total)
1651 return false;
1652
1653 if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1654 return false;
1655
1656 if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1657 return false;
1658
1659 if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1660 return false;
1661
1662 if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1663 return false;
1664
1665 if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1666 return false;
1667
1668 /* block DSC for now, as VBIOS does not currently support DSC timings */
1669 if (crtc_timing->flags.DSC)
1670 return false;
1671
1672 if (dc_is_dp_signal(link->connector_signal)) {
1673 unsigned int pix_clk_100hz;
1674 uint32_t numOdmPipes = 1;
1675 uint32_t id_src[4] = {0};
1676
1677 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1678 dc->res_pool->dp_clock_source,
1679 tg_inst, &pix_clk_100hz);
1680
1681 if (tg->funcs->get_optc_source)
1682 tg->funcs->get_optc_source(tg,
1683 &numOdmPipes, &id_src[0], &id_src[1]);
1684
1685 if (numOdmPipes == 2)
1686 pix_clk_100hz *= 2;
1687 if (numOdmPipes == 4)
1688 pix_clk_100hz *= 4;
1689
1690 // Note: In rare cases, HW pixclk may differ from crtc's pixclk
1691 // slightly due to rounding issues in 10 kHz units.
1692 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1693 return false;
1694
1695 if (!se || !se->funcs->dp_get_pixel_format)
1696 return false;
1697
1698 if (!se->funcs->dp_get_pixel_format(
1699 se,
1700 &hw_crtc_timing.pixel_encoding,
1701 &hw_crtc_timing.display_color_depth))
1702 return false;
1703
1704 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1705 return false;
1706
1707 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1708 return false;
1709 }
1710
1711 if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {
1712 return false;
1713 }
1714
1715 if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)
1716 return false;
1717
1718 if (dc->link_srv->edp_is_ilr_optimization_required(link, crtc_timing)) {
1719 DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n");
1720 return false;
1721 }
1722
1723 return true;
1724 }
1725
should_update_pipe_for_stream(struct dc_state * context,struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream)1726 static inline bool should_update_pipe_for_stream(
1727 struct dc_state *context,
1728 struct pipe_ctx *pipe_ctx,
1729 struct dc_stream_state *stream)
1730 {
1731 return (pipe_ctx->stream && pipe_ctx->stream == stream);
1732 }
1733
should_update_pipe_for_plane(struct dc_state * context,struct pipe_ctx * pipe_ctx,struct dc_plane_state * plane_state)1734 static inline bool should_update_pipe_for_plane(
1735 struct dc_state *context,
1736 struct pipe_ctx *pipe_ctx,
1737 struct dc_plane_state *plane_state)
1738 {
1739 return (pipe_ctx->plane_state == plane_state);
1740 }
1741
dc_enable_stereo(struct dc * dc,struct dc_state * context,struct dc_stream_state * streams[],uint8_t stream_count)1742 void dc_enable_stereo(
1743 struct dc *dc,
1744 struct dc_state *context,
1745 struct dc_stream_state *streams[],
1746 uint8_t stream_count)
1747 {
1748 int i, j;
1749 struct pipe_ctx *pipe;
1750
1751 for (i = 0; i < MAX_PIPES; i++) {
1752 if (context != NULL) {
1753 pipe = &context->res_ctx.pipe_ctx[i];
1754 } else {
1755 context = dc->current_state;
1756 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1757 }
1758
1759 for (j = 0; pipe && j < stream_count; j++) {
1760 if (should_update_pipe_for_stream(context, pipe, streams[j]) &&
1761 dc->hwss.setup_stereo)
1762 dc->hwss.setup_stereo(pipe, dc);
1763 }
1764 }
1765 }
1766
dc_trigger_sync(struct dc * dc,struct dc_state * context)1767 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
1768 {
1769 if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1770 enable_timing_multisync(dc, context);
1771 program_timing_sync(dc, context);
1772 }
1773 }
1774
get_stream_mask(struct dc * dc,struct dc_state * context)1775 static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
1776 {
1777 int i;
1778 unsigned int stream_mask = 0;
1779
1780 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1781 if (context->res_ctx.pipe_ctx[i].stream)
1782 stream_mask |= 1 << i;
1783 }
1784
1785 return stream_mask;
1786 }
1787
dc_z10_restore(const struct dc * dc)1788 void dc_z10_restore(const struct dc *dc)
1789 {
1790 if (dc->hwss.z10_restore)
1791 dc->hwss.z10_restore(dc);
1792 }
1793
dc_z10_save_init(struct dc * dc)1794 void dc_z10_save_init(struct dc *dc)
1795 {
1796 if (dc->hwss.z10_save_init)
1797 dc->hwss.z10_save_init(dc);
1798 }
1799
1800 /**
1801 * dc_commit_state_no_check - Apply context to the hardware
1802 *
1803 * @dc: DC object with the current status to be updated
1804 * @context: New state that will become the current status at the end of this function
1805 *
1806 * Applies given context to the hardware and copy it into current context.
1807 * It's up to the user to release the src context afterwards.
1808 *
1809 * Return: an enum dc_status result code for the operation
1810 */
dc_commit_state_no_check(struct dc * dc,struct dc_state * context)1811 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1812 {
1813 struct dc_bios *dcb = dc->ctx->dc_bios;
1814 enum dc_status result = DC_ERROR_UNEXPECTED;
1815 struct pipe_ctx *pipe;
1816 int i, k, l;
1817 struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1818 struct dc_state *old_state;
1819 bool subvp_prev_use = false;
1820
1821 dc_z10_restore(dc);
1822 dc_allow_idle_optimizations(dc, false);
1823
1824 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1825 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1826
1827 /* Check old context for SubVP */
1828 subvp_prev_use |= (old_pipe->stream && old_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM);
1829 if (subvp_prev_use)
1830 break;
1831 }
1832
1833 for (i = 0; i < context->stream_count; i++)
1834 dc_streams[i] = context->streams[i];
1835
1836 if (!dcb->funcs->is_accelerated_mode(dcb)) {
1837 disable_vbios_mode_if_required(dc, context);
1838 dc->hwss.enable_accelerated_mode(dc, context);
1839 }
1840
1841 if (context->stream_count > get_seamless_boot_stream_count(context) ||
1842 context->stream_count == 0)
1843 dc->hwss.prepare_bandwidth(dc, context);
1844
1845 /* When SubVP is active, all HW programming must be done while
1846 * SubVP lock is acquired
1847 */
1848 if (dc->hwss.subvp_pipe_control_lock)
1849 dc->hwss.subvp_pipe_control_lock(dc, context, true, true, NULL, subvp_prev_use);
1850
1851 if (dc->hwss.update_dsc_pg)
1852 dc->hwss.update_dsc_pg(dc, context, false);
1853
1854 disable_dangling_plane(dc, context);
1855 /* re-program planes for existing stream, in case we need to
1856 * free up plane resource for later use
1857 */
1858 if (dc->hwss.apply_ctx_for_surface) {
1859 for (i = 0; i < context->stream_count; i++) {
1860 if (context->streams[i]->mode_changed)
1861 continue;
1862 apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1863 dc->hwss.apply_ctx_for_surface(
1864 dc, context->streams[i],
1865 context->stream_status[i].plane_count,
1866 context); /* use new pipe config in new context */
1867 apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1868 dc->hwss.post_unlock_program_front_end(dc, context);
1869 }
1870 }
1871
1872 /* Program hardware */
1873 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1874 pipe = &context->res_ctx.pipe_ctx[i];
1875 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1876 }
1877
1878 result = dc->hwss.apply_ctx_to_hw(dc, context);
1879
1880 if (result != DC_OK) {
1881 /* Application of dc_state to hardware stopped. */
1882 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY;
1883 return result;
1884 }
1885
1886 dc_trigger_sync(dc, context);
1887
1888 /* Full update should unconditionally be triggered when dc_commit_state_no_check is called */
1889 for (i = 0; i < context->stream_count; i++) {
1890 uint32_t prev_dsc_changed = context->streams[i]->update_flags.bits.dsc_changed;
1891
1892 context->streams[i]->update_flags.raw = 0xFFFFFFFF;
1893 context->streams[i]->update_flags.bits.dsc_changed = prev_dsc_changed;
1894 }
1895
1896 /* Program all planes within new context*/
1897 if (dc->hwss.program_front_end_for_ctx) {
1898 dc->hwss.interdependent_update_lock(dc, context, true);
1899 dc->hwss.program_front_end_for_ctx(dc, context);
1900 dc->hwss.interdependent_update_lock(dc, context, false);
1901 dc->hwss.post_unlock_program_front_end(dc, context);
1902 }
1903
1904 if (dc->hwss.commit_subvp_config)
1905 dc->hwss.commit_subvp_config(dc, context);
1906 if (dc->hwss.subvp_pipe_control_lock)
1907 dc->hwss.subvp_pipe_control_lock(dc, context, false, true, NULL, subvp_prev_use);
1908
1909 for (i = 0; i < context->stream_count; i++) {
1910 const struct dc_link *link = context->streams[i]->link;
1911
1912 if (!context->streams[i]->mode_changed)
1913 continue;
1914
1915 if (dc->hwss.apply_ctx_for_surface) {
1916 apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1917 dc->hwss.apply_ctx_for_surface(
1918 dc, context->streams[i],
1919 context->stream_status[i].plane_count,
1920 context);
1921 apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1922 dc->hwss.post_unlock_program_front_end(dc, context);
1923 }
1924
1925 /*
1926 * enable stereo
1927 * TODO rework dc_enable_stereo call to work with validation sets?
1928 */
1929 for (k = 0; k < MAX_PIPES; k++) {
1930 pipe = &context->res_ctx.pipe_ctx[k];
1931
1932 for (l = 0 ; pipe && l < context->stream_count; l++) {
1933 if (context->streams[l] &&
1934 context->streams[l] == pipe->stream &&
1935 dc->hwss.setup_stereo)
1936 dc->hwss.setup_stereo(pipe, dc);
1937 }
1938 }
1939
1940 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1941 context->streams[i]->timing.h_addressable,
1942 context->streams[i]->timing.v_addressable,
1943 context->streams[i]->timing.h_total,
1944 context->streams[i]->timing.v_total,
1945 context->streams[i]->timing.pix_clk_100hz / 10);
1946 }
1947
1948 dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1949
1950 if (context->stream_count > get_seamless_boot_stream_count(context) ||
1951 context->stream_count == 0) {
1952 /* Must wait for no flips to be pending before doing optimize bw */
1953 wait_for_no_pipes_pending(dc, context);
1954 /* pplib is notified if disp_num changed */
1955 dc->hwss.optimize_bandwidth(dc, context);
1956 /* Need to do otg sync again as otg could be out of sync due to otg
1957 * workaround applied during clock update
1958 */
1959 dc_trigger_sync(dc, context);
1960 }
1961
1962 if (dc->hwss.update_dsc_pg)
1963 dc->hwss.update_dsc_pg(dc, context, true);
1964
1965 if (dc->ctx->dce_version >= DCE_VERSION_MAX)
1966 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
1967 else
1968 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
1969
1970 context->stream_mask = get_stream_mask(dc, context);
1971
1972 if (context->stream_mask != dc->current_state->stream_mask)
1973 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
1974
1975 for (i = 0; i < context->stream_count; i++)
1976 context->streams[i]->mode_changed = false;
1977
1978 /* Clear update flags that were set earlier to avoid redundant programming */
1979 for (i = 0; i < context->stream_count; i++) {
1980 context->streams[i]->update_flags.raw = 0x0;
1981 }
1982
1983 old_state = dc->current_state;
1984 dc->current_state = context;
1985
1986 dc_release_state(old_state);
1987
1988 dc_retain_state(dc->current_state);
1989
1990 return result;
1991 }
1992
1993 static bool commit_minimal_transition_state(struct dc *dc,
1994 struct dc_state *transition_base_context);
1995
1996 /**
1997 * dc_commit_streams - Commit current stream state
1998 *
1999 * @dc: DC object with the commit state to be configured in the hardware
2000 * @streams: Array with a list of stream state
2001 * @stream_count: Total of streams
2002 *
2003 * Function responsible for commit streams change to the hardware.
2004 *
2005 * Return:
2006 * Return DC_OK if everything work as expected, otherwise, return a dc_status
2007 * code.
2008 */
dc_commit_streams(struct dc * dc,struct dc_stream_state * streams[],uint8_t stream_count)2009 enum dc_status dc_commit_streams(struct dc *dc,
2010 struct dc_stream_state *streams[],
2011 uint8_t stream_count)
2012 {
2013 int i, j;
2014 struct dc_state *context;
2015 enum dc_status res = DC_OK;
2016 struct dc_validation_set set[MAX_STREAMS] = {0};
2017 struct pipe_ctx *pipe;
2018 bool handle_exit_odm2to1 = false;
2019
2020 if (dc->ctx->dce_environment == DCE_ENV_VIRTUAL_HW)
2021 return res;
2022
2023 if (!streams_changed(dc, streams, stream_count))
2024 return res;
2025
2026 DC_LOG_DC("%s: %d streams\n", __func__, stream_count);
2027
2028 for (i = 0; i < stream_count; i++) {
2029 struct dc_stream_state *stream = streams[i];
2030 struct dc_stream_status *status = dc_stream_get_status(stream);
2031
2032 dc_stream_log(dc, stream);
2033
2034 set[i].stream = stream;
2035
2036 if (status) {
2037 set[i].plane_count = status->plane_count;
2038 for (j = 0; j < status->plane_count; j++)
2039 set[i].plane_states[j] = status->plane_states[j];
2040 }
2041 }
2042
2043 /* ODM Combine 2:1 power optimization is only applied for single stream
2044 * scenario, it uses extra pipes than needed to reduce power consumption
2045 * We need to switch off this feature to make room for new streams.
2046 */
2047 if (stream_count > dc->current_state->stream_count &&
2048 dc->current_state->stream_count == 1) {
2049 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2050 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2051 if (pipe->next_odm_pipe)
2052 handle_exit_odm2to1 = true;
2053 }
2054 }
2055
2056 if (handle_exit_odm2to1)
2057 res = commit_minimal_transition_state(dc, dc->current_state);
2058
2059 context = dc_create_state(dc);
2060 if (!context)
2061 goto context_alloc_fail;
2062
2063 dc_resource_state_copy_construct_current(dc, context);
2064
2065 res = dc_validate_with_context(dc, set, stream_count, context, false);
2066 if (res != DC_OK) {
2067 BREAK_TO_DEBUGGER();
2068 goto fail;
2069 }
2070
2071 res = dc_commit_state_no_check(dc, context);
2072
2073 for (i = 0; i < stream_count; i++) {
2074 for (j = 0; j < context->stream_count; j++) {
2075 if (streams[i]->stream_id == context->streams[j]->stream_id)
2076 streams[i]->out.otg_offset = context->stream_status[j].primary_otg_inst;
2077
2078 if (dc_is_embedded_signal(streams[i]->signal)) {
2079 struct dc_stream_status *status = dc_stream_get_status_from_state(context, streams[i]);
2080
2081 if (dc->hwss.is_abm_supported)
2082 status->is_abm_supported = dc->hwss.is_abm_supported(dc, context, streams[i]);
2083 else
2084 status->is_abm_supported = true;
2085 }
2086 }
2087 }
2088
2089 fail:
2090 dc_release_state(context);
2091
2092 context_alloc_fail:
2093
2094 DC_LOG_DC("%s Finished.\n", __func__);
2095
2096 return res;
2097 }
2098
dc_acquire_release_mpc_3dlut(struct dc * dc,bool acquire,struct dc_stream_state * stream,struct dc_3dlut ** lut,struct dc_transfer_func ** shaper)2099 bool dc_acquire_release_mpc_3dlut(
2100 struct dc *dc, bool acquire,
2101 struct dc_stream_state *stream,
2102 struct dc_3dlut **lut,
2103 struct dc_transfer_func **shaper)
2104 {
2105 int pipe_idx;
2106 bool ret = false;
2107 bool found_pipe_idx = false;
2108 const struct resource_pool *pool = dc->res_pool;
2109 struct resource_context *res_ctx = &dc->current_state->res_ctx;
2110 int mpcc_id = 0;
2111
2112 if (pool && res_ctx) {
2113 if (acquire) {
2114 /*find pipe idx for the given stream*/
2115 for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
2116 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
2117 found_pipe_idx = true;
2118 mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
2119 break;
2120 }
2121 }
2122 } else
2123 found_pipe_idx = true;/*for release pipe_idx is not required*/
2124
2125 if (found_pipe_idx) {
2126 if (acquire && pool->funcs->acquire_post_bldn_3dlut)
2127 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
2128 else if (!acquire && pool->funcs->release_post_bldn_3dlut)
2129 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
2130 }
2131 }
2132 return ret;
2133 }
2134
is_flip_pending_in_pipes(struct dc * dc,struct dc_state * context)2135 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
2136 {
2137 int i;
2138 struct pipe_ctx *pipe;
2139
2140 for (i = 0; i < MAX_PIPES; i++) {
2141 pipe = &context->res_ctx.pipe_ctx[i];
2142
2143 // Don't check flip pending on phantom pipes
2144 if (!pipe->plane_state || (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM))
2145 continue;
2146
2147 /* Must set to false to start with, due to OR in update function */
2148 pipe->plane_state->status.is_flip_pending = false;
2149 dc->hwss.update_pending_status(pipe);
2150 if (pipe->plane_state->status.is_flip_pending)
2151 return true;
2152 }
2153 return false;
2154 }
2155
2156 /* Perform updates here which need to be deferred until next vupdate
2157 *
2158 * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered
2159 * but forcing lut memory to shutdown state is immediate. This causes
2160 * single frame corruption as lut gets disabled mid-frame unless shutdown
2161 * is deferred until after entering bypass.
2162 */
process_deferred_updates(struct dc * dc)2163 static void process_deferred_updates(struct dc *dc)
2164 {
2165 int i = 0;
2166
2167 if (dc->debug.enable_mem_low_power.bits.cm) {
2168 ASSERT(dc->dcn_ip->max_num_dpp);
2169 for (i = 0; i < dc->dcn_ip->max_num_dpp; i++)
2170 if (dc->res_pool->dpps[i]->funcs->dpp_deferred_update)
2171 dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);
2172 }
2173 }
2174
dc_post_update_surfaces_to_stream(struct dc * dc)2175 void dc_post_update_surfaces_to_stream(struct dc *dc)
2176 {
2177 int i;
2178 struct dc_state *context = dc->current_state;
2179
2180 if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0)
2181 return;
2182
2183 post_surface_trace(dc);
2184
2185 /*
2186 * Only relevant for DCN behavior where we can guarantee the optimization
2187 * is safe to apply - retain the legacy behavior for DCE.
2188 */
2189
2190 if (dc->ctx->dce_version < DCE_VERSION_MAX)
2191 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
2192 else {
2193 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
2194
2195 if (is_flip_pending_in_pipes(dc, context))
2196 return;
2197
2198 for (i = 0; i < dc->res_pool->pipe_count; i++)
2199 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
2200 context->res_ctx.pipe_ctx[i].plane_state == NULL) {
2201 context->res_ctx.pipe_ctx[i].pipe_idx = i;
2202 dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
2203 }
2204
2205 process_deferred_updates(dc);
2206
2207 dc->hwss.optimize_bandwidth(dc, context);
2208
2209 if (dc->hwss.update_dsc_pg)
2210 dc->hwss.update_dsc_pg(dc, context, true);
2211 }
2212
2213 dc->optimized_required = false;
2214 dc->wm_optimized_required = false;
2215 }
2216
init_state(struct dc * dc,struct dc_state * context)2217 static void init_state(struct dc *dc, struct dc_state *context)
2218 {
2219 /* Each context must have their own instance of VBA and in order to
2220 * initialize and obtain IP and SOC the base DML instance from DC is
2221 * initially copied into every context
2222 */
2223 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
2224 }
2225
dc_create_state(struct dc * dc)2226 struct dc_state *dc_create_state(struct dc *dc)
2227 {
2228 struct dc_state *context = kvzalloc(sizeof(struct dc_state),
2229 GFP_KERNEL);
2230
2231 if (!context)
2232 return NULL;
2233
2234 init_state(dc, context);
2235
2236 kref_init(&context->refcount);
2237
2238 return context;
2239 }
2240
dc_copy_state(struct dc_state * src_ctx)2241 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
2242 {
2243 int i, j;
2244 struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
2245
2246 if (!new_ctx)
2247 return NULL;
2248 memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
2249
2250 for (i = 0; i < MAX_PIPES; i++) {
2251 struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
2252
2253 if (cur_pipe->top_pipe)
2254 cur_pipe->top_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2255
2256 if (cur_pipe->bottom_pipe)
2257 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2258
2259 if (cur_pipe->prev_odm_pipe)
2260 cur_pipe->prev_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
2261
2262 if (cur_pipe->next_odm_pipe)
2263 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2264
2265 }
2266
2267 for (i = 0; i < new_ctx->stream_count; i++) {
2268 dc_stream_retain(new_ctx->streams[i]);
2269 for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
2270 dc_plane_state_retain(
2271 new_ctx->stream_status[i].plane_states[j]);
2272 }
2273
2274 kref_init(&new_ctx->refcount);
2275
2276 return new_ctx;
2277 }
2278
dc_retain_state(struct dc_state * context)2279 void dc_retain_state(struct dc_state *context)
2280 {
2281 kref_get(&context->refcount);
2282 }
2283
dc_state_free(struct kref * kref)2284 static void dc_state_free(struct kref *kref)
2285 {
2286 struct dc_state *context = container_of(kref, struct dc_state, refcount);
2287 dc_resource_state_destruct(context);
2288 kvfree(context);
2289 }
2290
dc_release_state(struct dc_state * context)2291 void dc_release_state(struct dc_state *context)
2292 {
2293 kref_put(&context->refcount, dc_state_free);
2294 }
2295
dc_set_generic_gpio_for_stereo(bool enable,struct gpio_service * gpio_service)2296 bool dc_set_generic_gpio_for_stereo(bool enable,
2297 struct gpio_service *gpio_service)
2298 {
2299 enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
2300 struct gpio_pin_info pin_info;
2301 struct gpio *generic;
2302 struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
2303 GFP_KERNEL);
2304
2305 if (!config)
2306 return false;
2307 pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
2308
2309 if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
2310 kfree(config);
2311 return false;
2312 } else {
2313 generic = dal_gpio_service_create_generic_mux(
2314 gpio_service,
2315 pin_info.offset,
2316 pin_info.mask);
2317 }
2318
2319 if (!generic) {
2320 kfree(config);
2321 return false;
2322 }
2323
2324 gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
2325
2326 config->enable_output_from_mux = enable;
2327 config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
2328
2329 if (gpio_result == GPIO_RESULT_OK)
2330 gpio_result = dal_mux_setup_config(generic, config);
2331
2332 if (gpio_result == GPIO_RESULT_OK) {
2333 dal_gpio_close(generic);
2334 dal_gpio_destroy_generic_mux(&generic);
2335 kfree(config);
2336 return true;
2337 } else {
2338 dal_gpio_close(generic);
2339 dal_gpio_destroy_generic_mux(&generic);
2340 kfree(config);
2341 return false;
2342 }
2343 }
2344
is_surface_in_context(const struct dc_state * context,const struct dc_plane_state * plane_state)2345 static bool is_surface_in_context(
2346 const struct dc_state *context,
2347 const struct dc_plane_state *plane_state)
2348 {
2349 int j;
2350
2351 for (j = 0; j < MAX_PIPES; j++) {
2352 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2353
2354 if (plane_state == pipe_ctx->plane_state) {
2355 return true;
2356 }
2357 }
2358
2359 return false;
2360 }
2361
get_plane_info_update_type(const struct dc_surface_update * u)2362 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
2363 {
2364 union surface_update_flags *update_flags = &u->surface->update_flags;
2365 enum surface_update_type update_type = UPDATE_TYPE_FAST;
2366
2367 if (!u->plane_info)
2368 return UPDATE_TYPE_FAST;
2369
2370 if (u->plane_info->color_space != u->surface->color_space) {
2371 update_flags->bits.color_space_change = 1;
2372 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2373 }
2374
2375 if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
2376 update_flags->bits.horizontal_mirror_change = 1;
2377 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2378 }
2379
2380 if (u->plane_info->rotation != u->surface->rotation) {
2381 update_flags->bits.rotation_change = 1;
2382 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2383 }
2384
2385 if (u->plane_info->format != u->surface->format) {
2386 update_flags->bits.pixel_format_change = 1;
2387 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2388 }
2389
2390 if (u->plane_info->stereo_format != u->surface->stereo_format) {
2391 update_flags->bits.stereo_format_change = 1;
2392 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2393 }
2394
2395 if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
2396 update_flags->bits.per_pixel_alpha_change = 1;
2397 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2398 }
2399
2400 if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
2401 update_flags->bits.global_alpha_change = 1;
2402 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2403 }
2404
2405 if (u->plane_info->dcc.enable != u->surface->dcc.enable
2406 || u->plane_info->dcc.dcc_ind_blk != u->surface->dcc.dcc_ind_blk
2407 || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
2408 /* During DCC on/off, stutter period is calculated before
2409 * DCC has fully transitioned. This results in incorrect
2410 * stutter period calculation. Triggering a full update will
2411 * recalculate stutter period.
2412 */
2413 update_flags->bits.dcc_change = 1;
2414 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2415 }
2416
2417 if (resource_pixel_format_to_bpp(u->plane_info->format) !=
2418 resource_pixel_format_to_bpp(u->surface->format)) {
2419 /* different bytes per element will require full bandwidth
2420 * and DML calculation
2421 */
2422 update_flags->bits.bpp_change = 1;
2423 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2424 }
2425
2426 if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
2427 || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
2428 update_flags->bits.plane_size_change = 1;
2429 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2430 }
2431
2432
2433 if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
2434 sizeof(union dc_tiling_info)) != 0) {
2435 update_flags->bits.swizzle_change = 1;
2436 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2437
2438 /* todo: below are HW dependent, we should add a hook to
2439 * DCE/N resource and validated there.
2440 */
2441 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
2442 /* swizzled mode requires RQ to be setup properly,
2443 * thus need to run DML to calculate RQ settings
2444 */
2445 update_flags->bits.bandwidth_change = 1;
2446 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2447 }
2448 }
2449
2450 /* This should be UPDATE_TYPE_FAST if nothing has changed. */
2451 return update_type;
2452 }
2453
get_scaling_info_update_type(const struct dc * dc,const struct dc_surface_update * u)2454 static enum surface_update_type get_scaling_info_update_type(
2455 const struct dc *dc,
2456 const struct dc_surface_update *u)
2457 {
2458 union surface_update_flags *update_flags = &u->surface->update_flags;
2459
2460 if (!u->scaling_info)
2461 return UPDATE_TYPE_FAST;
2462
2463 if (u->scaling_info->dst_rect.width != u->surface->dst_rect.width
2464 || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
2465 || u->scaling_info->scaling_quality.integer_scaling !=
2466 u->surface->scaling_quality.integer_scaling
2467 ) {
2468 update_flags->bits.scaling_change = 1;
2469
2470 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
2471 || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
2472 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
2473 || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
2474 /* Making dst rect smaller requires a bandwidth change */
2475 update_flags->bits.bandwidth_change = 1;
2476 }
2477
2478 if (u->scaling_info->src_rect.width != u->surface->src_rect.width
2479 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
2480
2481 update_flags->bits.scaling_change = 1;
2482 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
2483 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
2484 /* Making src rect bigger requires a bandwidth change */
2485 update_flags->bits.clock_change = 1;
2486 }
2487
2488 if (u->scaling_info->src_rect.width > dc->caps.max_optimizable_video_width &&
2489 (u->scaling_info->clip_rect.width > u->surface->clip_rect.width ||
2490 u->scaling_info->clip_rect.height > u->surface->clip_rect.height))
2491 /* Changing clip size of a large surface may result in MPC slice count change */
2492 update_flags->bits.bandwidth_change = 1;
2493
2494 if (u->scaling_info->src_rect.x != u->surface->src_rect.x
2495 || u->scaling_info->src_rect.y != u->surface->src_rect.y
2496 || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
2497 || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
2498 || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
2499 || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
2500 update_flags->bits.position_change = 1;
2501
2502 if (update_flags->bits.clock_change
2503 || update_flags->bits.bandwidth_change
2504 || update_flags->bits.scaling_change)
2505 return UPDATE_TYPE_FULL;
2506
2507 if (update_flags->bits.position_change)
2508 return UPDATE_TYPE_MED;
2509
2510 return UPDATE_TYPE_FAST;
2511 }
2512
det_surface_update(const struct dc * dc,const struct dc_surface_update * u)2513 static enum surface_update_type det_surface_update(const struct dc *dc,
2514 const struct dc_surface_update *u)
2515 {
2516 const struct dc_state *context = dc->current_state;
2517 enum surface_update_type type;
2518 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2519 union surface_update_flags *update_flags = &u->surface->update_flags;
2520
2521 if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
2522 update_flags->raw = 0xFFFFFFFF;
2523 return UPDATE_TYPE_FULL;
2524 }
2525
2526 update_flags->raw = 0; // Reset all flags
2527
2528 type = get_plane_info_update_type(u);
2529 elevate_update_type(&overall_type, type);
2530
2531 type = get_scaling_info_update_type(dc, u);
2532 elevate_update_type(&overall_type, type);
2533
2534 if (u->flip_addr) {
2535 update_flags->bits.addr_update = 1;
2536 if (u->flip_addr->address.tmz_surface != u->surface->address.tmz_surface) {
2537 update_flags->bits.tmz_changed = 1;
2538 elevate_update_type(&overall_type, UPDATE_TYPE_FULL);
2539 }
2540 }
2541 if (u->in_transfer_func)
2542 update_flags->bits.in_transfer_func_change = 1;
2543
2544 if (u->input_csc_color_matrix)
2545 update_flags->bits.input_csc_change = 1;
2546
2547 if (u->coeff_reduction_factor)
2548 update_flags->bits.coeff_reduction_change = 1;
2549
2550 if (u->gamut_remap_matrix)
2551 update_flags->bits.gamut_remap_change = 1;
2552
2553 if (u->gamma) {
2554 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
2555
2556 if (u->plane_info)
2557 format = u->plane_info->format;
2558 else if (u->surface)
2559 format = u->surface->format;
2560
2561 if (dce_use_lut(format))
2562 update_flags->bits.gamma_change = 1;
2563 }
2564
2565 if (u->lut3d_func || u->func_shaper)
2566 update_flags->bits.lut_3d = 1;
2567
2568 if (u->hdr_mult.value)
2569 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
2570 update_flags->bits.hdr_mult = 1;
2571 elevate_update_type(&overall_type, UPDATE_TYPE_MED);
2572 }
2573
2574 if (update_flags->bits.in_transfer_func_change) {
2575 type = UPDATE_TYPE_MED;
2576 elevate_update_type(&overall_type, type);
2577 }
2578
2579 if (update_flags->bits.lut_3d) {
2580 type = UPDATE_TYPE_FULL;
2581 elevate_update_type(&overall_type, type);
2582 }
2583
2584 if (dc->debug.enable_legacy_fast_update &&
2585 (update_flags->bits.gamma_change ||
2586 update_flags->bits.gamut_remap_change ||
2587 update_flags->bits.input_csc_change ||
2588 update_flags->bits.coeff_reduction_change)) {
2589 type = UPDATE_TYPE_FULL;
2590 elevate_update_type(&overall_type, type);
2591 }
2592 return overall_type;
2593 }
2594
check_update_surfaces_for_stream(struct dc * dc,struct dc_surface_update * updates,int surface_count,struct dc_stream_update * stream_update,const struct dc_stream_status * stream_status)2595 static enum surface_update_type check_update_surfaces_for_stream(
2596 struct dc *dc,
2597 struct dc_surface_update *updates,
2598 int surface_count,
2599 struct dc_stream_update *stream_update,
2600 const struct dc_stream_status *stream_status)
2601 {
2602 int i;
2603 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2604
2605 if (dc->idle_optimizations_allowed)
2606 overall_type = UPDATE_TYPE_FULL;
2607
2608 if (stream_status == NULL || stream_status->plane_count != surface_count)
2609 overall_type = UPDATE_TYPE_FULL;
2610
2611 if (stream_update && stream_update->pending_test_pattern) {
2612 overall_type = UPDATE_TYPE_FULL;
2613 }
2614
2615 /* some stream updates require passive update */
2616 if (stream_update) {
2617 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
2618
2619 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
2620 (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
2621 stream_update->integer_scaling_update)
2622 su_flags->bits.scaling = 1;
2623
2624 if (dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func)
2625 su_flags->bits.out_tf = 1;
2626
2627 if (stream_update->abm_level)
2628 su_flags->bits.abm_level = 1;
2629
2630 if (stream_update->dpms_off)
2631 su_flags->bits.dpms_off = 1;
2632
2633 if (stream_update->gamut_remap)
2634 su_flags->bits.gamut_remap = 1;
2635
2636 if (stream_update->wb_update)
2637 su_flags->bits.wb_update = 1;
2638
2639 if (stream_update->dsc_config)
2640 su_flags->bits.dsc_changed = 1;
2641
2642 if (stream_update->mst_bw_update)
2643 su_flags->bits.mst_bw = 1;
2644
2645 if (stream_update->stream && stream_update->stream->freesync_on_desktop &&
2646 (stream_update->vrr_infopacket || stream_update->allow_freesync ||
2647 stream_update->vrr_active_variable || stream_update->vrr_active_fixed))
2648 su_flags->bits.fams_changed = 1;
2649
2650 if (su_flags->raw != 0)
2651 overall_type = UPDATE_TYPE_FULL;
2652
2653 if (stream_update->output_csc_transform || stream_update->output_color_space)
2654 su_flags->bits.out_csc = 1;
2655
2656 /* Output transfer function changes do not require bandwidth recalculation,
2657 * so don't trigger a full update
2658 */
2659 if (!dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func)
2660 su_flags->bits.out_tf = 1;
2661 }
2662
2663 for (i = 0 ; i < surface_count; i++) {
2664 enum surface_update_type type =
2665 det_surface_update(dc, &updates[i]);
2666
2667 elevate_update_type(&overall_type, type);
2668 }
2669
2670 return overall_type;
2671 }
2672
2673 /*
2674 * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
2675 *
2676 * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
2677 */
dc_check_update_surfaces_for_stream(struct dc * dc,struct dc_surface_update * updates,int surface_count,struct dc_stream_update * stream_update,const struct dc_stream_status * stream_status)2678 enum surface_update_type dc_check_update_surfaces_for_stream(
2679 struct dc *dc,
2680 struct dc_surface_update *updates,
2681 int surface_count,
2682 struct dc_stream_update *stream_update,
2683 const struct dc_stream_status *stream_status)
2684 {
2685 int i;
2686 enum surface_update_type type;
2687
2688 if (stream_update)
2689 stream_update->stream->update_flags.raw = 0;
2690 for (i = 0; i < surface_count; i++)
2691 updates[i].surface->update_flags.raw = 0;
2692
2693 type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
2694 if (type == UPDATE_TYPE_FULL) {
2695 if (stream_update) {
2696 uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
2697 stream_update->stream->update_flags.raw = 0xFFFFFFFF;
2698 stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
2699 }
2700 for (i = 0; i < surface_count; i++)
2701 updates[i].surface->update_flags.raw = 0xFFFFFFFF;
2702 }
2703
2704 if (type == UPDATE_TYPE_FAST) {
2705 // If there's an available clock comparator, we use that.
2706 if (dc->clk_mgr->funcs->are_clock_states_equal) {
2707 if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
2708 dc->optimized_required = true;
2709 // Else we fallback to mem compare.
2710 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
2711 dc->optimized_required = true;
2712 }
2713
2714 dc->optimized_required |= dc->wm_optimized_required;
2715 }
2716
2717 return type;
2718 }
2719
stream_get_status(struct dc_state * ctx,struct dc_stream_state * stream)2720 static struct dc_stream_status *stream_get_status(
2721 struct dc_state *ctx,
2722 struct dc_stream_state *stream)
2723 {
2724 uint8_t i;
2725
2726 for (i = 0; i < ctx->stream_count; i++) {
2727 if (stream == ctx->streams[i]) {
2728 return &ctx->stream_status[i];
2729 }
2730 }
2731
2732 return NULL;
2733 }
2734
2735 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
2736
copy_surface_update_to_plane(struct dc_plane_state * surface,struct dc_surface_update * srf_update)2737 static void copy_surface_update_to_plane(
2738 struct dc_plane_state *surface,
2739 struct dc_surface_update *srf_update)
2740 {
2741 if (srf_update->flip_addr) {
2742 surface->address = srf_update->flip_addr->address;
2743 surface->flip_immediate =
2744 srf_update->flip_addr->flip_immediate;
2745 surface->time.time_elapsed_in_us[surface->time.index] =
2746 srf_update->flip_addr->flip_timestamp_in_us -
2747 surface->time.prev_update_time_in_us;
2748 surface->time.prev_update_time_in_us =
2749 srf_update->flip_addr->flip_timestamp_in_us;
2750 surface->time.index++;
2751 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
2752 surface->time.index = 0;
2753
2754 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
2755 }
2756
2757 if (srf_update->scaling_info) {
2758 surface->scaling_quality =
2759 srf_update->scaling_info->scaling_quality;
2760 surface->dst_rect =
2761 srf_update->scaling_info->dst_rect;
2762 surface->src_rect =
2763 srf_update->scaling_info->src_rect;
2764 surface->clip_rect =
2765 srf_update->scaling_info->clip_rect;
2766 }
2767
2768 if (srf_update->plane_info) {
2769 surface->color_space =
2770 srf_update->plane_info->color_space;
2771 surface->format =
2772 srf_update->plane_info->format;
2773 surface->plane_size =
2774 srf_update->plane_info->plane_size;
2775 surface->rotation =
2776 srf_update->plane_info->rotation;
2777 surface->horizontal_mirror =
2778 srf_update->plane_info->horizontal_mirror;
2779 surface->stereo_format =
2780 srf_update->plane_info->stereo_format;
2781 surface->tiling_info =
2782 srf_update->plane_info->tiling_info;
2783 surface->visible =
2784 srf_update->plane_info->visible;
2785 surface->per_pixel_alpha =
2786 srf_update->plane_info->per_pixel_alpha;
2787 surface->global_alpha =
2788 srf_update->plane_info->global_alpha;
2789 surface->global_alpha_value =
2790 srf_update->plane_info->global_alpha_value;
2791 surface->dcc =
2792 srf_update->plane_info->dcc;
2793 surface->layer_index =
2794 srf_update->plane_info->layer_index;
2795 }
2796
2797 if (srf_update->gamma &&
2798 (surface->gamma_correction !=
2799 srf_update->gamma)) {
2800 memcpy(&surface->gamma_correction->entries,
2801 &srf_update->gamma->entries,
2802 sizeof(struct dc_gamma_entries));
2803 surface->gamma_correction->is_identity =
2804 srf_update->gamma->is_identity;
2805 surface->gamma_correction->num_entries =
2806 srf_update->gamma->num_entries;
2807 surface->gamma_correction->type =
2808 srf_update->gamma->type;
2809 }
2810
2811 if (srf_update->in_transfer_func &&
2812 (surface->in_transfer_func !=
2813 srf_update->in_transfer_func)) {
2814 surface->in_transfer_func->sdr_ref_white_level =
2815 srf_update->in_transfer_func->sdr_ref_white_level;
2816 surface->in_transfer_func->tf =
2817 srf_update->in_transfer_func->tf;
2818 surface->in_transfer_func->type =
2819 srf_update->in_transfer_func->type;
2820 memcpy(&surface->in_transfer_func->tf_pts,
2821 &srf_update->in_transfer_func->tf_pts,
2822 sizeof(struct dc_transfer_func_distributed_points));
2823 }
2824
2825 if (srf_update->func_shaper &&
2826 (surface->in_shaper_func !=
2827 srf_update->func_shaper))
2828 memcpy(surface->in_shaper_func, srf_update->func_shaper,
2829 sizeof(*surface->in_shaper_func));
2830
2831 if (srf_update->lut3d_func &&
2832 (surface->lut3d_func !=
2833 srf_update->lut3d_func))
2834 memcpy(surface->lut3d_func, srf_update->lut3d_func,
2835 sizeof(*surface->lut3d_func));
2836
2837 if (srf_update->hdr_mult.value)
2838 surface->hdr_mult =
2839 srf_update->hdr_mult;
2840
2841 if (srf_update->blend_tf &&
2842 (surface->blend_tf !=
2843 srf_update->blend_tf))
2844 memcpy(surface->blend_tf, srf_update->blend_tf,
2845 sizeof(*surface->blend_tf));
2846
2847 if (srf_update->input_csc_color_matrix)
2848 surface->input_csc_color_matrix =
2849 *srf_update->input_csc_color_matrix;
2850
2851 if (srf_update->coeff_reduction_factor)
2852 surface->coeff_reduction_factor =
2853 *srf_update->coeff_reduction_factor;
2854
2855 if (srf_update->gamut_remap_matrix)
2856 surface->gamut_remap_matrix =
2857 *srf_update->gamut_remap_matrix;
2858 }
2859
copy_stream_update_to_stream(struct dc * dc,struct dc_state * context,struct dc_stream_state * stream,struct dc_stream_update * update)2860 static void copy_stream_update_to_stream(struct dc *dc,
2861 struct dc_state *context,
2862 struct dc_stream_state *stream,
2863 struct dc_stream_update *update)
2864 {
2865 struct dc_context *dc_ctx = dc->ctx;
2866
2867 if (update == NULL || stream == NULL)
2868 return;
2869
2870 if (update->src.height && update->src.width)
2871 stream->src = update->src;
2872
2873 if (update->dst.height && update->dst.width)
2874 stream->dst = update->dst;
2875
2876 if (update->out_transfer_func &&
2877 stream->out_transfer_func != update->out_transfer_func) {
2878 stream->out_transfer_func->sdr_ref_white_level =
2879 update->out_transfer_func->sdr_ref_white_level;
2880 stream->out_transfer_func->tf = update->out_transfer_func->tf;
2881 stream->out_transfer_func->type =
2882 update->out_transfer_func->type;
2883 memcpy(&stream->out_transfer_func->tf_pts,
2884 &update->out_transfer_func->tf_pts,
2885 sizeof(struct dc_transfer_func_distributed_points));
2886 }
2887
2888 if (update->hdr_static_metadata)
2889 stream->hdr_static_metadata = *update->hdr_static_metadata;
2890
2891 if (update->abm_level)
2892 stream->abm_level = *update->abm_level;
2893
2894 if (update->periodic_interrupt)
2895 stream->periodic_interrupt = *update->periodic_interrupt;
2896
2897 if (update->gamut_remap)
2898 stream->gamut_remap_matrix = *update->gamut_remap;
2899
2900 /* Note: this being updated after mode set is currently not a use case
2901 * however if it arises OCSC would need to be reprogrammed at the
2902 * minimum
2903 */
2904 if (update->output_color_space)
2905 stream->output_color_space = *update->output_color_space;
2906
2907 if (update->output_csc_transform)
2908 stream->csc_color_matrix = *update->output_csc_transform;
2909
2910 if (update->vrr_infopacket)
2911 stream->vrr_infopacket = *update->vrr_infopacket;
2912
2913 if (update->allow_freesync)
2914 stream->allow_freesync = *update->allow_freesync;
2915
2916 if (update->vrr_active_variable)
2917 stream->vrr_active_variable = *update->vrr_active_variable;
2918
2919 if (update->vrr_active_fixed)
2920 stream->vrr_active_fixed = *update->vrr_active_fixed;
2921
2922 if (update->crtc_timing_adjust)
2923 stream->adjust = *update->crtc_timing_adjust;
2924
2925 if (update->dpms_off)
2926 stream->dpms_off = *update->dpms_off;
2927
2928 if (update->hfvsif_infopacket)
2929 stream->hfvsif_infopacket = *update->hfvsif_infopacket;
2930
2931 if (update->vtem_infopacket)
2932 stream->vtem_infopacket = *update->vtem_infopacket;
2933
2934 if (update->vsc_infopacket)
2935 stream->vsc_infopacket = *update->vsc_infopacket;
2936
2937 if (update->vsp_infopacket)
2938 stream->vsp_infopacket = *update->vsp_infopacket;
2939
2940 if (update->adaptive_sync_infopacket)
2941 stream->adaptive_sync_infopacket = *update->adaptive_sync_infopacket;
2942
2943 if (update->dither_option)
2944 stream->dither_option = *update->dither_option;
2945
2946 if (update->pending_test_pattern)
2947 stream->test_pattern = *update->pending_test_pattern;
2948 /* update current stream with writeback info */
2949 if (update->wb_update) {
2950 int i;
2951
2952 stream->num_wb_info = update->wb_update->num_wb_info;
2953 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
2954 for (i = 0; i < stream->num_wb_info; i++)
2955 stream->writeback_info[i] =
2956 update->wb_update->writeback_info[i];
2957 }
2958 if (update->dsc_config) {
2959 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
2960 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
2961 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
2962 update->dsc_config->num_slices_v != 0);
2963
2964 /* Use temporarry context for validating new DSC config */
2965 struct dc_state *dsc_validate_context = dc_create_state(dc);
2966
2967 if (dsc_validate_context) {
2968 dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
2969
2970 stream->timing.dsc_cfg = *update->dsc_config;
2971 stream->timing.flags.DSC = enable_dsc;
2972 if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
2973 stream->timing.dsc_cfg = old_dsc_cfg;
2974 stream->timing.flags.DSC = old_dsc_enabled;
2975 update->dsc_config = NULL;
2976 }
2977
2978 dc_release_state(dsc_validate_context);
2979 } else {
2980 DC_ERROR("Failed to allocate new validate context for DSC change\n");
2981 update->dsc_config = NULL;
2982 }
2983 }
2984 }
2985
update_planes_and_stream_state(struct dc * dc,struct dc_surface_update * srf_updates,int surface_count,struct dc_stream_state * stream,struct dc_stream_update * stream_update,enum surface_update_type * new_update_type,struct dc_state ** new_context)2986 static bool update_planes_and_stream_state(struct dc *dc,
2987 struct dc_surface_update *srf_updates, int surface_count,
2988 struct dc_stream_state *stream,
2989 struct dc_stream_update *stream_update,
2990 enum surface_update_type *new_update_type,
2991 struct dc_state **new_context)
2992 {
2993 struct dc_state *context;
2994 int i, j;
2995 enum surface_update_type update_type;
2996 const struct dc_stream_status *stream_status;
2997 struct dc_context *dc_ctx = dc->ctx;
2998
2999 stream_status = dc_stream_get_status(stream);
3000
3001 if (!stream_status) {
3002 if (surface_count) /* Only an error condition if surf_count non-zero*/
3003 ASSERT(false);
3004
3005 return false; /* Cannot commit surface to stream that is not committed */
3006 }
3007
3008 context = dc->current_state;
3009
3010 update_type = dc_check_update_surfaces_for_stream(
3011 dc, srf_updates, surface_count, stream_update, stream_status);
3012
3013 /* update current stream with the new updates */
3014 copy_stream_update_to_stream(dc, context, stream, stream_update);
3015
3016 /* do not perform surface update if surface has invalid dimensions
3017 * (all zero) and no scaling_info is provided
3018 */
3019 if (surface_count > 0) {
3020 for (i = 0; i < surface_count; i++) {
3021 if ((srf_updates[i].surface->src_rect.width == 0 ||
3022 srf_updates[i].surface->src_rect.height == 0 ||
3023 srf_updates[i].surface->dst_rect.width == 0 ||
3024 srf_updates[i].surface->dst_rect.height == 0) &&
3025 (!srf_updates[i].scaling_info ||
3026 srf_updates[i].scaling_info->src_rect.width == 0 ||
3027 srf_updates[i].scaling_info->src_rect.height == 0 ||
3028 srf_updates[i].scaling_info->dst_rect.width == 0 ||
3029 srf_updates[i].scaling_info->dst_rect.height == 0)) {
3030 DC_ERROR("Invalid src/dst rects in surface update!\n");
3031 return false;
3032 }
3033 }
3034 }
3035
3036 if (update_type >= update_surface_trace_level)
3037 update_surface_trace(dc, srf_updates, surface_count);
3038
3039 if (update_type >= UPDATE_TYPE_FULL) {
3040 struct dc_plane_state *new_planes[MAX_SURFACES] = {0};
3041
3042 for (i = 0; i < surface_count; i++)
3043 new_planes[i] = srf_updates[i].surface;
3044
3045 /* initialize scratch memory for building context */
3046 context = dc_create_state(dc);
3047 if (context == NULL) {
3048 DC_ERROR("Failed to allocate new validate context!\n");
3049 return false;
3050 }
3051
3052 dc_resource_state_copy_construct(
3053 dc->current_state, context);
3054
3055 /* For each full update, remove all existing phantom pipes first.
3056 * Ensures that we have enough pipes for newly added MPO planes
3057 */
3058 if (dc->res_pool->funcs->remove_phantom_pipes)
3059 dc->res_pool->funcs->remove_phantom_pipes(dc, context, false);
3060
3061 /*remove old surfaces from context */
3062 if (!dc_rem_all_planes_for_stream(dc, stream, context)) {
3063
3064 BREAK_TO_DEBUGGER();
3065 goto fail;
3066 }
3067
3068 /* add surface to context */
3069 if (!dc_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) {
3070
3071 BREAK_TO_DEBUGGER();
3072 goto fail;
3073 }
3074 }
3075
3076 /* save update parameters into surface */
3077 for (i = 0; i < surface_count; i++) {
3078 struct dc_plane_state *surface = srf_updates[i].surface;
3079
3080 copy_surface_update_to_plane(surface, &srf_updates[i]);
3081
3082 if (update_type >= UPDATE_TYPE_MED) {
3083 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3084 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3085
3086 if (pipe_ctx->plane_state != surface)
3087 continue;
3088
3089 resource_build_scaling_params(pipe_ctx);
3090 }
3091 }
3092 }
3093
3094 if (update_type == UPDATE_TYPE_FULL) {
3095 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
3096 /* For phantom pipes we remove and create a new set of phantom pipes
3097 * for each full update (because we don't know if we'll need phantom
3098 * pipes until after the first round of validation). However, if validation
3099 * fails we need to keep the existing phantom pipes (because we don't update
3100 * the dc->current_state).
3101 *
3102 * The phantom stream/plane refcount is decremented for validation because
3103 * we assume it'll be removed (the free comes when the dc_state is freed),
3104 * but if validation fails we have to increment back the refcount so it's
3105 * consistent.
3106 */
3107 if (dc->res_pool->funcs->retain_phantom_pipes)
3108 dc->res_pool->funcs->retain_phantom_pipes(dc, dc->current_state);
3109 BREAK_TO_DEBUGGER();
3110 goto fail;
3111 }
3112 }
3113
3114 *new_context = context;
3115 *new_update_type = update_type;
3116
3117 return true;
3118
3119 fail:
3120 dc_release_state(context);
3121
3122 return false;
3123
3124 }
3125
commit_planes_do_stream_update(struct dc * dc,struct dc_stream_state * stream,struct dc_stream_update * stream_update,enum surface_update_type update_type,struct dc_state * context)3126 static void commit_planes_do_stream_update(struct dc *dc,
3127 struct dc_stream_state *stream,
3128 struct dc_stream_update *stream_update,
3129 enum surface_update_type update_type,
3130 struct dc_state *context)
3131 {
3132 int j;
3133
3134 // Stream updates
3135 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3136 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3137
3138 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_ctx->stream == stream) {
3139
3140 if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt)
3141 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);
3142
3143 if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
3144 stream_update->vrr_infopacket ||
3145 stream_update->vsc_infopacket ||
3146 stream_update->vsp_infopacket ||
3147 stream_update->hfvsif_infopacket ||
3148 stream_update->adaptive_sync_infopacket ||
3149 stream_update->vtem_infopacket) {
3150 resource_build_info_frame(pipe_ctx);
3151 dc->hwss.update_info_frame(pipe_ctx);
3152
3153 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3154 dc->link_srv->dp_trace_source_sequence(
3155 pipe_ctx->stream->link,
3156 DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
3157 }
3158
3159 if (stream_update->hdr_static_metadata &&
3160 stream->use_dynamic_meta &&
3161 dc->hwss.set_dmdata_attributes &&
3162 pipe_ctx->stream->dmdata_address.quad_part != 0)
3163 dc->hwss.set_dmdata_attributes(pipe_ctx);
3164
3165 if (stream_update->gamut_remap)
3166 dc_stream_set_gamut_remap(dc, stream);
3167
3168 if (stream_update->output_csc_transform)
3169 dc_stream_program_csc_matrix(dc, stream);
3170
3171 if (stream_update->dither_option) {
3172 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
3173 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
3174 &pipe_ctx->stream->bit_depth_params);
3175 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
3176 &stream->bit_depth_params,
3177 &stream->clamping);
3178 while (odm_pipe) {
3179 odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
3180 &stream->bit_depth_params,
3181 &stream->clamping);
3182 odm_pipe = odm_pipe->next_odm_pipe;
3183 }
3184 }
3185
3186
3187 /* Full fe update*/
3188 if (update_type == UPDATE_TYPE_FAST)
3189 continue;
3190
3191 if (stream_update->dsc_config)
3192 dc->link_srv->update_dsc_config(pipe_ctx);
3193
3194 if (stream_update->mst_bw_update) {
3195 if (stream_update->mst_bw_update->is_increase)
3196 dc->link_srv->increase_mst_payload(pipe_ctx,
3197 stream_update->mst_bw_update->mst_stream_bw);
3198 else
3199 dc->link_srv->reduce_mst_payload(pipe_ctx,
3200 stream_update->mst_bw_update->mst_stream_bw);
3201 }
3202
3203 if (stream_update->pending_test_pattern) {
3204 dc_link_dp_set_test_pattern(stream->link,
3205 stream->test_pattern.type,
3206 stream->test_pattern.color_space,
3207 stream->test_pattern.p_link_settings,
3208 stream->test_pattern.p_custom_pattern,
3209 stream->test_pattern.cust_pattern_size);
3210 }
3211
3212 if (stream_update->dpms_off) {
3213 if (*stream_update->dpms_off) {
3214 dc->link_srv->set_dpms_off(pipe_ctx);
3215 /* for dpms, keep acquired resources*/
3216 if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
3217 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
3218
3219 dc->optimized_required = true;
3220
3221 } else {
3222 if (get_seamless_boot_stream_count(context) == 0)
3223 dc->hwss.prepare_bandwidth(dc, dc->current_state);
3224 dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);
3225 }
3226 } else if (pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && stream_update->output_color_space
3227 && !stream->dpms_off && dc_is_dp_signal(pipe_ctx->stream->signal)) {
3228 /*
3229 * Workaround for firmware issue in some receivers where they don't pick up
3230 * correct output color space unless DP link is disabled/re-enabled
3231 */
3232 dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);
3233 }
3234
3235 if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
3236 bool should_program_abm = true;
3237
3238 // if otg funcs defined check if blanked before programming
3239 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
3240 if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
3241 should_program_abm = false;
3242
3243 if (should_program_abm) {
3244 if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
3245 dc->hwss.set_abm_immediate_disable(pipe_ctx);
3246 } else {
3247 pipe_ctx->stream_res.abm->funcs->set_abm_level(
3248 pipe_ctx->stream_res.abm, stream->abm_level);
3249 }
3250 }
3251 }
3252 }
3253 }
3254 }
3255
dc_dmub_should_send_dirty_rect_cmd(struct dc * dc,struct dc_stream_state * stream)3256 static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream)
3257 {
3258 if ((stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1
3259 || stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
3260 && stream->ctx->dce_version >= DCN_VERSION_3_1)
3261 return true;
3262
3263 if (stream->link->replay_settings.config.replay_supported)
3264 return true;
3265
3266 return false;
3267 }
3268
dc_dmub_update_dirty_rect(struct dc * dc,int surface_count,struct dc_stream_state * stream,struct dc_surface_update * srf_updates,struct dc_state * context)3269 void dc_dmub_update_dirty_rect(struct dc *dc,
3270 int surface_count,
3271 struct dc_stream_state *stream,
3272 struct dc_surface_update *srf_updates,
3273 struct dc_state *context)
3274 {
3275 union dmub_rb_cmd cmd;
3276 struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
3277 unsigned int i, j;
3278 unsigned int panel_inst = 0;
3279
3280 if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
3281 return;
3282
3283 if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
3284 return;
3285
3286 memset(&cmd, 0x0, sizeof(cmd));
3287 cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
3288 cmd.update_dirty_rect.header.sub_type = 0;
3289 cmd.update_dirty_rect.header.payload_bytes =
3290 sizeof(cmd.update_dirty_rect) -
3291 sizeof(cmd.update_dirty_rect.header);
3292 update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data;
3293 for (i = 0; i < surface_count; i++) {
3294 struct dc_plane_state *plane_state = srf_updates[i].surface;
3295 const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr;
3296
3297 if (!srf_updates[i].surface || !flip_addr)
3298 continue;
3299 /* Do not send in immediate flip mode */
3300 if (srf_updates[i].surface->flip_immediate)
3301 continue;
3302
3303 update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
3304 memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
3305 sizeof(flip_addr->dirty_rects));
3306 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3307 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3308
3309 if (pipe_ctx->stream != stream)
3310 continue;
3311 if (pipe_ctx->plane_state != plane_state)
3312 continue;
3313
3314 update_dirty_rect->panel_inst = panel_inst;
3315 update_dirty_rect->pipe_idx = j;
3316 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
3317 }
3318 }
3319 }
3320
build_dmub_update_dirty_rect(struct dc * dc,int surface_count,struct dc_stream_state * stream,struct dc_surface_update * srf_updates,struct dc_state * context,struct dc_dmub_cmd dc_dmub_cmd[],unsigned int * dmub_cmd_count)3321 static void build_dmub_update_dirty_rect(
3322 struct dc *dc,
3323 int surface_count,
3324 struct dc_stream_state *stream,
3325 struct dc_surface_update *srf_updates,
3326 struct dc_state *context,
3327 struct dc_dmub_cmd dc_dmub_cmd[],
3328 unsigned int *dmub_cmd_count)
3329 {
3330 union dmub_rb_cmd cmd;
3331 struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
3332 unsigned int i, j;
3333 unsigned int panel_inst = 0;
3334
3335 if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
3336 return;
3337
3338 if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
3339 return;
3340
3341 memset(&cmd, 0x0, sizeof(cmd));
3342 cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
3343 cmd.update_dirty_rect.header.sub_type = 0;
3344 cmd.update_dirty_rect.header.payload_bytes =
3345 sizeof(cmd.update_dirty_rect) -
3346 sizeof(cmd.update_dirty_rect.header);
3347 update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data;
3348 for (i = 0; i < surface_count; i++) {
3349 struct dc_plane_state *plane_state = srf_updates[i].surface;
3350 const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr;
3351
3352 if (!srf_updates[i].surface || !flip_addr)
3353 continue;
3354 /* Do not send in immediate flip mode */
3355 if (srf_updates[i].surface->flip_immediate)
3356 continue;
3357 update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
3358 update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
3359 memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
3360 sizeof(flip_addr->dirty_rects));
3361 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3362 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3363
3364 if (pipe_ctx->stream != stream)
3365 continue;
3366 if (pipe_ctx->plane_state != plane_state)
3367 continue;
3368 update_dirty_rect->panel_inst = panel_inst;
3369 update_dirty_rect->pipe_idx = j;
3370 dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd;
3371 dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT;
3372 (*dmub_cmd_count)++;
3373 }
3374 }
3375 }
3376
3377
3378 /**
3379 * build_dmub_cmd_list() - Build an array of DMCUB commands to be sent to DMCUB
3380 *
3381 * @dc: Current DC state
3382 * @srf_updates: Array of surface updates
3383 * @surface_count: Number of surfaces that have an updated
3384 * @stream: Corresponding stream to be updated in the current flip
3385 * @context: New DC state to be programmed
3386 *
3387 * @dc_dmub_cmd: Array of DMCUB commands to be sent to DMCUB
3388 * @dmub_cmd_count: Count indicating the number of DMCUB commands in dc_dmub_cmd array
3389 *
3390 * This function builds an array of DMCUB commands to be sent to DMCUB. This function is required
3391 * to build an array of commands and have them sent while the OTG lock is acquired.
3392 *
3393 * Return: void
3394 */
build_dmub_cmd_list(struct dc * dc,struct dc_surface_update * srf_updates,int surface_count,struct dc_stream_state * stream,struct dc_state * context,struct dc_dmub_cmd dc_dmub_cmd[],unsigned int * dmub_cmd_count)3395 static void build_dmub_cmd_list(struct dc *dc,
3396 struct dc_surface_update *srf_updates,
3397 int surface_count,
3398 struct dc_stream_state *stream,
3399 struct dc_state *context,
3400 struct dc_dmub_cmd dc_dmub_cmd[],
3401 unsigned int *dmub_cmd_count)
3402 {
3403 // Initialize cmd count to 0
3404 *dmub_cmd_count = 0;
3405 build_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context, dc_dmub_cmd, dmub_cmd_count);
3406 }
3407
commit_planes_for_stream_fast(struct dc * dc,struct dc_surface_update * srf_updates,int surface_count,struct dc_stream_state * stream,struct dc_stream_update * stream_update,enum surface_update_type update_type,struct dc_state * context)3408 static void commit_planes_for_stream_fast(struct dc *dc,
3409 struct dc_surface_update *srf_updates,
3410 int surface_count,
3411 struct dc_stream_state *stream,
3412 struct dc_stream_update *stream_update,
3413 enum surface_update_type update_type,
3414 struct dc_state *context)
3415 {
3416 int i, j;
3417 struct pipe_ctx *top_pipe_to_program = NULL;
3418 dc_z10_restore(dc);
3419
3420 top_pipe_to_program = resource_get_otg_master_for_stream(
3421 &context->res_ctx,
3422 stream);
3423
3424 if (dc->debug.visual_confirm) {
3425 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3426 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3427
3428 if (pipe->stream && pipe->plane_state)
3429 dc_update_viusal_confirm_color(dc, context, pipe);
3430 }
3431 }
3432
3433 for (i = 0; i < surface_count; i++) {
3434 struct dc_plane_state *plane_state = srf_updates[i].surface;
3435 /*set logical flag for lock/unlock use*/
3436 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3437 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3438
3439 if (!pipe_ctx->plane_state)
3440 continue;
3441 if (should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3442 continue;
3443 pipe_ctx->plane_state->triplebuffer_flips = false;
3444 if (update_type == UPDATE_TYPE_FAST &&
3445 dc->hwss.program_triplebuffer &&
3446 !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {
3447 /*triple buffer for VUpdate only*/
3448 pipe_ctx->plane_state->triplebuffer_flips = true;
3449 }
3450 }
3451 }
3452
3453 build_dmub_cmd_list(dc,
3454 srf_updates,
3455 surface_count,
3456 stream,
3457 context,
3458 context->dc_dmub_cmd,
3459 &(context->dmub_cmd_count));
3460 hwss_build_fast_sequence(dc,
3461 context->dc_dmub_cmd,
3462 context->dmub_cmd_count,
3463 context->block_sequence,
3464 &(context->block_sequence_steps),
3465 top_pipe_to_program);
3466 hwss_execute_sequence(dc,
3467 context->block_sequence,
3468 context->block_sequence_steps);
3469 /* Clear update flags so next flip doesn't have redundant programming
3470 * (if there's no stream update, the update flags are not cleared).
3471 * Surface updates are cleared unconditionally at the beginning of each flip,
3472 * so no need to clear here.
3473 */
3474 if (top_pipe_to_program->stream)
3475 top_pipe_to_program->stream->update_flags.raw = 0;
3476 }
3477
wait_for_outstanding_hw_updates(struct dc * dc,const struct dc_state * dc_context)3478 static void wait_for_outstanding_hw_updates(struct dc *dc, const struct dc_state *dc_context)
3479 {
3480 /*
3481 * This function calls HWSS to wait for any potentially double buffered
3482 * operations to complete. It should be invoked as a pre-amble prior
3483 * to full update programming before asserting any HW locks.
3484 */
3485 int pipe_idx;
3486 int opp_inst;
3487 int opp_count = dc->res_pool->pipe_count;
3488 struct hubp *hubp;
3489 int mpcc_inst;
3490 const struct pipe_ctx *pipe_ctx;
3491
3492 for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
3493 pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx];
3494
3495 if (!pipe_ctx->stream)
3496 continue;
3497
3498 if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear)
3499 pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg);
3500
3501 hubp = pipe_ctx->plane_res.hubp;
3502 if (!hubp)
3503 continue;
3504
3505 mpcc_inst = hubp->inst;
3506 // MPCC inst is equal to pipe index in practice
3507 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
3508 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
3509 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
3510 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
3511 break;
3512 }
3513 }
3514 }
3515 }
3516
commit_planes_for_stream(struct dc * dc,struct dc_surface_update * srf_updates,int surface_count,struct dc_stream_state * stream,struct dc_stream_update * stream_update,enum surface_update_type update_type,struct dc_state * context)3517 static void commit_planes_for_stream(struct dc *dc,
3518 struct dc_surface_update *srf_updates,
3519 int surface_count,
3520 struct dc_stream_state *stream,
3521 struct dc_stream_update *stream_update,
3522 enum surface_update_type update_type,
3523 struct dc_state *context)
3524 {
3525 int i, j;
3526 struct pipe_ctx *top_pipe_to_program = NULL;
3527 bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST);
3528 bool subvp_prev_use = false;
3529 bool subvp_curr_use = false;
3530
3531 // Once we apply the new subvp context to hardware it won't be in the
3532 // dc->current_state anymore, so we have to cache it before we apply
3533 // the new SubVP context
3534 subvp_prev_use = false;
3535 dc_z10_restore(dc);
3536 if (update_type == UPDATE_TYPE_FULL)
3537 wait_for_outstanding_hw_updates(dc, context);
3538
3539 if (update_type == UPDATE_TYPE_FULL) {
3540 dc_allow_idle_optimizations(dc, false);
3541
3542 if (get_seamless_boot_stream_count(context) == 0)
3543 dc->hwss.prepare_bandwidth(dc, context);
3544
3545 if (dc->hwss.update_dsc_pg)
3546 dc->hwss.update_dsc_pg(dc, context, false);
3547
3548 context_clock_trace(dc, context);
3549 }
3550
3551 top_pipe_to_program = resource_get_otg_master_for_stream(
3552 &context->res_ctx,
3553 stream);
3554
3555 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3556 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3557
3558 // Check old context for SubVP
3559 subvp_prev_use |= (old_pipe->stream && old_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM);
3560 if (subvp_prev_use)
3561 break;
3562 }
3563
3564 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3565 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3566
3567 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
3568 subvp_curr_use = true;
3569 break;
3570 }
3571 }
3572
3573 if (dc->debug.visual_confirm)
3574 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3575 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3576
3577 if (pipe->stream && pipe->plane_state)
3578 dc_update_viusal_confirm_color(dc, context, pipe);
3579 }
3580
3581 if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
3582 struct pipe_ctx *mpcc_pipe;
3583 struct pipe_ctx *odm_pipe;
3584
3585 for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
3586 for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3587 odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
3588 }
3589
3590 if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
3591 if (top_pipe_to_program &&
3592 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
3593 if (should_use_dmub_lock(stream->link)) {
3594 union dmub_hw_lock_flags hw_locks = { 0 };
3595 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
3596
3597 hw_locks.bits.lock_dig = 1;
3598 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
3599
3600 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
3601 true,
3602 &hw_locks,
3603 &inst_flags);
3604 } else
3605 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
3606 top_pipe_to_program->stream_res.tg);
3607 }
3608
3609 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3610 if (dc->hwss.subvp_pipe_control_lock)
3611 dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use);
3612 dc->hwss.interdependent_update_lock(dc, context, true);
3613
3614 } else {
3615 if (dc->hwss.subvp_pipe_control_lock)
3616 dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
3617 /* Lock the top pipe while updating plane addrs, since freesync requires
3618 * plane addr update event triggers to be synchronized.
3619 * top_pipe_to_program is expected to never be NULL
3620 */
3621 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
3622 }
3623
3624 dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context);
3625
3626 // Stream updates
3627 if (stream_update)
3628 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
3629
3630 if (surface_count == 0) {
3631 /*
3632 * In case of turning off screen, no need to program front end a second time.
3633 * just return after program blank.
3634 */
3635 if (dc->hwss.apply_ctx_for_surface)
3636 dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
3637 if (dc->hwss.program_front_end_for_ctx)
3638 dc->hwss.program_front_end_for_ctx(dc, context);
3639
3640 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3641 dc->hwss.interdependent_update_lock(dc, context, false);
3642 } else {
3643 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
3644 }
3645 dc->hwss.post_unlock_program_front_end(dc, context);
3646
3647 if (update_type != UPDATE_TYPE_FAST)
3648 if (dc->hwss.commit_subvp_config)
3649 dc->hwss.commit_subvp_config(dc, context);
3650
3651 /* Since phantom pipe programming is moved to post_unlock_program_front_end,
3652 * move the SubVP lock to after the phantom pipes have been setup
3653 */
3654 if (dc->hwss.subvp_pipe_control_lock)
3655 dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes,
3656 NULL, subvp_prev_use);
3657 return;
3658 }
3659
3660 if (update_type != UPDATE_TYPE_FAST) {
3661 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3662 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3663
3664 if ((dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP ||
3665 dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH) &&
3666 pipe_ctx->stream && pipe_ctx->plane_state) {
3667 /* Only update visual confirm for SUBVP and Mclk switching here.
3668 * The bar appears on all pipes, so we need to update the bar on all displays,
3669 * so the information doesn't get stale.
3670 */
3671 dc->hwss.update_visual_confirm_color(dc, pipe_ctx,
3672 pipe_ctx->plane_res.hubp->inst);
3673 }
3674 }
3675 }
3676
3677 for (i = 0; i < surface_count; i++) {
3678 struct dc_plane_state *plane_state = srf_updates[i].surface;
3679 /*set logical flag for lock/unlock use*/
3680 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3681 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3682 if (!pipe_ctx->plane_state)
3683 continue;
3684 if (should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3685 continue;
3686 pipe_ctx->plane_state->triplebuffer_flips = false;
3687 if (update_type == UPDATE_TYPE_FAST &&
3688 dc->hwss.program_triplebuffer != NULL &&
3689 !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {
3690 /*triple buffer for VUpdate only*/
3691 pipe_ctx->plane_state->triplebuffer_flips = true;
3692 }
3693 }
3694 if (update_type == UPDATE_TYPE_FULL) {
3695 /* force vsync flip when reconfiguring pipes to prevent underflow */
3696 plane_state->flip_immediate = false;
3697 }
3698 }
3699
3700 // Update Type FULL, Surface updates
3701 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3702 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3703
3704 if (!pipe_ctx->top_pipe &&
3705 !pipe_ctx->prev_odm_pipe &&
3706 should_update_pipe_for_stream(context, pipe_ctx, stream)) {
3707 struct dc_stream_status *stream_status = NULL;
3708
3709 if (!pipe_ctx->plane_state)
3710 continue;
3711
3712 /* Full fe update*/
3713 if (update_type == UPDATE_TYPE_FAST)
3714 continue;
3715
3716 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
3717
3718 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
3719 /*turn off triple buffer for full update*/
3720 dc->hwss.program_triplebuffer(
3721 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
3722 }
3723 stream_status =
3724 stream_get_status(context, pipe_ctx->stream);
3725
3726 if (dc->hwss.apply_ctx_for_surface)
3727 dc->hwss.apply_ctx_for_surface(
3728 dc, pipe_ctx->stream, stream_status->plane_count, context);
3729 }
3730 }
3731 if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
3732 dc->hwss.program_front_end_for_ctx(dc, context);
3733 if (dc->debug.validate_dml_output) {
3734 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3735 struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
3736 if (cur_pipe->stream == NULL)
3737 continue;
3738
3739 cur_pipe->plane_res.hubp->funcs->validate_dml_output(
3740 cur_pipe->plane_res.hubp, dc->ctx,
3741 &context->res_ctx.pipe_ctx[i].rq_regs,
3742 &context->res_ctx.pipe_ctx[i].dlg_regs,
3743 &context->res_ctx.pipe_ctx[i].ttu_regs);
3744 }
3745 }
3746 }
3747
3748 // Update Type FAST, Surface updates
3749 if (update_type == UPDATE_TYPE_FAST) {
3750 if (dc->hwss.set_flip_control_gsl)
3751 for (i = 0; i < surface_count; i++) {
3752 struct dc_plane_state *plane_state = srf_updates[i].surface;
3753
3754 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3755 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3756
3757 if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
3758 continue;
3759
3760 if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3761 continue;
3762
3763 // GSL has to be used for flip immediate
3764 dc->hwss.set_flip_control_gsl(pipe_ctx,
3765 pipe_ctx->plane_state->flip_immediate);
3766 }
3767 }
3768
3769 /* Perform requested Updates */
3770 for (i = 0; i < surface_count; i++) {
3771 struct dc_plane_state *plane_state = srf_updates[i].surface;
3772
3773 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3774 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3775
3776 if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
3777 continue;
3778
3779 if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3780 continue;
3781
3782 /*program triple buffer after lock based on flip type*/
3783 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
3784 /*only enable triplebuffer for fast_update*/
3785 dc->hwss.program_triplebuffer(
3786 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
3787 }
3788 if (pipe_ctx->plane_state->update_flags.bits.addr_update)
3789 dc->hwss.update_plane_addr(dc, pipe_ctx);
3790 }
3791 }
3792 }
3793
3794 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3795 dc->hwss.interdependent_update_lock(dc, context, false);
3796 } else {
3797 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
3798 }
3799
3800 if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
3801 if (top_pipe_to_program &&
3802 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
3803 top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
3804 top_pipe_to_program->stream_res.tg,
3805 CRTC_STATE_VACTIVE);
3806 top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
3807 top_pipe_to_program->stream_res.tg,
3808 CRTC_STATE_VBLANK);
3809 top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
3810 top_pipe_to_program->stream_res.tg,
3811 CRTC_STATE_VACTIVE);
3812
3813 if (should_use_dmub_lock(stream->link)) {
3814 union dmub_hw_lock_flags hw_locks = { 0 };
3815 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
3816
3817 hw_locks.bits.lock_dig = 1;
3818 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
3819
3820 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
3821 false,
3822 &hw_locks,
3823 &inst_flags);
3824 } else
3825 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
3826 top_pipe_to_program->stream_res.tg);
3827 }
3828
3829 if (subvp_curr_use) {
3830 /* If enabling subvp or transitioning from subvp->subvp, enable the
3831 * phantom streams before we program front end for the phantom pipes.
3832 */
3833 if (update_type != UPDATE_TYPE_FAST) {
3834 if (dc->hwss.enable_phantom_streams)
3835 dc->hwss.enable_phantom_streams(dc, context);
3836 }
3837 }
3838
3839 if (update_type != UPDATE_TYPE_FAST)
3840 dc->hwss.post_unlock_program_front_end(dc, context);
3841
3842 if (subvp_prev_use && !subvp_curr_use) {
3843 /* If disabling subvp, disable phantom streams after front end
3844 * programming has completed (we turn on phantom OTG in order
3845 * to complete the plane disable for phantom pipes).
3846 */
3847 dc->hwss.apply_ctx_to_hw(dc, context);
3848 }
3849
3850 if (update_type != UPDATE_TYPE_FAST)
3851 if (dc->hwss.commit_subvp_config)
3852 dc->hwss.commit_subvp_config(dc, context);
3853 /* Since phantom pipe programming is moved to post_unlock_program_front_end,
3854 * move the SubVP lock to after the phantom pipes have been setup
3855 */
3856 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3857 if (dc->hwss.subvp_pipe_control_lock)
3858 dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use);
3859 } else {
3860 if (dc->hwss.subvp_pipe_control_lock)
3861 dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
3862 }
3863
3864 // Fire manual trigger only when bottom plane is flipped
3865 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3866 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3867
3868 if (!pipe_ctx->plane_state)
3869 continue;
3870
3871 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
3872 !pipe_ctx->stream || !should_update_pipe_for_stream(context, pipe_ctx, stream) ||
3873 !pipe_ctx->plane_state->update_flags.bits.addr_update ||
3874 pipe_ctx->plane_state->skip_manual_trigger)
3875 continue;
3876
3877 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
3878 pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
3879 }
3880 }
3881
3882 /**
3883 * could_mpcc_tree_change_for_active_pipes - Check if an OPP associated with MPCC might change
3884 *
3885 * @dc: Used to get the current state status
3886 * @stream: Target stream, which we want to remove the attached planes
3887 * @surface_count: Number of surface update
3888 * @is_plane_addition: [in] Fill out with true if it is a plane addition case
3889 *
3890 * DCN32x and newer support a feature named Dynamic ODM which can conflict with
3891 * the MPO if used simultaneously in some specific configurations (e.g.,
3892 * 4k@144). This function checks if the incoming context requires applying a
3893 * transition state with unnecessary pipe splitting and ODM disabled to
3894 * circumvent our hardware limitations to prevent this edge case. If the OPP
3895 * associated with an MPCC might change due to plane additions, this function
3896 * returns true.
3897 *
3898 * Return:
3899 * Return true if OPP and MPCC might change, otherwise, return false.
3900 */
could_mpcc_tree_change_for_active_pipes(struct dc * dc,struct dc_stream_state * stream,int surface_count,bool * is_plane_addition)3901 static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc,
3902 struct dc_stream_state *stream,
3903 int surface_count,
3904 bool *is_plane_addition)
3905 {
3906
3907 struct dc_stream_status *cur_stream_status = stream_get_status(dc->current_state, stream);
3908 bool force_minimal_pipe_splitting = false;
3909 bool subvp_active = false;
3910 uint32_t i;
3911
3912 *is_plane_addition = false;
3913
3914 if (cur_stream_status &&
3915 dc->current_state->stream_count > 0 &&
3916 dc->debug.pipe_split_policy != MPC_SPLIT_AVOID) {
3917 /* determine if minimal transition is required due to MPC*/
3918 if (surface_count > 0) {
3919 if (cur_stream_status->plane_count > surface_count) {
3920 force_minimal_pipe_splitting = true;
3921 } else if (cur_stream_status->plane_count < surface_count) {
3922 force_minimal_pipe_splitting = true;
3923 *is_plane_addition = true;
3924 }
3925 }
3926 }
3927
3928 if (cur_stream_status &&
3929 dc->current_state->stream_count == 1 &&
3930 dc->debug.enable_single_display_2to1_odm_policy) {
3931 /* determine if minimal transition is required due to dynamic ODM*/
3932 if (surface_count > 0) {
3933 if (cur_stream_status->plane_count > 2 && cur_stream_status->plane_count > surface_count) {
3934 force_minimal_pipe_splitting = true;
3935 } else if (surface_count > 2 && cur_stream_status->plane_count < surface_count) {
3936 force_minimal_pipe_splitting = true;
3937 *is_plane_addition = true;
3938 }
3939 }
3940 }
3941
3942 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3943 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3944
3945 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
3946 subvp_active = true;
3947 break;
3948 }
3949 }
3950
3951 /* For SubVP when adding or removing planes we need to add a minimal transition
3952 * (even when disabling all planes). Whenever disabling a phantom pipe, we
3953 * must use the minimal transition path to disable the pipe correctly.
3954 *
3955 * We want to use the minimal transition whenever subvp is active, not only if
3956 * a plane is being added / removed from a subvp stream (MPO plane can be added
3957 * to a DRR pipe of SubVP + DRR config, in which case we still want to run through
3958 * a min transition to disable subvp.
3959 */
3960 if (cur_stream_status && subvp_active) {
3961 /* determine if minimal transition is required due to SubVP*/
3962 if (cur_stream_status->plane_count > surface_count) {
3963 force_minimal_pipe_splitting = true;
3964 } else if (cur_stream_status->plane_count < surface_count) {
3965 force_minimal_pipe_splitting = true;
3966 *is_plane_addition = true;
3967 }
3968 }
3969
3970 return force_minimal_pipe_splitting;
3971 }
3972
3973 /**
3974 * commit_minimal_transition_state - Create a transition pipe split state
3975 *
3976 * @dc: Used to get the current state status
3977 * @transition_base_context: New transition state
3978 *
3979 * In some specific configurations, such as pipe split on multi-display with
3980 * MPO and/or Dynamic ODM, removing a plane may cause unsupported pipe
3981 * programming when moving to new planes. To mitigate those types of problems,
3982 * this function adds a transition state that minimizes pipe usage before
3983 * programming the new configuration. When adding a new plane, the current
3984 * state requires the least pipes, so it is applied without splitting. When
3985 * removing a plane, the new state requires the least pipes, so it is applied
3986 * without splitting.
3987 *
3988 * Return:
3989 * Return false if something is wrong in the transition state.
3990 */
commit_minimal_transition_state(struct dc * dc,struct dc_state * transition_base_context)3991 static bool commit_minimal_transition_state(struct dc *dc,
3992 struct dc_state *transition_base_context)
3993 {
3994 struct dc_state *transition_context = dc_create_state(dc);
3995 enum pipe_split_policy tmp_mpc_policy = 0;
3996 bool temp_dynamic_odm_policy = 0;
3997 bool temp_subvp_policy = 0;
3998 enum dc_status ret = DC_ERROR_UNEXPECTED;
3999 unsigned int i, j;
4000 unsigned int pipe_in_use = 0;
4001 bool subvp_in_use = false;
4002 bool odm_in_use = false;
4003
4004 if (!transition_context)
4005 return false;
4006 /* Setup:
4007 * Store the current ODM and MPC config in some temp variables to be
4008 * restored after we commit the transition state.
4009 */
4010
4011 /* check current pipes in use*/
4012 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4013 struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];
4014
4015 if (pipe->plane_state)
4016 pipe_in_use++;
4017 }
4018
4019 /* If SubVP is enabled and we are adding or removing planes from any main subvp
4020 * pipe, we must use the minimal transition.
4021 */
4022 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4023 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4024
4025 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
4026 subvp_in_use = true;
4027 break;
4028 }
4029 }
4030
4031 /* If ODM is enabled and we are adding or removing planes from any ODM
4032 * pipe, we must use the minimal transition.
4033 */
4034 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4035 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4036
4037 if (pipe->stream && pipe->next_odm_pipe) {
4038 odm_in_use = true;
4039 break;
4040 }
4041 }
4042
4043 /* When the OS add a new surface if we have been used all of pipes with odm combine
4044 * and mpc split feature, it need use commit_minimal_transition_state to transition safely.
4045 * After OS exit MPO, it will back to use odm and mpc split with all of pipes, we need
4046 * call it again. Otherwise return true to skip.
4047 *
4048 * Reduce the scenarios to use dc_commit_state_no_check in the stage of flip. Especially
4049 * enter/exit MPO when DCN still have enough resources.
4050 */
4051 if (pipe_in_use != dc->res_pool->pipe_count && !subvp_in_use && !odm_in_use) {
4052 dc_release_state(transition_context);
4053 return true;
4054 }
4055
4056 if (!dc->config.is_vmin_only_asic) {
4057 tmp_mpc_policy = dc->debug.pipe_split_policy;
4058 dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
4059 }
4060
4061 temp_dynamic_odm_policy = dc->debug.enable_single_display_2to1_odm_policy;
4062 dc->debug.enable_single_display_2to1_odm_policy = false;
4063
4064 temp_subvp_policy = dc->debug.force_disable_subvp;
4065 dc->debug.force_disable_subvp = true;
4066
4067 dc_resource_state_copy_construct(transition_base_context, transition_context);
4068
4069 /* commit minimal state */
4070 if (dc->res_pool->funcs->validate_bandwidth(dc, transition_context, false)) {
4071 for (i = 0; i < transition_context->stream_count; i++) {
4072 struct dc_stream_status *stream_status = &transition_context->stream_status[i];
4073
4074 for (j = 0; j < stream_status->plane_count; j++) {
4075 struct dc_plane_state *plane_state = stream_status->plane_states[j];
4076
4077 /* force vsync flip when reconfiguring pipes to prevent underflow
4078 * and corruption
4079 */
4080 plane_state->flip_immediate = false;
4081 }
4082 }
4083
4084 ret = dc_commit_state_no_check(dc, transition_context);
4085 }
4086
4087 /* always release as dc_commit_state_no_check retains in good case */
4088 dc_release_state(transition_context);
4089
4090 /* TearDown:
4091 * Restore original configuration for ODM and MPO.
4092 */
4093 if (!dc->config.is_vmin_only_asic)
4094 dc->debug.pipe_split_policy = tmp_mpc_policy;
4095
4096 dc->debug.enable_single_display_2to1_odm_policy = temp_dynamic_odm_policy;
4097 dc->debug.force_disable_subvp = temp_subvp_policy;
4098
4099 if (ret != DC_OK) {
4100 /* this should never happen */
4101 BREAK_TO_DEBUGGER();
4102 return false;
4103 }
4104
4105 /* force full surface update */
4106 for (i = 0; i < dc->current_state->stream_count; i++) {
4107 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
4108 dc->current_state->stream_status[i].plane_states[j]->update_flags.raw = 0xFFFFFFFF;
4109 }
4110 }
4111
4112 return true;
4113 }
4114
4115 /**
4116 * update_seamless_boot_flags() - Helper function for updating seamless boot flags
4117 *
4118 * @dc: Current DC state
4119 * @context: New DC state to be programmed
4120 * @surface_count: Number of surfaces that have an updated
4121 * @stream: Corresponding stream to be updated in the current flip
4122 *
4123 * Updating seamless boot flags do not need to be part of the commit sequence. This
4124 * helper function will update the seamless boot flags on each flip (if required)
4125 * outside of the HW commit sequence (fast or slow).
4126 *
4127 * Return: void
4128 */
update_seamless_boot_flags(struct dc * dc,struct dc_state * context,int surface_count,struct dc_stream_state * stream)4129 static void update_seamless_boot_flags(struct dc *dc,
4130 struct dc_state *context,
4131 int surface_count,
4132 struct dc_stream_state *stream)
4133 {
4134 if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
4135 /* Optimize seamless boot flag keeps clocks and watermarks high until
4136 * first flip. After first flip, optimization is required to lower
4137 * bandwidth. Important to note that it is expected UEFI will
4138 * only light up a single display on POST, therefore we only expect
4139 * one stream with seamless boot flag set.
4140 */
4141 if (stream->apply_seamless_boot_optimization) {
4142 stream->apply_seamless_boot_optimization = false;
4143
4144 if (get_seamless_boot_stream_count(context) == 0)
4145 dc->optimized_required = true;
4146 }
4147 }
4148 }
4149
populate_fast_updates(struct dc_fast_update * fast_update,struct dc_surface_update * srf_updates,int surface_count,struct dc_stream_update * stream_update)4150 static void populate_fast_updates(struct dc_fast_update *fast_update,
4151 struct dc_surface_update *srf_updates,
4152 int surface_count,
4153 struct dc_stream_update *stream_update)
4154 {
4155 int i = 0;
4156
4157 if (stream_update) {
4158 fast_update[0].out_transfer_func = stream_update->out_transfer_func;
4159 fast_update[0].output_csc_transform = stream_update->output_csc_transform;
4160 }
4161
4162 for (i = 0; i < surface_count; i++) {
4163 fast_update[i].flip_addr = srf_updates[i].flip_addr;
4164 fast_update[i].gamma = srf_updates[i].gamma;
4165 fast_update[i].gamut_remap_matrix = srf_updates[i].gamut_remap_matrix;
4166 fast_update[i].input_csc_color_matrix = srf_updates[i].input_csc_color_matrix;
4167 fast_update[i].coeff_reduction_factor = srf_updates[i].coeff_reduction_factor;
4168 }
4169 }
4170
fast_updates_exist(struct dc_fast_update * fast_update,int surface_count)4171 static bool fast_updates_exist(struct dc_fast_update *fast_update, int surface_count)
4172 {
4173 int i;
4174
4175 if (fast_update[0].out_transfer_func ||
4176 fast_update[0].output_csc_transform)
4177 return true;
4178
4179 for (i = 0; i < surface_count; i++) {
4180 if (fast_update[i].flip_addr ||
4181 fast_update[i].gamma ||
4182 fast_update[i].gamut_remap_matrix ||
4183 fast_update[i].input_csc_color_matrix ||
4184 fast_update[i].coeff_reduction_factor)
4185 return true;
4186 }
4187
4188 return false;
4189 }
4190
full_update_required(struct dc * dc,struct dc_surface_update * srf_updates,int surface_count,struct dc_stream_update * stream_update,struct dc_stream_state * stream)4191 static bool full_update_required(struct dc *dc,
4192 struct dc_surface_update *srf_updates,
4193 int surface_count,
4194 struct dc_stream_update *stream_update,
4195 struct dc_stream_state *stream)
4196 {
4197
4198 int i;
4199 struct dc_stream_status *stream_status;
4200 const struct dc_state *context = dc->current_state;
4201
4202 for (i = 0; i < surface_count; i++) {
4203 if (srf_updates &&
4204 (srf_updates[i].plane_info ||
4205 srf_updates[i].scaling_info ||
4206 (srf_updates[i].hdr_mult.value &&
4207 srf_updates[i].hdr_mult.value != srf_updates->surface->hdr_mult.value) ||
4208 srf_updates[i].in_transfer_func ||
4209 srf_updates[i].func_shaper ||
4210 srf_updates[i].lut3d_func ||
4211 srf_updates[i].blend_tf ||
4212 srf_updates[i].surface->force_full_update ||
4213 (srf_updates[i].flip_addr &&
4214 srf_updates[i].flip_addr->address.tmz_surface != srf_updates[i].surface->address.tmz_surface) ||
4215 !is_surface_in_context(context, srf_updates[i].surface)))
4216 return true;
4217 }
4218
4219 if (stream_update &&
4220 (((stream_update->src.height != 0 && stream_update->src.width != 0) ||
4221 (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
4222 stream_update->integer_scaling_update) ||
4223 stream_update->hdr_static_metadata ||
4224 stream_update->abm_level ||
4225 stream_update->periodic_interrupt ||
4226 stream_update->vrr_infopacket ||
4227 stream_update->vsc_infopacket ||
4228 stream_update->vsp_infopacket ||
4229 stream_update->hfvsif_infopacket ||
4230 stream_update->vtem_infopacket ||
4231 stream_update->adaptive_sync_infopacket ||
4232 stream_update->dpms_off ||
4233 stream_update->allow_freesync ||
4234 stream_update->vrr_active_variable ||
4235 stream_update->vrr_active_fixed ||
4236 stream_update->gamut_remap ||
4237 stream_update->output_color_space ||
4238 stream_update->dither_option ||
4239 stream_update->wb_update ||
4240 stream_update->dsc_config ||
4241 stream_update->mst_bw_update ||
4242 stream_update->func_shaper ||
4243 stream_update->lut3d_func ||
4244 stream_update->pending_test_pattern ||
4245 stream_update->crtc_timing_adjust))
4246 return true;
4247
4248 if (stream) {
4249 stream_status = dc_stream_get_status(stream);
4250 if (stream_status == NULL || stream_status->plane_count != surface_count)
4251 return true;
4252 }
4253 if (dc->idle_optimizations_allowed)
4254 return true;
4255
4256 return false;
4257 }
4258
fast_update_only(struct dc * dc,struct dc_fast_update * fast_update,struct dc_surface_update * srf_updates,int surface_count,struct dc_stream_update * stream_update,struct dc_stream_state * stream)4259 static bool fast_update_only(struct dc *dc,
4260 struct dc_fast_update *fast_update,
4261 struct dc_surface_update *srf_updates,
4262 int surface_count,
4263 struct dc_stream_update *stream_update,
4264 struct dc_stream_state *stream)
4265 {
4266 return fast_updates_exist(fast_update, surface_count)
4267 && !full_update_required(dc, srf_updates, surface_count, stream_update, stream);
4268 }
4269
dc_update_planes_and_stream(struct dc * dc,struct dc_surface_update * srf_updates,int surface_count,struct dc_stream_state * stream,struct dc_stream_update * stream_update)4270 bool dc_update_planes_and_stream(struct dc *dc,
4271 struct dc_surface_update *srf_updates, int surface_count,
4272 struct dc_stream_state *stream,
4273 struct dc_stream_update *stream_update)
4274 {
4275 struct dc_state *context;
4276 enum surface_update_type update_type;
4277 int i;
4278 struct mall_temp_config mall_temp_config;
4279 struct dc_fast_update fast_update[MAX_SURFACES] = {0};
4280
4281 /* In cases where MPO and split or ODM are used transitions can
4282 * cause underflow. Apply stream configuration with minimal pipe
4283 * split first to avoid unsupported transitions for active pipes.
4284 */
4285 bool force_minimal_pipe_splitting = 0;
4286 bool is_plane_addition = 0;
4287
4288 populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);
4289 force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes(
4290 dc,
4291 stream,
4292 surface_count,
4293 &is_plane_addition);
4294
4295 /* on plane addition, minimal state is the current one */
4296 if (force_minimal_pipe_splitting && is_plane_addition &&
4297 !commit_minimal_transition_state(dc, dc->current_state))
4298 return false;
4299
4300 if (!update_planes_and_stream_state(
4301 dc,
4302 srf_updates,
4303 surface_count,
4304 stream,
4305 stream_update,
4306 &update_type,
4307 &context))
4308 return false;
4309
4310 /* on plane removal, minimal state is the new one */
4311 if (force_minimal_pipe_splitting && !is_plane_addition) {
4312 /* Since all phantom pipes are removed in full validation,
4313 * we have to save and restore the subvp/mall config when
4314 * we do a minimal transition since the flags marking the
4315 * pipe as subvp/phantom will be cleared (dc copy constructor
4316 * creates a shallow copy).
4317 */
4318 if (dc->res_pool->funcs->save_mall_state)
4319 dc->res_pool->funcs->save_mall_state(dc, context, &mall_temp_config);
4320 if (!commit_minimal_transition_state(dc, context)) {
4321 dc_release_state(context);
4322 return false;
4323 }
4324 if (dc->res_pool->funcs->restore_mall_state)
4325 dc->res_pool->funcs->restore_mall_state(dc, context, &mall_temp_config);
4326
4327 /* If we do a minimal transition with plane removal and the context
4328 * has subvp we also have to retain back the phantom stream / planes
4329 * since the refcount is decremented as part of the min transition
4330 * (we commit a state with no subvp, so the phantom streams / planes
4331 * had to be removed).
4332 */
4333 if (dc->res_pool->funcs->retain_phantom_pipes)
4334 dc->res_pool->funcs->retain_phantom_pipes(dc, context);
4335 update_type = UPDATE_TYPE_FULL;
4336 }
4337
4338 update_seamless_boot_flags(dc, context, surface_count, stream);
4339 if (fast_update_only(dc, fast_update, srf_updates, surface_count, stream_update, stream) &&
4340 !dc->debug.enable_legacy_fast_update) {
4341 commit_planes_for_stream_fast(dc,
4342 srf_updates,
4343 surface_count,
4344 stream,
4345 stream_update,
4346 update_type,
4347 context);
4348 } else {
4349 if (!stream_update &&
4350 dc->hwss.is_pipe_topology_transition_seamless &&
4351 !dc->hwss.is_pipe_topology_transition_seamless(
4352 dc, dc->current_state, context)) {
4353
4354 DC_LOG_ERROR("performing non-seamless pipe topology transition with surface only update!\n");
4355 BREAK_TO_DEBUGGER();
4356 }
4357 commit_planes_for_stream(
4358 dc,
4359 srf_updates,
4360 surface_count,
4361 stream,
4362 stream_update,
4363 update_type,
4364 context);
4365 }
4366
4367 if (dc->current_state != context) {
4368
4369 /* Since memory free requires elevated IRQL, an interrupt
4370 * request is generated by mem free. If this happens
4371 * between freeing and reassigning the context, our vsync
4372 * interrupt will call into dc and cause a memory
4373 * corruption BSOD. Hence, we first reassign the context,
4374 * then free the old context.
4375 */
4376
4377 struct dc_state *old = dc->current_state;
4378
4379 dc->current_state = context;
4380 dc_release_state(old);
4381
4382 // clear any forced full updates
4383 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4384 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4385
4386 if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
4387 pipe_ctx->plane_state->force_full_update = false;
4388 }
4389 }
4390 return true;
4391 }
4392
dc_commit_updates_for_stream(struct dc * dc,struct dc_surface_update * srf_updates,int surface_count,struct dc_stream_state * stream,struct dc_stream_update * stream_update,struct dc_state * state)4393 void dc_commit_updates_for_stream(struct dc *dc,
4394 struct dc_surface_update *srf_updates,
4395 int surface_count,
4396 struct dc_stream_state *stream,
4397 struct dc_stream_update *stream_update,
4398 struct dc_state *state)
4399 {
4400 const struct dc_stream_status *stream_status;
4401 enum surface_update_type update_type;
4402 struct dc_state *context;
4403 struct dc_context *dc_ctx = dc->ctx;
4404 int i, j;
4405 struct dc_fast_update fast_update[MAX_SURFACES] = {0};
4406
4407 populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);
4408 stream_status = dc_stream_get_status(stream);
4409 context = dc->current_state;
4410
4411 update_type = dc_check_update_surfaces_for_stream(
4412 dc, srf_updates, surface_count, stream_update, stream_status);
4413
4414 /* TODO: Since change commit sequence can have a huge impact,
4415 * we decided to only enable it for DCN3x. However, as soon as
4416 * we get more confident about this change we'll need to enable
4417 * the new sequence for all ASICs.
4418 */
4419 if (dc->ctx->dce_version >= DCN_VERSION_3_2) {
4420 /*
4421 * Previous frame finished and HW is ready for optimization.
4422 */
4423 if (update_type == UPDATE_TYPE_FAST)
4424 dc_post_update_surfaces_to_stream(dc);
4425
4426 dc_update_planes_and_stream(dc, srf_updates,
4427 surface_count, stream,
4428 stream_update);
4429 return;
4430 }
4431
4432 if (update_type >= update_surface_trace_level)
4433 update_surface_trace(dc, srf_updates, surface_count);
4434
4435
4436 if (update_type >= UPDATE_TYPE_FULL) {
4437
4438 /* initialize scratch memory for building context */
4439 context = dc_create_state(dc);
4440 if (context == NULL) {
4441 DC_ERROR("Failed to allocate new validate context!\n");
4442 return;
4443 }
4444
4445 dc_resource_state_copy_construct(state, context);
4446
4447 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4448 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
4449 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4450
4451 if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
4452 new_pipe->plane_state->force_full_update = true;
4453 }
4454 } else if (update_type == UPDATE_TYPE_FAST) {
4455 /*
4456 * Previous frame finished and HW is ready for optimization.
4457 */
4458 dc_post_update_surfaces_to_stream(dc);
4459 }
4460
4461
4462 for (i = 0; i < surface_count; i++) {
4463 struct dc_plane_state *surface = srf_updates[i].surface;
4464
4465 copy_surface_update_to_plane(surface, &srf_updates[i]);
4466
4467 if (update_type >= UPDATE_TYPE_MED) {
4468 for (j = 0; j < dc->res_pool->pipe_count; j++) {
4469 struct pipe_ctx *pipe_ctx =
4470 &context->res_ctx.pipe_ctx[j];
4471
4472 if (pipe_ctx->plane_state != surface)
4473 continue;
4474
4475 resource_build_scaling_params(pipe_ctx);
4476 }
4477 }
4478 }
4479
4480 copy_stream_update_to_stream(dc, context, stream, stream_update);
4481
4482 if (update_type >= UPDATE_TYPE_FULL) {
4483 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
4484 DC_ERROR("Mode validation failed for stream update!\n");
4485 dc_release_state(context);
4486 return;
4487 }
4488 }
4489
4490 TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
4491
4492 update_seamless_boot_flags(dc, context, surface_count, stream);
4493 if (fast_update_only(dc, fast_update, srf_updates, surface_count, stream_update, stream) &&
4494 !dc->debug.enable_legacy_fast_update) {
4495 commit_planes_for_stream_fast(dc,
4496 srf_updates,
4497 surface_count,
4498 stream,
4499 stream_update,
4500 update_type,
4501 context);
4502 } else {
4503 commit_planes_for_stream(
4504 dc,
4505 srf_updates,
4506 surface_count,
4507 stream,
4508 stream_update,
4509 update_type,
4510 context);
4511 }
4512 /*update current_State*/
4513 if (dc->current_state != context) {
4514
4515 struct dc_state *old = dc->current_state;
4516
4517 dc->current_state = context;
4518 dc_release_state(old);
4519
4520 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4521 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4522
4523 if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
4524 pipe_ctx->plane_state->force_full_update = false;
4525 }
4526 }
4527
4528 /* Legacy optimization path for DCE. */
4529 if (update_type >= UPDATE_TYPE_FULL && dc_ctx->dce_version < DCE_VERSION_MAX) {
4530 dc_post_update_surfaces_to_stream(dc);
4531 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
4532 }
4533
4534 return;
4535
4536 }
4537
dc_get_current_stream_count(struct dc * dc)4538 uint8_t dc_get_current_stream_count(struct dc *dc)
4539 {
4540 return dc->current_state->stream_count;
4541 }
4542
dc_get_stream_at_index(struct dc * dc,uint8_t i)4543 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
4544 {
4545 if (i < dc->current_state->stream_count)
4546 return dc->current_state->streams[i];
4547 return NULL;
4548 }
4549
dc_interrupt_to_irq_source(struct dc * dc,uint32_t src_id,uint32_t ext_id)4550 enum dc_irq_source dc_interrupt_to_irq_source(
4551 struct dc *dc,
4552 uint32_t src_id,
4553 uint32_t ext_id)
4554 {
4555 return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
4556 }
4557
4558 /*
4559 * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
4560 */
dc_interrupt_set(struct dc * dc,enum dc_irq_source src,bool enable)4561 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
4562 {
4563
4564 if (dc == NULL)
4565 return false;
4566
4567 return dal_irq_service_set(dc->res_pool->irqs, src, enable);
4568 }
4569
dc_interrupt_ack(struct dc * dc,enum dc_irq_source src)4570 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
4571 {
4572 dal_irq_service_ack(dc->res_pool->irqs, src);
4573 }
4574
dc_power_down_on_boot(struct dc * dc)4575 void dc_power_down_on_boot(struct dc *dc)
4576 {
4577 if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
4578 dc->hwss.power_down_on_boot)
4579 dc->hwss.power_down_on_boot(dc);
4580 }
4581
dc_set_power_state(struct dc * dc,enum dc_acpi_cm_power_state power_state)4582 void dc_set_power_state(
4583 struct dc *dc,
4584 enum dc_acpi_cm_power_state power_state)
4585 {
4586 struct kref refcount;
4587 struct display_mode_lib *dml;
4588
4589 if (!dc->current_state)
4590 return;
4591
4592 switch (power_state) {
4593 case DC_ACPI_CM_POWER_STATE_D0:
4594 dc_resource_state_construct(dc, dc->current_state);
4595
4596 dc_z10_restore(dc);
4597
4598 dc->hwss.init_hw(dc);
4599
4600 if (dc->hwss.init_sys_ctx != NULL &&
4601 dc->vm_pa_config.valid) {
4602 dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
4603 }
4604
4605 break;
4606 default:
4607 ASSERT(dc->current_state->stream_count == 0);
4608 /* Zero out the current context so that on resume we start with
4609 * clean state, and dc hw programming optimizations will not
4610 * cause any trouble.
4611 */
4612 dml = kzalloc(sizeof(struct display_mode_lib),
4613 GFP_KERNEL);
4614
4615 ASSERT(dml);
4616 if (!dml)
4617 return;
4618
4619 /* Preserve refcount */
4620 refcount = dc->current_state->refcount;
4621 /* Preserve display mode lib */
4622 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
4623
4624 dc_resource_state_destruct(dc->current_state);
4625 memset(dc->current_state, 0,
4626 sizeof(*dc->current_state));
4627
4628 dc->current_state->refcount = refcount;
4629 dc->current_state->bw_ctx.dml = *dml;
4630
4631 kfree(dml);
4632
4633 break;
4634 }
4635 }
4636
dc_resume(struct dc * dc)4637 void dc_resume(struct dc *dc)
4638 {
4639 uint32_t i;
4640
4641 for (i = 0; i < dc->link_count; i++)
4642 dc->link_srv->resume(dc->links[i]);
4643 }
4644
dc_is_dmcu_initialized(struct dc * dc)4645 bool dc_is_dmcu_initialized(struct dc *dc)
4646 {
4647 struct dmcu *dmcu = dc->res_pool->dmcu;
4648
4649 if (dmcu)
4650 return dmcu->funcs->is_dmcu_initialized(dmcu);
4651 return false;
4652 }
4653
get_clock_requirements_for_state(struct dc_state * state,struct AsicStateEx * info)4654 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
4655 {
4656 info->displayClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
4657 info->engineClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
4658 info->memoryClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
4659 info->maxSupportedDppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
4660 info->dppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
4661 info->socClock = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
4662 info->dcfClockDeepSleep = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
4663 info->fClock = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
4664 info->phyClock = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
4665 }
dc_set_clock(struct dc * dc,enum dc_clock_type clock_type,uint32_t clk_khz,uint32_t stepping)4666 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
4667 {
4668 if (dc->hwss.set_clock)
4669 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
4670 return DC_ERROR_UNEXPECTED;
4671 }
dc_get_clock(struct dc * dc,enum dc_clock_type clock_type,struct dc_clock_config * clock_cfg)4672 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
4673 {
4674 if (dc->hwss.get_clock)
4675 dc->hwss.get_clock(dc, clock_type, clock_cfg);
4676 }
4677
4678 /* enable/disable eDP PSR without specify stream for eDP */
dc_set_psr_allow_active(struct dc * dc,bool enable)4679 bool dc_set_psr_allow_active(struct dc *dc, bool enable)
4680 {
4681 int i;
4682 bool allow_active;
4683
4684 for (i = 0; i < dc->current_state->stream_count ; i++) {
4685 struct dc_link *link;
4686 struct dc_stream_state *stream = dc->current_state->streams[i];
4687
4688 link = stream->link;
4689 if (!link)
4690 continue;
4691
4692 if (link->psr_settings.psr_feature_enabled) {
4693 if (enable && !link->psr_settings.psr_allow_active) {
4694 allow_active = true;
4695 if (!dc_link_set_psr_allow_active(link, &allow_active, false, false, NULL))
4696 return false;
4697 } else if (!enable && link->psr_settings.psr_allow_active) {
4698 allow_active = false;
4699 if (!dc_link_set_psr_allow_active(link, &allow_active, true, false, NULL))
4700 return false;
4701 }
4702 }
4703 }
4704
4705 return true;
4706 }
4707
dc_allow_idle_optimizations(struct dc * dc,bool allow)4708 void dc_allow_idle_optimizations(struct dc *dc, bool allow)
4709 {
4710 if (dc->debug.disable_idle_power_optimizations)
4711 return;
4712
4713 if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)
4714 if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))
4715 return;
4716
4717 if (allow == dc->idle_optimizations_allowed)
4718 return;
4719
4720 if (dc->hwss.apply_idle_power_optimizations && dc->clk_mgr != NULL &&
4721 dc->hwss.apply_idle_power_optimizations(dc, allow))
4722 dc->idle_optimizations_allowed = allow;
4723 }
4724
4725 /* set min and max memory clock to lowest and highest DPM level, respectively */
dc_unlock_memory_clock_frequency(struct dc * dc)4726 void dc_unlock_memory_clock_frequency(struct dc *dc)
4727 {
4728 if (dc->clk_mgr->funcs->set_hard_min_memclk)
4729 dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
4730
4731 if (dc->clk_mgr->funcs->set_hard_max_memclk)
4732 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
4733 }
4734
4735 /* set min memory clock to the min required for current mode, max to maxDPM */
dc_lock_memory_clock_frequency(struct dc * dc)4736 void dc_lock_memory_clock_frequency(struct dc *dc)
4737 {
4738 if (dc->clk_mgr->funcs->get_memclk_states_from_smu)
4739 dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
4740
4741 if (dc->clk_mgr->funcs->set_hard_min_memclk)
4742 dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
4743
4744 if (dc->clk_mgr->funcs->set_hard_max_memclk)
4745 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
4746 }
4747
blank_and_force_memclk(struct dc * dc,bool apply,unsigned int memclk_mhz)4748 static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz)
4749 {
4750 struct dc_state *context = dc->current_state;
4751 struct hubp *hubp;
4752 struct pipe_ctx *pipe;
4753 int i;
4754
4755 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4756 pipe = &context->res_ctx.pipe_ctx[i];
4757
4758 if (pipe->stream != NULL) {
4759 dc->hwss.disable_pixel_data(dc, pipe, true);
4760
4761 // wait for double buffer
4762 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);
4763 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
4764 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);
4765
4766 hubp = pipe->plane_res.hubp;
4767 hubp->funcs->set_blank_regs(hubp, true);
4768 }
4769 }
4770
4771 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz);
4772 dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz);
4773
4774 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4775 pipe = &context->res_ctx.pipe_ctx[i];
4776
4777 if (pipe->stream != NULL) {
4778 dc->hwss.disable_pixel_data(dc, pipe, false);
4779
4780 hubp = pipe->plane_res.hubp;
4781 hubp->funcs->set_blank_regs(hubp, false);
4782 }
4783 }
4784 }
4785
4786
4787 /**
4788 * dc_enable_dcmode_clk_limit() - lower clocks in dc (battery) mode
4789 * @dc: pointer to dc of the dm calling this
4790 * @enable: True = transition to DC mode, false = transition back to AC mode
4791 *
4792 * Some SoCs define additional clock limits when in DC mode, DM should
4793 * invoke this function when the platform undergoes a power source transition
4794 * so DC can apply/unapply the limit. This interface may be disruptive to
4795 * the onscreen content.
4796 *
4797 * Context: Triggered by OS through DM interface, or manually by escape calls.
4798 * Need to hold a dclock when doing so.
4799 *
4800 * Return: none (void function)
4801 *
4802 */
dc_enable_dcmode_clk_limit(struct dc * dc,bool enable)4803 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable)
4804 {
4805 unsigned int softMax = 0, maxDPM = 0, funcMin = 0, i;
4806 bool p_state_change_support;
4807
4808 if (!dc->config.dc_mode_clk_limit_support)
4809 return;
4810
4811 softMax = dc->clk_mgr->bw_params->dc_mode_softmax_memclk;
4812 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries; i++) {
4813 if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz > maxDPM)
4814 maxDPM = dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;
4815 }
4816 funcMin = (dc->clk_mgr->clks.dramclk_khz + 999) / 1000;
4817 p_state_change_support = dc->clk_mgr->clks.p_state_change_support;
4818
4819 if (enable && !dc->clk_mgr->dc_mode_softmax_enabled) {
4820 if (p_state_change_support) {
4821 if (funcMin <= softMax)
4822 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, softMax);
4823 // else: No-Op
4824 } else {
4825 if (funcMin <= softMax)
4826 blank_and_force_memclk(dc, true, softMax);
4827 // else: No-Op
4828 }
4829 } else if (!enable && dc->clk_mgr->dc_mode_softmax_enabled) {
4830 if (p_state_change_support) {
4831 if (funcMin <= softMax)
4832 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, maxDPM);
4833 // else: No-Op
4834 } else {
4835 if (funcMin <= softMax)
4836 blank_and_force_memclk(dc, true, maxDPM);
4837 // else: No-Op
4838 }
4839 }
4840 dc->clk_mgr->dc_mode_softmax_enabled = enable;
4841 }
dc_is_plane_eligible_for_idle_optimizations(struct dc * dc,struct dc_plane_state * plane,struct dc_cursor_attributes * cursor_attr)4842 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
4843 struct dc_cursor_attributes *cursor_attr)
4844 {
4845 if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane, cursor_attr))
4846 return true;
4847 return false;
4848 }
4849
4850 /* cleanup on driver unload */
dc_hardware_release(struct dc * dc)4851 void dc_hardware_release(struct dc *dc)
4852 {
4853 dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(dc);
4854
4855 if (dc->hwss.hardware_release)
4856 dc->hwss.hardware_release(dc);
4857 }
4858
dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc * dc)4859 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc)
4860 {
4861 if (dc->current_state)
4862 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down = true;
4863 }
4864
4865 /**
4866 * dc_is_dmub_outbox_supported - Check if DMUB firmware support outbox notification
4867 *
4868 * @dc: [in] dc structure
4869 *
4870 * Checks whether DMUB FW supports outbox notifications, if supported DM
4871 * should register outbox interrupt prior to actually enabling interrupts
4872 * via dc_enable_dmub_outbox
4873 *
4874 * Return:
4875 * True if DMUB FW supports outbox notifications, False otherwise
4876 */
dc_is_dmub_outbox_supported(struct dc * dc)4877 bool dc_is_dmub_outbox_supported(struct dc *dc)
4878 {
4879 switch (dc->ctx->asic_id.chip_family) {
4880
4881 case FAMILY_YELLOW_CARP:
4882 /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
4883 if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
4884 !dc->debug.dpia_debug.bits.disable_dpia)
4885 return true;
4886 break;
4887
4888 case AMDGPU_FAMILY_GC_11_0_1:
4889 case AMDGPU_FAMILY_GC_11_5_0:
4890 if (!dc->debug.dpia_debug.bits.disable_dpia)
4891 return true;
4892 break;
4893
4894 default:
4895 break;
4896 }
4897
4898 /* dmub aux needs dmub notifications to be enabled */
4899 return dc->debug.enable_dmub_aux_for_legacy_ddc;
4900
4901 }
4902
4903 /**
4904 * dc_enable_dmub_notifications - Check if dmub fw supports outbox
4905 *
4906 * @dc: [in] dc structure
4907 *
4908 * Calls dc_is_dmub_outbox_supported to check if dmub fw supports outbox
4909 * notifications. All DMs shall switch to dc_is_dmub_outbox_supported. This
4910 * API shall be removed after switching.
4911 *
4912 * Return:
4913 * True if DMUB FW supports outbox notifications, False otherwise
4914 */
dc_enable_dmub_notifications(struct dc * dc)4915 bool dc_enable_dmub_notifications(struct dc *dc)
4916 {
4917 return dc_is_dmub_outbox_supported(dc);
4918 }
4919
4920 /**
4921 * dc_enable_dmub_outbox - Enables DMUB unsolicited notification
4922 *
4923 * @dc: [in] dc structure
4924 *
4925 * Enables DMUB unsolicited notifications to x86 via outbox.
4926 */
dc_enable_dmub_outbox(struct dc * dc)4927 void dc_enable_dmub_outbox(struct dc *dc)
4928 {
4929 struct dc_context *dc_ctx = dc->ctx;
4930
4931 dmub_enable_outbox_notification(dc_ctx->dmub_srv);
4932 DC_LOG_DC("%s: dmub outbox notifications enabled\n", __func__);
4933 }
4934
4935 /**
4936 * dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message
4937 * Sets port index appropriately for legacy DDC
4938 * @dc: dc structure
4939 * @link_index: link index
4940 * @payload: aux payload
4941 *
4942 * Returns: True if successful, False if failure
4943 */
dc_process_dmub_aux_transfer_async(struct dc * dc,uint32_t link_index,struct aux_payload * payload)4944 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
4945 uint32_t link_index,
4946 struct aux_payload *payload)
4947 {
4948 uint8_t action;
4949 union dmub_rb_cmd cmd = {0};
4950
4951 ASSERT(payload->length <= 16);
4952
4953 cmd.dp_aux_access.header.type = DMUB_CMD__DP_AUX_ACCESS;
4954 cmd.dp_aux_access.header.payload_bytes = 0;
4955 /* For dpia, ddc_pin is set to NULL */
4956 if (!dc->links[link_index]->ddc->ddc_pin)
4957 cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_DPIA;
4958 else
4959 cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC;
4960
4961 cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst;
4962 cmd.dp_aux_access.aux_control.sw_crc_enabled = 0;
4963 cmd.dp_aux_access.aux_control.timeout = 0;
4964 cmd.dp_aux_access.aux_control.dpaux.address = payload->address;
4965 cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux;
4966 cmd.dp_aux_access.aux_control.dpaux.length = payload->length;
4967
4968 /* set aux action */
4969 if (payload->i2c_over_aux) {
4970 if (payload->write) {
4971 if (payload->mot)
4972 action = DP_AUX_REQ_ACTION_I2C_WRITE_MOT;
4973 else
4974 action = DP_AUX_REQ_ACTION_I2C_WRITE;
4975 } else {
4976 if (payload->mot)
4977 action = DP_AUX_REQ_ACTION_I2C_READ_MOT;
4978 else
4979 action = DP_AUX_REQ_ACTION_I2C_READ;
4980 }
4981 } else {
4982 if (payload->write)
4983 action = DP_AUX_REQ_ACTION_DPCD_WRITE;
4984 else
4985 action = DP_AUX_REQ_ACTION_DPCD_READ;
4986 }
4987
4988 cmd.dp_aux_access.aux_control.dpaux.action = action;
4989
4990 if (payload->length && payload->write) {
4991 memcpy(cmd.dp_aux_access.aux_control.dpaux.data,
4992 payload->data,
4993 payload->length
4994 );
4995 }
4996
4997 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
4998
4999 return true;
5000 }
5001
get_link_index_from_dpia_port_index(const struct dc * dc,uint8_t dpia_port_index)5002 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
5003 uint8_t dpia_port_index)
5004 {
5005 uint8_t index, link_index = 0xFF;
5006
5007 for (index = 0; index < dc->link_count; index++) {
5008 /* ddc_hw_inst has dpia port index for dpia links
5009 * and ddc instance for legacy links
5010 */
5011 if (!dc->links[index]->ddc->ddc_pin) {
5012 if (dc->links[index]->ddc_hw_inst == dpia_port_index) {
5013 link_index = index;
5014 break;
5015 }
5016 }
5017 }
5018 ASSERT(link_index != 0xFF);
5019 return link_index;
5020 }
5021
5022 /**
5023 * dc_process_dmub_set_config_async - Submits set_config command
5024 *
5025 * @dc: [in] dc structure
5026 * @link_index: [in] link_index: link index
5027 * @payload: [in] aux payload
5028 * @notify: [out] set_config immediate reply
5029 *
5030 * Submits set_config command to dmub via inbox message.
5031 *
5032 * Return:
5033 * True if successful, False if failure
5034 */
dc_process_dmub_set_config_async(struct dc * dc,uint32_t link_index,struct set_config_cmd_payload * payload,struct dmub_notification * notify)5035 bool dc_process_dmub_set_config_async(struct dc *dc,
5036 uint32_t link_index,
5037 struct set_config_cmd_payload *payload,
5038 struct dmub_notification *notify)
5039 {
5040 union dmub_rb_cmd cmd = {0};
5041 bool is_cmd_complete = true;
5042
5043 /* prepare SET_CONFIG command */
5044 cmd.set_config_access.header.type = DMUB_CMD__DPIA;
5045 cmd.set_config_access.header.sub_type = DMUB_CMD__DPIA_SET_CONFIG_ACCESS;
5046
5047 cmd.set_config_access.set_config_control.instance = dc->links[link_index]->ddc_hw_inst;
5048 cmd.set_config_access.set_config_control.cmd_pkt.msg_type = payload->msg_type;
5049 cmd.set_config_access.set_config_control.cmd_pkt.msg_data = payload->msg_data;
5050
5051 if (!dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) {
5052 /* command is not processed by dmub */
5053 notify->sc_status = SET_CONFIG_UNKNOWN_ERROR;
5054 return is_cmd_complete;
5055 }
5056
5057 /* command processed by dmub, if ret_status is 1, it is completed instantly */
5058 if (cmd.set_config_access.header.ret_status == 1)
5059 notify->sc_status = cmd.set_config_access.set_config_control.immed_status;
5060 else
5061 /* cmd pending, will receive notification via outbox */
5062 is_cmd_complete = false;
5063
5064 return is_cmd_complete;
5065 }
5066
5067 /**
5068 * dc_process_dmub_set_mst_slots - Submits MST solt allocation
5069 *
5070 * @dc: [in] dc structure
5071 * @link_index: [in] link index
5072 * @mst_alloc_slots: [in] mst slots to be allotted
5073 * @mst_slots_in_use: [out] mst slots in use returned in failure case
5074 *
5075 * Submits mst slot allocation command to dmub via inbox message
5076 *
5077 * Return:
5078 * DC_OK if successful, DC_ERROR if failure
5079 */
dc_process_dmub_set_mst_slots(const struct dc * dc,uint32_t link_index,uint8_t mst_alloc_slots,uint8_t * mst_slots_in_use)5080 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
5081 uint32_t link_index,
5082 uint8_t mst_alloc_slots,
5083 uint8_t *mst_slots_in_use)
5084 {
5085 union dmub_rb_cmd cmd = {0};
5086
5087 /* prepare MST_ALLOC_SLOTS command */
5088 cmd.set_mst_alloc_slots.header.type = DMUB_CMD__DPIA;
5089 cmd.set_mst_alloc_slots.header.sub_type = DMUB_CMD__DPIA_MST_ALLOC_SLOTS;
5090
5091 cmd.set_mst_alloc_slots.mst_slots_control.instance = dc->links[link_index]->ddc_hw_inst;
5092 cmd.set_mst_alloc_slots.mst_slots_control.mst_alloc_slots = mst_alloc_slots;
5093
5094 if (!dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
5095 /* command is not processed by dmub */
5096 return DC_ERROR_UNEXPECTED;
5097
5098 /* command processed by dmub, if ret_status is 1 */
5099 if (cmd.set_config_access.header.ret_status != 1)
5100 /* command processing error */
5101 return DC_ERROR_UNEXPECTED;
5102
5103 /* command processed and we have a status of 2, mst not enabled in dpia */
5104 if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 2)
5105 return DC_FAIL_UNSUPPORTED_1;
5106
5107 /* previously configured mst alloc and used slots did not match */
5108 if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 3) {
5109 *mst_slots_in_use = cmd.set_mst_alloc_slots.mst_slots_control.mst_slots_in_use;
5110 return DC_NOT_SUPPORTED;
5111 }
5112
5113 return DC_OK;
5114 }
5115
5116 /**
5117 * dc_process_dmub_dpia_hpd_int_enable - Submits DPIA DPD interruption
5118 *
5119 * @dc: [in] dc structure
5120 * @hpd_int_enable: [in] 1 for hpd int enable, 0 to disable
5121 *
5122 * Submits dpia hpd int enable command to dmub via inbox message
5123 */
dc_process_dmub_dpia_hpd_int_enable(const struct dc * dc,uint32_t hpd_int_enable)5124 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
5125 uint32_t hpd_int_enable)
5126 {
5127 union dmub_rb_cmd cmd = {0};
5128
5129 cmd.dpia_hpd_int_enable.header.type = DMUB_CMD__DPIA_HPD_INT_ENABLE;
5130 cmd.dpia_hpd_int_enable.enable = hpd_int_enable;
5131
5132 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
5133
5134 DC_LOG_DEBUG("%s: hpd_int_enable(%d)\n", __func__, hpd_int_enable);
5135 }
5136
5137 /**
5138 * dc_print_dmub_diagnostic_data - Print DMUB diagnostic data for debugging
5139 *
5140 * @dc: [in] dc structure
5141 *
5142 *
5143 */
dc_print_dmub_diagnostic_data(const struct dc * dc)5144 void dc_print_dmub_diagnostic_data(const struct dc *dc)
5145 {
5146 dc_dmub_srv_log_diagnostic_data(dc->ctx->dmub_srv);
5147 }
5148
5149 /**
5150 * dc_disable_accelerated_mode - disable accelerated mode
5151 * @dc: dc structure
5152 */
dc_disable_accelerated_mode(struct dc * dc)5153 void dc_disable_accelerated_mode(struct dc *dc)
5154 {
5155 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0);
5156 }
5157
5158
5159 /**
5160 * dc_notify_vsync_int_state - notifies vsync enable/disable state
5161 * @dc: dc structure
5162 * @stream: stream where vsync int state changed
5163 * @enable: whether vsync is enabled or disabled
5164 *
5165 * Called when vsync is enabled/disabled Will notify DMUB to start/stop ABM
5166 * interrupts after steady state is reached.
5167 */
dc_notify_vsync_int_state(struct dc * dc,struct dc_stream_state * stream,bool enable)5168 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable)
5169 {
5170 int i;
5171 int edp_num;
5172 struct pipe_ctx *pipe = NULL;
5173 struct dc_link *link = stream->sink->link;
5174 struct dc_link *edp_links[MAX_NUM_EDP];
5175
5176
5177 if (link->psr_settings.psr_feature_enabled)
5178 return;
5179
5180 if (link->replay_settings.replay_feature_enabled)
5181 return;
5182
5183 /*find primary pipe associated with stream*/
5184 for (i = 0; i < MAX_PIPES; i++) {
5185 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
5186
5187 if (pipe->stream == stream && pipe->stream_res.tg)
5188 break;
5189 }
5190
5191 if (i == MAX_PIPES) {
5192 ASSERT(0);
5193 return;
5194 }
5195
5196 dc_get_edp_links(dc, edp_links, &edp_num);
5197
5198 /* Determine panel inst */
5199 for (i = 0; i < edp_num; i++) {
5200 if (edp_links[i] == link)
5201 break;
5202 }
5203
5204 if (i == edp_num) {
5205 return;
5206 }
5207
5208 if (pipe->stream_res.abm && pipe->stream_res.abm->funcs->set_abm_pause)
5209 pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst);
5210 }
5211
5212 /*****************************************************************************
5213 * dc_abm_save_restore() - Interface to DC for save+pause and restore+un-pause
5214 * ABM
5215 * @dc: dc structure
5216 * @stream: stream where vsync int state changed
5217 * @pData: abm hw states
5218 *
5219 ****************************************************************************/
dc_abm_save_restore(struct dc * dc,struct dc_stream_state * stream,struct abm_save_restore * pData)5220 bool dc_abm_save_restore(
5221 struct dc *dc,
5222 struct dc_stream_state *stream,
5223 struct abm_save_restore *pData)
5224 {
5225 int i;
5226 int edp_num;
5227 struct pipe_ctx *pipe = NULL;
5228 struct dc_link *link = stream->sink->link;
5229 struct dc_link *edp_links[MAX_NUM_EDP];
5230
5231
5232 /*find primary pipe associated with stream*/
5233 for (i = 0; i < MAX_PIPES; i++) {
5234 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
5235
5236 if (pipe->stream == stream && pipe->stream_res.tg)
5237 break;
5238 }
5239
5240 if (i == MAX_PIPES) {
5241 ASSERT(0);
5242 return false;
5243 }
5244
5245 dc_get_edp_links(dc, edp_links, &edp_num);
5246
5247 /* Determine panel inst */
5248 for (i = 0; i < edp_num; i++)
5249 if (edp_links[i] == link)
5250 break;
5251
5252 if (i == edp_num)
5253 return false;
5254
5255 if (pipe->stream_res.abm &&
5256 pipe->stream_res.abm->funcs->save_restore)
5257 return pipe->stream_res.abm->funcs->save_restore(
5258 pipe->stream_res.abm,
5259 i,
5260 pData);
5261 return false;
5262 }
5263
dc_query_current_properties(struct dc * dc,struct dc_current_properties * properties)5264 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties)
5265 {
5266 unsigned int i;
5267 bool subvp_in_use = false;
5268
5269 for (i = 0; i < dc->current_state->stream_count; i++) {
5270 if (dc->current_state->streams[i]->mall_stream_config.type != SUBVP_NONE) {
5271 subvp_in_use = true;
5272 break;
5273 }
5274 }
5275 properties->cursor_size_limit = subvp_in_use ? 64 : dc->caps.max_cursor_size;
5276 }
5277
5278 /**
5279 *****************************************************************************
5280 * dc_set_edp_power() - DM controls eDP power to be ON/OFF
5281 *
5282 * Called when DM wants to power on/off eDP.
5283 * Only work on links with flag skip_implict_edp_power_control is set.
5284 *
5285 *****************************************************************************
5286 */
dc_set_edp_power(const struct dc * dc,struct dc_link * edp_link,bool powerOn)5287 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
5288 bool powerOn)
5289 {
5290 if (edp_link->connector_signal != SIGNAL_TYPE_EDP)
5291 return;
5292
5293 if (edp_link->skip_implict_edp_power_control == false)
5294 return;
5295
5296 edp_link->dc->link_srv->edp_set_panel_power(edp_link, powerOn);
5297 }
5298
5299