xref: /openbmc/linux/drivers/i2c/busses/i2c-davinci.c (revision 59738ab2)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * TI DAVINCI I2C adapter driver.
4  *
5  * Copyright (C) 2006 Texas Instruments.
6  * Copyright (C) 2007 MontaVista Software Inc.
7  *
8  * Updated by Vinod & Sudhakar Feb 2005
9  *
10  * ----------------------------------------------------------------------------
11  *
12  * ----------------------------------------------------------------------------
13  */
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/clk.h>
19 #include <linux/errno.h>
20 #include <linux/sched.h>
21 #include <linux/err.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/io.h>
25 #include <linux/slab.h>
26 #include <linux/cpufreq.h>
27 #include <linux/gpio/consumer.h>
28 #include <linux/of.h>
29 #include <linux/platform_data/i2c-davinci.h>
30 #include <linux/pm_runtime.h>
31 
32 /* ----- global defines ----------------------------------------------- */
33 
34 #define DAVINCI_I2C_TIMEOUT	(1*HZ)
35 #define DAVINCI_I2C_MAX_TRIES	2
36 #define DAVINCI_I2C_OWN_ADDRESS	0x08
37 #define I2C_DAVINCI_INTR_ALL    (DAVINCI_I2C_IMR_SCD | \
38 				 DAVINCI_I2C_IMR_ARDY | \
39 				 DAVINCI_I2C_IMR_NACK | \
40 				 DAVINCI_I2C_IMR_AL)
41 
42 #define DAVINCI_I2C_OAR_REG	0x00
43 #define DAVINCI_I2C_IMR_REG	0x04
44 #define DAVINCI_I2C_STR_REG	0x08
45 #define DAVINCI_I2C_CLKL_REG	0x0c
46 #define DAVINCI_I2C_CLKH_REG	0x10
47 #define DAVINCI_I2C_CNT_REG	0x14
48 #define DAVINCI_I2C_DRR_REG	0x18
49 #define DAVINCI_I2C_SAR_REG	0x1c
50 #define DAVINCI_I2C_DXR_REG	0x20
51 #define DAVINCI_I2C_MDR_REG	0x24
52 #define DAVINCI_I2C_IVR_REG	0x28
53 #define DAVINCI_I2C_EMDR_REG	0x2c
54 #define DAVINCI_I2C_PSC_REG	0x30
55 #define DAVINCI_I2C_FUNC_REG	0x48
56 #define DAVINCI_I2C_DIR_REG	0x4c
57 #define DAVINCI_I2C_DIN_REG	0x50
58 #define DAVINCI_I2C_DOUT_REG	0x54
59 #define DAVINCI_I2C_DSET_REG	0x58
60 #define DAVINCI_I2C_DCLR_REG	0x5c
61 
62 #define DAVINCI_I2C_IVR_AAS	0x07
63 #define DAVINCI_I2C_IVR_SCD	0x06
64 #define DAVINCI_I2C_IVR_XRDY	0x05
65 #define DAVINCI_I2C_IVR_RDR	0x04
66 #define DAVINCI_I2C_IVR_ARDY	0x03
67 #define DAVINCI_I2C_IVR_NACK	0x02
68 #define DAVINCI_I2C_IVR_AL	0x01
69 
70 #define DAVINCI_I2C_STR_BB	BIT(12)
71 #define DAVINCI_I2C_STR_RSFULL	BIT(11)
72 #define DAVINCI_I2C_STR_SCD	BIT(5)
73 #define DAVINCI_I2C_STR_ARDY	BIT(2)
74 #define DAVINCI_I2C_STR_NACK	BIT(1)
75 #define DAVINCI_I2C_STR_AL	BIT(0)
76 
77 #define DAVINCI_I2C_MDR_NACK	BIT(15)
78 #define DAVINCI_I2C_MDR_STT	BIT(13)
79 #define DAVINCI_I2C_MDR_STP	BIT(11)
80 #define DAVINCI_I2C_MDR_MST	BIT(10)
81 #define DAVINCI_I2C_MDR_TRX	BIT(9)
82 #define DAVINCI_I2C_MDR_XA	BIT(8)
83 #define DAVINCI_I2C_MDR_RM	BIT(7)
84 #define DAVINCI_I2C_MDR_IRS	BIT(5)
85 
86 #define DAVINCI_I2C_IMR_AAS	BIT(6)
87 #define DAVINCI_I2C_IMR_SCD	BIT(5)
88 #define DAVINCI_I2C_IMR_XRDY	BIT(4)
89 #define DAVINCI_I2C_IMR_RRDY	BIT(3)
90 #define DAVINCI_I2C_IMR_ARDY	BIT(2)
91 #define DAVINCI_I2C_IMR_NACK	BIT(1)
92 #define DAVINCI_I2C_IMR_AL	BIT(0)
93 
94 /* set SDA and SCL as GPIO */
95 #define DAVINCI_I2C_FUNC_PFUNC0	BIT(0)
96 
97 /* set SCL as output when used as GPIO*/
98 #define DAVINCI_I2C_DIR_PDIR0	BIT(0)
99 /* set SDA as output when used as GPIO*/
100 #define DAVINCI_I2C_DIR_PDIR1	BIT(1)
101 
102 /* read SCL GPIO level */
103 #define DAVINCI_I2C_DIN_PDIN0 BIT(0)
104 /* read SDA GPIO level */
105 #define DAVINCI_I2C_DIN_PDIN1 BIT(1)
106 
107 /*set the SCL GPIO high */
108 #define DAVINCI_I2C_DSET_PDSET0	BIT(0)
109 /*set the SDA GPIO high */
110 #define DAVINCI_I2C_DSET_PDSET1	BIT(1)
111 
112 /* set the SCL GPIO low */
113 #define DAVINCI_I2C_DCLR_PDCLR0	BIT(0)
114 /* set the SDA GPIO low */
115 #define DAVINCI_I2C_DCLR_PDCLR1	BIT(1)
116 
117 /* timeout for pm runtime autosuspend */
118 #define DAVINCI_I2C_PM_TIMEOUT	1000	/* ms */
119 
120 struct davinci_i2c_dev {
121 	struct device           *dev;
122 	void __iomem		*base;
123 	struct completion	cmd_complete;
124 	struct clk              *clk;
125 	int			cmd_err;
126 	u8			*buf;
127 	size_t			buf_len;
128 	int			irq;
129 	int			stop;
130 	u8			terminate;
131 	struct i2c_adapter	adapter;
132 #ifdef CONFIG_CPU_FREQ
133 	struct notifier_block	freq_transition;
134 #endif
135 	struct davinci_i2c_platform_data *pdata;
136 };
137 
138 /* default platform data to use if not supplied in the platform_device */
139 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
140 	.bus_freq	= 100,
141 	.bus_delay	= 0,
142 };
143 
davinci_i2c_write_reg(struct davinci_i2c_dev * i2c_dev,int reg,u16 val)144 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
145 					 int reg, u16 val)
146 {
147 	writew_relaxed(val, i2c_dev->base + reg);
148 }
149 
davinci_i2c_read_reg(struct davinci_i2c_dev * i2c_dev,int reg)150 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
151 {
152 	return readw_relaxed(i2c_dev->base + reg);
153 }
154 
davinci_i2c_reset_ctrl(struct davinci_i2c_dev * i2c_dev,int val)155 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
156 								int val)
157 {
158 	u16 w;
159 
160 	w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
161 	if (!val)	/* put I2C into reset */
162 		w &= ~DAVINCI_I2C_MDR_IRS;
163 	else		/* take I2C out of reset */
164 		w |= DAVINCI_I2C_MDR_IRS;
165 
166 	davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
167 }
168 
i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev * dev)169 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
170 {
171 	struct davinci_i2c_platform_data *pdata = dev->pdata;
172 	u16 psc;
173 	u32 clk;
174 	u32 d;
175 	u32 clkh;
176 	u32 clkl;
177 	u32 input_clock = clk_get_rate(dev->clk);
178 	struct device_node *of_node = dev->dev->of_node;
179 
180 	/* NOTE: I2C Clock divider programming info
181 	 * As per I2C specs the following formulas provide prescaler
182 	 * and low/high divider values
183 	 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
184 	 *                       module clk
185 	 *
186 	 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
187 	 *
188 	 * Thus,
189 	 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
190 	 *
191 	 * where if PSC == 0, d = 7,
192 	 *       if PSC == 1, d = 6
193 	 *       if PSC > 1 , d = 5
194 	 *
195 	 * Note:
196 	 * d is always 6 on Keystone I2C controller
197 	 */
198 
199 	/*
200 	 * Both Davinci and current Keystone User Guides recommend a value
201 	 * between 7MHz and 12MHz. In reality 7MHz module clock doesn't
202 	 * always produce enough margin between SDA and SCL transitions.
203 	 * Measurements show that the higher the module clock is, the
204 	 * bigger is the margin, providing more reliable communication.
205 	 * So we better target for 12MHz.
206 	 */
207 	psc = (input_clock / 12000000) - 1;
208 	if ((input_clock / (psc + 1)) > 12000000)
209 		psc++;	/* better to run under spec than over */
210 	d = (psc >= 2) ? 5 : 7 - psc;
211 
212 	if (of_node && of_device_is_compatible(of_node, "ti,keystone-i2c"))
213 		d = 6;
214 
215 	clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000));
216 	/* Avoid driving the bus too fast because of rounding errors above */
217 	if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000)
218 		clk++;
219 	/*
220 	 * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at
221 	 * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH
222 	 * to LOW ratio as 1 to 2 is more safe.
223 	 */
224 	if (pdata->bus_freq > 100)
225 		clkl = (clk << 1) / 3;
226 	else
227 		clkl = (clk >> 1);
228 	/*
229 	 * It's not always possible to have 1 to 2 ratio when d=7, so fall back
230 	 * to minimal possible clkh in this case.
231 	 *
232 	 * Note:
233 	 * CLKH is not allowed to be 0, in this case I2C clock is not generated
234 	 * at all
235 	 */
236 	if (clk > clkl + d) {
237 		clkh = clk - clkl - d;
238 		clkl -= d;
239 	} else {
240 		clkh = 1;
241 		clkl = clk - (d << 1);
242 	}
243 
244 	davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
245 	davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
246 	davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
247 
248 	dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
249 }
250 
251 /*
252  * This function configures I2C and brings I2C out of reset.
253  * This function is called during I2C init function. This function
254  * also gets called if I2C encounters any errors.
255  */
i2c_davinci_init(struct davinci_i2c_dev * dev)256 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
257 {
258 	struct davinci_i2c_platform_data *pdata = dev->pdata;
259 
260 	/* put I2C into reset */
261 	davinci_i2c_reset_ctrl(dev, 0);
262 
263 	/* compute clock dividers */
264 	i2c_davinci_calc_clk_dividers(dev);
265 
266 	/* Respond at reserved "SMBus Host" slave address" (and zero);
267 	 * we seem to have no option to not respond...
268 	 */
269 	davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, DAVINCI_I2C_OWN_ADDRESS);
270 
271 	dev_dbg(dev->dev, "PSC  = %d\n",
272 		davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
273 	dev_dbg(dev->dev, "CLKL = %d\n",
274 		davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
275 	dev_dbg(dev->dev, "CLKH = %d\n",
276 		davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
277 	dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
278 		pdata->bus_freq, pdata->bus_delay);
279 
280 
281 	/* Take the I2C module out of reset: */
282 	davinci_i2c_reset_ctrl(dev, 1);
283 
284 	/* Enable interrupts */
285 	davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
286 
287 	return 0;
288 }
289 
290 /*
291  * This routine does i2c bus recovery by using i2c_generic_scl_recovery
292  * which is provided by I2C Bus recovery infrastructure.
293  */
davinci_i2c_prepare_recovery(struct i2c_adapter * adap)294 static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap)
295 {
296 	struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
297 
298 	/* Disable interrupts */
299 	davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0);
300 
301 	/* put I2C into reset */
302 	davinci_i2c_reset_ctrl(dev, 0);
303 }
304 
davinci_i2c_unprepare_recovery(struct i2c_adapter * adap)305 static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap)
306 {
307 	struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
308 
309 	i2c_davinci_init(dev);
310 }
311 
312 static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = {
313 	.recover_bus = i2c_generic_scl_recovery,
314 	.prepare_recovery = davinci_i2c_prepare_recovery,
315 	.unprepare_recovery = davinci_i2c_unprepare_recovery,
316 };
317 
davinci_i2c_set_scl(struct i2c_adapter * adap,int val)318 static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
319 {
320 	struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
321 
322 	if (val)
323 		davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG,
324 				      DAVINCI_I2C_DSET_PDSET0);
325 	else
326 		davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG,
327 				      DAVINCI_I2C_DCLR_PDCLR0);
328 }
329 
davinci_i2c_get_scl(struct i2c_adapter * adap)330 static int davinci_i2c_get_scl(struct i2c_adapter *adap)
331 {
332 	struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
333 	int val;
334 
335 	/* read the state of SCL */
336 	val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
337 	return val & DAVINCI_I2C_DIN_PDIN0;
338 }
339 
davinci_i2c_get_sda(struct i2c_adapter * adap)340 static int davinci_i2c_get_sda(struct i2c_adapter *adap)
341 {
342 	struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
343 	int val;
344 
345 	/* read the state of SDA */
346 	val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
347 	return val & DAVINCI_I2C_DIN_PDIN1;
348 }
349 
davinci_i2c_scl_prepare_recovery(struct i2c_adapter * adap)350 static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap)
351 {
352 	struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
353 
354 	davinci_i2c_prepare_recovery(adap);
355 
356 	/* SCL output, SDA input */
357 	davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0);
358 
359 	/* change to GPIO mode */
360 	davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG,
361 			      DAVINCI_I2C_FUNC_PFUNC0);
362 }
363 
davinci_i2c_scl_unprepare_recovery(struct i2c_adapter * adap)364 static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap)
365 {
366 	struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
367 
368 	/* change back to I2C mode */
369 	davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0);
370 
371 	davinci_i2c_unprepare_recovery(adap);
372 }
373 
374 static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = {
375 	.recover_bus = i2c_generic_scl_recovery,
376 	.set_scl = davinci_i2c_set_scl,
377 	.get_scl = davinci_i2c_get_scl,
378 	.get_sda = davinci_i2c_get_sda,
379 	.prepare_recovery = davinci_i2c_scl_prepare_recovery,
380 	.unprepare_recovery = davinci_i2c_scl_unprepare_recovery,
381 };
382 
383 /*
384  * Waiting for bus not busy
385  */
i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev * dev)386 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev)
387 {
388 	unsigned long timeout = jiffies + dev->adapter.timeout;
389 
390 	do {
391 		if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB))
392 			return 0;
393 		schedule_timeout_uninterruptible(1);
394 	} while (time_before_eq(jiffies, timeout));
395 
396 	dev_warn(dev->dev, "timeout waiting for bus ready\n");
397 	i2c_recover_bus(&dev->adapter);
398 
399 	/*
400 	 * if bus is still "busy" here, it's most probably a HW problem like
401 	 * short-circuit
402 	 */
403 	if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)
404 		return -EIO;
405 
406 	return 0;
407 }
408 
409 /*
410  * Low level master read/write transaction. This function is called
411  * from i2c_davinci_xfer.
412  */
413 static int
i2c_davinci_xfer_msg(struct i2c_adapter * adap,struct i2c_msg * msg,int stop)414 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
415 {
416 	struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
417 	struct davinci_i2c_platform_data *pdata = dev->pdata;
418 	u32 flag;
419 	u16 w;
420 	unsigned long time_left;
421 
422 	if (msg->addr == DAVINCI_I2C_OWN_ADDRESS) {
423 		dev_warn(dev->dev, "transfer to own address aborted\n");
424 		return -EADDRNOTAVAIL;
425 	}
426 
427 	/* Introduce a delay, required for some boards (e.g Davinci EVM) */
428 	if (pdata->bus_delay)
429 		udelay(pdata->bus_delay);
430 
431 	/* set the slave address */
432 	davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
433 
434 	dev->buf = msg->buf;
435 	dev->buf_len = msg->len;
436 	dev->stop = stop;
437 
438 	davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
439 
440 	reinit_completion(&dev->cmd_complete);
441 	dev->cmd_err = 0;
442 
443 	/* Take I2C out of reset and configure it as master */
444 	flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
445 
446 	/* if the slave address is ten bit address, enable XA bit */
447 	if (msg->flags & I2C_M_TEN)
448 		flag |= DAVINCI_I2C_MDR_XA;
449 	if (!(msg->flags & I2C_M_RD))
450 		flag |= DAVINCI_I2C_MDR_TRX;
451 	if (msg->len == 0)
452 		flag |= DAVINCI_I2C_MDR_RM;
453 
454 	/* Enable receive or transmit interrupts */
455 	w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
456 	if (msg->flags & I2C_M_RD)
457 		w |= DAVINCI_I2C_IMR_RRDY;
458 	else
459 		w |= DAVINCI_I2C_IMR_XRDY;
460 	davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
461 
462 	dev->terminate = 0;
463 
464 	/*
465 	 * Write mode register first as needed for correct behaviour
466 	 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
467 	 * occurring before we have loaded DXR
468 	 */
469 	davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
470 
471 	/*
472 	 * First byte should be set here, not after interrupt,
473 	 * because transmit-data-ready interrupt can come before
474 	 * NACK-interrupt during sending of previous message and
475 	 * ICDXR may have wrong data
476 	 * It also saves us one interrupt, slightly faster
477 	 */
478 	if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
479 		davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
480 		dev->buf_len--;
481 	}
482 
483 	/* Set STT to begin transmit now DXR is loaded */
484 	flag |= DAVINCI_I2C_MDR_STT;
485 	if (stop && msg->len != 0)
486 		flag |= DAVINCI_I2C_MDR_STP;
487 	davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
488 
489 	time_left = wait_for_completion_timeout(&dev->cmd_complete,
490 						dev->adapter.timeout);
491 	if (!time_left) {
492 		dev_err(dev->dev, "controller timed out\n");
493 		i2c_recover_bus(adap);
494 		dev->buf_len = 0;
495 		return -ETIMEDOUT;
496 	}
497 	if (dev->buf_len) {
498 		/* This should be 0 if all bytes were transferred
499 		 * or dev->cmd_err denotes an error.
500 		 */
501 		dev_err(dev->dev, "abnormal termination buf_len=%zu\n",
502 			dev->buf_len);
503 		dev->terminate = 1;
504 		wmb();
505 		dev->buf_len = 0;
506 		return -EREMOTEIO;
507 	}
508 
509 	/* no error */
510 	if (likely(!dev->cmd_err))
511 		return msg->len;
512 
513 	/* We have an error */
514 	if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
515 		i2c_davinci_init(dev);
516 		return -EIO;
517 	}
518 
519 	if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
520 		if (msg->flags & I2C_M_IGNORE_NAK)
521 			return msg->len;
522 		w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
523 		w |= DAVINCI_I2C_MDR_STP;
524 		davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
525 		return -EREMOTEIO;
526 	}
527 	return -EIO;
528 }
529 
530 /*
531  * Prepare controller for a transaction and call i2c_davinci_xfer_msg
532  */
533 static int
i2c_davinci_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)534 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
535 {
536 	struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
537 	int i;
538 	int ret;
539 
540 	dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
541 
542 	ret = pm_runtime_resume_and_get(dev->dev);
543 	if (ret < 0) {
544 		dev_err(dev->dev, "Failed to runtime_get device: %d\n", ret);
545 		return ret;
546 	}
547 
548 	ret = i2c_davinci_wait_bus_not_busy(dev);
549 	if (ret < 0) {
550 		dev_warn(dev->dev, "timeout waiting for bus ready\n");
551 		goto out;
552 	}
553 
554 	for (i = 0; i < num; i++) {
555 		ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
556 		dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
557 			ret);
558 		if (ret < 0)
559 			goto out;
560 	}
561 
562 	ret = num;
563 
564 out:
565 	pm_runtime_mark_last_busy(dev->dev);
566 	pm_runtime_put_autosuspend(dev->dev);
567 
568 	return ret;
569 }
570 
i2c_davinci_func(struct i2c_adapter * adap)571 static u32 i2c_davinci_func(struct i2c_adapter *adap)
572 {
573 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
574 }
575 
terminate_read(struct davinci_i2c_dev * dev)576 static void terminate_read(struct davinci_i2c_dev *dev)
577 {
578 	u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
579 	w |= DAVINCI_I2C_MDR_NACK;
580 	davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
581 
582 	/* Throw away data */
583 	davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
584 	if (!dev->terminate)
585 		dev_err(dev->dev, "RDR IRQ while no data requested\n");
586 }
terminate_write(struct davinci_i2c_dev * dev)587 static void terminate_write(struct davinci_i2c_dev *dev)
588 {
589 	u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
590 	w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
591 	davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
592 
593 	if (!dev->terminate)
594 		dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
595 }
596 
597 /*
598  * Interrupt service routine. This gets called whenever an I2C interrupt
599  * occurs.
600  */
i2c_davinci_isr(int this_irq,void * dev_id)601 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
602 {
603 	struct davinci_i2c_dev *dev = dev_id;
604 	u32 stat;
605 	int count = 0;
606 	u16 w;
607 
608 	if (pm_runtime_suspended(dev->dev))
609 		return IRQ_NONE;
610 
611 	while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
612 		dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
613 		if (count++ == 100) {
614 			dev_warn(dev->dev, "Too much work in one IRQ\n");
615 			break;
616 		}
617 
618 		switch (stat) {
619 		case DAVINCI_I2C_IVR_AL:
620 			/* Arbitration lost, must retry */
621 			dev->cmd_err |= DAVINCI_I2C_STR_AL;
622 			dev->buf_len = 0;
623 			complete(&dev->cmd_complete);
624 			break;
625 
626 		case DAVINCI_I2C_IVR_NACK:
627 			dev->cmd_err |= DAVINCI_I2C_STR_NACK;
628 			dev->buf_len = 0;
629 			complete(&dev->cmd_complete);
630 			break;
631 
632 		case DAVINCI_I2C_IVR_ARDY:
633 			davinci_i2c_write_reg(dev,
634 				DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
635 			if (((dev->buf_len == 0) && (dev->stop != 0)) ||
636 			    (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
637 				w = davinci_i2c_read_reg(dev,
638 							 DAVINCI_I2C_MDR_REG);
639 				w |= DAVINCI_I2C_MDR_STP;
640 				davinci_i2c_write_reg(dev,
641 						      DAVINCI_I2C_MDR_REG, w);
642 			}
643 			complete(&dev->cmd_complete);
644 			break;
645 
646 		case DAVINCI_I2C_IVR_RDR:
647 			if (dev->buf_len) {
648 				*dev->buf++ =
649 				    davinci_i2c_read_reg(dev,
650 							 DAVINCI_I2C_DRR_REG);
651 				dev->buf_len--;
652 				if (dev->buf_len)
653 					continue;
654 
655 				davinci_i2c_write_reg(dev,
656 					DAVINCI_I2C_STR_REG,
657 					DAVINCI_I2C_IMR_RRDY);
658 			} else {
659 				/* signal can terminate transfer */
660 				terminate_read(dev);
661 			}
662 			break;
663 
664 		case DAVINCI_I2C_IVR_XRDY:
665 			if (dev->buf_len) {
666 				davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
667 						      *dev->buf++);
668 				dev->buf_len--;
669 				if (dev->buf_len)
670 					continue;
671 
672 				w = davinci_i2c_read_reg(dev,
673 							 DAVINCI_I2C_IMR_REG);
674 				w &= ~DAVINCI_I2C_IMR_XRDY;
675 				davinci_i2c_write_reg(dev,
676 						      DAVINCI_I2C_IMR_REG,
677 						      w);
678 			} else {
679 				/* signal can terminate transfer */
680 				terminate_write(dev);
681 			}
682 			break;
683 
684 		case DAVINCI_I2C_IVR_SCD:
685 			davinci_i2c_write_reg(dev,
686 				DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
687 			complete(&dev->cmd_complete);
688 			break;
689 
690 		case DAVINCI_I2C_IVR_AAS:
691 			dev_dbg(dev->dev, "Address as slave interrupt\n");
692 			break;
693 
694 		default:
695 			dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
696 			break;
697 		}
698 	}
699 
700 	return count ? IRQ_HANDLED : IRQ_NONE;
701 }
702 
703 #ifdef CONFIG_CPU_FREQ
i2c_davinci_cpufreq_transition(struct notifier_block * nb,unsigned long val,void * data)704 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
705 				     unsigned long val, void *data)
706 {
707 	struct davinci_i2c_dev *dev;
708 
709 	dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
710 
711 	i2c_lock_bus(&dev->adapter, I2C_LOCK_ROOT_ADAPTER);
712 	if (val == CPUFREQ_PRECHANGE) {
713 		davinci_i2c_reset_ctrl(dev, 0);
714 	} else if (val == CPUFREQ_POSTCHANGE) {
715 		i2c_davinci_calc_clk_dividers(dev);
716 		davinci_i2c_reset_ctrl(dev, 1);
717 	}
718 	i2c_unlock_bus(&dev->adapter, I2C_LOCK_ROOT_ADAPTER);
719 
720 	return 0;
721 }
722 
i2c_davinci_cpufreq_register(struct davinci_i2c_dev * dev)723 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
724 {
725 	dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
726 
727 	return cpufreq_register_notifier(&dev->freq_transition,
728 					 CPUFREQ_TRANSITION_NOTIFIER);
729 }
730 
i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev * dev)731 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
732 {
733 	cpufreq_unregister_notifier(&dev->freq_transition,
734 				    CPUFREQ_TRANSITION_NOTIFIER);
735 }
736 #else
i2c_davinci_cpufreq_register(struct davinci_i2c_dev * dev)737 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
738 {
739 	return 0;
740 }
741 
i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev * dev)742 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
743 {
744 }
745 #endif
746 
747 static const struct i2c_algorithm i2c_davinci_algo = {
748 	.master_xfer	= i2c_davinci_xfer,
749 	.functionality	= i2c_davinci_func,
750 };
751 
752 static const struct of_device_id davinci_i2c_of_match[] = {
753 	{.compatible = "ti,davinci-i2c", },
754 	{.compatible = "ti,keystone-i2c", },
755 	{},
756 };
757 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
758 
davinci_i2c_probe(struct platform_device * pdev)759 static int davinci_i2c_probe(struct platform_device *pdev)
760 {
761 	struct davinci_i2c_dev *dev;
762 	struct i2c_adapter *adap;
763 	struct i2c_bus_recovery_info *rinfo;
764 	int r, irq;
765 
766 	irq = platform_get_irq(pdev, 0);
767 	if (irq < 0)
768 		return irq;
769 
770 	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
771 	if (!dev)
772 		return -ENOMEM;
773 
774 	init_completion(&dev->cmd_complete);
775 
776 	dev->dev = &pdev->dev;
777 	dev->irq = irq;
778 	dev->pdata = dev_get_platdata(&pdev->dev);
779 	platform_set_drvdata(pdev, dev);
780 
781 	if (!dev->pdata && pdev->dev.of_node) {
782 		u32 prop;
783 
784 		dev->pdata = devm_kzalloc(&pdev->dev,
785 			sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
786 		if (!dev->pdata)
787 			return -ENOMEM;
788 
789 		memcpy(dev->pdata, &davinci_i2c_platform_data_default,
790 			sizeof(struct davinci_i2c_platform_data));
791 		if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
792 			&prop))
793 			dev->pdata->bus_freq = prop / 1000;
794 
795 		dev->pdata->has_pfunc =
796 			of_property_read_bool(pdev->dev.of_node,
797 					      "ti,has-pfunc");
798 	} else if (!dev->pdata) {
799 		dev->pdata = &davinci_i2c_platform_data_default;
800 	}
801 
802 	dev->clk = devm_clk_get(&pdev->dev, NULL);
803 	if (IS_ERR(dev->clk))
804 		return PTR_ERR(dev->clk);
805 
806 	dev->base = devm_platform_ioremap_resource(pdev, 0);
807 	if (IS_ERR(dev->base)) {
808 		return PTR_ERR(dev->base);
809 	}
810 
811 	pm_runtime_set_autosuspend_delay(dev->dev,
812 					 DAVINCI_I2C_PM_TIMEOUT);
813 	pm_runtime_use_autosuspend(dev->dev);
814 
815 	pm_runtime_enable(dev->dev);
816 
817 	r = pm_runtime_resume_and_get(dev->dev);
818 	if (r < 0) {
819 		dev_err(dev->dev, "failed to runtime_get device: %d\n", r);
820 		goto err_pm;
821 	}
822 
823 	i2c_davinci_init(dev);
824 
825 	r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
826 			pdev->name, dev);
827 	if (r) {
828 		dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
829 		goto err_unuse_clocks;
830 	}
831 
832 	r = i2c_davinci_cpufreq_register(dev);
833 	if (r) {
834 		dev_err(&pdev->dev, "failed to register cpufreq\n");
835 		goto err_unuse_clocks;
836 	}
837 
838 	adap = &dev->adapter;
839 	i2c_set_adapdata(adap, dev);
840 	adap->owner = THIS_MODULE;
841 	adap->class = I2C_CLASS_DEPRECATED;
842 	strscpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
843 	adap->algo = &i2c_davinci_algo;
844 	adap->dev.parent = &pdev->dev;
845 	adap->timeout = DAVINCI_I2C_TIMEOUT;
846 	adap->dev.of_node = pdev->dev.of_node;
847 
848 	if (dev->pdata->has_pfunc)
849 		adap->bus_recovery_info = &davinci_i2c_scl_recovery_info;
850 	else if (dev->pdata->gpio_recovery) {
851 		rinfo =  &davinci_i2c_gpio_recovery_info;
852 		adap->bus_recovery_info = rinfo;
853 		rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl",
854 						  GPIOD_OUT_HIGH_OPEN_DRAIN);
855 		if (IS_ERR(rinfo->scl_gpiod)) {
856 			r = PTR_ERR(rinfo->scl_gpiod);
857 			goto err_unuse_clocks;
858 		}
859 		rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
860 		if (IS_ERR(rinfo->sda_gpiod)) {
861 			r = PTR_ERR(rinfo->sda_gpiod);
862 			goto err_unuse_clocks;
863 		}
864 	}
865 
866 	adap->nr = pdev->id;
867 	r = i2c_add_numbered_adapter(adap);
868 	if (r)
869 		goto err_unuse_clocks;
870 
871 	pm_runtime_mark_last_busy(dev->dev);
872 	pm_runtime_put_autosuspend(dev->dev);
873 
874 	return 0;
875 
876 err_unuse_clocks:
877 	pm_runtime_dont_use_autosuspend(dev->dev);
878 	pm_runtime_put_sync(dev->dev);
879 err_pm:
880 	pm_runtime_disable(dev->dev);
881 
882 	return r;
883 }
884 
davinci_i2c_remove(struct platform_device * pdev)885 static void davinci_i2c_remove(struct platform_device *pdev)
886 {
887 	struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
888 	int ret;
889 
890 	i2c_davinci_cpufreq_deregister(dev);
891 
892 	i2c_del_adapter(&dev->adapter);
893 
894 	ret = pm_runtime_get_sync(&pdev->dev);
895 	if (ret < 0)
896 		dev_err(&pdev->dev, "Failed to resume device\n");
897 	else
898 		davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
899 
900 	pm_runtime_dont_use_autosuspend(dev->dev);
901 	pm_runtime_put_sync(dev->dev);
902 	pm_runtime_disable(dev->dev);
903 }
904 
davinci_i2c_suspend(struct device * dev)905 static int davinci_i2c_suspend(struct device *dev)
906 {
907 	struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev);
908 
909 	/* put I2C into reset */
910 	davinci_i2c_reset_ctrl(i2c_dev, 0);
911 
912 	return 0;
913 }
914 
davinci_i2c_resume(struct device * dev)915 static int davinci_i2c_resume(struct device *dev)
916 {
917 	struct davinci_i2c_dev *i2c_dev = dev_get_drvdata(dev);
918 
919 	/* take I2C out of reset */
920 	davinci_i2c_reset_ctrl(i2c_dev, 1);
921 
922 	return 0;
923 }
924 
925 static const struct dev_pm_ops davinci_i2c_pm = {
926 	.suspend        = davinci_i2c_suspend,
927 	.resume         = davinci_i2c_resume,
928 	NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
929 				  pm_runtime_force_resume)
930 };
931 
932 static const struct platform_device_id davinci_i2c_driver_ids[] = {
933 	{ .name = "i2c_davinci", },
934 	{ /* sentinel */ }
935 };
936 MODULE_DEVICE_TABLE(platform, davinci_i2c_driver_ids);
937 
938 static struct platform_driver davinci_i2c_driver = {
939 	.probe		= davinci_i2c_probe,
940 	.remove_new	= davinci_i2c_remove,
941 	.id_table	= davinci_i2c_driver_ids,
942 	.driver		= {
943 		.name	= "i2c_davinci",
944 		.pm	= pm_sleep_ptr(&davinci_i2c_pm),
945 		.of_match_table = davinci_i2c_of_match,
946 	},
947 };
948 
949 /* I2C may be needed to bring up other drivers */
davinci_i2c_init_driver(void)950 static int __init davinci_i2c_init_driver(void)
951 {
952 	return platform_driver_register(&davinci_i2c_driver);
953 }
954 subsys_initcall(davinci_i2c_init_driver);
955 
davinci_i2c_exit_driver(void)956 static void __exit davinci_i2c_exit_driver(void)
957 {
958 	platform_driver_unregister(&davinci_i2c_driver);
959 }
960 module_exit(davinci_i2c_exit_driver);
961 
962 MODULE_AUTHOR("Texas Instruments India");
963 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
964 MODULE_LICENSE("GPL");
965