1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * ddr_defs.h 4 * 5 * ddr specific header 6 * 7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 8 */ 9 10 #ifndef _DDR_DEFS_H 11 #define _DDR_DEFS_H 12 13 #include <asm/arch/hardware.h> 14 #include <asm/emif.h> 15 16 /* AM335X EMIF Register values */ 17 #define VTP_CTRL_READY (0x1 << 5) 18 #define VTP_CTRL_ENABLE (0x1 << 6) 19 #define VTP_CTRL_START_EN (0x1) 20 #ifdef CONFIG_AM43XX 21 #define DDR_CKE_CTRL_NORMAL 0x3 22 #else 23 #define DDR_CKE_CTRL_NORMAL 0x1 24 #endif 25 #define PHY_EN_DYN_PWRDN (0x1 << 20) 26 27 /* Micron MT47H128M16RT-25E */ 28 #define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005 29 #define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9 30 #define MT47H128M16RT25E_EMIF_TIM2 0x243631CA 31 #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F 32 #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 33 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a 34 #define MT47H128M16RT25E_RATIO 0x80 35 #define MT47H128M16RT25E_RD_DQS 0x12 36 #define MT47H128M16RT25E_PHY_WR_DATA 0x40 37 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80 38 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B 39 40 /* Micron MT41J128M16JT-125 */ 41 #define MT41J128MJT125_EMIF_READ_LATENCY 0x100006 42 #define MT41J128MJT125_EMIF_TIM1 0x0888A39B 43 #define MT41J128MJT125_EMIF_TIM2 0x26337FDA 44 #define MT41J128MJT125_EMIF_TIM3 0x501F830F 45 #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2 46 #define MT41J128MJT125_EMIF_SDREF 0x0000093B 47 #define MT41J128MJT125_ZQ_CFG 0x50074BE4 48 #define MT41J128MJT125_RATIO 0x40 49 #define MT41J128MJT125_INVERT_CLKOUT 0x1 50 #define MT41J128MJT125_RD_DQS 0x3B 51 #define MT41J128MJT125_WR_DQS 0x85 52 #define MT41J128MJT125_PHY_WR_DATA 0xC1 53 #define MT41J128MJT125_PHY_FIFO_WE 0x100 54 #define MT41J128MJT125_IOCTRL_VALUE 0x18B 55 56 /* Micron MT41J128M16JT-125 at 400MHz*/ 57 #define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007 58 #define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB 59 #define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA 60 #define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF 61 #define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2 62 #define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30 63 #define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4 64 #define MT41J128MJT125_RATIO_400MHz 0x80 65 #define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0 66 #define MT41J128MJT125_RD_DQS_400MHz 0x3A 67 #define MT41J128MJT125_WR_DQS_400MHz 0x3B 68 #define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76 69 #define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96 70 71 /* Micron MT41K128M16JT-187E */ 72 #define MT41K128MJT187E_EMIF_READ_LATENCY 0x06 73 #define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB 74 #define MT41K128MJT187E_EMIF_TIM2 0x36337FDA 75 #define MT41K128MJT187E_EMIF_TIM3 0x501F830F 76 #define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2 77 #define MT41K128MJT187E_EMIF_SDREF 0x0000093B 78 #define MT41K128MJT187E_ZQ_CFG 0x50074BE4 79 #define MT41K128MJT187E_RATIO 0x40 80 #define MT41K128MJT187E_INVERT_CLKOUT 0x1 81 #define MT41K128MJT187E_RD_DQS 0x3B 82 #define MT41K128MJT187E_WR_DQS 0x85 83 #define MT41K128MJT187E_PHY_WR_DATA 0xC1 84 #define MT41K128MJT187E_PHY_FIFO_WE 0x100 85 #define MT41K128MJT187E_IOCTRL_VALUE 0x18B 86 87 /* Micron MT41J64M16JT-125 */ 88 #define MT41J64MJT125_EMIF_SDCFG 0x61C04A32 89 90 /* Micron MT41J256M16JT-125 */ 91 #define MT41J256MJT125_EMIF_SDCFG 0x61C04B32 92 93 /* Micron MT41J256M8HX-15E */ 94 #define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006 95 #define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B 96 #define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA 97 #define MT41J256M8HX15E_EMIF_TIM3 0x501F830F 98 #define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32 99 #define MT41J256M8HX15E_EMIF_SDREF 0x0000093B 100 #define MT41J256M8HX15E_ZQ_CFG 0x50074BE4 101 #define MT41J256M8HX15E_RATIO 0x40 102 #define MT41J256M8HX15E_INVERT_CLKOUT 0x1 103 #define MT41J256M8HX15E_RD_DQS 0x3B 104 #define MT41J256M8HX15E_WR_DQS 0x85 105 #define MT41J256M8HX15E_PHY_WR_DATA 0xC1 106 #define MT41J256M8HX15E_PHY_FIFO_WE 0x100 107 #define MT41J256M8HX15E_IOCTRL_VALUE 0x18B 108 109 /* Micron MT41K256M16HA-125E */ 110 #define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007 111 #define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB 112 #define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA 113 #define MT41K256M16HA125E_EMIF_TIM3 0x501F867F 114 #define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 115 #define MT41K256M16HA125E_EMIF_SDREF 0xC30 116 #define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 117 #define MT41K256M16HA125E_RATIO 0x80 118 #define MT41K256M16HA125E_INVERT_CLKOUT 0x0 119 #define MT41K256M16HA125E_RD_DQS 0x38 120 #define MT41K256M16HA125E_WR_DQS 0x44 121 #define MT41K256M16HA125E_PHY_WR_DATA 0x7D 122 #define MT41K256M16HA125E_PHY_FIFO_WE 0x94 123 #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B 124 125 /* Micron MT41J512M8RH-125 on EVM v1.5 */ 126 #define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006 127 #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B 128 #define MT41J512M8RH125_EMIF_TIM2 0x26517FDA 129 #define MT41J512M8RH125_EMIF_TIM3 0x501F84EF 130 #define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2 131 #define MT41J512M8RH125_EMIF_SDREF 0x0000093B 132 #define MT41J512M8RH125_ZQ_CFG 0x50074BE4 133 #define MT41J512M8RH125_RATIO 0x80 134 #define MT41J512M8RH125_INVERT_CLKOUT 0x0 135 #define MT41J512M8RH125_RD_DQS 0x3B 136 #define MT41J512M8RH125_WR_DQS 0x3C 137 #define MT41J512M8RH125_PHY_FIFO_WE 0xA5 138 #define MT41J512M8RH125_PHY_WR_DATA 0x74 139 #define MT41J512M8RH125_IOCTRL_VALUE 0x18B 140 141 /* Samsung K4B2G1646E-BIH9 */ 142 #define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007 143 #define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B 144 #define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA 145 #define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF 146 #define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2 147 #define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30 148 #define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4 149 #define K4B2G1646EBIH9_RATIO 0x80 150 #define K4B2G1646EBIH9_INVERT_CLKOUT 0x0 151 #define K4B2G1646EBIH9_RD_DQS 0x35 152 #define K4B2G1646EBIH9_WR_DQS 0x3A 153 #define K4B2G1646EBIH9_PHY_FIFO_WE 0x97 154 #define K4B2G1646EBIH9_PHY_WR_DATA 0x76 155 #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B 156 157 #define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294 158 #define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 159 #define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 160 #define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294 161 #define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294 162 #define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 163 #define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 164 165 #define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 166 #define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 167 #define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84 168 #define DDR3_DATA0_IOCTRL_VALUE 0x84 169 #define DDR3_DATA1_IOCTRL_VALUE 0x84 170 #define DDR3_DATA2_IOCTRL_VALUE 0x84 171 #define DDR3_DATA3_IOCTRL_VALUE 0x84 172 173 /** 174 * Configure DMM 175 */ 176 void config_dmm(const struct dmm_lisa_map_regs *regs); 177 178 /** 179 * Configure SDRAM 180 */ 181 void config_sdram(const struct emif_regs *regs, int nr); 182 void config_sdram_emif4d5(const struct emif_regs *regs, int nr); 183 184 /** 185 * Set SDRAM timings 186 */ 187 void set_sdram_timings(const struct emif_regs *regs, int nr); 188 189 /** 190 * Configure DDR PHY 191 */ 192 void config_ddr_phy(const struct emif_regs *regs, int nr); 193 194 struct ddr_cmd_regs { 195 unsigned int resv0[7]; 196 unsigned int cm0csratio; /* offset 0x01C */ 197 unsigned int resv1[3]; 198 unsigned int cm0iclkout; /* offset 0x02C */ 199 unsigned int resv2[8]; 200 unsigned int cm1csratio; /* offset 0x050 */ 201 unsigned int resv3[3]; 202 unsigned int cm1iclkout; /* offset 0x060 */ 203 unsigned int resv4[8]; 204 unsigned int cm2csratio; /* offset 0x084 */ 205 unsigned int resv5[3]; 206 unsigned int cm2iclkout; /* offset 0x094 */ 207 unsigned int resv6[3]; 208 }; 209 210 struct ddr_data_regs { 211 unsigned int dt0rdsratio0; /* offset 0x0C8 */ 212 unsigned int resv1[4]; 213 unsigned int dt0wdsratio0; /* offset 0x0DC */ 214 unsigned int resv2[4]; 215 unsigned int dt0wiratio0; /* offset 0x0F0 */ 216 unsigned int resv3; 217 unsigned int dt0wimode0; /* offset 0x0F8 */ 218 unsigned int dt0giratio0; /* offset 0x0FC */ 219 unsigned int resv4; 220 unsigned int dt0gimode0; /* offset 0x104 */ 221 unsigned int dt0fwsratio0; /* offset 0x108 */ 222 unsigned int resv5[4]; 223 unsigned int dt0dqoffset; /* offset 0x11C */ 224 unsigned int dt0wrsratio0; /* offset 0x120 */ 225 unsigned int resv6[4]; 226 unsigned int dt0rdelays0; /* offset 0x134 */ 227 unsigned int dt0dldiff0; /* offset 0x138 */ 228 unsigned int resv7[12]; 229 }; 230 231 /** 232 * This structure represents the DDR registers on AM33XX devices. 233 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that 234 * correspond to DATA1 registers defined here. 235 */ 236 struct ddr_regs { 237 unsigned int resv0[3]; 238 unsigned int cm0config; /* offset 0x00C */ 239 unsigned int cm0configclk; /* offset 0x010 */ 240 unsigned int resv1[2]; 241 unsigned int cm0csratio; /* offset 0x01C */ 242 unsigned int resv2[3]; 243 unsigned int cm0iclkout; /* offset 0x02C */ 244 unsigned int resv3[4]; 245 unsigned int cm1config; /* offset 0x040 */ 246 unsigned int cm1configclk; /* offset 0x044 */ 247 unsigned int resv4[2]; 248 unsigned int cm1csratio; /* offset 0x050 */ 249 unsigned int resv5[3]; 250 unsigned int cm1iclkout; /* offset 0x060 */ 251 unsigned int resv6[4]; 252 unsigned int cm2config; /* offset 0x074 */ 253 unsigned int cm2configclk; /* offset 0x078 */ 254 unsigned int resv7[2]; 255 unsigned int cm2csratio; /* offset 0x084 */ 256 unsigned int resv8[3]; 257 unsigned int cm2iclkout; /* offset 0x094 */ 258 unsigned int resv9[12]; 259 unsigned int dt0rdsratio0; /* offset 0x0C8 */ 260 unsigned int resv10[4]; 261 unsigned int dt0wdsratio0; /* offset 0x0DC */ 262 unsigned int resv11[4]; 263 unsigned int dt0wiratio0; /* offset 0x0F0 */ 264 unsigned int resv12; 265 unsigned int dt0wimode0; /* offset 0x0F8 */ 266 unsigned int dt0giratio0; /* offset 0x0FC */ 267 unsigned int resv13; 268 unsigned int dt0gimode0; /* offset 0x104 */ 269 unsigned int dt0fwsratio0; /* offset 0x108 */ 270 unsigned int resv14[4]; 271 unsigned int dt0dqoffset; /* offset 0x11C */ 272 unsigned int dt0wrsratio0; /* offset 0x120 */ 273 unsigned int resv15[4]; 274 unsigned int dt0rdelays0; /* offset 0x134 */ 275 unsigned int dt0dldiff0; /* offset 0x138 */ 276 }; 277 278 /** 279 * Encapsulates DDR CMD control registers. 280 */ 281 struct cmd_control { 282 unsigned long cmd0csratio; 283 unsigned long cmd0csforce; 284 unsigned long cmd0csdelay; 285 unsigned long cmd0iclkout; 286 unsigned long cmd1csratio; 287 unsigned long cmd1csforce; 288 unsigned long cmd1csdelay; 289 unsigned long cmd1iclkout; 290 unsigned long cmd2csratio; 291 unsigned long cmd2csforce; 292 unsigned long cmd2csdelay; 293 unsigned long cmd2iclkout; 294 }; 295 296 /** 297 * Encapsulates DDR DATA registers. 298 */ 299 struct ddr_data { 300 unsigned long datardsratio0; 301 unsigned long datawdsratio0; 302 unsigned long datawiratio0; 303 unsigned long datagiratio0; 304 unsigned long datafwsratio0; 305 unsigned long datawrsratio0; 306 }; 307 308 /** 309 * Configure DDR CMD control registers 310 */ 311 void config_cmd_ctrl(const struct cmd_control *cmd, int nr); 312 313 /** 314 * Configure DDR DATA registers 315 */ 316 void config_ddr_data(const struct ddr_data *data, int nr); 317 318 /** 319 * This structure represents the DDR io control on AM33XX devices. 320 */ 321 struct ddr_cmdtctrl { 322 unsigned int cm0ioctl; 323 unsigned int cm1ioctl; 324 unsigned int cm2ioctl; 325 unsigned int resv2[12]; 326 unsigned int dt0ioctl; 327 unsigned int dt1ioctl; 328 unsigned int dt2ioctrl; 329 unsigned int dt3ioctrl; 330 unsigned int resv3[4]; 331 unsigned int emif_sdram_config_ext; 332 }; 333 334 struct ctrl_ioregs { 335 unsigned int cm0ioctl; 336 unsigned int cm1ioctl; 337 unsigned int cm2ioctl; 338 unsigned int dt0ioctl; 339 unsigned int dt1ioctl; 340 unsigned int dt2ioctrl; 341 unsigned int dt3ioctrl; 342 unsigned int emif_sdram_config_ext; 343 }; 344 345 /** 346 * Configure DDR io control registers 347 */ 348 void config_io_ctrl(const struct ctrl_ioregs *ioregs); 349 350 struct ddr_ctrl { 351 unsigned int ddrioctrl; 352 unsigned int resv1[325]; 353 unsigned int ddrckectrl; 354 }; 355 356 #ifdef CONFIG_TI816X 357 void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl, 358 const struct emif_regs *regs, 359 const struct dmm_lisa_map_regs *lisa_regs, int nrs); 360 #else 361 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, 362 const struct ddr_data *data, const struct cmd_control *ctrl, 363 const struct emif_regs *regs, int nr); 364 #endif 365 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size); 366 367 #endif /* _DDR_DEFS_H */ 368