1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dm_services.h"
28 #include "include/logger_interface.h"
29 #include "../dce110/irq_service_dce110.h"
30
31
32 #include "dcn/dcn_3_1_4_offset.h"
33 #include "dcn/dcn_3_1_4_sh_mask.h"
34
35 #include "irq_service_dcn314.h"
36
37 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
38
39 #define DCN_BASE__INST0_SEG2 0x000034C0
40
to_dal_irq_source_dcn314(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)41 static enum dc_irq_source to_dal_irq_source_dcn314(struct irq_service *irq_service,
42 uint32_t src_id,
43 uint32_t ext_id)
44 {
45 switch (src_id) {
46 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
47 return DC_IRQ_SOURCE_VBLANK1;
48 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
49 return DC_IRQ_SOURCE_VBLANK2;
50 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
51 return DC_IRQ_SOURCE_VBLANK3;
52 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
53 return DC_IRQ_SOURCE_VBLANK4;
54 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
55 return DC_IRQ_SOURCE_VBLANK5;
56 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
57 return DC_IRQ_SOURCE_VBLANK6;
58 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
59 return DC_IRQ_SOURCE_DC1_VLINE0;
60 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
61 return DC_IRQ_SOURCE_DC2_VLINE0;
62 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
63 return DC_IRQ_SOURCE_DC3_VLINE0;
64 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
65 return DC_IRQ_SOURCE_DC4_VLINE0;
66 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
67 return DC_IRQ_SOURCE_DC5_VLINE0;
68 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
69 return DC_IRQ_SOURCE_DC6_VLINE0;
70 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
71 return DC_IRQ_SOURCE_PFLIP1;
72 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
73 return DC_IRQ_SOURCE_PFLIP2;
74 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
75 return DC_IRQ_SOURCE_PFLIP3;
76 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
77 return DC_IRQ_SOURCE_PFLIP4;
78 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
79 return DC_IRQ_SOURCE_PFLIP5;
80 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
81 return DC_IRQ_SOURCE_PFLIP6;
82 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
83 return DC_IRQ_SOURCE_VUPDATE1;
84 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
85 return DC_IRQ_SOURCE_VUPDATE2;
86 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
87 return DC_IRQ_SOURCE_VUPDATE3;
88 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
89 return DC_IRQ_SOURCE_VUPDATE4;
90 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
91 return DC_IRQ_SOURCE_VUPDATE5;
92 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
93 return DC_IRQ_SOURCE_VUPDATE6;
94 case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
95 return DC_IRQ_SOURCE_DMCUB_OUTBOX;
96 case DCN_1_0__SRCID__DC_HPD1_INT:
97 /* generic src_id for all HPD and HPDRX interrupts */
98 switch (ext_id) {
99 case DCN_1_0__CTXID__DC_HPD1_INT:
100 return DC_IRQ_SOURCE_HPD1;
101 case DCN_1_0__CTXID__DC_HPD2_INT:
102 return DC_IRQ_SOURCE_HPD2;
103 case DCN_1_0__CTXID__DC_HPD3_INT:
104 return DC_IRQ_SOURCE_HPD3;
105 case DCN_1_0__CTXID__DC_HPD4_INT:
106 return DC_IRQ_SOURCE_HPD4;
107 case DCN_1_0__CTXID__DC_HPD5_INT:
108 return DC_IRQ_SOURCE_HPD5;
109 case DCN_1_0__CTXID__DC_HPD6_INT:
110 return DC_IRQ_SOURCE_HPD6;
111 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
112 return DC_IRQ_SOURCE_HPD1RX;
113 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
114 return DC_IRQ_SOURCE_HPD2RX;
115 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
116 return DC_IRQ_SOURCE_HPD3RX;
117 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
118 return DC_IRQ_SOURCE_HPD4RX;
119 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
120 return DC_IRQ_SOURCE_HPD5RX;
121 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
122 return DC_IRQ_SOURCE_HPD6RX;
123 default:
124 return DC_IRQ_SOURCE_INVALID;
125 }
126 break;
127
128 default:
129 return DC_IRQ_SOURCE_INVALID;
130 }
131 }
132
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)133 static bool hpd_ack(
134 struct irq_service *irq_service,
135 const struct irq_source_info *info)
136 {
137 uint32_t addr = info->status_reg;
138 uint32_t value = dm_read_reg(irq_service->ctx, addr);
139 uint32_t current_status =
140 get_reg_field_value(
141 value,
142 HPD0_DC_HPD_INT_STATUS,
143 DC_HPD_SENSE_DELAYED);
144
145 dal_irq_service_ack_generic(irq_service, info);
146
147 value = dm_read_reg(irq_service->ctx, info->enable_reg);
148
149 set_reg_field_value(
150 value,
151 current_status ? 0 : 1,
152 HPD0_DC_HPD_INT_CONTROL,
153 DC_HPD_INT_POLARITY);
154
155 dm_write_reg(irq_service->ctx, info->enable_reg, value);
156
157 return true;
158 }
159
160 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
161 .set = NULL,
162 .ack = hpd_ack
163 };
164
165 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
166 .set = NULL,
167 .ack = NULL
168 };
169
170 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
171 .set = NULL,
172 .ack = NULL
173 };
174
175 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
176 .set = NULL,
177 .ack = NULL
178 };
179
180 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
181 .set = NULL,
182 .ack = NULL
183 };
184
185 static const struct irq_source_info_funcs outbox_irq_info_funcs = {
186 .set = NULL,
187 .ack = NULL
188 };
189
190 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
191 .set = NULL,
192 .ack = NULL
193 };
194
195 #undef BASE_INNER
196 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
197
198 /* compile time expand base address. */
199 #define BASE(seg) \
200 BASE_INNER(seg)
201
202 #define SRI(reg_name, block, id)\
203 (BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
204 reg ## block ## id ## _ ## reg_name)
205
206 #define SRI_DMUB(reg_name)\
207 (BASE(reg ## reg_name ## _BASE_IDX) + \
208 reg ## reg_name)
209
210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
211 .enable_reg = SRI(reg1, block, reg_num),\
212 .enable_mask = \
213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 .enable_value = {\
215 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
216 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
217 },\
218 .ack_reg = SRI(reg2, block, reg_num),\
219 .ack_mask = \
220 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
221 .ack_value = \
222 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
223
224 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
225 .enable_reg = SRI_DMUB(reg1),\
226 .enable_mask = \
227 reg1 ## __ ## mask1 ## _MASK,\
228 .enable_value = {\
229 reg1 ## __ ## mask1 ## _MASK,\
230 ~reg1 ## __ ## mask1 ## _MASK \
231 },\
232 .ack_reg = SRI_DMUB(reg2),\
233 .ack_mask = \
234 reg2 ## __ ## mask2 ## _MASK,\
235 .ack_value = \
236 reg2 ## __ ## mask2 ## _MASK \
237
238 #define hpd_int_entry(reg_num)\
239 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
240 IRQ_REG_ENTRY(HPD, reg_num,\
241 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
242 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
243 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
244 .funcs = &hpd_irq_info_funcs\
245 }
246
247 #define hpd_rx_int_entry(reg_num)\
248 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
249 IRQ_REG_ENTRY(HPD, reg_num,\
250 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
251 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
252 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
253 .funcs = &hpd_rx_irq_info_funcs\
254 }
255 #define pflip_int_entry(reg_num)\
256 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
257 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
258 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
259 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
260 .funcs = &pflip_irq_info_funcs\
261 }
262
263 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
264 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
265 */
266 #define vupdate_no_lock_int_entry(reg_num)\
267 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
268 IRQ_REG_ENTRY(OTG, reg_num,\
269 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
270 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
271 .funcs = &vupdate_no_lock_irq_info_funcs\
272 }
273
274 #define vblank_int_entry(reg_num)\
275 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
276 IRQ_REG_ENTRY(OTG, reg_num,\
277 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
278 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
279 .funcs = &vblank_irq_info_funcs\
280 }
281
282 #define vline0_int_entry(reg_num)\
283 [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
284 IRQ_REG_ENTRY(OTG, reg_num,\
285 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
286 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
287 .funcs = &vline0_irq_info_funcs\
288 }
289 #define dmub_outbox_int_entry()\
290 [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
291 IRQ_REG_ENTRY_DMUB(\
292 DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
293 DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
294 .funcs = &outbox_irq_info_funcs\
295 }
296
297 #define dummy_irq_entry() \
298 {\
299 .funcs = &dummy_irq_info_funcs\
300 }
301
302 #define i2c_int_entry(reg_num) \
303 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
304
305 #define dp_sink_int_entry(reg_num) \
306 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
307
308 #define gpio_pad_int_entry(reg_num) \
309 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
310
311 #define dc_underflow_int_entry(reg_num) \
312 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
313
314 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
315 .set = dal_irq_service_dummy_set,
316 .ack = dal_irq_service_dummy_ack
317 };
318
319 static const struct irq_source_info
320 irq_source_info_dcn314[DAL_IRQ_SOURCES_NUMBER] = {
321 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
322 hpd_int_entry(0),
323 hpd_int_entry(1),
324 hpd_int_entry(2),
325 hpd_int_entry(3),
326 hpd_int_entry(4),
327 hpd_rx_int_entry(0),
328 hpd_rx_int_entry(1),
329 hpd_rx_int_entry(2),
330 hpd_rx_int_entry(3),
331 hpd_rx_int_entry(4),
332 i2c_int_entry(1),
333 i2c_int_entry(2),
334 i2c_int_entry(3),
335 i2c_int_entry(4),
336 i2c_int_entry(5),
337 i2c_int_entry(6),
338 dp_sink_int_entry(1),
339 dp_sink_int_entry(2),
340 dp_sink_int_entry(3),
341 dp_sink_int_entry(4),
342 dp_sink_int_entry(5),
343 dp_sink_int_entry(6),
344 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
345 pflip_int_entry(0),
346 pflip_int_entry(1),
347 pflip_int_entry(2),
348 pflip_int_entry(3),
349 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
350 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
351 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
352 gpio_pad_int_entry(0),
353 gpio_pad_int_entry(1),
354 gpio_pad_int_entry(2),
355 gpio_pad_int_entry(3),
356 gpio_pad_int_entry(4),
357 gpio_pad_int_entry(5),
358 gpio_pad_int_entry(6),
359 gpio_pad_int_entry(7),
360 gpio_pad_int_entry(8),
361 gpio_pad_int_entry(9),
362 gpio_pad_int_entry(10),
363 gpio_pad_int_entry(11),
364 gpio_pad_int_entry(12),
365 gpio_pad_int_entry(13),
366 gpio_pad_int_entry(14),
367 gpio_pad_int_entry(15),
368 gpio_pad_int_entry(16),
369 gpio_pad_int_entry(17),
370 gpio_pad_int_entry(18),
371 gpio_pad_int_entry(19),
372 gpio_pad_int_entry(20),
373 gpio_pad_int_entry(21),
374 gpio_pad_int_entry(22),
375 gpio_pad_int_entry(23),
376 gpio_pad_int_entry(24),
377 gpio_pad_int_entry(25),
378 gpio_pad_int_entry(26),
379 gpio_pad_int_entry(27),
380 gpio_pad_int_entry(28),
381 gpio_pad_int_entry(29),
382 gpio_pad_int_entry(30),
383 dc_underflow_int_entry(1),
384 dc_underflow_int_entry(2),
385 dc_underflow_int_entry(3),
386 dc_underflow_int_entry(4),
387 dc_underflow_int_entry(5),
388 dc_underflow_int_entry(6),
389 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
390 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
391 vupdate_no_lock_int_entry(0),
392 vupdate_no_lock_int_entry(1),
393 vupdate_no_lock_int_entry(2),
394 vupdate_no_lock_int_entry(3),
395 vblank_int_entry(0),
396 vblank_int_entry(1),
397 vblank_int_entry(2),
398 vblank_int_entry(3),
399 vline0_int_entry(0),
400 vline0_int_entry(1),
401 vline0_int_entry(2),
402 vline0_int_entry(3),
403 [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
404 [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
405 dmub_outbox_int_entry(),
406 };
407
408 static const struct irq_service_funcs irq_service_funcs_dcn314 = {
409 .to_dal_irq_source = to_dal_irq_source_dcn314
410 };
411
dcn314_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)412 static void dcn314_irq_construct(
413 struct irq_service *irq_service,
414 struct irq_service_init_data *init_data)
415 {
416 dal_irq_service_construct(irq_service, init_data);
417
418 irq_service->info = irq_source_info_dcn314;
419 irq_service->funcs = &irq_service_funcs_dcn314;
420 }
421
dal_irq_service_dcn314_create(struct irq_service_init_data * init_data)422 struct irq_service *dal_irq_service_dcn314_create(
423 struct irq_service_init_data *init_data)
424 {
425 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
426 GFP_KERNEL);
427
428 if (!irq_service)
429 return NULL;
430
431 dcn314_irq_construct(irq_service, init_data);
432 return irq_service;
433 }
434