1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2015 Broadcom Corporation
3 
4 #include <linux/delay.h>
5 #include <linux/io.h>
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/phy/phy.h>
9 #include <linux/platform_device.h>
10 
11 #define PCIE_CFG_OFFSET         0x00
12 #define PCIE1_PHY_IDDQ_SHIFT    10
13 #define PCIE0_PHY_IDDQ_SHIFT    2
14 
15 enum cygnus_pcie_phy_id {
16 	CYGNUS_PHY_PCIE0 = 0,
17 	CYGNUS_PHY_PCIE1,
18 	MAX_NUM_PHYS,
19 };
20 
21 struct cygnus_pcie_phy_core;
22 
23 /**
24  * struct cygnus_pcie_phy - Cygnus PCIe PHY device
25  * @core: pointer to the Cygnus PCIe PHY core control
26  * @id: internal ID to identify the Cygnus PCIe PHY
27  * @phy: pointer to the kernel PHY device
28  */
29 struct cygnus_pcie_phy {
30 	struct cygnus_pcie_phy_core *core;
31 	enum cygnus_pcie_phy_id id;
32 	struct phy *phy;
33 };
34 
35 /**
36  * struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control
37  * @dev: pointer to device
38  * @base: base register
39  * @lock: mutex to protect access to individual PHYs
40  * @phys: pointer to Cygnus PHY device
41  */
42 struct cygnus_pcie_phy_core {
43 	struct device *dev;
44 	void __iomem *base;
45 	struct mutex lock;
46 	struct cygnus_pcie_phy phys[MAX_NUM_PHYS];
47 };
48 
cygnus_pcie_power_config(struct cygnus_pcie_phy * phy,bool enable)49 static int cygnus_pcie_power_config(struct cygnus_pcie_phy *phy, bool enable)
50 {
51 	struct cygnus_pcie_phy_core *core = phy->core;
52 	unsigned shift;
53 	u32 val;
54 
55 	mutex_lock(&core->lock);
56 
57 	switch (phy->id) {
58 	case CYGNUS_PHY_PCIE0:
59 		shift = PCIE0_PHY_IDDQ_SHIFT;
60 		break;
61 
62 	case CYGNUS_PHY_PCIE1:
63 		shift = PCIE1_PHY_IDDQ_SHIFT;
64 		break;
65 
66 	default:
67 		mutex_unlock(&core->lock);
68 		dev_err(core->dev, "PCIe PHY %d invalid\n", phy->id);
69 		return -EINVAL;
70 	}
71 
72 	if (enable) {
73 		val = readl(core->base + PCIE_CFG_OFFSET);
74 		val &= ~BIT(shift);
75 		writel(val, core->base + PCIE_CFG_OFFSET);
76 		/*
77 		 * Wait 50 ms for the PCIe Serdes to stabilize after the analog
78 		 * front end is brought up
79 		 */
80 		msleep(50);
81 	} else {
82 		val = readl(core->base + PCIE_CFG_OFFSET);
83 		val |= BIT(shift);
84 		writel(val, core->base + PCIE_CFG_OFFSET);
85 	}
86 
87 	mutex_unlock(&core->lock);
88 	dev_dbg(core->dev, "PCIe PHY %d %s\n", phy->id,
89 		enable ? "enabled" : "disabled");
90 	return 0;
91 }
92 
cygnus_pcie_phy_power_on(struct phy * p)93 static int cygnus_pcie_phy_power_on(struct phy *p)
94 {
95 	struct cygnus_pcie_phy *phy = phy_get_drvdata(p);
96 
97 	return cygnus_pcie_power_config(phy, true);
98 }
99 
cygnus_pcie_phy_power_off(struct phy * p)100 static int cygnus_pcie_phy_power_off(struct phy *p)
101 {
102 	struct cygnus_pcie_phy *phy = phy_get_drvdata(p);
103 
104 	return cygnus_pcie_power_config(phy, false);
105 }
106 
107 static const struct phy_ops cygnus_pcie_phy_ops = {
108 	.power_on = cygnus_pcie_phy_power_on,
109 	.power_off = cygnus_pcie_phy_power_off,
110 	.owner = THIS_MODULE,
111 };
112 
cygnus_pcie_phy_probe(struct platform_device * pdev)113 static int cygnus_pcie_phy_probe(struct platform_device *pdev)
114 {
115 	struct device *dev = &pdev->dev;
116 	struct device_node *node = dev->of_node, *child;
117 	struct cygnus_pcie_phy_core *core;
118 	struct phy_provider *provider;
119 	unsigned cnt = 0;
120 	int ret;
121 
122 	if (of_get_child_count(node) == 0) {
123 		dev_err(dev, "PHY no child node\n");
124 		return -ENODEV;
125 	}
126 
127 	core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
128 	if (!core)
129 		return -ENOMEM;
130 
131 	core->dev = dev;
132 
133 	core->base = devm_platform_ioremap_resource(pdev, 0);
134 	if (IS_ERR(core->base))
135 		return PTR_ERR(core->base);
136 
137 	mutex_init(&core->lock);
138 
139 	for_each_available_child_of_node(node, child) {
140 		unsigned int id;
141 		struct cygnus_pcie_phy *p;
142 
143 		if (of_property_read_u32(child, "reg", &id)) {
144 			dev_err(dev, "missing reg property for %pOFn\n",
145 				child);
146 			ret = -EINVAL;
147 			goto put_child;
148 		}
149 
150 		if (id >= MAX_NUM_PHYS) {
151 			dev_err(dev, "invalid PHY id: %u\n", id);
152 			ret = -EINVAL;
153 			goto put_child;
154 		}
155 
156 		if (core->phys[id].phy) {
157 			dev_err(dev, "duplicated PHY id: %u\n", id);
158 			ret = -EINVAL;
159 			goto put_child;
160 		}
161 
162 		p = &core->phys[id];
163 		p->phy = devm_phy_create(dev, child, &cygnus_pcie_phy_ops);
164 		if (IS_ERR(p->phy)) {
165 			dev_err(dev, "failed to create PHY\n");
166 			ret = PTR_ERR(p->phy);
167 			goto put_child;
168 		}
169 
170 		p->core = core;
171 		p->id = id;
172 		phy_set_drvdata(p->phy, p);
173 		cnt++;
174 	}
175 
176 	dev_set_drvdata(dev, core);
177 
178 	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
179 	if (IS_ERR(provider)) {
180 		dev_err(dev, "failed to register PHY provider\n");
181 		return PTR_ERR(provider);
182 	}
183 
184 	dev_dbg(dev, "registered %u PCIe PHY(s)\n", cnt);
185 
186 	return 0;
187 put_child:
188 	of_node_put(child);
189 	return ret;
190 }
191 
192 static const struct of_device_id cygnus_pcie_phy_match_table[] = {
193 	{ .compatible = "brcm,cygnus-pcie-phy" },
194 	{ /* sentinel */ }
195 };
196 MODULE_DEVICE_TABLE(of, cygnus_pcie_phy_match_table);
197 
198 static struct platform_driver cygnus_pcie_phy_driver = {
199 	.driver = {
200 		.name = "cygnus-pcie-phy",
201 		.of_match_table = cygnus_pcie_phy_match_table,
202 	},
203 	.probe = cygnus_pcie_phy_probe,
204 };
205 module_platform_driver(cygnus_pcie_phy_driver);
206 
207 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
208 MODULE_DESCRIPTION("Broadcom Cygnus PCIe PHY driver");
209 MODULE_LICENSE("GPL v2");
210