1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2010 4 * Marvell Semiconductor <www.marvell.com> 5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 6 * Contributor: Mahavir Jain <mjain@marvell.com> 7 */ 8 9 #include <common.h> 10 #include <asm/arch/cpu.h> 11 #include <asm/arch/armada100.h> 12 13 /* 14 * Timer registers 15 * Refer Section A.6 in Datasheet 16 */ 17 struct armd1tmr_registers { 18 u32 clk_ctrl; /* Timer clk control reg */ 19 u32 match[9]; /* Timer match registers */ 20 u32 count[3]; /* Timer count registers */ 21 u32 status[3]; 22 u32 ie[3]; 23 u32 preload[3]; /* Timer preload value */ 24 u32 preload_ctrl[3]; 25 u32 wdt_match_en; 26 u32 wdt_match_r; 27 u32 wdt_val; 28 u32 wdt_sts; 29 u32 icr[3]; 30 u32 wdt_icr; 31 u32 cer; /* Timer count enable reg */ 32 u32 cmr; 33 u32 ilr[3]; 34 u32 wcr; 35 u32 wfar; 36 u32 wsar; 37 u32 cvwr; 38 }; 39 40 #define TIMER 0 /* Use TIMER 0 */ 41 /* Each timer has 3 match registers */ 42 #define MATCH_CMP(x) ((3 * TIMER) + x) 43 #define TIMER_LOAD_VAL 0xffffffff 44 #define COUNT_RD_REQ 0x1 45 46 DECLARE_GLOBAL_DATA_PTR; 47 /* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */ 48 49 /* For preventing risk of instability in reading counter value, 50 * first set read request to register cvwr and then read same 51 * register after it captures counter value. 52 */ read_timer(void)53 ulong read_timer(void) 54 { 55 struct armd1tmr_registers *armd1timers = 56 (struct armd1tmr_registers *) ARMD1_TIMER_BASE; 57 volatile int loop=100; 58 59 writel(COUNT_RD_REQ, &armd1timers->cvwr); 60 while (loop--); 61 return(readl(&armd1timers->cvwr)); 62 } 63 get_timer_masked(void)64 static ulong get_timer_masked(void) 65 { 66 ulong now = read_timer(); 67 68 if (now >= gd->arch.tbl) { 69 /* normal mode */ 70 gd->arch.tbu += now - gd->arch.tbl; 71 } else { 72 /* we have an overflow ... */ 73 gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl; 74 } 75 gd->arch.tbl = now; 76 77 return gd->arch.tbu; 78 } 79 get_timer(ulong base)80 ulong get_timer(ulong base) 81 { 82 return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) - 83 base); 84 } 85 __udelay(unsigned long usec)86 void __udelay(unsigned long usec) 87 { 88 ulong delayticks; 89 ulong endtime; 90 91 delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000)); 92 endtime = get_timer_masked() + delayticks; 93 94 while (get_timer_masked() < endtime); 95 } 96 97 /* 98 * init the Timer 99 */ timer_init(void)100 int timer_init(void) 101 { 102 struct armd1apb1_registers *apb1clkres = 103 (struct armd1apb1_registers *) ARMD1_APBC1_BASE; 104 struct armd1tmr_registers *armd1timers = 105 (struct armd1tmr_registers *) ARMD1_TIMER_BASE; 106 107 /* Enable Timer clock at 3.25 MHZ */ 108 writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers); 109 110 /* load value into timer */ 111 writel(0x0, &armd1timers->clk_ctrl); 112 /* Use Timer 0 Match Resiger 0 */ 113 writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]); 114 /* Preload value is 0 */ 115 writel(0x0, &armd1timers->preload[TIMER]); 116 /* Enable match comparator 0 for Timer 0 */ 117 writel(0x1, &armd1timers->preload_ctrl[TIMER]); 118 119 /* Enable timer 0 */ 120 writel(0x1, &armd1timers->cer); 121 /* init the gd->arch.tbu and gd->arch.tbl value */ 122 gd->arch.tbl = read_timer(); 123 gd->arch.tbu = 0; 124 125 return 0; 126 } 127 128 #define MPMU_APRR_WDTR (1<<4) 129 #define TMR_WFAR 0xbaba /* WDT Register First key */ 130 #define TMP_WSAR 0xeb10 /* WDT Register Second key */ 131 132 /* 133 * This function uses internal Watchdog Timer 134 * based reset mechanism. 135 * Steps to write watchdog registers (protected access) 136 * 1. Write key value to TMR_WFAR reg. 137 * 2. Write key value to TMP_WSAR reg. 138 * 3. Perform write operation. 139 */ reset_cpu(unsigned long ignored)140 void reset_cpu (unsigned long ignored) 141 { 142 struct armd1mpmu_registers *mpmu = 143 (struct armd1mpmu_registers *) ARMD1_MPMU_BASE; 144 struct armd1tmr_registers *armd1timers = 145 (struct armd1tmr_registers *) ARMD1_TIMER_BASE; 146 u32 val; 147 148 /* negate hardware reset to the WDT after system reset */ 149 val = readl(&mpmu->aprr); 150 val = val | MPMU_APRR_WDTR; 151 writel(val, &mpmu->aprr); 152 153 /* reset/enable WDT clock */ 154 writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr); 155 readl(&mpmu->wdtpcr); 156 writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr); 157 readl(&mpmu->wdtpcr); 158 159 /* clear previous WDT status */ 160 writel(TMR_WFAR, &armd1timers->wfar); 161 writel(TMP_WSAR, &armd1timers->wsar); 162 writel(0, &armd1timers->wdt_sts); 163 164 /* set match counter */ 165 writel(TMR_WFAR, &armd1timers->wfar); 166 writel(TMP_WSAR, &armd1timers->wsar); 167 writel(0xf, &armd1timers->wdt_match_r); 168 169 /* enable WDT reset */ 170 writel(TMR_WFAR, &armd1timers->wfar); 171 writel(TMP_WSAR, &armd1timers->wsar); 172 writel(0x3, &armd1timers->wdt_match_en); 173 174 while(1); 175 } 176 177 /* 178 * This function is derived from PowerPC code (read timebase as long long). 179 * On ARM it just returns the timer value. 180 */ get_ticks(void)181 unsigned long long get_ticks(void) 182 { 183 return get_timer(0); 184 } 185 186 /* 187 * This function is derived from PowerPC code (timebase clock frequency). 188 * On ARM it returns the number of timer ticks per second. 189 */ get_tbclk(void)190 ulong get_tbclk (void) 191 { 192 return (ulong)CONFIG_SYS_HZ; 193 } 194